Académique Documents
Professionnel Documents
Culture Documents
VLSI (B.Tech.)
S.NO Projects Titles Type
Front End(Verilog HDL/VHDL)
1 An Optimized Design of Area efficient FAM for Real time Arithmetic operations IEEE
Video Objects Motion Estimation Architecture using Adaptive Rood Pattern Search(ARPS)
2 IEEE
Algorithm
3 A Nano-Transmitter design for Ultra-Wide Band Communications IEEE
9 Low power VLSI architecture for adaptive filter and its application to noise cancellation IEEE
16 Built in generation of functional broadside tests using a fixed hardware structure IEEE
17 Constant and high speed adder design using QSD number system IEEE
21 Bar Code Reader(RFID Gun) with Reliable and Higher Throughput Anti-Collision Technique IEEE
Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
V S TECHNO SOLUTIONS
SMART SOLLUTIONS FOR SMART PEOPLE
A new approach to design fault coverage circuit with efficient hardware utilization for testing
22 IEEE
applications
23 Design of Parallel Carry-Save Pipelined RSFQ Multiplier IEEE
24 Single phase clock distribution using VLSI technology for low power IEEE
25 A VLSI architecture for video object motion estimation using a 2D hierarchical mesh model IEEE
26 High Speed FPGA implementation of FIR Filters for DSP Applications IEEE
27 Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique IEEE
28 A Novel Approach for parallel CRC generation FOR High Speed Application. IEEE
29 High speed Modified Booth Encoder multiplier for signed and unsigned numbers. IEEE
30 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation. IEEE
Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining
31 IEEE
concept using Verilog and FPGA
32 Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra IEEE
38 High Speed Booth Encoded Multiplier to Minimize the Computation time IEEE
39 Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation. IEEE
41 Efficient Weighted Pattern Generation Technique with Low Hardware Overhead IEEE
42 SCA-FF and SCAh-FF design for single cycle access test IEEE
44 A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm IEEE
Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
V S TECHNO SOLUTIONS
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57 Digitally Controlled Pulse Width Modulator for On-Chip Power Management IEEE
A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and
58 IEEE
Low Phase Noise Current Starved VCO
59 Area Efficient ROM-Embedded SRAM Cache IEEE
60 A Low Power MICS Band Phase - Locked Loop for High Resolution Retinal Prosthesis IEEE
Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
V S TECHNO SOLUTIONS
SMART SOLLUTIONS FOR SMART PEOPLE
Technique
3 A Noval Approach for parallel CRC generation FOR High Speed Application.
4 High speed Modified Booth Encoder multiplier for signed and unsigned numbers.
Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
5
Implementation.
Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block
6
Chaining concept using Verilog and FPGA
Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on
11
Fast FIR Algorithm
14 Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation.
Low Power Design Techniques Applied to Pipelined Parallel and Iterative CORDIC
17
Design
Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
V S TECHNO SOLUTIONS
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High Speed 3D DWT VlSI Architecture for Image Processing Using Lifting Based wavelet
24
Transform
30 Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag
36 High speed carry save multiplier based linear convolution using Vedic mathematics
42 Hardware modeling of binary coded decimal adder in field programmable gate array
Design and Implementation of Two Variable Multiplier Using KCM and Vedic
45
Mathematics.
Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com