UNIVERSITY PART-B ANSWERS

UNIT-1

1. Discuss about the DC load line and Q point. (OR) What is D.C. load line, how will
you select the operating point, explain it using common emitter amplifier
characteristics as an example?[NOV/DEC-06,09,11,12][MAY/JUN-12,13]

DC load line:-

It is the line on the output characteristics of a transistor circuit which gives

the values of IC and VCE corresponding to zero signal (or) DC conditions.

The transistor is biased with a common supply such that the base emitter
junction is forward biased and the collector base junction is reversed biased, i.e.
Transistor is in the active region.

In the absence of ac signal, the capacitors provide very high impedance, i.e. open
circuit. Therefore, the equivalent circuit for common emitter amplifier because, as shown
fig.

We get,

VCC-IC (RC+RE) VCE = 0

VCC = IC (RC+RE) + VCE ---------- 1

Where IC (RC+RE) is the voltage drop across RC and RE ,

and VCE is the collector emitter voltage. If we arrange the

 terms in equation 1 as

1 VCC
IC VCE
RC RE RC RE

1 VCC
VCE Rdc RC R E ---------- 2
Rdc Rdc

And com
axis, then we can draw a straight line on the graph
of IC Vs VCE which is having slope (-1/Rdc) & y intercept VCC/Rdc. To determine the two points
on the line we assume VCE = VCC & VCE = 0.

1. When VCE = VCC; IC = 0 and we get a point of cut-off

2. When VCE = 0; IC = VCC/Rdc & we get a point saturation region

point:

The term biasing appearing for the application of dc voltages to establish a fixed level of
current and voltage. For transistor amplifiers the resulting dc current and voltage establish an
operating point on the characteristics that define the region that will be employed for
amplification of the applied signal. Since the operating point is a fixed point on the
 characteristics, it is also called the quiescent point (abbreviated Q-point).The intersection
of the two points is called operating point.
By definition, quiescent means quiet, still, inactive. The above figure as a general output
device characteristic with three operating points indicated. The biasing circuit can be designed to
set the device operation at any of these points or others within the active region. Fig shows the

horizontal line for the maximum collector current ICmax and a vertical line at the
maximum collector-to-emitter voltage VCEmax. At the lower end of the scales are the cutoff
region, defined by IB 0 A, and the saturation region, defined by VCE VCEsat. The BJT device
could be biased to operate outside these maximum limits, but the result of such operation would
be either a considerable shortening of the lifetime of the device or destruction of the device.
Confining ourselves to the active region, one can select many different operating areas or points.

Fig. Transistor is driven into active region because the Q point is close to the Active
for the driven input signal.
 The chosen Q-point often depends on the intended use of the circuit. biased the BJT at a
desired operating point, the effect of temperature must also be taken into account. Temperature

current (ICEO) to change. Higher temperatures result in increased leakage currents in the device,
thereby changing the operating condition set by the biasing network. The result is that the
network design must also provide a degree of temperature stability so that temperature changes
result in minimum changes in the operating point. This maintenance of the operating point can be
specified by a stability factor, S, which indicates the degree of change in operating point due to a
temperature variation. A highly stable circuit is desirable,
and the stability of a few basic bias circuits will be compared.

For the BJT to be biased in its linear or active operating region the following must be true:
1. The base emitter junction must be forward-biased (p-region voltage more positive),
with a resulting forward-bias voltage of about 0.6 to 0.7 V.
2. The base collector junction must be reverse-biased (n-region more positive), with
the reverse-bias voltage being any value within the maximum limits of the device.

Active-region Cutoff-region Saturation-region

Region
operation operation operation

Base emitter junction Forward biased Reverse biased Forward biased

Base collector junction Reverse biased Reverse biased Forward biased

2. Explain the fixed biasing of BJT with analysis.[MAY/JUN-10]
Biasing:- The process of giving proper supply voltages and resistances for obtaining the Q
point is called biasing.

The fixed biasing is otherwise called as base bias. For the dc analysis the network can be isolated
from the indicated ac levels by replacing the capacitors with an open circuit equivalent. In
addition, the dc supply VCC can be separated into two supplies (for analysis purposes only) as
shown in Fig to permit a separation of input and output circuits. It also reduces the linkage
between the two to the base current IB. The VCC is connected directly to RB and RC just as in Fig.

Circuit Diagram:

Base Circuit:

Consider first the base

clockwise direction for the loop, we obtain

Note the polarity of the voltage drop across RB as established by the indicated direction of IB.
Solving the equation for the current IB will result in the following:
Equation -2 is certainly not a difficult one to remember if one simply keeps in mind that the base
current is the current through RB RB divided
by the resistance RB. The voltage across RB is the applied voltage VCC at one end less the drop
across the base-to-emitter junction (VBE). In addition, since the supply voltage VCC and the base
emitter voltage VBE are constants, the selection of a base resistor, RB, sets the level of base current
for the operating point.

Collector Circuit:
The collector emitter section of the network is the indicated direction of current IC and the
resulting polarity across RC. The magnitude of the collector current is related directly to IB
through

The base current is controlled by the level of R B and IC is related to IB by a constant

magnitude of IC is not a function of the resistance RC. Change RC to any level and it will not
affect the level of IB or IC as long as we remain in the active region of the device. However, as
we shall see, the level of RC will determine the magnitude of VCE, which is an important

closed loop of Fig. will result in the following:

and

which states in words that the voltage across the collector emitter region of a transistor in the
fixed-bias configuration is the supply voltage less the drop across RC

where VCE is the voltage from collector to emitter and VC and VE are the voltages from collector
and emitter to ground respectively. But in this case, since VE = 0 V,we have

In addition,since

And VE=0V
3. Determine the following for the fixed bias configuration of fig. [MAY/JUN-10]

(a) IBQ and ICQ. (c) VB and VC.

(b) VCEQ. (d) VBC

3. Explain the collector to base biasing of BJT with analysis.[NOV/DEC-09]

The fig shows the dc bias with voltage feedback. It is also called the collector to base boas. It is
an improvement over the fixed bias method. In this biasing resistor is connected between the
collector and base of the transistor to provide a feedback path. Thus I B flows through RB
and(IC+IB) flow through the RC.

Circuit Diagram:

Circuit Analysis:
Base Circuit:
Let us consider the base circuit, apply the voltage law to the base circuit we get,
VCC = (RB+RC)IB+ICRC+VBE
= (RB+RC)IB+ B RC+VBE
IB = VCC-VBE / RB RC
Collector Circuit:
Apply KVL to the output circuit
VCC = (IC+ IB) RC +VCE
VCE = VCC-(IC+IB)RC
4. Determine the quiescent levels of ICQ and VCEQ for the network of Fig.

5. Explain the Voltage divider biasing of BJT with analysis.[NOV/DEC -07,12]

In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of

silicon transistors, and the actual value of beta is usually not well defined, it would be desirable
to develop a bias circuit that is less dependent, or in fact, independent of the transistor beta If
analyzed on an exact basis the sensitivity to changes in betais quite small. If the circuit
parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally
independent of beta.
Circuit Diagram:
Base Circuit:

Let us consider base circuit,Voltage across

base R2 is the voltage VB,Apply KVL voltage
divider theorem to find the VB, we get,
 I>> IB

Collector Circuit:

Let us consider collector circuit, voltage across RE(VE) can be obtained as,

Apply KVL to the collector circuit,

Simplified Circuit of Voltage Divider Bias:

Her R1 and R2 are replaced by RB and VT , where RB B can be

calculated as,

6. For the circuit as shown in fig. Calculate VCE an

7. For the circuit shown in fig.IC Calculate RE,VEC and stability factor.
8. 8. Stability factor for a fixed bias circuit. [MAY/JUN-10] [NOV/DEC-09]
9. Explain about the fixed bias configuration for JFET with analysis.

The simplest of biasing arrangements for the n-channel JFET. Referred to as the fixed-bias
configuration, it is one of the few FET configurations that can be solved just as directly using
either a mathematical or graphical approach. The configuration of Fig. 6.1 includes the ac levels
Vi and Vo and the coupling capacitors (C1 and C

Circuit Diagram:

DC analysis:

The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as

appearing in the network.The fact that the negative terminal of the battery is connected directly
to the defined positive potential of VGS clearly reveals that the polarity of VGS is directly
opposite to that of VGG

Since VGG is a fixed dc supply, the voltage VCC is fixed in magnitude, and hence the name fixed
circuit.

The drain to source voltage of output circuit can be determined by applying KVL.
The Q point of the JFET amplifier with fixed bias circuit is given by:

Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be
ID calculated.
Graphical Analysis:
in. Recall that choosing VGS= VP/2 will result in a drain current of IDSS/4 when plotting the
equation. For the analysis of this chapter, the three points defined by IDSS, VP, and the intersection
just described will be sufficient for plotting the curve.

The fixed level of VGS has been superimposed as a vertical line at VGS= -VGG. At any point on the
vertical line, the level of VGS is VGG the level of ID must simply be determined on this vertical
line. The point where the two curves intersect is the common solution to the configuration-
commonly referred to as the quiescent or operating point. The subscript Q will be applied to
drain current and gate-to-source voltage to identify their levels at the Q-point. Note in Fig. 2 that
the quiescent level of ID is determined by drawing a horizontal line from the Q-point to the
vertical ID axis as shown in Fig. 2.
The drain-to-source voltage of the output sec
voltage law as follows
Determine the following for the network of Fig.
(a) VGSQ.
(b) IDQ.
(c) VDS.
(d) VD.
(e) VG.
(f) VS.

Graphical Approach:
The resulting Shockley curve and the vertical line at VGS=-2 V are provided in above fig. It is
certainly difficult to read beyond the second place without significantly in\
10. Discuss the various techniques of stabilization of Q-point in a transistor. [NOV/DEC-
09]
11. The amplifier shown in Fig. an n-channel FET for which, I D=0.8mA, VP=-20V and
IDSS=1.6mA. Assume that rd>Rd. Find (1) VGS (2) gm (3) Rs. [NOV/DEC-2007]