Krunal Patel

Mobile : +91 8000794133

E-mail : krunal07111990@gmail.com

Summary

Having 4 months of experience as iOS App Developer trainee in Agile Academy and done
various project using Xcode Tool.
Knowledge on Basic C++, Swift language, TCL and Perl language.
Ability to work independent and in team environment.

Tools Experience
Swift: Xcode Tool

Academic Qualification
Have completed M.Tech (VLSI Design) under Ganpat University in the year 9th July 2014.
Have successfully completed B.E in Electronics & Telecommunication under Gujarat
Technological University, Gujarat in the year 2012 with a CGPA of 6.67.

Technical Skills
Good knowledge of ASIC Design (RTL to GDSII) and Full Custom Design.

Basic knowledge in C++, OOPs.

Good knowledge on iOS Basic and Application Life Cycle.

Good knowledge on Controllers, ImageView, MapKit, SQLite.

Good understanding on XML and JSON Parsing.

Good understanding on Gestures and Animation, Multimedia (Audio and Video).

Good understanding on Local and Push Notifications.

Internship Experience
Project M-expert ASIC Design flow

Role Physical Design Trainee

Language Perl and TCL Language
Platform Synopsys Tools
Tools Synopsys IC Compiler
Team Size 2
Company name eiTRA(eInfochips Training & Research Academy) Ahmedabad
Duration August 2013 April 2014

Summary The project is focused on automated scripted flow using scripts for Physical Design. We
have implemented PLB(Processor Local Bus) performance is one of the peripheral of
PowerPC-405 processor core using scripting language.

The Processor Local Bus has different modules such as:

PLB Performance Monitor (PPM) PLB Arbiter

Tool Command Language is simple versatile language for controlling an extending

application. Where, Perl is especially for extracting report from design.
Responsibilities

Studied scripting languages.

Studied integration of scripting in EDA tools.
To build Directory structure and flow chart.
Successfully removed congestion using scripting.

Extra-curriculum activities
Seminar on Improvement to Technology Mapping for LUT-Based FPGAs,
Power Optimization of Design,
Electronics Below 10nm- Nano & Giga challenges in
Microelectronics.
Attended Half-Day workshop on SEMICONDUCTOR DEVICE TECHNOLOGY
PRESENT & FUTURE.
Attended lecture series on VLSI and Nano electronics by Prof. Kaushik Roy at IIT-GN.

Personal Details
Fathers Name : Sureshbhai Patel
Date of Birth : 7th November 1990
Gender : Male
Languages Known : English, Hindi & Gujarati
Hobbies & Interests : Football, Long Drive.
Address : Ahmedabad

DECLARATION:
I do hereby declare that all the particulars made above are true to the best of my knowledge and
belief.

Krunal Patel