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EtronTech EM639165

8Mega x 16 Synchronous DRAM (SDRAM)


(Rev 1.6, 02/2007)
Features Pin Assignment (Top View)
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz V DD
DQ0
1
2
54
53
V SS
DQ1 5
Fully synchronous operation V D DQ 3 52 V S SQ
DQ1 4 51 DQ1 4
Internal pipelined architecture DQ2 5 50 DQ1 3
2M word x 16-bit x 4-bank V S SQ 6 49 V D DQ
DQ3 7 48 DQ1 2
Programmable Mode registers DQ4 8 47 DQ1 1
- CAS# Latency: 2, or 3 V D DQ 9 46 V S SQ
DQ5 10 45 DQ1 0
- Burst Length: 1, 2, 4, 8, or full page DQ6 11 44 DQ9
- Burst Type: interleaved or linear burst V S SQ 12 43 V D DQ
DQ7 13 42 DQ8
- Burst stop function V DD 14 41 V SS
Auto Refresh and Self Refresh DQM L 15 40 NC
/W E 16 39 DQM U
4096 refresh cycles/64ms /CA S 17 38 CL K
CKE power down mode /RA S 18 37 CK E
/CS 19 36 NC
Single +3.3V power supply BA0 20 35 A11
Interface: LVTTL BA1
A 1 0 (A P )
21
22
34
33
A9
A8
54-pin 400 mil plastic TSOP II package A0 23 32 A7
Lead-free package is available A1
A2
24
25
31
30
A6
A5
A3 26 29 A4
V DD 27 28 V SS
Overview
The EM639165 SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is internally Key Specifications
configured as 4 Banks of 2M word x 16 DRAM with a EM639165 - 6/7
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write tCK3 Clock Cycle time(min.) 6/7 ns
accesses to the SDRAM are burst oriented; accesses tAC3 Access time from CLK(max.) 5/5.4 ns
start at a selected location and continue for a
programmed number of locations in a programmed tRAS Row Active time(min.) 42/42 ns
sequence. Accesses begin with the registration of a tRC Row Cycle time(min.) 60/63 ns
BankActivate command which is then followed by a
Read or Write command. Ordering Information
The EM639165 provides for programmable Read
Part Number Frequency Package
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function may EM639165TS-6G 166MHz TSOP II
be enabled to provide a self-timed row precharge that is
EM639165TS-6LG 166MHz TSOP II
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. EM639165TS-7G 143MHz TSOP II
By having a programmable mode register, the EM639165TS-7LG 143MHz TSOP II
system can choose the most suitable modes to L indicates Low Power.
maximize its performance. These devices are well suited G indicates Lead-free
for applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications.

Etron Technology, Inc.


No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech EM639165
Block Diagram

CLOCK CLOCK
CLOCL
BUFFER

CKE
De
co
der 2 MX16
CELL ARRAY
CS#
COMMAND CONTROL (BANK #A)
RAS#
CAS# DECODER SIGNAL
GENERATOR Column Decoder
WE#
UDQM
LDQM
DQ0
COLUMN
Buffer |
COUNTER
DQ15

MODE
REGISTER De
A0 co
ADDRESS der 2 MX16
~ BUFFER CELL ARRAY
A11
(BANK #B)
BA0
BA1
Column Decoder

REFRESH
COUNTER

De
co
der 2 MX16
CELL ARRAY
(BANK #C)

Column Decoder

De
co
der 2 MX16
CELL ARRAY
(BANK #D)

Column Decoder

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EtronTech EM639165

Pin Descriptions
Table 1. Pin Details of EM639165

Symbol Type Description


CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
BA0,BA1 Input Bank Select: BA0,BA1 input select the bank for operation.

BA1 BA0 Select Bank


0 0 BANK #A
0 1 BANK #B
1 0 BANK #C
1 1 BANK #D
A0-A11 Input Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A8 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
all banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
RAS# Input Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
CAS# Input Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."

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EtronTech EM639165
WE# Input Write Enable: The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
LDQM, Input Data Input/Output Mask: Controls output buffers in read mode and masks
UDQM
Input data in write mode.
DQ0-DQ15 Input / Data I/O: The DQ0-15 input and output data are synchronized with the positive
Output edges of CLK. The I/Os are maskable during Reads and Writes.
NC/RFU - No Connect: These pins should be left unconnected.
VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
( 3.3V 0.3V )
VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
(0V)
VDD Supply Power Supply: +3.3V 0.3V
VSS Supply Ground

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EtronTech EM639165
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )

Command State CKEn-1 CKEn DQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#
BankActivate Idle(3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L
PrechargeAll Any H X X X H X L L H L
Write Active(3) H X X V L Column L H L L
address
Write and AutoPrecharge Active(3) H X X V H (A0 ~ A8) L H L L
Read Active(3) H X X V L Column L H L H
address
Read and Autoprecharge Active(3) H X X V H (A0 ~ A8) L H L H
Mode Register Set Idle H X X OP code L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active(4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
AutoRefresh Idle H H X X X X L L L H
SelfRefresh Entry Idle H L X X X X L L L H
SelfRefresh Exit Idle H X X X
L H X X X X
(SelfRefresh) L H H H
Clock Suspend Mode Entry Active H L X X X X X X X X
Power Down Mode Entry Any(5) H X X X
H L X X X X
L H H H
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any L H X X X X H X X X
(PowerDown) L H H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable Active H X H X X X X X X X
Note: 1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.

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EtronTech EM639165
Commands
1 BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 signals. By
latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from
the time of bank activation. A subsequent BankActivate command to a different row in the same
bank can only be issued after the previous active row has been precharged (refer to the following
figure). The minimum time interval between successive BankActivate commands to the same bank
is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the
internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four
banks. tRRD(min.) specifies the minimum time required between activating different banks. After this
command is used, the Write command and the Block Write command perform the no mask write
operation.
T0 T1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6

CLK ..............

ADDRESS Bank A Bank A .............. Bank B Bank A


Row Addr. Col Addr. Row Addr. Row Addr.
RAS# - CAS# delay (tRCD) RAS# - RAS# delay time (tRRD)

COMM AND Bank A NOP NOP


R/W A with .............. Bank B NOP NOP Bank A
Activate AutoPrecharge Activate Activate
RAS# Cycle time (tRC)

AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.

3 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Dont care, A10 = "H", A0-A9 and A11 = Don't care)
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.

4 Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).

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EtronTech EM639165
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND
READ A NOP NOP NOP NOP NOP NOP NOP NOP

CAS# latency=2 DOUT A0 DOUT A1 DOUT A2 DOUT A3


tCK2, DQ's

CAS# latency=3 DOUT A0 DOUT A1 DOUT A2 DOUT A3


tCK3, DQ's

Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3)


The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP

CAS# latency=2 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3


tCK2, DQ's

CAS# latency=3
tCK3, DQ's DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3

Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

DQM

COMMAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP

DQ's DOUT A0 DINB 0 DINB1 DINB 2


Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 3)

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EtronTech EM639165
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK
1 Clk Interval

DQM

COMMAND BANKA READ A WRITE A


NOP NOP ACTIVATE NOP NOP NOP NOP

CAS# latency=2
tCK2, DQ's DIN A0 DIN A1 DIN A2 DIN A3

: "H" or "L"

Read to Write Interval (Burst Length 4, CAS# Latency = 2)

T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

DQM

COMMAND NOP NOP READ A NOP NOP WRITE B NOP NOP NOP

CAS# latency=2
tCK2, DQ's DIN B0 DIN B1 DIN B2 DIN B3

: "H" or "L"
Read to Write Interval (Burst Length 4, CAS# Latency = 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

ADDRESS Bank, Bank,


Bank(s)
Col A Row
tRP

COMMAND READ A NOP NOP NOP Precharge NOP NOP Activate NOP

CAS# latency=2
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK2, DQ's

CAS# latency=3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK3, DQ's

Read to Precharge (CAS# Latency = 2, 3)

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EtronTech EM639165
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COM M AND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP

DQ0 - DQ3 DIN A0 DIN A1 DIN A2 DIN A3 don't care

The first data element and the write Extra data is masked.
are registered on the same clock edge.
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COM MAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP

1 Clk Interval

DQ's DIN A0 DIN B0 DIN B1 DIN B2 DIN B3

Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)


The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.

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EtronTech EM639165
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP

CAS# latency=2
DIN A0 don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3
tCK2, DQ's

CAS# latency=3
tCK3, DQ's DIN A0 don't care don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3

Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
Input data for the write is masked.
data contention.

Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)

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The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0 T1 T2 T3 T4 T5 T6

CLK

DQM

tRP

COMMAND WRITE NOP Precharge NOP NOP Activate NOP

BANK
ADDRESS BANK (S) ROW
COL n
tWR

DQ DIN DIN
n n+ 1

: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",
A0-A8 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND Bank A NOP NOP Write A NOP NOP NOP NOP NOP
Activate AutoPrecharge

tDAL
CAS# latency=2
tCK2, DQ's
DIN A0 DIN A1
*
tDAL
CAS# latency=3
tCK3, DQ's
DIN A0 DIN A1
*
tDAL= tWR + tRP
* Begin AutoPrecharge
Bank can be reactivated at completion of tDAL

Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)


8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. One clock cycle is required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as all banks are in the idle state.

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EtronTech EM639165

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

CLK

tCK2

CKE
Clock min.

CS#

RAS#

CAS#

WE#

A11

A10

Address Key
A0-A9

DQM

tRP
DQ Hi-Z

PrechargeAll Mode Register Any


Set Command Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
The mode register is divided into various fields depending on functionality.

Address BS0,1 A11,10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length

*Note: RFU (Reserved for future use) should stay 0 during MRS cycle.

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Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 2, 4, 8, or full page.
A2 A1 A0 Burst Length
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page
Full Page Length : 512

Burst Type Field (A3)


The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.
A3 Burst Type
0 Sequential
1 Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which
is input to the device. The internal column address is varied by the Burst Length as shown in the
following table. When the value of column address, (n + m), in the table is larger than 255, only the
least significant 8 bits are effective.
Data n 0 1 2 3 4 5 6 7 - 255 256 257 -
Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -

2 words:

Burst Length 4 words:

8 words:

Full Page: Column address is repeated until terminated.


--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

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CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field.
tCAC(min) CAS# Latency X tCK
A6 A5 A4 CAS# Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved

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Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
A8 A7 Test Mode
0 0 normal mode
0 1 Vendor Use Only
1 X Vendor Use Only
Write Burst Length (A9)
This bit is used to select the burst write length.
A9 Write Burst Length
0 Burst
1 Single Bit

9 No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")

The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.

10 Burst Stop command


(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP

The burst ends after a delay equal to the CAS# latency.


CAS# latency=2 DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK2, DQ's

CAS# latency=3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK3, DQ's

Termination of a Burst Read Operation (Burst Length 4, CAS# Latency = 2, 3)

T0 T1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP

CAS# latency= 2, 3
DIN A0 DIN A1 DIN A2 don't care
DQ's

Input data for the Write is masked.

Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)

15 Rev 1.6 Feb. 2007


EtronTech EM639165
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.

12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = Dont care, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.

13 SelfRefresh Entry command


(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

14 SelfRefresh Exit command


This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.

15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.

16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.

17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system.

16 Rev 1.6 Feb. 2007


EtronTech EM639165
Absolute Maximum Rating
Symbol Item Rating Unit Note
VIN, VOUT Input, Output Voltage - 1.0 ~ 4.6 V 1
VDD, VDDQ Power Supply Voltage -1.0 ~ 4.6 V 1
TA Operating Temperature 0 ~ 70 C 1
TSTG Storage Temperature - 55 ~ 125 C 1
TSOLDER Soldering Temperature (10 second) 260 C 1
PD Power Dissipation 1 W 1
IOUT Short Circuit Output Current 50 mA 1

Recommended D.C. Operating Conditions (TA = 0~70C)


Symbol Parameter Min. Typ. Max. Unit Note
VDD Power Supply Voltage 3.0 3.3 3.6 V 2
VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2
VIH LVTTL Input High Voltage 2.0 3.0 VDDQ +0.3 V 2
VIL LVTTL Input Low Voltage - 0.3 0 0.8 V 2

Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25C)


Symbol Parameter Min. Max. Unit
CI Input Capacitance 2 5 pF
CI/O Input/Output Capacitance 4 6.5 pF
Note: These parameters are periodically sampled and are not 100% tested.

17 Rev 1.6 Feb. 2007


EtronTech EM639165

Recommended D.C. Operating Conditions (VDD = 3.3V 0.3V, TA = 0~70C)


- 6/7
Description/Test condition Symbol Max. Unit Note
Operating Current
3
tRC tRC(min), Outputs Open IDD1 120/110
One bank active
Precharge Standby Current in non-power down mode
tCK = tck(min), CS# VIH(min), CKE VIH IDD2N 20 3
Input signals are changed very 2clks
Precharge Standby Current in non-power down mode
IDD2NS 10
TCK = , CLK VIL(max), CKE VIH
Precharge Standby Current in power down mode
IDD2P 2 3
tCK = tck(min), CKE VIL(max)
Precharge Standby Current in power down mode mA
IDD2PS 2
TCK = , CKE VIL(max)
Active Standby Current in non-power down mode
tCK = tck(min), CKE VIH(min), CS# VIH(min) IDD3N 30
Input signals are changed very 2clks
Active Standby Current in non-power down mode
IDD3NS 25
CKE VIH(min), CLK VIL(max), tCK =
Operating Current (Burst mode)
IDD4 150/130 3, 4
tCK =tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
IDD5 210/210 3
tRC tRC(min)
Self Refresh Current Normal
2
VIH VDD - 0.2, 0V VIL 0.2V IDD6 mA
Lower Power
0.8

Parameter Description Min. Max. Unit Note


IIL Input Leakage Current - 1.0 1.0 A
( 0V VIN VDD, All other pins not under test = 0V )
IOL Output Leakage Current - 1.5 1.5 A
Output disable, 0V VOUT VDDQ)
VOH LVTTL Output "H" Level Voltage 2.4 V
( IOUT = -2mA )
VOL LVTTL Output "L" Level Voltage 0.4 V
( IOUT = 2mA )

18 Rev 1.6 Feb. 2007


EtronTech EM639165
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V0.3V, TA = 0~70C) (Note: 5, 6, 7, 8)

-6/7
Symbol A.C. Parameter Min. Max. Unit Note
tRC Row cycle time
60/63
(same bank)
tRCD RAS# to CAS# delay
18/20
(same bank)
tRP Precharge to refresh/row activate command
(same bank) 20/20 ns
tRRD Row activate to row activate delay
12/14
(different banks)
tRAS Row activate to precharge time
42/42 100000
(same bank)
tWR Write recovery time 2
CLK
tCCD CAS# to CAS# Delay time 1
tCK2 CL* = 2 9/10
Clock cycle time 9
tCK3 CL* = 3 6/7
tCH Clock high time 2.5/2.5 10
tCL Clock low time 2.5/2.5 10
tAC2 Access time from CLK CL* = 2 7/7
10
tAC3 (positive edge) CL* = 3 5/5.4 ns
tOH Data output hold time 2.5/2.7 9
tLZ Data output low impedance 1
tHZ Data output high impedance 5/5.4 8
tIS Data/Address/Control Input set-up time 1.5/1.5 10
tIH Data/Address/Control Input hold time 1 10
tPDE Power Down Exit set-up time 1.5/1.5
* CL is CAS# Latency.

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.

19 Rev 1.6 Feb. 2007


EtronTech EM639165
6. A.C. Test Conditions

LVTTL Interface
Reference Level of Output Signals 1.4V / 1.4V
Output Load Reference to the Under Output Load (B)
Input Signal Levels 2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V

1.4V
3.3V

1.2k 50

Z0= 50
Output Output

30pF 30pF
870

LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a
fixed slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.

9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200seconds minimum is required. Then, it is recommended that DQM is
held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.

20 Rev 1.6 Feb. 2007


EtronTech EM639165

Timing Waveforms

Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCH tCL tCK2

CKE t IS Begin AutoPrecharge Begin AutoPrecharge


Bank A Bank B
t IS tIH t IS

CS#

RAS#

CAS#

WE#

BA0,1

tIH
A10 RAx RBx RAy RAz RBy

t IS
A0-A9,A11 RBx CAx RBx CBx RAy CAy RAz RBy

DQM
tRCD tDAL t IS
tRC tIH t WR tRP tRRD
Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

Activate Write with Activate Write with Activate Write Precharge Activate Activate
Command AutoPrecharge Command AutoPrecharge Command Command Command Command Command
Bank A Command Bank B Command Bank A Bank A Bank A Bank A Bank B
Bank A Bank B

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EtronTech EM639165

Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13

CLK

tCH tCL tCK2


CKE Begin AutoPrecharge
t IS Bank B

t IS t IH tIH

CS#

RAS#

CAS#

WE#

BA0,1

t IH
A10 RAx RBx RAy

t IS
A0-A9,A11 RAx CAx RBx CBx RAy

tRRD
tRAS
DQM tRC
tAC2 tAC2 t HZ tRP
Hi-Z tRCD t LZ
DQ Ax0 Ax1 Bx0 Bx1

t OH t HZ

Activate Read Activate Read with Precharge Activate


Command Command Command Auto Precharge Command Command
Bank A Bank A Bank B Command Bank A Bank A
Bank B

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EtronTech EM639165

Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

tRC tRC
DQM tRP

DQ Ax0 Ax1 Ax2 Ax3

PrechargeAll AutoRefresh AutoRefresh Activate Read


Command Command Command Command Command
Bank A Bank A

23 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 4. Power on Sequence and Auto Refresh (CBR)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
CKE High level Minimum of 2 Refresh Cycles are required
is reauired

CS#

RAS#

CAS#

WE#

BA0,1

A10

Address Key

A0-A9,A11

DQM
tRP tRC
DQ Hi-Z

PrechargeALL 1st AutoRefresh 2nd Auto Refresh Any


Command Command Command Command
Mode Register
Inputs must be Set Command
stable for 200 s

24 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 5. Self Refresh Entry & Exit Cycle

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19

CLK
*Note 2
*Note 1 *Note 4 tRC(min) *Note 7

CKE *Note 3 tPDE


tSRX
*Note 5
t IS
*Note 6
CS#

RAS#
*Note 8
*Note 8

CAS#

BA0,1

A0-A9,A11

WE#

DQM

Hi-Z Hi-Z
DQ

Self Refresh Enter SelfRefresh Exit AutoRefresh

Note: To Enter SelfRefresh Mode


1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
1. System clock restart and be stable before returning CKE high.
2. Enable CKE and CKE should be set high for minimum time of tSRX.
3. CS# starts from high.
4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.

25 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 6.1. Clock Suspension During Burst Read (Using CKE)


(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22
7

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

DQM
tHZ

DQ Hi-Z Ax3
Ax0 Ax1 Ax2

Activate Clock Suspend Clock Suspend Clock Suspend


Command 1 Cycle 2 Cycles 3 Cycles
Bank A
Read
Command
Bank A

Note: CKE to CLK disable/enable = 1 clock

26 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 6.2. Clock Suspension During Burst Read (Using CKE)


(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

DQM
tHZ
DQHi-Z Ax0 Ax1 Ax3
Ax2

Clock Suspend
Activate Read Clock Suspend 2 Cycles Clock Suspend
Command Command 1 Cycle 3 Cycles
Bank A Bank A

Note: CKE to CLK disable/enable = 1 clock

27 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 6.3. Clock Suspension During Burst Read (Using CKE)


(Burst Length=4, CAS# Latency=3)

T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10
RAx

A0-A9,A11 RAx CAx

DQM

tHZ
DQ Hi-Z
Ax0 Ax1 Ax2 Ax3

Clock Suspend
Activate Read Clock Suspend Clock Suspend 3 Cycles
Command Command 1 Cycle 2 Cycles
Bank A Bank A

Note: CKE to CLK disable/enable = 1 clock

28 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 7.1. Clock Suspension During Burst Write (Using CKE)


(Burst Length = 4, CAS# Latency = 1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

DQM

DQ
Hi-Z DAx0 DAx1
DAx2 DAx3

Activate Clock Suspend Clock Suspend Clock Suspend


Command 1 Cycle 2 Cycles 3 Cycles
Bank A
Write
Command
Bank A

Note: CKE to CLK disable/enable = 1 clock

29 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 7.2. Clock Suspension During Burst Write (Using CKE)


(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2
2
CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

DQM

DQ Hi-Z DAx0 DAx1 DAx2 DAx3

Activate Clock Suspend Clock Suspend Clock Suspend


Command 1 Cycle 2 Cycles 3 Cycles
Bank A
Write
Command
Bank A

Note: CKE to CLK disable/enable = 1 clock

30 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 7.3. Clock Suspension During Burst Write (Using CKE)


(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0-A9,A11 RAx CAx

DQM

DQ
Hi-Z DAx0 DAx2 DAx3
DAx1

Activate Clock Suspend Clock Suspend Clock Suspend


Command 1 Cycle 2 Cycles 3 Cycles
Bank A Write
Command
Bank A

Note: CKE to CLK disable/enable = 1 clock

31 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2 tPDE
t IS
CKE

Valid

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

RAx CAx
A0~A9,A11

DQM
tHZ
Hi-Z
Ax0 Ax1 Ax2 Ax3
DQ

ACTIVE PRECHARGE
STANDBY STANDBY
Activate Read Clock Mask Clock Mask Precharge Power Down
Command Command Start End Command Mode Exit
Bank A Bank A Bank A
Power Down Power Down Any
Mode Entry Mode Exit Command
Power Down
Mode Entry

32 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 9.1. Random Column Read (Page within same Bank)


(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAw RAz

A0~A9,A11 RAw CAw CAx CAy RAz CAz

DQM

Hi-Z
DQ Aw0 Aw1 Aw2 Aw3Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3

Activate Read Read Precharge Read


Command Command Command Command Command
Bank A Bank A Bank A Bank A Bank A
Read Activate
Command Command
Bank A Bank A

33 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 9.2. Random Column Read (Page within same Bank)


(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAw RAz

RAw CAw CAx CAy RAz CAz


A0~A9,A11

DQM

Hi-Z
DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3

Activate Read Read Read Precharge Activate Read


Command Command Command Command Command Command Command
Bank A Bank A Bank A Bank A Bank A Bank A Bank A

34 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 9.3. Random Column Read (Page within same Bank)


(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAw RAz

A0~A9,A11 CAy CAz


RAw CAw CAx RAz

DQM

Hi-Z Az0
DQ Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3

Activate Read Read Read Precharge Activate Read


Command Command Command Command Command Command Command
Bank A Bank A Bank A Bank A Bank A Bank A Bank A

35 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 10.1. Random Column Write (Page within same Bank)


(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBw RBz

A0~A9,A11 RBw CBw CBy RBz CBz


CBx

DQM

DQHi-Z DBw0DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3

Activate Write Write Precharge Write


Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank B
Write Activate
Command Command
Bank B Bank B

36 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 10.2. Random Column Write (Page within same Bank)


(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBw RBz

A0~A9,A11 RBw CBw CBx CBy RBz CBz

DQM

Hi-Z DBz0 DBz1DBz2 DBz3


DQ DBw0 DBw1DBw2 DBw3 DBx0 DBx1DBy0 DBy1 DBy2 DBy3

Activate Write Write Write Precharge Activate Write


Command Command Command Command Command Command Command
Bank A Bank B Bank B Bank B Bank B Bank B Bank B

37 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 10.3. Random Column Write (Page within same Bank)


(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBw RBz

A0~A9,A11 RBw CBw CBx CBy RBz CBz

DQM

Hi-Z
DQ DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2

Activate Write Write Write Precharge Activate Write


Command Command Command Command Command Command Command
Bank A Bank B Bank B Bank B Bank B Bank B Bank B

38 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 11.1. Random Row Read (Interleaving Banks)


(Burst Length=8, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE High

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBx RAx RBy

RBx CBx RAx RBy CBy


A0~A9,A11 CAx

tRCD
DQM tAC1 tRP

Hi-Z
DQ
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2

Activate Precharge Read Precharge


Activate Command Command Command Command
Command Bank A Bank B Bank B Bank A
Bank B
Read Activate
Read Command
Command Command
Bank B Bank B
Bank A

39 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 11.2. Random Row Read (Interleaving Banks)


(Burst Length=8, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBx RAx RBy

A0~A9,A11 RBx CBx RAx CAx RBy CBy

tRCD tAC2 tRP


DQM

Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3
DQ Ax4 Ax5 Ax6 Ax7 By0 By1

Activate Read Activate Precharge Activate Read


Command Command Command Command Command Command
Bank B Bank B Bank A Bank B Bank B Bank B
Read
Command
Bank A

40 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 11.3. Random Row Read (Interleaving Banks)


(Burst Length=8, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RBx RAx RBy

RBx RAx CAx RBy


A0~A9,A11 CBx CBy

tRCD tAC3 tRP


DQM

Hi-Z
DQ Bx6 Bx7 Ax7 By0
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6

Activate Read Activate Read Precharge Activate Read Precharge


Command Command Command Command Command Command Command Command
Bank B Bank B Bank A Bank A Bank B Bank B Bank B Bank A

41 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 12.1. Random Row Write (Interleaving Banks)


(Burst Length=8, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKEHigh

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RAy

A0~A9,A11 RAx CAx RBx CBx RAy CAy

tRCD tRP tWR


DQM

Hi-Z
DQ DAx0 DAx1 DAx2
DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3

Activate Activate Precharge Precharge Write


Command Command Command Command Command
Bank A Bank B Bank A Bank B Bank A
Write Write Activate
Command Command Command
Bank A Bank B Bank A

42 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 12.2. Random Row Write (Interleaving Banks)


(Burst Length=8, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RAy

A0~A9,A11 RAx CAx RBx CBx RAy CAy

tRCD tWR* tRP tWR*


DQM

Hi-Z
DQ DAx0 DAx1 DAx2 DAx3 DAx4DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1DAy2 DAy3 DAy4

Activate Write Activate Write Activate Write


Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank A Bank A
Precharge Precharge
Command Command
Bank A Bank B

* tWR > tWR(min.)

43 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 12.3. Random Row Write (Interleaving Banks)


(Burst Length=8, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3

CKE High

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RAy

A0~A9,A11 RAx CAx RBx CBx RAy CAy

tRCD tWR* tRP tWR*


DQM

Hi-Z
DQ DAx0 DAx1 DAx2 DAx3DAx4 DAx5 DAx6 DAx7 DBx0 DBx1DBx2 DBx3 DBx4 DBx5 DBx6 DBx7DAy0 DAy1 DAy2 DAy3

Activate Write Activate Write Precharge Activate Write Precharge


Command Command Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank A Bank A Bank A Bank B

* tWR > tWR(min.)

44 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

RAx CAx CAy CAz


A0~A9,A11

DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0DAy1 DAy3 Az0 Az1
Az3

Activate Write The Write Data Read The Read Data Precharge
Command Command is Masked with a Command is Masked with a Command
Bank A Bank A Zero Clock Bank A Two Clock Bank B
Read Latency Latency
Command
Bank A

45 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0~A9,A11 RAx CAx CAy CAz

DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3

Activate Read Write The Write Data Read The Read Data
Command Command Command is Masked with a Command is Masked with a
Bank A Bank A Bank A Zero Clock Bank A Two Clock
Latency Latency

46 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

CAx CAy CAz


A0~A9,A11 RAx

DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3

Activate Read Write The Write Data Read The Read Data
Command Command Command is Masked with a Command is Masked with a
Bank A Bank A Bank A Zero Clock Bank A Two Clock
Latency Latency

47 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBw

RAx RAx RBw CBw CBx CBy CAy CBz


A0~A9,A11

tRCD tAC1
DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3

Activate Activate Read Read Read Read Precharge Precharge


Command Command Command Command Command Command Command Command
Bank A Bank B Read Bank B Bank B Bank A Bank B Bank A Bank B
Read
Command Command
Bank A Bank B

48 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RAx

A0~A9,A11 RAx CAy RAx CBw CBx CBy CAy CBz

tRCD tAC2
DQM

DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3

Activate Read Activate Read Read Read Read Read Precharge


Command Command Command Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank B Bank B Bank A Bank B Bank B
Precharge
Command
Bank A

49 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx
A10

A0~A9,A11 RAx CAx RBx CBx CBy CBz CAy

tRCD tAC3
DQM

DQ Hi-Z
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3

Precharge
Activate Read Read Read Read Read Prechaerge Command
Command Command Command Command Command CommandCommand Bank A
Bank A Bank A Bank B Bank B Bank B Bank A Bank B
Activate
Command
Bank B

50 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBw

CBy CBz
RAx CAx RBw CBw CBx CAy
A0~A9,A11
tRP
tRCD tWR tRP
DQM

tRRD
Hi-Z
DQ DAx0 DBz2
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz3

Activate Activate Write Write Write Write Write Precharge


Command Command Command Command Command Command Command Command
Bank A Bank B Bank B Bank B Bank B Bank A Bank B Bank B
Precharge
Write Command
Command Bank A
Bank A

51 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBw

A0~A9,A11 RAx CAx RBw CBw CBx CBy CAy CBz

tRCD tRP tWR tRP


DQM
tRRD

DQ Hi-Z DAx0DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1DBy0 DBy1DAy0 DAy1 DBz0 DBz1 DBz2 DBz3

Activate Write Activate Write Write Write Write Write Precharge


Command Command Command Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank B Bank B Bank A Bank B Bank B
Precharge
Command
Bank A

52 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBw

RAx CAx RBw CBw CBx CBy CAy CBz


A0~A9,A11

tRCD tWR tRP tWR(min)


DQM
tRRD > tRRD(min)
Hi-Z
DQ DAx0 DAx1 DAx2 DAx3DBw0 DBw1DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3

Activate Activate Write Write Write Write Write Precharge


Command Command Command Command Command Command Command Command
Bank A Bank B Bank B Bank B Bank B Bank A Bank B Bank B
Write Precharge
Command Command
Bank A Bank A

53 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy RBz


A10

RAx CAx RBx CBx CAy RBy CBy RBz CBz


A0~A9,A11

DQM

Hi-Z
DQ Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By3 Bz2
Ax0 By2 Bz0 Bz1 Bz3

Activate Activate Activate Read with Activate


Command Command Command Auto Precharge Command
Bank A Bank B Bank B Command Bank B
Read Read with Bank B
Auto Precharge Read with Read with
Command Auto Precharge Auto Precharge
Bank A Command
Bank B Command Command
Bank A Bank B

54 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy RAz


A10

RAx CAx RBx CBx RAy RBy CBy RAz CAz


A0~A9,A11

DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2

Activate Read Activate Read with Read with Activate Read with Activate Read with
Command Command Command Auto Precharge Auto Precharge Command Auto Precharge Command Auto Precharge
Bank A Bank A Bank B Command Command Bank B Command Bank A Command
Bank B Bank A Bank B Bank A

55 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

CKE High

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RBy

A0~A9,A11 RAx CAx RBx CBx CAy RBy CBy

DQM

Hi-Z
DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3

Activate Activate Read with Activate Read with


Command Command Auto Precharge Command Auto Precharge
Bank A Bank B Command Bank B Command
Read Bank B Read with Bank B
Command Auto Precharge
Bank A Command
Bank A

56 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK1
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RBy RAz

RAx CAx RBx CBx CAy RBy CBy RAz CAz


A0~A9,A11

DQM

DQ Hi-Z DAx0 DAx1 DAx2 DAx3


DBx0 DBx1 DBx2 DBx3 DAy0 DAy1DAy2 DAy3 DBy0
DBy1 DBy2 DBy3 DAz0 DAz0 DAz0DAz0

Activate Activate Write with Activate Write with Activate


Command Command Auto Precharge Command Auto Precharge Command
Bank A Bank B Command Bank B Command Bank A
Write Bank B Write with Bank B
Command Auto Precharge Write with
Bank A Command Auto Precharge
Bank A Command
Bank A

57 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy RAz


A10

A0~A9,A11 RAx CAx RBx CBx CAy RBy CBy RAz CAz

DQM

Hi-Z
DQ DAx0 DAx1 DAx2 DAx3
DBx0 DBx1DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3

Activate Write Activate Write with Write with Activate Write with Activate Write with
Command Command Command Auto Precharge Auto Precharge Command Auto Precharge Command Auto Precharge
Bank A Bank A Bank B Command Command Bank B Command Bank A Command
Bank B Bank A Bank B Bank A

58 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
High
CKE

CS#

RAS#

CAS#

WE#

`
BA0,1

A9 RAx RBx RBy

A0~A9,A11 RAx CAx RBx CBx CAy RBy CBy

DQM

Hi-Z
DQ DAx0 DAx1 DAx2 DAx3DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2DBy3

Activate Activate Write with Write with Activate Write with


Command Command Auto Precharge Auto Precharge Command Auto Precharge
Bank A Bank B Command Command Bank B Command
Write Bank B Bank A Bank B
Command
Bank A

59 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx
A10 RBx RBy

A0~A9,A11 RBx CBx RBy


RAx CAx

tRRD tRP
DQM

Hi-Z
DQ Ax Ax+1 Ax+2 Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7
Ax-2 Ax-1 Ax Ax+1 Bx

Activate Activate Read Precharge


Command Command Command Command
Bank A Bank B The burst counter wraps Bank B Bank B
from the highest order Full Page burst operation does not Burst Stop Activate
Read page address back to zero terminate when the burst length is satisfied; Command Command
Command during this time interval the burst counter increments and continues Bank B
Bank A bursting beginning with the starting address.

60 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
CKE High

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy


A10

RAx CAx RBx CBx RBy


A0~A9,A11

tRP
DQM

Hi-Z
DQ Ax Ax+1 Ax+2Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5 Bx+6

Activate Read Activate Read Precharge Activate


Command Command Command CommandFull Page burst operation does not Command Command
Bank A Bank A Bank B Bank Bterminate when the burst length is satisfied; Bank B Bank B
The burst counter wraps the burst counter increments and continues
from the highest order bursting beginning with the starting address.
page address back to zero
during this time interval Burst Stop
Command

61 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy


A10

RAx CAx RBx CBx RBy


A0~A9,A11

tRP
DQM

DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5

Activate Read Activate Read Full Page burst operation does not Precharge Activate
Command Command Command Command terminate when the burst length is Command Command
Bank A Bank A Bank B Bank B satisfied; the burst counter Bank B Bank B
The burst counter wraps increments and continues
from the highest order bursting beginning with the Burst Stop
page address back to zero starting address. Command
during this time interval

62 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy


A10

RAx CAx RBx CBx RBy


A0~A9,A11

DQM

DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1


DBx DBx+ 1
DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7

Activate Activate Write Data is ignored Precharge


Command Command Command Command
Bank A Bank B Bank B Bank B
The burst counter wraps Full Page burst operation does Burst Stop
not terminate when the burst Command Activate
from the highest order Command
Write page address back to zero length is satisfied; the burst counter
Command increments and continues bursting Bank B
during this time interval
Bank A beginning with the starting address.

63 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy


A10

A0~A9,A11 RAx CAx RBx CBx RBy

DQM

Hi-Z
DQ DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6

Activate Write Activate Write Data is ignored Precharge Activate


Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank B Bank B
The burst counter wraps Full Page burst operation does Burst Stop
from the highest order not terminate when the burst Command
page address back to zero length is satisfied; the burst counter
during this time interval increments and continues bursting
beginning with the starting address.

64 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RBx RBy


A10

A0~A9,A11 RAx CAx RBx CBx RBy

DQM
Data is ignored

DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx DBx+ 1
DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5

Activate Write Activate Write Precharge Activate


Command Command Command Command Command Command
Bank A Bank A Bank B Bank B Bank B Bank B
The burst counter wraps Full Page burst operation does Burst Stop
from the highest order not terminate when the burst Command
page address back to zero length is satisfied; the burst counter
during this time interval increments and continues bursting
beginning with the starting address.

65 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2
CKE High

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx

A0~A9,A11 RAx CAx CAy CAz

LDQM

UDQM

DQ0 - DQ7 Ax0 Ax1 Ax2 DAy1DAy2 Az1 Az2

Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az1 Az2 Az3


DQ8 - DQ15 Az0

Activate Read Upper 3 Bytes Lower Byte Write Upper 3 Bytes Read Lower Byte Lower Byte
Command Commandare masked is masked Command are masked Command is masked is masked
Bank A Bank A Bank A Bank A

66 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 21. Random Row Read (Interleaving Banks)


(Burst Length=2, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK1
High
CKE Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A

CS#

RAS#

CAS#

WE#

BA0,1

RBu RAu RBv RAv RBw RAw RBx RAx RBy RAy RBz RAz
A10

RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz
A0~A9,A11

tRP tRP tRP tRP tRP tRP tRP tRP tRP tRP
DQM

DQ Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0

Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate Activate
Command Command Command Command Command Command Command Command Command Command Command Command
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A
Read Read Read Read Read Read Read Read Read Read Read
Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A Bank B
with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto with Auto
Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge Precharge

67 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RBw

A0~A9,A11 RAx RBx CAx CBx CAy CBy CAz CBz RBw
tRP

DQM
tRRD tRCD
DQ
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2

Activate Activate Read Read Read Read Precharge


Command Command Command Command Command Command Command Bank B
Bank A Bank B Bank B Read Bank B Bank A Bank B (Precharge Temination)
Read Command Activate
Command Bank A Command
Bank A Bank B

68 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RBx RBw

A0~A9,A11 RAx RBx CAx CBx CAy CBy CAz CBz RBw

tWR tRP

DQM

tRRD tRCD
DQ DAx0 DBx0DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1
DBz2

Activate Activate Write Write Write Write Precharge


Command Command Command Command Command Command Command Bank B
Bank A Bank B Bank B Bank B Bank A Bank B (Precharge Temination)
Write
Write Command Activate
Command Bank A Write Data Command
Bank A is masked Bank B

69 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK1
CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10 RAx RAy RAz

CAy
RAx CAx RAy RAz CAz
A0~A9,A11
tRP
tWR tRP Precharge
Termination of
a Read Burst.
DQM

DQ DAz6 DAz7
DAx0 DAx1
DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2
DAz3 DAz4 DAz5

Activate Read Precharge Write


Precharge Termination Precharge Command Command Command
Command of a Write Burst. Command
Bank A Bank A Bank A Bank A
Write data is masked. Bank A
Write Activate
Command Activate
Command Command
Bank A Bank A
Bank A

70 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 24.2. Precharge Termination of a Burst


(Burst Length=8 or Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK2
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RAy RAz


A10

RAy CAy RAz CAz


RAx CAx
A0~A9,A11
tWR tRP tRP tRP

DQM

DQ DAx0 DAx1
DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2

Activate Write Precharge Activate Read Precharge Activate Read Precharge


Command Command Command Command Command Command Command Command Command
Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A
Precharge Termination
Precharge Termination of a Read Burst
of a Write Burst.
Write data is masked.

71 Rev 1.6 Feb. 2007


EtronTech EM639165

Figure 24.3. Precharge Termination of a Burst


(Burst Length=4, 8 or Full Page, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK
tCK3
High
CKE

CS#

RAS#

CAS#

WE#

BA0,1

RAx RAy RAz


A10

RAx CAx RAy CAy RAz


A0~A9,A11
tWR tRP tRP
DQM

DQ DAx0 DAx1 Ay0 Ay1 Ay2

Activate Write Precharge Activate Read Precharge Activate Precharge Termination


Command Command Command Command Command Command Command of a Read Burst
Bank A Bank A Bank A Bank A Bank A Bank A Bank A

Write Data
is masked Precharge Termination
of a Write Burst

72 Rev 1.6 Feb. 2007


EtronTech EM639165

54 Pin TSOP II Package Outline Drawing Information

54 28

0.254
HE
E

L1

1 27
D

A1 A2

C
A
S B e L L1
y

Symbol Dimension in inch Dimension in mm


Min Normal Max Min Normal Max
A - - 0.047 - - 1.194
A1 0.002 0.00395 0.0059 0.05 0.1 0.150
A2 - - 0.0411 - - 1.044
B 0.012 0.015 0.016 0.3 0.35 0.40
c 0.0047 0.0065 0.0083 0.120 0.165 0.210
D 0.872 0.8755 0.879 22.149 22.238 22.327
E 0.3960 0.400 0.4040 10.058 10.16 10.262
e - 0.0315 - - 0.80 -
HE 0.462 0.466 0.470 11.735 11.8365 11.938
L 0.016 0.020 0.0235 0.406 0.50 0.597
L1 - 0.033 - - 0.84 -
S - 0.035 - - 0.88 -
y - - 0.004 - - 0.10
0 - 5 0 - 5
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm

73 Rev 1.6 Feb. 2007