Académique Documents
Professionnel Documents
Culture Documents
i
work. These are the dynamic errors caused by parasitic capacitance in wires and
transistors and glitches caused by asymmetry in the settling behavior of a current
source.
The encoding used for the digital control word in a current steering DAC has a
large influence on the circuit performance, e.g., in terms static linearity and
glitches. In this work, two DAC architectures are developed. These are denoted
the decomposed and partially decomposed architectures and utilize encoding
strategies aiming at a high circuit performance by avoiding unnecessary switch-
ing of current sources. The developed architectures are compared with the well-
known binary-weighted and segmented architectures using behavioral-level sim-
ulations.
It can be hard to meet a DAC design specification using a straightforward imple-
mentation. Techniques for compensation of errors that can be applied to improve
the DAC linearity are studied. The well-known dynamic element matching
(DEM) techniques are used for transforming spurious tones caused by matching
errors into white or shaped noise. An overview of these techniques are given in
this work and a DEM technique for the decomposed DAC architecture is devel-
oped. In modulation, feedback of the quantization error is utilized to spec-
trally shape the quantization noise to reduce its power within the signal band. A
technique based on this principle is developed for spectral shaping of DAC non-
linearity errors utilizing a DAC model in a feedback loop. Two examples of utili-
zation of the technique are given.
Four different current-steering DACs implemented in CMOS technology are
developed to enable comparison between behavioral-level simulations and mea-
surements on actual implementations and to provide platforms for evaluation of
different techniques for linearity improvement. For example, a 14-bit DEM DAC
is implemented and measurement results are compared with simulation results. A
good agreement between measured and simulated results is obtained. Moreover,
a configurable 12-bit DAC capable of operating with different degrees of seg-
mentation and decomposition is implemented to evaluate the proposed decom-
posed architecture. Measurement results agree with results from behavioral-level
simulations and indicate that the decomposed architecture is a viable alternative
to the commonly used segmented architecture.
ii
Acknowledgments
First of all, I would like to thank my supervisor, Prof. Mark Vesterbacka for his
guidance and enthusiasm. I would also like to thank all my colleagues at Elec-
tronics Systems, Linkping University, for contributing to a pleasant working
environment. Special thanks go to Lic. Eng. Robert Hgglund, Lic. Eng. Henrik
Ohlsson, and Ph.D. Oscar Gustafsson for interesting discussions on research and
life in general.
My former colleagues at Ericsson Microelectronics also deserve my gratitude.
Specifically, I would like to thank Ph.D. J. Jacob Wikner, M.Sc. Niklas U.
Andersson, and Ph.D. Mikael Karlsson Rudberg. I also thank Ph.D. Gunnar
Bjrklund and M.Sc. Magnus Hgglund for supporting my work during the years
I spent doing research at Ericsson Microelectronics.
Finally, I thank my wonderful family, especially my wife Helena and my daugh-
ter Elin, for always believing in me and supporting me.
The work was supported by the Microelectronics Research Center (MERC) at
Ericsson Microelectronics and the Center for Industrial Information Technology
(CENIIT) at Linkping University.
iii
iv
Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Sampling and Reconstruction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Pulse-Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Ideal Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.4 Reconstruction with Square Pulses . . . . . . . . . . . . . . . . . . 3
1.1.5 The Ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Telecommunication Applications . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Digital Subscriber Line Applications . . . . . . . . . . . . . . . . . 6
1.2.2 The Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.3 Effects of Nonideal Transmission . . . . . . . . . . . . . . . . . . . 8
1.2.4 DACs for DSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Metrics in the Code Domain . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2 Metrics in the Frequency Domain . . . . . . . . . . . . . . . . . . 13
1.4 Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1 Nyquist-Rate and Oversampled Converters . . . . . . . . . . . 17
1.4.2 Current-Steering DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.3 Charge-Redistribution DACs . . . . . . . . . . . . . . . . . . . . . . 20
1.4.4 R-2R Ladder DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.5 Resistor-String DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.6 DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
v
1.5.1 Large-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.2 Small-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.4 Device Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.5 CMOS Transistors in Current-Steering DACs . . . . . . . . . 33
1.6 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.3 Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.6.4 Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7.1 Journal Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.7.2 Conference Publications . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.7.3 Theses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.4 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chapter 2
Modeling of Current-Steering DACs . . . . . . . . . . . . . 45
2.1 Evaluation of Performance Metrics for Static Errors . . . . . . 46
2.2 Modeling of Matching Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2.2 Modeling of Random Matching Errors . . . . . . . . . . . . . . 48
2.2.3 Modeling of Linearly Graded Matching Errors . . . . . . . . 51
2.3 Modeling of Finite Output Impedance . . . . . . . . . . . . . . . . . . 56
2.3.1 Finite Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.3.2 Finite Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.4 Modeling of Glitches due to Rise/Fall Asymmetry . . . . . . . . . 68
2.4.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.2 Model Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.4.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.4.4 Glitches in the Differential Output . . . . . . . . . . . . . . . . . . 91
Chapter 3
Digital Encoding in Current-Steering DACs . . . . . . . 93
3.1 Binary-Weighted DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.2 Segmented DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
vi
3.3 Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.1 1-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.2 Multi-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . 98
3.3.3 Properties of Decomposed DACs . . . . . . . . . . . . . . . . . . . 99
3.4 Partially Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.5 Other Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.6 Comparison of Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.6.1 Influence of Matching Errors . . . . . . . . . . . . . . . . . . . . . 105
3.6.2 Influence of Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.6.3 Simulation Result Summary . . . . . . . . . . . . . . . . . . . . . . 114
3.7 Encoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.7.1 Decomposition Encoder Implementation . . . . . . . . . . . . 114
3.7.2 Binary-to-Thermometer Encoder Implementation . . . . . 115
Chapter 4
Correction and Compensation of Errors . . . . . . . . . 117
4.1 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.1.1 Generalized DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1.2 DEM Utilizing Switching Trees . . . . . . . . . . . . . . . . . . . 120
4.1.3 Mismatch-Shaping DEM . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.4 DEM in Decomposed DACs . . . . . . . . . . . . . . . . . . . . . 123
4.2 Distributed Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.3 Modulation of Expected Errors . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.2 Spectral Shaping of Output Impedance Related Errors . 131
4.3.3 Yield Enhancement of Binary-Weighted DACs . . . . . . 132
Chapter 5
Test-Chip Implementations . . . . . . . . . . . . . . . . . . . . 139
5.1 Design and Measurement Strategies . . . . . . . . . . . . . . . . . . . 139
5.1.1 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2 A 14-bit Segmented DAC in 0.35 m CMOS . . . . . . . . . . . . 144
5.2.1 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3 A 14-bit PRDEM DAC in 0.35 m CMOS . . . . . . . . . . . . . . 147
5.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
vii
5.3.2 Simulations and Comparison with Measurements . . . . . 148
5.4 A 14-bit Dual DAC in 0.25 m CMOS . . . . . . . . . . . . . . . . . 152
5.4.1 Architecture and Implementation . . . . . . . . . . . . . . . . . . 152
5.4.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.5 A 12-bit Configurable DAC in 0.35 m CMOS . . . . . . . . . . 155
5.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.5.2 Pcell-Based Design Approach . . . . . . . . . . . . . . . . . . . . 156
5.5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.5.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Chapter 6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
viii
1 Introduction
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs), are interface circuits between the analog and digital domains.
They are used in, e.g., digital audio applications, data communication applica-
tions, and other types of applications where conversion between analog and digi-
tal signal representation is required. This thesis covers different aspects related to
modeling, error correction, and implementation of DACs for communication
applications. This chapter is an introduction to the thesis providing relevant back-
ground information and an overview of the thesis and the authors contributions
to the different areas.
1
Introduction
where n is the sequence index and T is the sample period. If z(t) is band limited,
having no spectral content above a frequency f 0 , and the sampling frequency
f s = 1 T has the property
then the analog signal z(t) can be reconstructed from the discrete-time signal
x(n) according to the sampling theorem [1].
where p(t) is a pulse. A model system for constructing y(t) is shown in Fig. 1.1.
An intermediate signal y 0(t) given by
y 0(t) = x(n)(t nT ) = z(t) (t nT ) (1.4)
n = n =
is constructed, where (t) is the unit impulse. Let denote angular frequency
and let Z () and Y 0() denote the Fourier transforms of z(t) and y 0(t) , respec-
tively. Y 0() can be expressed as [2]
1
Y 0() = ---
T 2
Z ( k ------) = f s
T Z ( k2 f s) . (1.5)
k = k =
Further, y 0(t) is filtered with a filter having the impulse response p(t) , resulting
in the reconstructed output y(t) . Hence, the Fourier transform of y(t) is
Y () = P()Y 0() = P() f s
Z ( k2 f s) ,
(1.6)
k =
where P() is the Fourier transform of p(t) . Different choices of the pulse p(t)
are discussed in the following sections.
2
Digital-to-Analog Conversion
PAM y0(t)
x(n) P(w) y(t)
d(t), T
PAM
x(n) y(t)
p(t), T
This is obtained if the filter in Fig. 1.1 is an ideal low-pass filter with bandwidth
f s 2 , i.e.,
T for < f
P() = s . (1.8)
0 otherwise
The shape of the pulse p(t) for ideal reconstruction can be found by performing
an inverse Fourier transform on (1.8), resulting in [2]
sin ( f s t )
p(t) = -----------------------
- = sinc( f s t) . (1.9)
f st
1 for T T
--- t < ---
p(t) = 2 2 , (1.10)
0 otherwise
3
Introduction
P() = T sinc ------------ . (1.12)
2 f s
The input to the DAC is digital and, hence, it is quantized. Therefore, even for an
ideal DAC, the output is subject to a quantization error. The quantization error
q(n) , sometimes referred to as quantization noise, can often be accurately mod-
eled with a white-noise signal having rectangular distribution. In the case of trun-
cation,
4
Digital-to-Analog Conversion
A
|Z(2f)|
0
4 3 2 1 0 1 2 3 4
Normalized frequency (f/fs)
(a)
TA
|Y (2f)|
0
0
4 3 2 1 0 1 2 3 4
Normalized frequency (f/fs)
(b)
A
|Y(2f)|
0
4 3 2 1 0 1 2 3 4
Normalized frequency (f/fs)
(c)
A
|Y(2f)|
0
4 3 2 1 0 1 2 3 4
Normalized frequency (f/fs)
(d)
Figure 1.2 Illustration of the effects of using different pulses for reconstruction on the sig-
nal spectrum. Z () and Y 0() are shown in (a) and (b), respectively, and
Y () using sinc and square pulses for reconstruction are shown in (c) and (d),
respectively.
5
Introduction
2
dx --- dx =
x----2- x 2
Var(q(n)) =
0
------ .
12
(1.16)
0
6
Telecommunication Applications
upstream band to ensure low interference between POTS and ADSL transmis-
sion. Another type of ADSL is the echo-canceled hybrid (ECH) ADSL [4], in
which the downstream band overlaps the upstream band to increase the down-
stream data rate compared with FDM ADSL. ECH ADSL requires the use of
echo cancellation to separate received data from transmitted data [4].
0 4 30 138 1104
Frequency [kHz]
As can be seen from Fig. 1.3, the maximum signal bandwidth in ADSL is
approximately 1 MHz. For DMT VDSL, the standard allows bandwidths up to
approximately 18 MHz [5], i.e., roughly an order of magnitude higher than for
ADSL.
7
Introduction
AFE
line driver
anti-aliasing
ADC
filter
receive amplifier
8
Telecommunication Applications
9
Introduction
are plotted in Fig. 1.5(c). For this case, there is no one-to-one mapping between
the original and the distorted constellation. Instead, due to intermodulation dis-
tortion, the location of the points are dependent on the data transmitted on the
other tones. For more severe nonlinearities, the regions in which the points can
appear start to overlap, which in turn results in bit errors in the transmission. The
situation is similar when noise is present. The constellation resulting from addi-
tion of a white Gaussian noise sequence, (n) N(0, 0.1) , is plotted in
Fig. 1.5(d).
0.75 0.75
0.25 0.25
bk
bk
0.25 0.25
0.75 0.75
(a) (b)
0.75 0.75
0.25 0.25
bk
bk
0.25 0.25
0.75 0.75
(c) (d)
Figure 1.5 (a) 16 QAM constellation, (b) linearly distorted constellation, (c) nonlinearly
distorted constellation, and (d) constellation with added noise.
10
Performance Metrics
The nonlinearities and the noise set limits on the feasible size of the constellation,
i.e., how many data bits that can be allocated to each carrier [4]. Therefore, it is
important that the components in the transmitters and the receiver have good
noise and linearity properties, which is a motivation for having the linearity prop-
erties of DACs as one of the main focuses in this work.
11
Introduction
The gain K and the offset y offset are chosen such that y nom(x) is a best-fit (least
squares) straight line with respect to the actual transfer characteristic. Some-
times, alternative choices for the nominal characteristic are used [11], e.g., using
the endpoints of the characteristic to define a straight line according to
11
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Figure 1.6 Transfer characteristic of nonideal 4-bit DAC plotted together with best-fit nom-
inal transfer characteristic.
Integral Nonlinearity
The INL of a DAC is defined as
y(x) y nom(x)
INL(x) = ---------------------------------
- (1.24)
K
12
Performance Metrics
0.4
0.3
0.2
0.1
INL
0
0.1
0.2
0.3
0.4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Differential Nonlinearity
The DNL of a DAC is defined as
13
Introduction
0.3
0.2
0.1
0
0.1
DNL
0.2
0.3
0.4
0.5
0.6
0.7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Sinusoidal test signals are often used for DAC characterization. A typical power
spectral density (PSD) plot of the output from a DAC with a single-tone input is
shown in Fig. 1.9. The largest peak in Fig. 1.9 represents the signal, whereas the
spectral content at other frequencies are unwanted signal impurities. These signal
impurities are usually divided into noise and distortion, even if it can be difficult
to make a clear distinction between the two. Noise is independent of the signal,
whereas distortion is signal dependent [12]. In the frequency domain, noise is
often characterized by a smooth spectral density, whereas (nonlinear) distortion
is visible as distinctive peaks in the output spectrum. There are, however, gray
zones present in the analysis. For example, quantization errors are clearly signal
dependent, but are often considered as sources of noise.
0
20
40 SFDR
PSD [dB]
60
80
100
120
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency (f/f )
s
14
Performance Metrics
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is used to characterize how well the signal can be
distinguished from the noise. SNR is defined as
P signal
-,
SNR = --------------- (1.27)
P noise
where P signal is the signal power and P noise is the noise power.
Signal-to-Noise-and-Distortion Ratio
If a large amount of distortion is present in the output, the signal quality is better
characterized with the signal-to-noise-and-distortion ratio (SNDR, in some litera-
ture abbreviated SINAD). SNDR is defined as
P signal
SNDR = ---------------
-, (1.28)
P nd
where P nd is the total power for the noise and the distortion.
SNDR 1.76- .
ENOB = ------------------------------- (1.30)
6.02
P signal
SFDR = ---------------
-, (1.31)
P ls
where P ls is the power of the largest spurious tone at the DAC output. The SFDR
is indicated in Fig. 1.9.
15
Introduction
20
PSD [dB]
40 MTPR
60
80
100
0 0.1 0.2 0.3 0.4 0.5
Normalized frequency (f/f )
s
In a single-tone test, the only relevant parameters are the amplitude and the fre-
quency of the test tone. In an MTPR test, however, the degrees of freedom are
higher. Besides the amplitude, the resulting MTPR is depending on which tone
that has zero amplitude, and also the mutual phase differences between the other
tones. Hence, it is easier to set up and interpret the result from a single-tone test.
Therefore, the single-tone performance metrics are often used, even if they give
insufficient information. In this work, multi-tone tests are used to some extent,
but not as much as single-tone tests.
16
Converter Architectures
where f 0 is the bandwidth of the signal. A data converter with f s just a small
fraction larger than 2 f 0 is commonly referred to as a Nyquist-rate converter
[9, 11], whereas a data converter with f s considerably larger than 2 f 0 is
referred to as an oversampled converter [9, 11]. The oversampling ratio (OSR) is
defined as
fs
OSR = --------
-. (1.34)
2f0
There are several reasons for using oversampling. If the number of bits in a con-
verter is large, the quantization noise is approximately white. Hence, the PSD of
the quantization noise is approximately constant, i.e.,
2 f
PSD Q( f ) ------ -----s . (1.35)
12 2
From (1.35), it is evident that the total noise power within the signal band
( f f 0 ) is decreased if f s is increased. Hence, an oversampled converter has
less quantization noise power within the signal band than a Nyquist-rate con-
verter with the same .
17
Introduction
Another reason for using oversampling is that it simplifies the design of the (ana-
log) anti-aliasing filters for ADCs and image-rejection filters for DACs. The
unfiltered output spectra for a Nyquist-rate DAC and a DAC with OSR = 2 are
shown in Fig. 1.11(a) and (b), respectively (the desired spectrum is plotted in
Fig. 1.2(a)). The spectral images that appear around multiples of f s are better
separated for the oversampled converter, since its sampling frequency is higher
than that of the Nyquist-rate DAC. Further, the output of the oversampled con-
verter is less distorted by the sinc weighting within the signal band, and the spec-
tral images are better attenuated by the sinc weighting. Hence, requirements on
the filters for attenuation of the spectral images is lower for the oversampled con-
verter than for the Nyquist-rate converter. The relaxed filter requirements a
allows for larger design margin and/or a reduced filter order compared with the
Nyquist-rate case.
I+ = l bl I l (1.36)
I = l bl I l = l I l l bl I l , (1.37)
I diff = I + I = 2 l bl I l l I l . (1.38)
There are also positive, negative, and differential output voltages, which are the
corresponding currents multiplied with the load resistance R L . In an ideal cur-
rent-steering DAC, each current I l is given by
I l = w l I unit , (1.39)
18
Converter Architectures
A
|Y(2f)|
0
8f0 6f0 4f0 2f0 0 2f
0
4f0 6f0 8f0
Frequency
(a)
A
|Y(2f)|
0
8f0 6f0 4f0 2f0 0 2f
0
4f0 6f0 8f0
Frequency
(b)
Figure 1.11 Output spectra from (a) Nyquist-rate DAC and (b) oversampled DAC.
where w l is the integer weight of the current source and I unit is the unit current.
If the digital control word represents the DAC input x , i.e.,
x = l bl wl , (1.40)
19
Introduction
VDD
Il1 Il Il+1
bl1 bl bl+1
I+ I
V+ V
RL RL
we have that
l bl I l = xI unit . (1.41)
wl = 2 l , (1.42)
20
Converter Architectures
for proper operation. This operational amplifier limits the speed of the circuit,
making the charge-redistribution DAC less suited for wideband applications than
the current-steering DAC. The charges in Fig. 1.13 are given by
Q l = V ref b l C l (1.44)
and
Q L = V out C L . (1.45)
The total charge, Q tot , on all capacitor plates connected to the negative input of
the operational amplifier is constant over time. Q tot is given by
Q tot = Q L + l Ql , (1.46)
Q tot C
V out = ---------
CL
- V ref l bl ------
CL
l
-. (1.47)
C l = w l C unit , (1.48)
where w l is the integer weight of the capacitor and C unit is the unit capacitance.
If the digital control word represents the input x as in (1.40), then
QL
CL
Vout
Ql1 Ql Ql+1
Cl1 Cl Cl+1
bl1 bl bl+1
Vref
21
Introduction
Q tot C unit
- V ref -----------
V out = --------- -x . (1.49)
CL Cl
It should be noted that the circuit diagram in Fig. 1.13 only illustrates the basic
principle behind charge-redistribution conversion. Since Q tot cannot be changed,
one must settle with the value that results from the fabrication of the circuit. This
value will be different for different circuits, and the offset voltage for the DAC
cannot be controlled. Therefore, in an actual implementation of a charge-redistri-
bution DAC, a more elaborate circuit structure than that in Fig. 1.13 must be used
where, e.g., part of the clock cycle is used for offset-voltage compensation [11].
and, hence,
N1
R L I ref
V out = --------------
2N 1
- bl 2 l . (1.51)
l=0
Hence, the R-2R ladder DAC in Fig. 1.14 is a binary-weighted DAC. A benefit of
this R-2R ladder DAC, compared with a binary-weighted current-steering DAC,
is that equal currents flow through all switches and, hence, it is easier to obtain
good mutual matching between the individual switches. Drawbacks of the R-2R
ladder architecture are that it requires high-precision linear resistors and that the
use of an operational amplifier may limit the speed of the circuit.
22
Converter Architectures
VDD
Iref Iref Iref Iref Iref
b0 b1 b3 bN2 bN1
IL RL
Vout
R R R
R 2R 2R 2R
encoder
Vref+
R
Vout
Vref
1.4.6 DACs
DACs utilizing modulation [20] are different from the previously presented
converter architectures in that oversampling is used in conjunction with prepro-
cessing of the input in order to allow the input to be represented internally with
23
Introduction
fewer bits. The quantization noise added by the extra quantization step is shaped
with a feedback filter so that most of its power appears outside of the signal band.
A general modulator is shown in Fig. 1.16(a). This system is nonlinear and,
consequently, difficult to analyze. The quantizer is often modeled with the addi-
tion of an error signal, e(n) , as shown in Fig. 1.16(b), in order to get a linear sys-
tem that is simpler to analyze. In the frequency domain, the output Y (z) can be
expressed in terms of the input X (z) and the quantization error E(z) as
STF(z) = 1 (1.53)
and
NTF(z) = 1 z 1 . (1.54)
The spectrum of the 8-bit input is shown in Fig. 1.16(c), and the corresponding 1-
bit output is shown in Fig. 1.16(d). The main benefit of using a modulator
with a 1-bit output is that the output can be reconstructed with a DAC having
only two quantization levels. Even if these quantization levels differ from those
intended by the designer due to process variations, the INL and DNL will be 0 for
all codes. Hence, the static linearity of the 1-bit DAC is perfect. Using a first-
order modulator with a 1-bit quantizer requires a high OSR that often cannot be
afforded in high-speed communication applications. In order to reduce the OSR,
the use of multi-bit quantizers and/or higher-order modulators are required.
24
CMOS Technology
(a) (b)
Modulator input Modulator output
0 0
PSD [dB/Hz]
PSD [dB/Hz]
50 50
(c) (d)
Figure 1.16 (a) General modulator and (b) modulator with quantizer modeled with an
added error signal. The spectra for the 8-bit input and the 1-bit output of a first-
order modulator (OSR = 128) are shown in (c) and (d), respectively.
polycrystalline silicon (poly), which is separated from the substrate with a thin
layer of silicon dioxide (oxide). Free electrons in the substrate can be attracted to
the region under the gate and form a conducting channel between the drain and
the source by applying a proper voltage at the gate. The principle of a PMOS
transistor is similar, but the type of doping used is opposite to that of the NMOS
transistor.
The DAC circuits in this work have all been implemented in CMOS technology.
A brief overview of the characteristics of CMOS transistors is given in this sec-
tion.
25
Introduction
A symbol for an NMOS transistor is shown in Fig. 1.17(a). It has four terminals;
gate (G), source (S), drain (D), and bulk (B). In all implementations presented in
this work, the bulk terminal is connected to ground for all NMOS transistors. In
that case, the symbol in Fig. 1.17(b), where the bulk terminal is omitted, can be
used instead. Similar symbols for PMOS transistors are shown in Fig. 1.17(c) and
(d), where the omitted bulk terminal in Fig. 1.17(d) implies that the bulk is con-
nected to the supply voltage ( V DD ).
D D
ID
G
G B VDS
VBS
VGS S S
(a) (b)
S
VSG S
VSB
G B VSD
G
ID
D
D
(c) (d)
Figure 1.17 Device symbols for (a) four-terminal NMOS transistor, (b) NMOS transistor
with the bulk connected to ground, (c) four-terminal PMOS transistor, and (d)
PMOS transistor with the bulk connected the supply voltage.
In the simple model, the transistors have three different regions of operation; the
cut-off region, the linear region, and the saturation region. The approximate cur-
rent-voltage relationships for NMOS and PMOS devices are listed in the follow-
ing sections. The model parameters, e.g., carrier mobility and body-effect
constants, for NMOS and PMOS transistor typically have different values. How-
ever, we use the same notation for the two transistor types in order to avoid the
use of additional indices.
NMOS Devices
An NMOS transistor operates in the cut-off region if
V GS < V T , (1.55)
where V T is the threshold voltage of the transistor. In the transistor model used
here,
26
CMOS Technology
ID = 0 (1.56)
in the cut-off region. In reality, a small subthreshold current flows in the device.
When V GS is increased such that
V GS V T , (1.57)
a channel of free electrons is formed under the gate and the transistor is conduct-
ing current.
In the linear operation region,
V DS 2
I D = 0 C ox ----- V eff V DS ----------- ,
W
(1.59)
L 2
where 0 is the electron mobility and C ox is the oxide capacitance per unit area.
W and L are the width and the length of the transistor, respectively.
The saturation region is characterized by the relationship
V DS V eff (1.60)
0 C ox W 2
- ----- V ( 1 + ( V DS V eff ) ) .
I D = --------------- (1.61)
2 L eff
is a parameter known as the channel-length modulation parameter and is
roughly proportional to 1 L . Due to the body effect, the threshold voltage of the
transistor is dependent on the bulk-to-source voltage according to
V T = V T, 0 + ( 2 F V BS 2 F ) , (1.62)
PMOS Devices
A PMOS transistor in the cut-off region is characterized by
27
Introduction
V SG < V T , (1.63)
ID = 0 . (1.64)
V SG V T . (1.65)
where V eff is the effective source-to-gate voltage. The current is modeled with
V SD 2
I D = 0 C ox ----- V eff V SD ----------
- ,
W
(1.67)
L 2
where 0 is the hole mobility, which is typically a factor three or so lower than
the electron mobility for an NMOS transistor.
The transistor operates in the saturation region when
V SD V eff , (1.68)
0 C ox W 2
- ----- V ( 1 + ( V SD V eff ) ) .
I D = --------------- (1.69)
2 L eff
The threshold voltage, which is negative, varies with the source-to-bulk voltage
according to
V T = V T, 0 ( 2 F V SB 2 F ) . (1.70)
28
CMOS Technology
I D
gm = , (1.71)
V GS Q
I D
g mbs = , (1.72)
V BS Q
and
I D
g ds = , (1.73)
V DS Q
where the index Q indicates that the partial derivatives are evaluated in the quies-
cent point. For both the linear region and the saturation region, we have
gm
g mbs = -------------------------------------
-. (1.74)
2 2 F V BS
In analog circuits, the transistors are usually biased to operate in the saturation
region, because the transconductance, g m , is higher and the output conductance,
g ds , is lower than in the linear region for the same V GS . In the saturation region,
we have
id
G D
vgs gmvgs gmbsvbs gds vds
S
(a)
S
vsg gmvsg gmsbvsb gds vsd
G D
id
(b)
Figure 1.18 Simple small-signal models for (a) NMOS and (b) PMOS transistors.
29
Introduction
W
g m 2 0 C ox ----- I D (1.75)
L
and
g ds I D . (1.76)
gm
g msb = -------------------------------------
-, (1.77)
2 2 F V SB
in both the linear region and the saturation region. Further, in the saturation
region, we have
W
g m 2 0 C ox ----- I D (1.78)
L
and
g ds I D . (1.79)
1.5.3 Parasitics
The transistor models discussed in Sec. 1.5.1 and Sec. 1.5.2 model the transistor
behavior for low signal frequencies. For higher frequencies, the transistor behav-
ior is also influenced by capacitive parasitics [11]. Simple small-signal models of
NMOS and PMOS transistors with parasitic capacitances included are shown in
Fig. 1.19(a) and (b), respectively. In Fig. 1.19, it is assumed that the bulk termi-
nals are connected to small-signal ground, i.e., constant voltages. The source-to-
bulk capacitance, C SB , and the drain-to-bulk capacitance, C DB , are depletion
capacitances in the reverse-biased p-n junctions between the source and the bulk
and the drain and the bulk, respectively. They also include the depletion capaci-
tance between the conducting channel and the bulk. In the saturation region, the
channel is pinched off at the drain side, and the channel-to-bulk capacitance is
entirely associated with the source-to-bulk capacitance [11]. The gate-to-source
capacitance, C GS , and the gate-to-drain capacitance, C GD , are due to the thin
oxide layer between the gate and the substrate. They consist of an overlap capac-
itance, caused by a small overlap between the gate and the diffused drain and
source areas, and of a capacitance between the gate and the channel. Due to that
the channel is pinched off in the saturation region, the gate-to-channel capaci-
tance is entirely associated with the gate-to-source capacitance.
30
CMOS Technology
CGD CDB
G D
CGS gmvgs gmbsvbs gds
S
CSB
(a)
CSB
S
CGS gmvsg gmsbvsb gds
G D
CGD CDB
(b)
Figure 1.19 Simple small-signal models for (a) NMOS and (b) PMOS transistors with para-
sitic capacitances included.
31
Introduction
order Taylor expansion) as indicated in Fig. 1.20(b). The global variations are,
therefore, also referred to in terms of parameter gradients or as linearly graded
errors.
(a)
(b)
Figure 1.20 (a) Two nominally identical rectangular devices and (b) illustration of circular
parameter variation over a wafer.
Let P denote the difference in the value of parameter P between the two
devices. According to [23], P can be modeled as a stochastic variable with
Gaussian distribution having zero expectation value and variance
A P2
(P) = -------- + S P2 D 2 ,
2 (1.80)
WL
where A P and S P are proportionality constants for parameter P . A further anal-
ysis in [23], using the simple square-law model for a MOS device in saturation,
yields that the difference in drain current between two transistors has a Gaussian
distribution and that
32
CMOS Technology
2(I D) 4 2(V T)
-+
2()
---------------
- = ---------------------------- ------------
-, (1.81)
ID 2 ( V GS V T ) 2
where
W
= 0 C ox ----- (1.82)
L
and 2() denotes the variance operator. Having well-matched drain currents is
important in order to obtain high accuracy in a current-steering DAC. Some gen-
eral guidelines for obtaining good matching can be extracted from (1.80) and
(1.81). For example, the local variations have less influence on the parameters for
transistors with large areas than for transistors with small areas, and the influence
of the global variations is decreased if the devices are placed closer together.
There is, of course, a trade-off, since increasing the device dimensions also
causes an increase in the minimum required distance between two devices. From
(1.81), it can be concluded that increasing the effective gate-to-source voltage
decreases the influence of variations in the threshold voltage.
In [24], it is argued that (1.80) is applied incorrectly to the threshold voltage in
the analysis in [23], and a mismatch model, based on the BSIM3 MOS model,
that better fits observed data is derived. However, the general guidelines for tran-
sistor matching that were observed from (1.80) and (1.81) are still valid with this
more accurate mismatch model.
Apart from device geometries and biasing, there are other factors that influence
the matching accuracy. For example, wire routing in low-level metal layers over
transistors having critical matching requirements should be avoided [25]. More-
over, it is important that the devices have the same geometrical boundary condi-
tions. Therefore, an array of transistors or capacitors is often surrounded by a
frame of unused dummy elements that ensures that the outer devices in the array
have the same surroundings as the inner devices.
33
Introduction
1
R out = ----------------------- . (1.83)
g ds, source
1 g m, casc
R out ----------------------- ------------------
-. (1.84)
g ds, source g ds, casc
Usually, g m g ds for a transistor biased in the saturation region. Hence, the out-
put resistance for the current source using a cascode transistor is much higher
than for a single-transistor current source. For higher frequencies, the magnitude
of the output impedance is limited by capacitive parasitics. The output imped-
ance of a current source is approximately
Z out = ---------
1 - + sC 1 ,
out (1.85)
R out
where C out is the effective capacitance to ground associated with the output node
of the current source. For the current source in Fig. 1.21(a), C out is approxi-
mately a parallel connection of C GD and C DB for transistor Msource. For the cur-
rent source in Fig. 1.21(b), C out is approximately a parallel connection of C GD
and C DB for transistor Mcasc, the parasitics in transistor Msource are suppressed
due to the use of a cascode transistor. If the widths of Msource and Mcasc are
approximately the same, then C out is approximately the same for both types of
current source. Hence, their output impedances are approximately the same for
high frequencies.
34
CMOS Technology
Vbias Msource
Vbias Msource
Vcasc Mcasc
Iout
Iout
(a) (b)
Figure 1.21 PMOS current source implemented (a) with a single transistor and (b) with a
cascode transistor.
The Switch
A differential current switch can, e.g., be implemented with two PMOS transis-
tors, as depicted in Fig. 1.22(a). If both transistors are simultaneously cut off,
charge is accumulated at the output node of the current source. This results in
severe glitches in the transient response of the DAC when one of the transistors in
the switch starts to conduct. Therefore, when the state of the switch is changed, it
is important to have a short moment when both transistors are conducting in
order to avoid charge accumulation [26]. This is obtained with the nonoverlap-
ping control signals shown in Fig. 1.22(b). If NMOS transistors are used in the
switch, the control signals should instead be overlapping in order to avoid having
both transistors simultaneously off.
Q+
Q
Iin
high
Voltage
Q+ Q
I+ I
low
Time
(a) (b)
Figure 1.22 (a) Differential switch implemented with two PMOS transistors and (b) proper
control signals for the switch in (a).
35
Introduction
1.6.1 Chapter 2
Behavioral-level modeling and simulation of current-steering DACs is presented
in Chapter 2. In order to interpret presented simulation results correctly, it is
important to know how the results have been evaluated. Therefore, the methods
used in this thesis for evaluation of static errors are outlined in Sec. 2.1.
One limiting factor for the static linearity of a current-steering DAC is mismatch
between current sources. In Sec. 2.2, behavioral-level modeling of matching
errors is discussed. Modeling of random matching errors, which is used in later
parts of the thesis for evaluation of different techniques, is presented in
Sec. 2.2.2. This type of model is well known and has been used previously by
others. In Sec. 2.2.3, modeling of linearly graded matching errors is discussed.
The authors contribution to this part is a mathematical analysis of this type of
error.
Another factor that limits the linearity, both static and dynamic, is the finite out-
put impedance in the current sources which is discussed in Sec. 2.3. This is a well
known problem. The authors contribution to the field is the development of two
different behavioral-level models presented in Sec. 2.3.2.
Glitches present in the DAC output are yet another factor that degrades the DAC
linearity discussed in Chapter 2. One source of glitches is asymmetry in the set-
tling behavior when switching on and off a current source. A model of this spe-
cific glitch source has been developed by the author as a generalization of a
model presented previously by others. The developed model is presented in
Sec. 2.4 together with extensive mathematical analyses. All work presented in
Sec. 2.4 is original work by the author.
1.6.2 Chapter 3
The code used for representing the digital control word in a current-steering DAC
has a large influence on the circuit performance. Different types of codes and
their respective properties are discussed in Chapter 3. First, the well known
binary-weighted and segmented DAC architectures are presented in Sec. 3.1 and
36
Outline of the Thesis
Sec. 3.2, respectively. Then, the novel decomposed DAC architecture, which has
been developed by the author together with Prof. Mark Vesterbacka is presented
in Sec. 3.3. This is followed by an extension of the decomposed architecture,
denoted the partially decomposed architecture, proposed by the author which is
presented in Sec. 3.4, and a short discussion on miscellaneous other codes given
in Sec. 3.5.
The behavioral-level DAC models of random matching errors and glitches pre-
sented in Chapter 2 are utilized to compare the different types of architectures
with respect to their impact on the circuit performance in Sec. 3.6. All work pre-
sented in Sec. 3.6 is original work by the author.
In order for an architecture to be of practical interest, it must be possible to
implement at a reasonable hardware cost, e.g., in terms of circuit area and power
consumption. In Sec. 3.7, means for implementing the digital encoders required
in the segmented and decomposed DAC architectures are discussed. The inten-
tion with this section is to show that the hardware overheads for implementing
these encoders are not unreasonably large but rather quite small.
1.6.3 Chapter 4
In Chapter 4, different techniques for improving the DAC linearity are presented.
A family of techniques for reducing the distortion due to mismatch known as
dynamic element matching (DEM) is presented in Sec. 4.1. Presentations of
well-known DEM techniques in Sec. 4.1.1 - Sec. 4.1.3, are followed by a presen-
tation of a DEM technique for the decomposed DAC architecture proposed by the
author and Prof. Mark Vesterbacka in Sec. 4.1.4.
A well-known technique for reducing the influence of graded parameter varia-
tions over the chip area denoted distributed biasing is presented in Sec. 4.2. This
technique is utilized in two of the DAC implementations presented in Chapter 5.
An oversampling technique based on modulation developed by the author is
presented in Sec. 4.3. The technique utilizes a model of the DAC nonlinearity in
a feedback loop for spectral shaping of the resulting distortion. In Sec. 4.3.2, the
technique is used for suppressing the influence of output impedance related
errors utilizing one of the models presented in Sec. 2.3.2. The utilization of the
technique for enhancing the yield of binary-weighted DACs with respect to non-
linearity errors caused by mismatch is presented in Sec. 4.3.3. All the work pre-
sented in Sec. 4.3 is original work by the author.
37
Introduction
1.6.4 Chapter 5
The DAC chips developed in this work used for investigating different techniques
and ideas are presented in Chapter 5. Overall descriptions of design strategies
and measurement setups used are presented in Sec. 5.1, followed by presenta-
tions of the different implementations given in chronological order.
The first chip developed in this work is a 14-bit DAC utilizing 5-bit segmentation
and is presented in Sec. 5.2. The chip was designed in corporation with M.Sc.
Niklas U Andersson and Ph.D. J Jacob Wikner, but a major part of the design
work for this circuit was performed by the author. The circuit has been utilized
for measurements on the technique for spectral shaping of nonlinearity errors
presented in Sec. 4.3.2.
The second chip, presented in Sec. 5.3, is a 14-bit DAC that was developed for
evaluation of dynamic element matching techniques. Included in this section is a
comparison between measurement and simulation results. A majority of the
design and simulations were performed by M.Sc. Niklas U Andersson. The
authors contribution to the work includes design of miscellaneous digital build-
ing blocks and development of models used in the simulations.
The third chip, presented in Sec. 5.4, is a dual 14-bit DAC implemented with a
doubly segmented architecture. The chip utilizes distributed biasing discussed in
Sec. 4.2 for suppression of graded parameter variations over the chip area. The
work performed on this chip was evenly distributed between the author and
M.Sc. Niklas U Andersson and was assisted by Ph.D. J Jacob Wikner.
The fourth chip, which was designed by the author and is presented in Sec. 5.5, is
a 12-bit configurable DAC used for comparison between the decomposed archi-
tecture, proposed in Sec. 3.4, with the well-known segmented and binary-
weighted architectures. A result of the design work is a design methodology for
efficient layout generation based on parameterized cells. This methodology is
also overviewed in Sec. 5.5.
1.7 Publications
Publications related to the work presented in this thesis authored or coauthored
by the author are listed in this section. The publications are listed in chronologi-
cal order for each category. Publications upon which the thesis is based are
marked with an asterisk (*) before the number in the list below, whereas remain-
ing publications cover related work not included in the thesis.
38
Publications
39
Introduction
40
Abbreviations
1.7.3 Theses
* 21 O. Andersson, Mismatch Modeling and Design of CMOS Current-Steering
Digital-to-Analog Converters, Master Thesis, LiTH-ISY-EX-3026,
Linkping, Sweden, 1999.
* 22 K.O. Andersson, Studies on Performance Limitations in CMOS DACs,
Linkping studies in science and technology, Thesis No. 976, Linkping,
Nov. 2002, ISBN 91-7373-452-7.
1.7.4 Patents
23 K.O. Andersson, Improved current-steering D/A conversion, Swedish
patent SE-0000731, 2001.
* 24 K.O. Andersson and J.J. Wikner, Digital-to-analog converter having error
correction, Swedish patent SE-0201272, 2003.
25 K.O. Andersson, Current-steering DAC, pending Swedish patent.
1.8 Abbreviations
The abbreviations used in the thesis are listed below.
ADC Analog-to-digital converter
ADSL Asymmetric digital subscriber line
AFE Analog front end
CMOS Complementary metal-oxide-semiconductor
CO Central office
CPE Customer premises equipment
DAC Digital-to-analog converter
DCVS Differential cascode voltage switch
41
Introduction
42
Abbreviations
43
Introduction
44
2 Modeling of Current-
Steering DACs
Transistor-level simulations of complex circuits using accurate transistor models
require long simulation times. For example, an N -bit current-steering DAC con-
tains 2 N 1 unit current sources, a large number of switches, circuitry for
encoding the input to the corresponding control word and for generation of
proper control signals, etc. For N in the order of 12 to 14, it may take several
days merely to simulate the circuits response to a ramp input going through all
possible input values. Hence, a transistor-level model of a DAC used in a system
simulation is likely to be a severe bottleneck limiting the overall system simula-
tion speed. Moreover, investigations of stochastic parameter variations using,
e.g., Monte Carlo analyses require multiple simulation runs with different param-
eter values, making the use of models on transistor level unsuitable.
The reasons above motivate the need for behavioral-level models with reasonably
short simulation times. Behavioral-level models can also be used to find the
requirements on different building blocks on high abstraction levels, supporting
the use of efficient top-down design methodologies [28].
Models of different nonideal properties in current-steering DACs that have been
used and developed in this work are presented in this chapter. Evaluation of per-
formance metrics in the presence of static errors are discussed in Sec. 2.1. Mod-
eling of the influence of matching errors in current sources is presented in
Sec. 2.2, and the influence of finite output impedance in the current sources is
discussed in Sec. 2.3. Sec. 2.4 is devoted to behavioral-level modeling of glitches
due to asymmetry in the settling behavior when switching on and off a current
source.
45
Modeling of Current-Steering DACs
where K is the nominal gain and y offset is the nominal offset. In this section, we
discuss and motivate the approach used in this work for evaluation of perfor-
mance metrics for static errors. For the calculation of the SNDR, it is required
that the total power of noise and distortion, P nd is calculated. For an input
sequence x(n) , n = 0, 1, , n max , P nd is given by
n max
1
P nd = ---------------------
n max + 1 [ y(x(n)) ynom(x(n)) ]2 . (2.2)
n=0
If the input value x has the probability p(x) to occur, we may express P nd as
2N 1
P nd = p(x) [ y(x) y nom(x) ] 2 . (2.3)
x=0
In, e.g., an ADSL modem, the signal is transferred to the copper wire via a trans-
former that removes the dc component of the signal. Hence, we are not interested
in the dc term of the error y y nom . If the DAC is subject to a pure gain error
(i.e., a deviation from the desired K ), the error is a linear function of the input
and cannot easily be distinguished from the nominal output signal in, e.g., mea-
surements with a spectrum analyzer. Therefore, we choose the values of K and
y offset that minimizes P nd . A consequence of this is that we allow different
nominal characteristics for different input sequences.
An endpoint definition of the nominal characteristics
46
Modeling of Matching Errors
2N 1
1 -
P nd = ---------------
2N 1 K 2 INL 2(x) . (2.5)
x=0
wk = 2 k (2.6)
are considered in this section. The models discussed here are applied to other
DAC architectures in later chapters.
The mathematical notation used for the modeling of matching errors in this work
is introduced in Sec. 2.2.1. As discussed in Sec. 1.5.4, sources of matching errors
in CMOS transistors is usually divided into two main groups; short-distance vari-
ations and long-distance variations. Modeling of the former type is discussed in
Sec. 2.2.2, whereas the influence of the latter type is modeled in Sec. 2.2.3.
47
Modeling of Current-Steering DACs
2.2.1 Notation
On a behavioral level, matching errors in the transistors constituting the current
sources can be modeled with additional error current sources connected in paral-
lel with the nominal current sources. This is illustrated for a unit current source in
Fig. 2.1(a). The output current is given by
where m is an index that uniquely identifies the unit current source, I unit is the
nominal unit current, and m is the error current associated with the unit current
source.
A similar model for a weighted current source with weight w l is shown in
Fig. 2.1(b). A current source with weight w l is usually implemented with w l unit
current sources connected in parallel. Assume that the indices associated with
these unit current sources constitute a set A l . Then,
I l = w l I unit +
m Al
m , (2.8)
where the first term is the nominal output current and the second term is the error
current l .
Iunit dm wlIunit Dl
Iunit, m Il
(a) (b)
Figure 2.1 Models of (a) a unit current source and (b) a weighted current source subject to
matching errors.
m N(0, ) . (2.9)
48
Modeling of Matching Errors
l =
mA
m , (2.10)
l
l N ( 0, w l ) . (2.11)
Moreover, the errors l are mutually uncorrelated since the sets A l are disjoint.
Let b lx denote the individual bits of the control word for a given input x . The
DNL errors are given by
K I unit (2.13)
l ( blx blx 1 )l
DNL(x) = -------------------------------------------- . (2.14)
I unit
1
Var(DNL(x)) = ----------
2
I unit l
( b lx b lx 1 ) 2 Var( l) =
2 2
= ----------
2
I unit
l
b x b x 1 w = ----------S
l l l
I 2
unit
( x) , (2.15)
where
49
Modeling of Current-Steering DACs
is the total number of switched unit current sources in the transition from x 1 to
x at the DAC input. S(x) is only dependent on how the digital input is encoded to
form the control word. Hence, S(x) can be used as a high-level performance met-
ric to compare different encoding strategies; a small S(x) results in a small prob-
ability of a large DNL(x) , whereas a larger S(x) results in a larger probability of
a large DNL(x) . S(x) is plotted for a 12-bit binary-weighted DAC in Fig. 2.2.
The large peak at the middle code transition typically results in large DNL errors,
making the binary-weighted DAC architecture unsuitable for obtaining good
static linearity.
2047
1023
511
1 2048 4095
x
Several analyses on how random matching errors influence the INL of a DAC
have been presented in the literature [30, 31, 32, 33]. An endpoint definition of
the nominal characteristics (see (1.23)) is used in all the analyses presented in
[30, 31, 32, 33]. The DAC yield was defined in [30, 31, 32] as the relative num-
ber of DACs having
50
Modeling of Matching Errors
where the latter DAC clearly has a higher associated average power of noise and
distortion (calculated with (2.5)) than the former.
The approach favored in this work is to determine the yield in terms of the
SNDR. As an example, we consider a Monte Carlo type analysis of a 12-bit
binary-weighted DAC. The matching errors are characterized by the relative stan-
dard deviation
- = 10 % ,
--------- (2.20)
I unit
and simulations are performed for 10 4 different stochastic outcomes. The input
x(n) consists of clipped and quantized values of observations from uncorrelated
stochastic variables with Gaussian distribution having expectation value
( 2 12 1 ) 2 and standard deviation 464, yielding an approximate clipping prob-
ability of 10 5 . The length of the test signal is set to 2 14 samples. P nd is evalu-
ated in accordance with the discussion in Sec. 2.1, and the signal power is
calculated with
1-
P signal = ------- [y
2 14 n nom
(x(n)) y nom(x) ] 2 , (2.21)
where x denotes the average value of the input x(n) . A histogram of the resulting
SNDR values is shown in Fig. 2.3. We let SNDR req denote the required SNDR,
and define the yield as the relative number of DACs having SNDR SNDR req .
The yield resulting from the simulations is plotted as a function of SNDR req in
Fig. 2.3(b). Plots similar to that shown in Fig. 2.3(b) are used in Chapter 4 for
illustration of how the use of different techniques for error compensation influ-
ence the DAC performance.
51
Modeling of Current-Steering DACs
500
0
35 40 45 50 55 60 65
SNDR
(a)
60
50
40
30
20
10
0
35 40 45 50 55 60 65
SNDRreq
(b)
Figure 2.3 Results from the Monte Carlo type analysis of the 12-bit binary-weighted DAC.
A histogram of the obtained SNDR values are plotted in (a), and the yield is
plotted versus the required SNDR in (b).
the output current from the unit current source whose center coordinate is
( X , Y ) . In accordance with the discussion on long-distance parameter variations
in Sec. 1.5.4, we make a first-order approximation of the unit currents yielding
52
Modeling of Matching Errors
( X, Y ) = k X X + k Y Y . (2.23)
One approach for assigning unit current sources to the different bits in a binary-
weighted DAC is illustrated for the 6-bit case in Fig. 2.4(b). This approach results
in simple routing of wires for connecting the unit current sources in parallel, but
is known to have poor properties for suppressing linearly graded matching errors.
Here, we use this approach to illustrate the influence of linearly graded matching
errors on the DAC linearity. The assignment of unit current sources is character-
ized by two parameters; the number of bits, N , and the number of weighted cur-
rent sources fitted into the bottom row of the array, M . In the example in
Fig. 2.4(b), N = 6 and M = 3 . The current source in the lower right corner of
Fig. 2.4(b) is an unused dummy element.
Y Y
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
X 4 4 4 4 4 4 4 4 X
4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3
2 2 2 2 1 1 0
(a) (b)
Figure 2.4 (a) Array of unit current sources and (b) unit current source assignment for a 6-
bit binary-weighted DAC.
According to analyses presented in [27] and [34], the matching errors l can be
approximated with
kY l
------ ( 2 2 l + N M ) for l = 0, , M 1
l = 2 , (2.24)
kY
-(3 2
-----
2l M 2 l + N M ) for l = M , , N 1
2
where the influence of parameter k X has been neglected since it only influences
the errors for the M LSBs which are typically much smaller than for the more
significant bits.
Assuming that the individual bits, b l(n) , of the input are uncorrelated, the power
of the error signal caused by mismatch can be approximated with [27, 34]
53
Modeling of Current-Steering DACs
2 4N - 2
P error = ----------------------- k . (2.25)
210 2 2M Y
For a sinusoidal signal, acos(t) , the signal power is given by
a2 .
P signal = ----- (2.26)
2
Normalizing the DAC output by setting I unit = 1 yields that the amplitude of a
full-scale sinusoidal signal is
2N 1
a = ---------------- 2 N 1 , (2.27)
2
where the approximation is valid if N is large, i.e., 2 N 1 . For this signal,
2N
P signal = 2
---------- . (2.28)
8
Further, the power of the quantization noise is given by
1- .
P Q = ----- (2.29)
12
Assuming that the error caused by mismatch and the quantization error are
uncorrelated, we can express SNDR as
P signal
SNDR = --------------------------- 105 2 2 ( N + M ) - .
= ------------------------------------------------------- (2.30)
P error + P Q 4 2 4N k Y2 + 70 2 2M
For large k Y , the second term in the denominator can be neglected and
54
Modeling of Matching Errors
SNDR vs. |k |
Y
90
simulated
80
calculated
70
SNDR [dB]
60
50
40
30
20
10 7 6 5 4 3 2
10 10 10 10 10 10
|kY|
(a)
SFDR vs. |kY|
120
110 simulated
100 calculated
90
SFDR [dB]
80
70
60
50
40
30
20
10 7 6 5 4 3 2
10 10 10 10 10 10
|kY|
(b)
Figure 2.5 Simulated and calculated values of (a) SNDR and (b) SFDR plotted as functions
of k Y .
ancy (approximately 3 dB for k Y > 10 5 ) is due to that the assumption that the
individual bits are uncorrelated is incorrect for a sinusoidal input. An extended
analysis given in [34], that takes the correlation between b N 1(n) and b N 2(n)
into account, yields a maximum deviation of approximately 0.1 dB. Simulated
and calculated values of SFDR are plotted as functions of k Y in Fig. 2.5(b). A
good agreement between calculated and simulated values is observed also for the
55
Modeling of Current-Steering DACs
SFDR. For small k Y , the simulated SFDR is limited by the noise floor given by
the quantization noise, which explains the discrepancy between the two curves
for small k Y .
As mentioned in the beginning of this section, the simple approach for assigning
unit current sources to the different bits illustrated in Fig. 2.4(b) has poor proper-
ties for suppressing linearly graded matching errors. Several strategies of assign-
ing unit current sources developed for suppressing the influence of linearly
graded matching errors appear in the literature (e.g., [35, 36, 37, 38, 39, 40]).
The principle behind all of these strategies is to spread out the unit current
sources that constitute a weighted current source over the array. The improved
performance resulting from these methods comes to the cost of increased wire-
routing complexity. A simple modification of the original approach illustrated in
Fig. 2.4(b) is illustrated in Fig. 2.6(a). For the modified approach, half of the unit
current sources have been moved to the bottom of the array, which results only in
a slight increase of wire-routing complexity. The influence on the DAC perfor-
mance is illustrated in Fig. 2.6(b), where simulated values of SNDR for the origi-
nal and modified approaches are plotted as functions of k Y . The input signal
used is a full-scale sinusoid, and the parameter values are N = 14 and M = 7 .
For large values of k Y , the modified approach results in approximately 11 dB
higher SNDR than the original approach.
56
Modeling of Finite Output Impedance
Y
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3 X
2 2 2 2 1 1 0
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
(a)
SNDR vs. |kY|
90
original
80
modified
70
SNDR [dB]
60
50
40
30
20
10 7 6 5 4 3 2
10 10 10 10 10 10
|kY|
(b)
Figure 2.6 (a) Illustration of a modified approach for assigning unit current sources and (b)
SNDR comparison between the original and the modified approaches.
VDD
xIunit Runit/x
Vout(x)
RL
Figure 2.7 Equivalent model of current-steering DAC with finite output resistance in the
current sources.
57
Modeling of Current-Steering DACs
V DD
V out(x) = I unit + -----------
x
---------------------------- R L , (2.33)
R unit RL
1 + ----------- x
R unit
State-Space Model
The modeling of the current source and the switch is considered first. In previous
presentations of the model [27, 43], the current source and the switch were con-
sidered separately. The switch was modeled with a resistance, which is inaccurate
if the switch transistor is operated in the saturation region. Therefore, a different
approach where the switch and the current source are modeled together is used
here.
The model of the combined current source and switch is shown in Fig. 2.8(a).
There are three important parameters for this model; the resistances R l and R s, l
and the capacitance C l . We consider two different types of CMOS implementa-
tions of the current source and switch, which are shown in Fig. 2.8(b) and (c).
The implementation shown in Fig. 2.8(b) is a PMOS current source with an
NMOS switch, whereas a PMOS current source with a PMOS switch is shown in
Fig. 2.8(b). In the following, we discuss the mapping of these two types of circuit
elements to the linearized model in Fig. 2.8(a). There are, of course, also two
types of circuit elements with NMOS current sources. These are not discussed
58
Modeling of Finite Output Impedance
here, but the derivation of model parameters is similar. This is also true for cur-
rent sources utilizing cascode transistors, which are also discarded from the dis-
cussion given here.
Il
Rl Cl
Rs, l
bl
(a)
VDD VDD
(b) (c)
Figure 2.8 (a) Linearized model of a current source and a switch, (b) PMOS current source
with NMOS switch, and (c) PMOS current source with PMOS switch.
First, we consider the case in Fig. 2.8(b) where a PMOS current source is used
together with an NMOS switch. One of the two transistors in the switch is con-
ducting, and the other is off. It is desirable to have a high output resistance in the
current source transistor. Therefore, it is common to use a transistor length much
higher than the minimum transistor length available in the process. This results in
a small W L for the current source transistor, which in turn yields a relatively
large V SG . The consequence of this is that in order to bias the current source
transistor in the saturation region, which is required to get a high output resis-
tance, the V SD of that transistor must also be relatively large. A simple analysis
using the transistor models given in Sec. 1.5.1 yields that the conducting switch
transistor is in the linear region if the V SD of the current source transistor is
larger than the V T of the switch transistor, which is likely to be the case. In this
case, the mapping to the linearized model is straightforward. R s, l is the on resis-
59
Modeling of Current-Steering DACs
tance of the switch transistor, R l is the output resistance of the current source
transistor, and C l is the total parasitic capacitance at the drain node of the current
source transistor. C l is mainly a sum of C DB and C GD for the three transistors.
The mapping of the circuit elements in Fig. 2.8(c) to the linearized model is not
as straightforward as for the previous case. A simple analysis using the transistor
models given in Sec. 1.5.1 yields that the switch transistor is in the saturation
region as long as the output voltage, i.e., the drain potential of the switch transis-
tor, is smaller than the threshold voltage of the switch. Since the current source
transistor requires a large V SD , the switch transistor has a large V SB if the
body is tied to V DD . Therefore, it also has a large V T . Hence, it is likely that the
switch transistor is in the saturation region. Actually, it is desirable to operate the
switch transistor in the saturation region since it then acts as a cascode transistor
for the current source. The small signal equivalent of the circuit element in
Fig. 2.8(c) is shown in Fig. 2.9 and is used to calculate the output impedance. C P
is the total parasitic capacitance at the drain node of the current source, mainly a
sum of C GD and C DB of the current source transistor and C GS and C SB of the
switch transistors. In Fig. 2.9, g m, sw and g ds, sw are small signal parameters for
the conducting switch transistor, i.e., either M sw+ or M sw , whereas g ds, cs is
the output conductance for transistor M cs .
gds, cs CP
vx
vxgm, sw gds, sw
output terminal to
which the conducting
i
switch transistor
v
is connected
Figure 2.9 Small-signal equivalent of a PMOS current source with PMOS switch.
g ds, sw
v x = --------------------------------------------------------------------------
-v . (2.35)
g m, sw + g ds, sw + g ds, cs + sC P
60
Modeling of Finite Output Impedance
g ds, sw ( g ds, cs + sC P )
i = --------------------------------------------------------------------------
-v , (2.36)
g m, sw + g ds, sw + g ds, cs + sC P
g m, sw + g ds, sw + g ds, cs sC P
----------------------------------------------------------
- + ------------------------------ -
v g ds, sw g ds, cs g ds, sw g ds, cs
Z out = -- = ------------------------------------------------------------------------------------------------- . (2.37)
i sC P
1 + ------------- -
g ds, cs
R l ( sC l ) R s, l + R l + sC l R l R s, l
Z out = R s, l + -------------------------------
- = ---------------------------------------------------
-. (2.38)
R + 1 ( sC ) l l 1 + sC R l l
In order to properly map the circuit element in Fig. 2.8(c) to the linearized model
in Fig. 2.8(a), the two expressions for Z out given by (2.37) and (2.38) must be
equal. Hence,
C l R l R s, l C P ( g ds, sw g ds, cs ) 1 -
R s, l = --------------------- = ----------------------------------------------
- = --------------- (2.39)
C l Rl C P g ds, cs g ds, sw
and
g m, sw + g ds, sw + g ds, cs
R s, l + R l = ----------------------------------------------------------
- =
g ds, sw g ds, cs
g m, sw + g ds, sw 1 -.
= -------------------------------------
- + --------------- (2.40)
g ds, sw g ds, cs g ds, sw
g m, sw + g ds, sw
R l = -------------------------------------
-. (2.41)
g ds, sw g ds, cs
Another identity that can be derived from the equality of (2.37) and (2.38) is
g m, sw + g ds, sw CP
C l R l = C l -------------------------------------
- = -------------
-, (2.42)
g ds, sw g ds, cs g ds, cs
where the first equality is derived using (2.41). Solving for C l in (2.42) yields
61
Modeling of Current-Steering DACs
g ds, sw
C l = C P -------------------------------------
-. (2.43)
g m, sw +g ds, sw
The output wire and load are modeled with a resistor in parallel with a capacitor.
The load capacitance includes the parasitic capacitance at the output nodes of the
switch transistors as well as the parasitic capacitance in the wires, pads, and
printed circuit board (PCB). A more accurate model is obtained if the output
wires are instead modeled with distributed elements or as transmission lines [44].
However, the goal here is to obtain a simple model with few circuit nodes in
order to have short simulation times. Therefore, the lumped element model is
used for the output wires and load. For the same reason, parasitic inductances
have been ignored. A schematic view of the complete model is shown in
Fig. 2.10.
Il1 Il Il+1
V+ V
RL CL CL RL
Figure 2.10 Schematic view of the DAC model including capacitive parasitics.
We now consider one of the output terminals during one update period, i.e.,
between two consecutive update instants. For simplicity, we consider the time
interval 0 t < T . The output terminal has K current sources connected to it. For
simple notation, we let these current sources be indexed l = 1, 2, , K . The sit-
uation is illustrated in Fig. 2.11.
The system in Fig. 2.11 is described by the differential equations
62
Modeling of Finite Output Impedance
I1 IK
V1 VK
R1 C1 RK CK
Rs, 1 Rs, K
Io, 1 Io, K
V
I
RL CL
V l(t)
- C l V l(t) ,
I o, l(t) = I l ---------- (2.44)
R l t
V l(t) V (t)
-,
I o, l(t) = -------------------------- (2.45)
R s, l
I (t) = V (t ) ,
--------- (2.46)
RL
and
K
I (t) =
I o, l(t) C t V (t) . (2.47)
l=1
V (t) = -----
1
I V l(t) ---- 1 + V (t) ---------
1- + --------- 1
. (2.48)
t l Cl l R l R s, l R s, l
63
Modeling of Current-Steering DACs
A1 A2
A = , (2.53)
A3 a
where
-----
1 1 - ------
1
R - + ----------
R C1
0 0
1 s, 1
0 -----
1 1 - ------
1
A1 = R - + ----------
R C2
0
, (2.54)
2 s, 2
0 0 1 1 - -------
------- + -----------
1-
R K R CK
s, K
1 1 1 T
A 2 = ------------------, ------------------, , -------------------- , (2.55)
R s, 1 C 1 R s, 2 C 2 R s, K C K
1 1 1
A 3 = ------------------, ------------------, , -------------------- , (2.56)
R s, 1 C L R s, 2 C L R s, K C L
and
K
1
a = ------
RL
-+ --------- 1-
1 ------
R s, l C L
. (2.57)
l=1
64
Modeling of Finite Output Impedance
I1 I2 IK T
B = AV (0) + ------ , ------, , -------
-, 0 (2.58)
C1 C2 CK
and u(t) is a unit step used to apply the initial conditions given by B at time
t = 0 . We define the output vector
65
Modeling of Current-Steering DACs
Parameter Value
I l , [ A ] 1.22 2 l
R l , [ G ] 1.00 2 l
C l , [ fF ] 0.50 2 l
100 , l = 0, , 7
R s, l , [ ]
100 2 7 l , l = 8, , 13
RL , [ ] 50
C L , [ pF ] 50
Table 2.1 Model parameter values used in the simulations.
Low-Complexity Model
The fundamental source of nonlinear behavior in the state-space model is the
connection of a signal dependent network of parasitic components to the DAC
output. In this section, we briefly discuss a model structure with lower computa-
tional complexity than the state-space model. A more thorough description of
this low-complexity model is given in [27]. A possible use for a model with low
computational complexity is that it can be implemented on chip at an acceptable
cost and be used for error compensation [48]. An example where the low-com-
plexity model is used for error compensation is given in Sec. 4.3.2.
In its present form, the low-complexity model operates in discrete time and esti-
mates the DAC settling error, i.e., the deviation from the desired output level at
the end of the update period. As discussed in the presentation of the state-space
model, only considering the output at the end of the update period may result in
inaccurate results. Further model development is required in order to take this
into account.
We let y x(n) and y(n) denote the desired (i.e., settled) and actual outputs for a
given input x(n) , respectively. The output sequence y(n) can be expressed as
66
Modeling of Finite Output Impedance
20
PSD [dB/Hz]
40
60
80
100
120
0 1 2 3 4 5
Frequency [Hz] 6
x 10
(a)
SFDR vs. fsignal
86
84
82
SFDR [dB]
80
78
76
74 5 6 7
10 10 10
Frequency [Hz]
(b)
Figure 2.12 (a) Example of an output spectrum from the state-space model and (b) simu-
lated SFDR as a function of the signal frequency.
where y x(n) y(n 1) is the size of the desired step at the output and e rel(n) is
an error factor which we refer to as the relative step error. In the first approach to
establish a low-complexity model, we assume that e rel(n) is a function only of
the present input value x(n) . We use the abbreviated notation
67
Modeling of Current-Steering DACs
This assumption is based on that the matrix A given by (2.53), which in some
sense represents a time constant of the system, is a function only of the present
input x(n) .
We normalize the DAC output such that
z1
Figure 2.13 Block diagram of the low-complexity model in its simplest form.
By assuming that e rel is a function of only the present input, the influence of the
initial values of the internal node voltages (i.e., V 1, , V K ) of the circuit in
Fig. 2.11 is neglected. These initial values are roughly determined by the previ-
ous input x(n 1) . It was shown in [27] that the agreement between the low-
complexity model and the state-space model is improved if it is assumed that e rel
is also a function of the previous input, i.e.,
68
Modeling of Glitches due to Rise/Fall Asymmetry
x(n)
1erel(n) y(n)
LUT
z1
z1
The glitch properties of a DAC are often specified by the area of the glitch at the
worst-case code transition [3, 51, 52], which is often the middle code transition.
However, specifying the worst-case glitch area does not provide enough informa-
tion on how the glitches affect the DAC performance, e.g., in the frequency
domain which is important in many communication applications [10]. Therefore,
behavioral-level models that describe how glitches caused by different types of
error sources affect the DAC performance are important. However, such behav-
ioral-level models are rarely presented in the literature. In [49], a statistical anal-
ysis of glitches caused by static timing mismatch between individual bits in the
DAC control word is presented. Different settling behavior when switching on
and off current sources, i.e., asymmetry in the rise/fall behavior, also causes
glitches. This type of glitch was modeled in [51], where the current wave forms
when switching on and off current sources were described by damped sinusoids
having different amplitudes and frequencies depending on the type of switching
(on or off). In this section, the glitch model presented in [51] is generalized in the
sense that the current wave forms when switching on and off current sources are
described by arbitrary functions. This generalization enables powerful analyses,
both in the time domain and in the frequency domain. The work presented in this
section is original work of the author and appears in [53].
First, an analysis of a 1-bit DAC is presented in order to illustrate the basic con-
cept. The analysis of the 1-bit DAC is followed by an analysis of a general multi-
bit DAC. Further, the developed model is analyzed in the frequency domain and a
simple method for estimating the resulting frequency-domain behavior is devel-
oped. The method can be utilized by DAC designers to derive requirements on
the current source settling behavior to fulfill a given frequency-domain specifica-
tion through behavioral-level simulations. This approach can potentially be used
to relax circuit requirements compared with requirements based on a worst-case
analysis.
69
Modeling of Current-Steering DACs
Prerequisites for the modeling are presented in Sec. 2.4.1. The actual modeling is
presented in Sec. 2.4.2. Some examples on utilization of the developed model
and methods are given in Sec. 2.4.3. A short discussion on how the use of a dif-
ferential output is modeled is given in Sec. 2.4.4.
2.4.1 Preliminaries
Due to different nonideal properties of DAC components, it is in practice not pos-
sible to implement a block that exactly performs the PAM operation given by
(1.3). As discussed in Sec. 1.2.3, nonlinearity errors are usually of special impor-
tance since they are more difficult to compensate for than linear errors. We let
y nom(t) denote the nominal DAC output obtained from the PAM operation
y nom(t) = K nom x(n) p(t nT ) , (2.65)
n =
where K nom is the nominal DAC gain and p(t) is the nominal pulse. Further, let
y(t) denote the actual output. The error in the DAC output is the difference
between y(t) and y nom(t) . In the modeling presented in this section, we do only
consider the contribution due to rise/fall asymmetry in the current sources. Fol-
lowing the terminology used in [51], we denote the resulting error a glitch.
Hence, for this particular scenario, we define the glitch signal, y g(t) , as
If other error sources are included, e.g., mismatch in current sources or finite out-
put impedance, (2.65) may be used to define a general error signal rather than a
glitch signal.
In order for the definition in (2.65) to make sense, we also have to provide defini-
tions for the nominal gain and the nominal pulse. Choosing the proper nominal
pulse shape is not trivial. If the initial intention is to design a DAC with a certain
pulse shape (e.g., a square pulse), an intuitive approach is to use that pulse as the
nominal pulse. In [51], a pulse shape expressed with a tanh function was chosen
as the nominal pulse. In this work, we do not use a specific pulse shape. Instead,
the following approach is used. A set F of reconstruction filters is formed, con-
taining all filters that can be implemented at an acceptable cost. What an accept-
able cost is is up to the circuit designer to decide and is not defined here, but can,
e.g., be defined in terms of filter order, etc. Further, a set P of allowed pulse wave
forms is formed. The set P contains all pulses that in combination with a recon-
struction filter in F performs signal reconstruction that only deviates from ideal
reconstruction within acceptable bounds. What these acceptable bounds are is
70
Modeling of Glitches due to Rise/Fall Asymmetry
also a choice for the circuit designer and is not defined here, but can, e.g., be
expressed in terms of rejection of spectral images and maximum attenuation
within the Nyquist band. In order to decide which element in P to choose as
p(t) , we define the signal energy, E(z(t), ) , of the continuous-time signal z(t)
on the time interval = [ t 0, t 1 ] as
Using this definition of the signal energy, the SNDR due to glitches is given by
E(y nom(t), )
SNDR = ------------------------------
-, (2.68)
E(y g(t), )
provided that E(y nom(t), ) and E(y g(t), ) are both finite, which is the case, e.g.,
if the signals only adopt finite values and have finite extension in time. If the
interval is infinite, the energy may also be infinite and the SNDR has to be
defined in terms of power instead of energy as in Sec. 1.3.2. For cases where the
SNDR is a relevant metric of the DAC performance, the glitch energy E(y g(t), )
is a relevant metric for the glitch size. The term glitch energy is sometimes used
for the area of the glitch, even if this is not strictly correct [3]. Here, the term
glitch energy is used for the signal energy of the glitch signal.
We restrict the problem to only include contributions to the nonlinear distortion
in the DAC output. This is accomplished by choosing the nominal gain, K nom ,
and the nominal pulse, p(t) , from an allowed set of gain factors (e.g., allowed
ranges of unit currents or reference voltages, depending on the type of DAC that
is used) and the set P , respectively, such that the average glitch energy over all
time intervals of the type [ nT , ( n + 1 )T ) is minimized. This can be seen as a
least-squares adaptation of the nominal DAC transfer characteristics.
71
Modeling of Current-Steering DACs
I A = wI unit (2.69)
and
IB = 0 , (2.70)
where wI unit is the settled output current from the current source. At time
t = 0 , a switching is initiated, and at time t = T , the system has settled such
that
IA = 0 (2.71)
and
I B = wI unit . (2.72)
For the time interval ( 0, T ) , we allow the two currents I A and I B to have arbi-
trary waveforms with the only boundary condition being that the currents have
reached their final values before t = T . For example, the current waveforms
may look like the ones in Fig. 2.15(b), in which case I A = I off and I B = I on .
In general, the total output current from the current source is not constant during
the switching, as indicated in Fig. 2.15(b). Further, we assume that the CS cell is
symmetric in the sense that if the current is instead switched from the negative to
the positive output terminal, then I A = I on and I B = I off . Also, if no switching
takes place, the currents are assumed to remain constant during the whole inter-
val. The system analyzed is assumed to be time invariant and memoryless, i.e.,
for every n such that a switching is initiated at time nT , the current waveforms
are the same during the interval ( nT , ( n + 1 )T ) regardless of the history of the
control signal and the value of n .
We continue with the analysis of the single-ended output at the positive output
terminal, letting I out(t) denote the output current at that terminal. The result for
the negative output terminal is obtained by simply replacing b(n) with 1 b(n) .
We define two functions of time, s on(t) and s off(t) , with the properties
72
Modeling of Glitches due to Rise/Fall Asymmetry
CS cell
IA IB
I+ I
load
(a)
Ion
Ioff
Ion + Ioff
wI
unit
Current
0 T
t
(b)
Figure 2.15 (a) 1-bit current-steering DAC and (b) output current waveforms during switch-
ing.
s on(t) = s off(t) = 0 for t 0 , (2.73)
1 for t T
and
If s on(t) and s off(t) are equal, the DAC performs a PAM operation with the pulse
shape
73
Modeling of Current-Steering DACs
Hence, the DAC is linear and no glitches occur. In this work, s on(t) and s off(t)
are assumed to be unequal. In [51], the current waveforms during switching on
and off a current source were modeled with damped sinusoids with different
amplitudes and frequencies depending on the type of switching (on or off). The
model developed in [51] was compared with transistor-level models and a good
agreement was observed. The use of unequal s on(t) and s off(t) as a source of
glitches is merely a generalization of using damped sinusoids with different
amplitudes and frequencies and is motivated with the good agreement with tran-
sistor-level models observed in [51].
We define a function s(t) from which the nominal pulse shape is to be derived.
s(t) is equal to s on(t) and s off(t) for t ( 0, T ) and defines the nominal current
waveforms according to
and
Choosing the proper nominal pulse shape is equivalent to choosing the proper
s(t) . For a 1-bit DAC, the determination of s(t) is straightforward, since half of
the switching events involves switching in one direction, and the other half
switching in the opposite directions. The average glitch energy is given by
T
P
E g = -----s ( I on(t) I on, nom(t) ) 2 + ( I off(t) I off, nom(t) ) 2 dt =
2
0
T
P s w 2 I unit 2
- [ ( s on(t) s(t) ) 2 + ( s off(t) s(t) ) 2 ] dt =
= -----------------------
2
0
T
P s w 2 I unit 2
=
2
-----------------------
- f (t) dt , (2.79)
0
Where P s is the probability for a switching event to occur. Since the integrand
f (t) 0 for every t , E g is minimized by minimizing f (t) for every t . It is
readily shown that this is accomplished by choosing
74
Modeling of Glitches due to Rise/Fall Asymmetry
s on(t) + s off(t)
s(t) = ---------------------------------
-. (2.80)
2
The resulting glitches are
s on(t) s off(t)
I on, g(t) = I on(t) I on, nom(t) = wI unit --------------------------------- (2.81)
2
and
s on(t) s off(t)
I off, g(t) = I off(t) I off, nom(t) = wI unit ---------------------------------, (2.82)
2
respectively. Hence, every time a switching event occurs, the same glitch
I g(t) = I on, g(t) = I off, g(t) is present at the DAC output, regardless of the type
of switching (on or off).
The nominal DAC output for an input sequence b(n) is given by
I out, nom(t) = wI unit b(n) p(t nT ) , (2.83)
n =
where
I out, g(t) = wI unit ( b(n) b(n 1) ) p g(t nT ) (2.86)
n =
s on(t) s off(t)
p g(t) = --------------------------------- . (2.87)
2
The expression ( b(n) b(n 1) ) appearing in (2.86) is used to detect whether
or not a switching event occurs at t = nT .
75
Modeling of Current-Steering DACs
I+ I
load
Figure 2.16 N -bit DAC topology with arbitrary encoding of the control word.
and
or
and
depending on the type of switching. The functions s on(t) and s off(t) have the
properties given in (2.73). Further, we assume that all CS cells have identical
s on(t) and s off(t) .
76
Modeling of Glitches due to Rise/Fall Asymmetry
As in the analysis of the 1-bit DAC, we analyze the behavior of the positive out-
put terminal, letting I out(t) denote the output current at that terminal. For an
input sequence x(n) , we can express the corresponding output current in the
interval ( n 1 )T t nT as
I out(t) =
= I unit x(n 1) +
lL
w l s on(t nT )
lL
w l s off(t nT ) ,
(2.92)
on off
where
and
I out, nom(t) = I unit x(n 1) +
l L
wl
lL
w l s(t nT ) ,
(2.95)
on off
where s(t) is a function that describes the nominal switching behavior of the
DAC. The choice of s(t) is not as straightforward as for the 1-bit DAC and
involves assumptions on the statistics of the input sequence.
To simplify the notation, we consider the case n = 0 and, hence, the time inter-
val ( 0, T ) . The glitch current is
As for the 1-bit DAC, s(t) should be chosen to minimize the average glitch
energy per switching event. Let a denote the event characterized by
x( 1) = x a1 and x(0) = x 0a . Further, let A denote the (finite) set of all possible
a . To each a , there are associated sets L on, a and L off, a , as defined in (2.93) and
(2.94). The average glitch energy is given by
77
Modeling of Current-Steering DACs
T
Eg =
aA
P(a) ( I out
a 2
, g (t) ) dt , (2.97)
0
where
a
I out, g (t) =
= I unit
l L
w l ( s on(t) s(t) )
lL
w l ( s off(t) s(t) )
(2.98)
on, a off, a
and P(a) is the probability for the event a to occur. If a is such that
a
x( 1) = x(0) , then I out, g (t) = 0 , so events of this type give zero contributions
to E g , regardless of the choice of s(t) . We combine the events for which
x( 1) x(0) into pairs of events ( a, b ) for which
x 0a = x b1 (2.99)
and
x a1 = x 0b . (2.100)
The pairs ( a, b ) and ( b, a ) are considered identical, and the set of all pairs is
denoted AB . We can now rewrite (2.97) as
T
Eg =
( a, b ) AB
[ P(a) ( I out
a 2 2
, g (t) ) + P(b) ( I out (t) ) ] dt
b =
0
=
( a, b ) AB
E g( a, b ) . (2.101)
In order to derive the proper s(t) , we have to make an assumption on the statisti-
cal properties of the input sequence. The assumption is that
78
Modeling of Glitches due to Rise/Fall Asymmetry
a =
n on
lL
wl (2.103)
on, a
and
a =
n off
l L off, a
wl , (2.104)
and
b = na
n off (2.106)
on
E g( a, b )
e g( a, b ) = ---------------------
2 P(a)
=
I unit
T
= [ ( nona on(t) noff
a (t) ) 2 + ( n a (t) n a (t) ) 2 ] dt
off off on on off =
0
T
= f (t) dt , (2.107)
0
where
and
s on(t) + s off(t)
s(t) = ---------------------------------
-. (2.110)
2
79
Modeling of Current-Steering DACs
Since this choice of s(t) minimizes each term in (2.101) separately, it also mini-
mizes E g . Hence, assuming that P(a) = P(b) for every ( a, b ) AB results in
the same s(t) as for the 1-bit DAC and, therefore, the same nominal pulse p(t) .
Inserting (2.110) into (2.96) yields the glitch current
s on(t) s off(t)
I out, g(t) = w l --------------------------------- I unit
2
lL L on off
where
s on(t) s off(t)
p g(t) = --------------------------------- (2.112)
2
and
n tot =
lL L
wl . (2.113)
on off
The number n tot is the total number of unit sources that are subject to a switch-
ing operation. For an input sequence x(n) , the nominal and actual DAC outputs
can be expressed as
I out, nom(t) = I unit x(n) p(t nT ) (2.114)
n =
and
respectively, where
80
Modeling of Glitches due to Rise/Fall Asymmetry
is the total number of switched unit current sources during the transition from
x(n 1) to x(n) at the DAC input and is dependent on the encoding strategy
(e.g., degree of segmentation). In order to have small glitches, it is desirable to
have small values of g(n) . Hence, g(n) can be used as a high-level performance
metric to compare different encoding strategies, just as the metric S(x) defined in
Sec. 2.2.2 as the total number of switched unit current sources in the transition
from x 1 to x . We introduce the notation
S ( x ) = G ( x , x 1) . (2.118)
G(x(n 1), x(n)) and S(x) are used in Chapter 3 for high-level comparison of
different DAC architectures.
where P() and P g() are the Fourier transforms of p(t) and p g(t) , respec-
tively, and
X (e jT ) = x(n)e jnT (2.121)
n =
and
G(e jT ) = g(n)e jnT (2.122)
n =
81
Modeling of Current-Steering DACs
are the (discrete-time) Fourier transforms of x(n) and g(n) , respectively. The first
term in (2.120), X (e jT )P() , is the spectrum of the nominal output and the sec-
ond term, G(e jT )P g() , is the spectrum of the glitch signal.
From this point, we restrict the analysis to the Nyquist band ( T , T ) .
In accordance with the commonly used concept of input-referred noise, we intro-
duce the concept of input-referred glitches. The input referred glitch spectrum is
defined as
P g()
G ir(e jT ) = -------------
- G(e jT ) . (2.123)
P()
It is readily verified that within the Nyquist band,
i.e., the input-referred glitch is a signal in the discrete-time input domain that
applied to the input of the nominal PAM block results in the same spectrum as the
glitch signal within the Nyquist band.
In order to make the concept of input-referred glitches practically useful, the
analysis is continued with a few approximations. If p(t) is close to a square pulse
then
-) .
P() T sinc(----------- (2.125)
2 f s
P g(0)
G ir(e jT ) ---------------
- G(e jT ) . (2.128)
P(0)
82
Modeling of Glitches due to Rise/Fall Asymmetry
P g(0)
g ir(n) = ---------------
- g(n) (2.129)
P(0)
and compare this with the squared absolute value of the DFT of the input
sequence in order to obtain SNR values for different frequency bands, etc. Note
that g ir(n) is not the inverse transform of G ir(e jT ) but only an approximation.
A more accurate approach is to form a sampled version of the output
where T 1 T in order to reduce aliasing effects [3], and analyze the DFT of
z(m) . This approach has a higher computational cost than the previous, since it
requires T T 1 more samples. Both methods are used and compared in
Sec. 2.4.3.
83
Modeling of Current-Steering DACs
I out, g(t) =
= K
x(n) p g, linear(t nT ) + g(n) p g(t nT )
(2.131)
n = n =
where the first part is a linear function of the input sequence that does not con-
tribute with any nonlinear distortion and can be compensated for using a linear
filter.
An important piece of information that can be extracted from the model is that
the magnitude and the area of the glitch associated with the transition from
x(n 1) to x(n) is proportional to the total number of switched unit current
sources g(n) . This has been stated previously by others (see, e.g., [50, 52]), but
only motivated with intuitive argumentation.
In many cases, the glitch specification of a DAC is given in terms of the worst-
case glitch area [3, 51, 52]. Worst-case analyses have a tendency of resulting in
unnecessarily hard circuit requirements. Applying the simple frequency-domain
analysis on signals that are typical for a given application allows the designer to
instead use behavioral-level simulations in discrete time to obtain requirements
on P g(0) P(0) . These requirements can be used as design targets on lower
abstraction levels in the design of current sources, switches, and switch drivers.
Note that P(0) can be calculated with
P(0) = p(t) dt (2.132)
In the derivation for the multi-bit case, it is stated that if the input is constant dur-
ing two consecutive samples, no switching and, hence, no glitches occur. This
assumes a static mapping between the digital input and the control word. In a
DAC utilizing dynamic element matching (DEM), which is discussed in Sec. 4.1,
redundancy in the control word is exploited by random selection of different rep-
resentations of the same input value in order to reduce nonlinear distortion aris-
ing from current source mismatch. In a DEM DAC, switching can occur even if
84
Modeling of Glitches due to Rise/Fall Asymmetry
the input is constant. Even if the properties of a DEM DAC do not conform with
the assumptions used in the derivation, the results given in (2.114)-(2.116) are
valid also for a DEM DAC.
The rise/fall asymmetry is not the only existing source of glitches. Due to mis-
match in parasitic load capacitances and driving capabilities between different
signal paths in, e.g., the clock distribution network of the digital part, there will
be a static timing mismatch between different bits in the control word which is
another source of glitches. This type of error has a stochastic component, i.e., it
varies from chip to chip, and is strongly layout dependent. A statistical analysis
of timing errors caused by mismatch in DACs is given in [49]. Glitches may also
be caused by cross talk from the digital parts of the DAC. These glitches are also
strongly layout dependent and have to be addressed at the layout level. Note that
properties such as the signal dependency for glitches caused by other sources
might differ considerably from the corresponding properties of the derived
model. In order to obtain an accurate general glitch model, it is of course required
that models of all relevant glitch sources are combined into one model. This is,
however, beyond the scope of the present work.
2.4.3 Examples
A few examples on application of the developed model are given in this section.
An analytical examination of the properties of a fully thermometer-coded DAC is
presented, followed by simulation examples on one binary-weighted and one
thermometer-coded DAC.
85
Modeling of Current-Steering DACs
resulting in
Hence, even-order distortion appears in the output. The spurious tone with largest
amplitude is the second harmonic (corresponding to the term with k = 1 in
(2.138)). The SFDR is in linear scale approximately given by
x a2
= ----------------------------
3 P(0) 2
SFDR lin = ------------------------------------------ (2.139)
P g(0) 4x a T
---------------
2 4T P g(0)
P(0) 3 - ----------------
-
3 P(0) ) 20log () .
SFDR log = 20log 10(----------------------- (2.140)
4T P g(0) 10
Hence, the SFDR decreases 20 dB/dec with increasing signal frequency. Since
P(0) is roughly proportional to T (see, e.g., (2.125)), the factor P(0) T that
appears in (2.139) and (2.140) is approximately constant. Therefore, T has little
or no influence on the SFDR, even though it may seem from (2.139) and (2.140)
that T has a large influence on the SFDR.
Simulation Examples
Some examples of simulations performed in MATLAB, intended to illustrate the
application of the developed model, are presented in this section. The functions
s on(t) and s off(t) used in the simulations are plotted together with the resulting
s(t) in Fig. 2.17(a). In the transition region, s on(t) and s off(t) are described by
one period of a sine wave superpositioned onto a straight line. The resulting
pulses p(t) and p g(t) are plotted in Fig. 2.17(b).
Two different 8-bit DACs are considered, one binary-weighted DAC and one
fully thermometer-coded DAC. A sinusoidal input sequence
28 1
x(n) = -------------- ( 1 + sin(2 f N n) ) (2.141)
2
86
Modeling of Glitches due to Rise/Fall Asymmetry
s (t)
on
soff(t)
s(t)
1
0 T
t
(a)
p(t)
p (t)
g
I
unit
0 T
t
(b)
Figure 2.17 Waveforms used in the simulations. The functions s on(t) , s off(t) , and s(t) are
plotted in (a), whereas the resulting pulses p(t) and p g(t) are plotted in (b).
87
Modeling of Current-Steering DACs
actual output
nominal output
300
Iout/Iunit
200
100
0
10 12 14 16 18 20
t/T
(a)
actual output
nominal output
300
Iout/Iunit
200
100
0
10 12 14 16 18 20
t/T
(b)
Figure 2.18 Transient responses for 8-bit DACs. The output from a binary-weighted DAC is
plotted in (a) and the output from a thermometer-coded DAC is plotted in (b).
where g ir(n) is defined in (2.129). For the waveforms used in the simulations,
P g(0)
- 0.030 .
--------------- (2.143)
P(0)
88
Modeling of Glitches due to Rise/Fall Asymmetry
200
150
Iout, g/Iunit
100
50
0
10 12 14 16 18 20
t/T
(a)
200
150
Iout, g/Iunit
100
50
0
10 12 14 16 18 20
t/T
(b)
Figure 2.19 Glitch currents for 8-bit DACs. The glitches for a binary-weighted DAC is plot-
ted in (a) and the glitches for a thermometer-coded DAC is plotted in (b)
The magnitude of the DFT of x g(n) for the binary-weighted DAC is plotted in dB
scale in Fig. 2.20(a). The corresponding plot for the thermometer-coded DAC is
shown in Fig. 2.20(b). The signal spectra shown in Fig. 2.20 have been normal-
ized with respect to the power of the fundamental tone.
Simulations were also performed using the more accurate method utilizing
z(m) = y(mT 1) with T 1 = T 16 . The resulting spectra are almost identical to
those plotted in Fig. 2.20. This indicates that the simple method of calculating the
89
Modeling of Current-Steering DACs
PSD [dB] 20
40
60
80
(a)
20
PSD [dB]
40
60
80
(b)
Figure 2.20 Magnitude of the DFT of x g(n) for (a) a binary-weighted 8-bit DAC and (b) a
thermometer-coded 8-bit DAC.
DFT of x g(n) gives a good estimation of the amplitudes of the spurious tones, at
least for the waveforms used in these examples, even though the corresponding
phases might be incorrectly estimated.
The SFDR values for the thermometer-coded DAC estimated from the simula-
tions are plotted as a function of f N in Fig. 2.21, together with the theoretical
values given by (2.140). Good agreement is observed between the different meth-
ods.
90
Modeling of Glitches due to Rise/Fall Asymmetry
45
40
35
2 1
10 10
Normalized frequency (f/fs)
Figure 2.21 SFDR as a function of f N for the thermometer-coded 8-bit DAC estimated with
different methods.
91
Modeling of Current-Steering DACs
2N 1
I out, diff(t) = 2I unit
x(n) p(t nT ) 2I unit ---------------- ,
2
(2.144)
n =
where
s on(t) + s off(t)
s(t) = ---------------------------------
-. (2.146)
2
Hence, the differential output may be described with a PAM operation using the
same pulse as for the nominal output in the single-ended case.
92
3 Digital Encoding in
Current-Steering DACs
From the modeling of matching errors and glitches presented in Sec. 2.2 and
Sec. 2.4, respectively, we realize that the performance of a current-steering DAC
is dependent on the sizes of the weights and the mapping of the digital input to
the control word. In this chapter, we give an overview of current-steering DAC
architectures that utilize different sets of weights and ways of mapping the digital
input to the control word. Some of these architectures are well established and
some have been developed in this work.
The well-established binary-weighted and segmented DAC architectures are
overviewed in Sec. 3.1 and Sec. 3.2, respectively. The decomposed and partially
decomposed DAC architectures, that have been developed in this work, are pre-
sented in Sec. 3.3 and Sec. 3.4, respectively. Miscellaneous code types are briefly
overviewed in Sec. 3.5. The architectures discussed in Sec. 3.1-Sec. 3.4 are com-
pared in Sec. 3.6 using some of the behavioral-level models from Chapter 2.
In Chapter 2, we introduced the number of switched unit current sources in the
transition from x 1 to x and in a general transition from x(n 1) to x(n) as
high-level metrics for comparing different architectures in terms of static linear-
ity and glitch properties. These metrics are frequently used in this chapter to
investigate the properties of the different architectures. In order to make fair com-
parisons, one must take into account the hardware costs associated with the
codes. It is difficult to define a general measure of hardware cost. Here, we use
the number of bits in the control word as a rough measure of hardware cost. The
number of bits in the control word is equal to the required number of switches
and control wires and, therefore, it is related to the circuit area. However, the cir-
cuit area is usually dominated by the area required for the current sources. Fur-
93
Digital Encoding in Current-Steering DACs
ther, it is not a good design strategy to use the same size for the transistors in all
switches in the DAC. The transistors conducting currents with large weights
should be made wider than transistors conducting currents with small weights.
Therefore, the number of bits in the control word may be inaccurate as a measure
of hardware cost, but it is nevertheless used here due to the lack of a better met-
ric.
wl = 2 l . (3.1)
In the digital blocks, it is common to represent the data in a closely related code
such as twos-complement code. Therefore, no or very simple encoding is
required to form the control word in a binary-weighted DAC, resulting in a low
hardware complexity. On the other hand, the performance of a binary-weighted
DAC is usually poor due to the large number of switched unit current sources.
The traditional example is to consider the middle code transition, from the code
where b N 1 = 0 and all other b l = 1 to the code where b N 1 = 1 and all
other b l = 0 . For this transition, all unit current sources in the circuit are subject
to switching, resulting in a large glitch and a large DNL error, as discussed in
Chapter 2. This is illustrated in Fig. 3.1(a), where S(x) , i.e., the number of
switched unit current sources in the transition from x 1 to x , is plotted for a 6-
bit binary-weighted DAC. The large peak in the middle of the plot corresponds to
the middle code transition. G(x(n), x(n 1)) , i.e., the number of switched unit
current sources in the transition from x(n 1) to x(n) , for the 6-bit binary-
weighted DAC is visualized in Fig. 3.1(b). The values of x(n) and x(n 1) are
given on the x and y axes, respectively. The different values of G(x(n), x(n 1))
are represented with different shades of gray, as indicated on the scale in the right
part of Fig. 3.1(b). It is observed that for points in the upper left and lower right
quadrants, corresponding to transitions for which b N 1 changes, the values of
G(x(n), x(n 1)) are large even if the corresponding values of x(n) x(n 1)
are small. Hence, there are many code transitions for which a small change at the
input results in large glitches due to that most of the unit current sources are
switching. The one-dimensional plot in Fig. 3.1 may mislead the observer to
believe that there is only one such code transition.
94
Segmented DACs
x(n1)
S(x)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(a) (b)
Figure 3.1 (a) S(x) and (b) G(x(n), x(n 1)) for a 6-bit binary-weighted DAC.
l
wl = 2 for the binary-weighted LSBs . (3.2)
2 N K for the thermometer-coded MSBs
NB seg(N , K ) = N K + 2 K 1 . (3.3)
95
Digital Encoding in Current-Steering DACs
and (d), where S(x) and G(x(n), x(n 1)) are plotted for a 3-bit segmented 6-bit
DAC. The plots for a 6-bit segmented, or fully thermometer-coded, 6-bit DAC
are shown in Fig. 3.2(e) and (f). It is readily deduced that for any type of code
used in a current-steering DAC,
96
Decomposed DACs
x(n1)
S(x)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(a) (b)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(c) (d)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(e) (f)
Figure 3.2 S(x) and G(x(n), x(n 1)) for segmented 6-bit DACs. The plots for 2-bit seg-
mentation are shown in (a) and (b), the plots for 3-bit segmentation are shown in
(c) and (d), and the plots for 6-bit segmentation are shown in (e) and (f).
97
Digital Encoding in Current-Steering DACs
Table 3.1, the column in the middle represents the 1-bit word, whereas the three
columns to the right represents the first ( N 1 )-bit word and the three columns
to the left represents the second ( N 1 )-bit word.
NB dec(N , M ) = 2 M ( N M + 1 ) 1 (3.6)
98
Decomposed DACs
N3
1-layer 1
N2 encoder N3
1-layer 1
encoder N2 N3
1-layer 1
N1 encoder N3
N 1-layer 1
encoder N1 N3
1-layer 1
N2 encoder N3
1-layer 1
encoder N2 N3
1-layer 1
encoder N3
99
Digital Encoding in Current-Steering DACs
3. The largest bit weights for M -layer decomposition and ( M + 1 )-bit segmenta-
tion are equal. A consequence of this is that the largest values of S(x) are also
equal in the two cases.
The number of bits in the control word is included as a metric for hardware com-
plexity in the performance comparisons presented in Sec. 3.6.
Consider once again the middle code transition. In a binary-weighted DAC,
2 N 1 (i.e., all) unit current sources are switched. This value is reduced to
2 N 1 1 using 2-bit segmentation. For a 1-layer decomposed DAC, the only
thing that happens in this code transition is that the bit in the 1-bit word is
changed from 0 to 1. Hence, only one unit current source is switched. This is
shown in Fig. 3.4(a), where S(x) is plotted for a 1-layer decomposed 6-bit DAC.
The large peak that is present at the middle code transition for the 2-bit seg-
mented DAC (Fig. 3.2(a)) is removed using 1-layer decomposition. For the
remaining values of x , the values of S(x) are equal for the two architectures. The
difference between the two architectures is more obvious if a general code transi-
tion from x(n 1) to x(n) is considered. Examining Fig. 3.2(b) and (f) and
Fig. 3.4(c), we find that for the upper left and lower right quadrants, the values of
G(x(n), x(n 1)) for the 1-layer decomposed DAC is equal to those of the fully
thermometer-coded DAC, whereas the values for the 2-bit segmented DAC are
higher. Hence, for approximately half of the code transitions, the 1-layer decom-
posed DAC is optimal in terms of the number of switched unit current sources.
For the two other quadrants, the values of G(x(n), x(n 1)) for the 1-layer
decomposed and 2-bit segmented DACs are equal.
The values of S(x) and G(x(n), x(n 1)) for a 2-layer decomposed 6-bit DAC are
plotted in Fig. 3.4(c) and (d), respectively. The maximum value of S(x) is the
same as for a 3-bit segmented DAC, but it appears for fewer values of x . In terms
of G(x(n), x(n 1)) , the number of transitions for which the 2-layer decomposed
DAC is equivalent to a fully thermometer-coded DAC is higher than the corre-
sponding number for a 1-layer decomposed DAC. S(x) and G(x(n), x(n 1)) for
a 3-layer decomposed 6-bit DAC are plotted in Fig. 3.4(e) and (f), respectively, in
order to further illustrate how the number of switched unit current sources is
affected by an increasing number of layers.
100
Partially Decomposed DACs
x(n1)
S(x)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(a) (b)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(c) (d)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(e) (f)
Figure 3.4 S(x) and G(x(n), x(n 1)) for decomposed 6-bit DACs. The plots for 1-layer
decomposition are shown in (a) and (b), the plots for 2-layer decomposition are
shown in (c) and (d), and the plots for 3-layer decomposition are shown in (e)
and (f).
101
Digital Encoding in Current-Steering DACs
of that an M -layer decomposed DAC has more bits in the control word than an
( M + 1 )-bit segmented DAC. This is illustrated in Fig. 3.5, where
NB seg(6, M + 1) and NB dec(6, M ) given by (3.3) and (3.6), respectively, are
plotted as functions of M .
1
NB
10
(M+1)bit segmented
Mlayer decomposed
0
10
0 1 2 3 4 5
M
Figure 3.5 Number of bits in the control words for 6-bit DACs utilizing M -layer decompo-
sition and ( M + 1 )-bit segmentation.
102
Other Codes
N2 N3 N4
1-layer 1 1-layer 1 1-layer 1
N1 encoder N2 encoder N3 encoder N4
N 1-layer 1
encoder N1 N2 N3 N3
1-layer 1 1-layer 1 1-layer 1
encoder N2 encoder N3 encoder N3
The number of bits in the control word for an N -bit DAC utilizing M -layer par-
tial decomposition is
103
Digital Encoding in Current-Steering DACs
x(n1)
S(x)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(a) (b)
31 31 31
15
7
0 0
1 32 63 0 31 63
x x(n)
(c) (d)
Figure 3.7 S(x) and G(x(n), x(n 1)) for 6-bit DACs utilizing a special case of partial
decomposition. The plots for 3-layer partial decomposition are shown in (a) and
(b), and the plots for 4-layer partial decomposition are shown in (c) and (d).
2 14 1- = 8191.5 .
x dc = ---------------- (3.8)
2
104
Comparison of Codes
Test signals x 1(n) and x 2(n) are both sinusoidal signals with normalized fre-
quency
f signal
f N = --------------- 0.142 . (3.9)
fs
2 14 1-
x 1, ac = ---------------- (3.10)
2
and
2 14 1- ,
x 2, ac = ---------------- (3.11)
16
respectively. Test signals x 3(n) and x 4(n) are both (clipped) white Gaussian sig-
nals with standard deviations
3 1800 (3.12)
and
4 220 , (3.13)
respectively.
105
Digital Encoding in Current-Steering DACs
between the best and the worst values. The differences between the architectures
are even smaller when considering the SFDR plots shown in Fig. 3.9(a) and (b)
where all values are between 70 dB and 71 dB.
68 68
SNDR [dB]
SNDR [dB]
67 67
segmented segmented
66 66 decomposed
decomposed
partially decomposed partially decomposed
65 65 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.8 SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .
71 71
SFDR [dB]
SFDR [dB]
70.5 70.5
70 70 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.9 SFDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .
106
Comparison of Codes
Results from simulations using test signal x 2(n) are shown in Fig. 3.10 and
Fig. 3.11. Here, clear improvements are present when the degrees of segmenta-
tion and decomposition are increased. SNDR is plotted as a function of M and
the number of bits in the control word in Fig. 3.10(a) and (b), respectively. There
is a 9 dB span between the best and the worst values plotted. Fig. 3.10 shows an
advantage for the decomposed and partially decomposed architectures when the
parameter M is used in the comparison. Specifically, an 8 dB improvement over
the binary-weighted architecture is obtained by simply applying 1-layer decom-
position. If instead the number of bits in the control word is the important param-
eter, the three architectures yield similar performance. Similar relations between
the architectures are observed in the SFDR plots shown in Fig. 3.11(a) and (b).
58 58
56 56
SNDR [dB]
SNDR [dB]
54 54
52 52
segmented segmented
decomposed decomposed
50 partially decomposed
50 partially decomposed
48 48 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.10 SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .
We now consider the results for the Gaussian distributed test signals. SNDR
using test signal x 3(n) is plotted as a function of M and the number of bits in the
control word in Fig. 3.12(a) and (b), respectively. Also for this signal, there are
clearly visible performance improvements when the degrees of segmentation and
decomposition are increased. Plotting SNDR vs. M indicates a small advantage
for the decomposed and partially decomposed architectures, whereas plotting
SNDR vs. the number of bits in the control word indicates a small advantage for
the segmented architecture.
For the test signals used so far, the three architectures have similar behavior when
the number of bits in the control word is considered as the relevant measure of
hardware complexity. For some cases, the partially decomposed and decomposed
107
Digital Encoding in Current-Steering DACs
62 62
60 60
SFDR [dB]
SFDR [dB]
58 58
56 56
segmented segmented
decomposed decomposed
54 partially decomposed
54 partially decomposed
52 52 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.11 SFDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .
60 60
SNDR [dB]
SNDR [dB]
58 58
56 56
segmented segmented
54 decomposed 54 decomposed
partially decomposed partially decomposed
52 52 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.12 SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 3(n) .
architectures are slightly better than the segmented. For other cases, the relation
is the opposite. For signal x 4(n) , which has a Gaussian distribution with small
standard deviation, the situation is different. SNDR is plotted as a function of M
and the number of bits in the control word in Fig. 3.13(a) and (b), respectively. A
benefit of the decomposed and partially decomposed architecture is that by
merely applying 1-layer decomposition, the SNDR improvement over the binary-
108
Comparison of Codes
50 50
SNDR [dB]
SNDR [dB]
45 45
segmented segmented
40 40 decomposed
decomposed
partially decomposed partially decomposed
35 35 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.13 SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 4(n) .
The simulation results for the four test signals can be summarized as follows.
Making pairwise comparisons between the different architectures using the
parameter M yields higher performance for the decomposed and partially
decomposed architectures than for the segmented architecture. Using the number
of bits as the relevant measure of hardware complexity yields similar perfor-
mance for all architectures for the first three test signals. For test signal x 4(n) ,
there was a clear advantage for the decomposed and the partially decomposed
architectures. Comparing M -layer decomposition with M -layer partial decom-
position shows that they have nearly identical performance, other than for the
full-scale sinusoidal test signal. Due to the lower hardware complexity, the par-
tially decomposed architecture is preferred over the decomposed architecture.
P g(0) P g(0)
g ir, k(n) = --------------- - G(x k(n), x k(n 1))
- g k(n) = --------------- (3.14)
P(0) P(0)
109
Digital Encoding in Current-Steering DACs
P g(0)
---------------
- = 0.003 . (3.15)
P(0)
The total power of noise and distortion, P nd , and the signal power, P signal , are
calculated as the variances of g ir, k(n) and x k(n) , respectively. Hence, dc compo-
nents in the signals are discarded and the quantization error is not considered in
the calculations.
The calculation of SFDR for the sinusoidal test signals utilizes the DFT of the
signal
110
Comparison of Codes
62 62
61 61
SNDR [dB]
SNDR [dB]
60 60
59 59
segmented segmented
decomposed decomposed
58 partially decomposed
58 partially decomposed
57 57 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.14 SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .
62 62
SFDR [dB]
SFDR [dB]
60 60
segmented segmented
58 58 decomposed
decomposed
partially decomposed partially decomposed
56 56 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.15 SFDR due to glitches plotted as functions of (a) M and (b) the number of bits in
the control word for the different architectures using test signal x 1(n) .
The SNDR values resulting from test signals x 3(n) and x 4(n) are plotted in
Fig. 3.18 and Fig. 3.19, respectively. For test signal x 3(n) , the three architectures
have similar performance when plotted vs. the number of bits in the control word.
However, for signal x 4(n) , which has a smaller standard deviation than x 3(n) ,
111
Digital Encoding in Current-Steering DACs
60 60
SNDR [dB]
SNDR [dB]
50 50
segmented segmented
40 40 decomposed
decomposed
partially decomposed partially decomposed
30 30 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.16 SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .
60 60
55 55
SFDR [dB]
SFDR [dB]
50 50
45 45
segmented segmented
decomposed decomposed
40 partially decomposed
40 partially decomposed
35 35 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.17 SFDR due to glitches plotted as functions of (a) M and (b) the number of bits in
the control word for the different architectures using test signal x 2(n) .
112
Comparison of Codes
55 55
SNDR [dB]
SNDR [dB]
50 50
segmented segmented
45 45 decomposed
decomposed
partially decomposed partially decomposed
40 40 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.18 SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 3(n) .
50 50
SNDR [dB]
SNDR [dB]
40 40
segmented segmented
30 30 decomposed
decomposed
partially decomposed partially decomposed
20 20 1 2 3 4
0 2 4 6 8 10 10 10 10
M NB
(a) (b)
Figure 3.19 SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 4(n) .
113
Digital Encoding in Current-Steering DACs
114
Encoder Implementation
MSB
(N1)-bit word #2
LSB
MSB
N-bit input
(N1)-bit word #1
LSB
LSB
Implementing the 1-layer encoders in Fig. 3.3 according to the structure illus-
trated in Fig. 3.20 results in the implementation of a multi-layer encoder. Natu-
rally, since the MSB of each binary-weighted word is connected to several gate
inputs, additional drivers are required for these bits in order to obtain sufficient
speed. Also for the multi-layer case, it is possible to increase the speed of the
encoder and reduce the transistor count by properly replacing AND and NAND
gates with NAND and NOR gates and by inserting inverters in the proper places.
115
Digital Encoding in Current-Steering DACs
the output. The simplest type of binary-to-thermometer encoder, i.e., the 2-bit
encoder, is illustrated in Fig. 3.21(a). It consists of one AND gate and one OR
gate. In Fig. 3.21 it is shown how a ( K 1 )-bit encoder can be used together with
a set of AND gates and OR gates to implement a K -bit encoder. The ( K 1 )-bit
encoder used for the implementation of the K -bit encoder is implemented in the
same way utilizing a ( K 2 )-bit encoder, which in turn utilizes a ( K 3 )-bit
encoder, etc. A more thorough description of this type of encoder is given in [27].
A similar (possibly identical) solution has been used by others [58]. As for the
decomposition encoders discussed in Sec. 3.7.1, an increase in speed and a
decrease in transistor count can be obtained through appropriate replacing of
AND and OR gates with NAND and NOR gates. This is further discussed in [27].
t3
b1 t2
t1
b0
(a)
t2K1
t2K2
t2K1+1
bK t2K1
t2K11
bK1
t2K12
(K1)-bit
binary-to-thermometer
encoder
b1
b0 t1
(b)
Figure 3.21 Implementation of (a) 2-bit and (b) K -bit binary-to-thermometer encoders.
116
4 Correction and
Compensation of Errors
It can be hard to meet a DAC design specification using a straightforward imple-
mentation. In this chapter, techniques for improvement of the DAC linearity are
discussed. Dynamic element matching techniques are used for transforming spu-
rious tones caused by matching errors into white or shaped noise. These tech-
niques are overviewed in Sec. 4.1 together with a technique developed in this
work for the decomposed DAC architecture. Distributed biasing of current
sources, which has been used in two of the implemented DACs presented in
Chapter 5 to reduce the errors due to linearly graded parameter variations, is dis-
cussed in Sec. 4.2. In modulation, feedback of the quantization error is uti-
lized to spectrally shape the quantization noise to reduce its power within the
signal band. A technique based on this principle has been developed for spectral
shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop.
The basic idea is presented in Sec. 4.2 together with two examples of utilization
of the technique.
117
Correction and Compensation of Errors
In all of the DAC architectures discussed in Chapter 3, the mapping from the
input to the control word is static, i.e., a given input x results in the same control
word each time it is applied. If mismatch is the dominating error source and we
consider the output in discrete time, this static mapping from the input to the con-
trol word results in the same error
every time a given input x is applied. In other words, the error sequence e(n) is a
function only of the input sequence x(n) , i.e.
118
Dynamic Element Matching
x2(n) x3(n)
binary-to-thermometer encoder
x1(n)
scrambler
combined output
1-bit
r(n) DACs
Let t l(n) and u l(n) denote the individual bits of x 2(n) and x 3(n) , respectively.
The scrambler maps each t l(n) onto a unique u k(n) such that u k(n) = t l(n) .
Which t l(n) is mapped onto what u k(n) is determined by the control signal r(n) .
Each u l(n) controls one of the 1-bit DACs with an associated error l . Consider
first the case of a static mapping, i.e., letting r(n) be constant yielding that each
bit in x 2(n) is mapped onto the same bit in x 3(n) for every n . For simplicity, we
let
119
Correction and Compensation of Errors
Hence, if the input is periodic, the error is also periodic, resulting in harmonic
distortion at the output. If instead r(n) is not constant, the mapping between the
bits in x 2(n) and x 3(n) is dynamic and the error adopts noise-like properties
rather than resulting in harmonic distortion, provided that the control signal r(n)
is properly chosen.
For an N -bit input, x 2(n) and x 3(n) both have 2 N 1 bits. Hence, there are
n map = ( 2 N 1 )! (4.6)
different mappings between the bits in x 2(n) and x 3(n) (i.e., ways to reorder the
bits in x 2(n) ). For large N , implementing a scrambler capable of performing all
different mappings results in a large hardware overhead. Therefore, a proper sub-
set of the n map different mappings that enables an efficient hardware implemen-
tation should be selected. There is a large amount of research on DEM circuit
techniques with reduced hardware complexity presented in the literature (see,
e.g., [62, 63, 64]). Some of these techniques are overviewed in the following. For
comparisons of different networks used for DEM realizations, see, e.g., [65, 66].
120
Dynamic Element Matching
the k LSBs of the input are mapped onto out 2 . The number of output bits for
each switch is linearly decreasing with decreasing layer index, and the tree is ter-
minated with the switching layer consisting of 1-bit outputs. These 1-bit signals
constitute a scrambled, thermometer coded word that is used to control 1-bit
DACs, whose outputs are summed yielding the total output for the DEM DAC.
An additional bit with the same weight as the LSB, and fixed value 0, is added
to the input to give the LSBs the same total weight as the MSB. This is required
because there is an even number of output bits from the switching tree, whereas a
thermometer coded word has an odd number of bits. This causes at least one of
the output bits from the tree to have the value 0.
layer 1
2
switch
r1(n)
layer N1
N
switch
rN1(n)
layer N
to 1-bit DACs
N N+1
x(n) switch
1 rN(n)
0
N
switch
rN1(n)
2
switch
r1(n)
Figure 4.2 Binary switching tree for implementing the FRDEM technique.
121
Correction and Compensation of Errors
the PRDEM technique [62]. In PRDEM, the switching tree is terminated before
1-bit outputs are reached, resulting in a lower hardware complexity. The outputs
of the last layer are used as inputs to DAC banks consisting of one 1-bit DAC and
one multi-bit DAC. Design, modeling, and measurements of a current-steering
PRDEM DAC is discussed in Sec. 5.3. From the simulations and measurements
presented there, we find that randomization in a few layers only is enough for
making the distortion due to mismatch negligible compared with the dynamic
errors. Hence, terminating the switching tree after a few layers is acceptable.
1
u l(n) = ----- x 1(n) + z l(n) , (4.7)
M
where M is the number of 1-bit signals and z l(n) is a signal with very little power
within the signal band. The total output is
M M
y(n) = 1-
----
M
( K + l ) x 1(n) + ----M1- ( K + l ) zl(n) =
l=1 l=1
M M
= x 1(n) K 1 +
l + ( K + l ) zl(n) , (4.8)
l=1 l=1
where K is a gain factor. The first term in the right-hand side of (4.8) is the
desired output (with a slight gain error). The second term is the error e(n) due to
mismatch. Moreover
M M
x 1(n) = ul(n) = x 1(n) + z l ( n) , (4.9)
l=1 l=1
yielding
122
Dynamic Element Matching
M
zl(n) = 0 . (4.10)
l=1
Since each z l(n) has very little power within the signal band, so does e(n) . The
construction of the different u l(n) is nontrivial. Several circuit solutions have
been proposed (see, e.g., [67, 68, 70, 71]), and there are also solutions where the
different u l(n) are multi-bit words.
Proposed Technique
The proposed technique is illustrated in Fig. 4.3 with the modified 1-layer
decomposition encoder. A normal 1-layer encoder is cascaded with a block that
performs conditional pairwise scrambling of the bits having equal weights. We
let b l1 and b l2 denote bit l of the first and the second multi-bit output word from
the normal 1-layer encoder, respectively. The corresponding outputs from the
scrambler are denoted c l1 and c l2 , respectively. The bits of the 1-bit words are
denoted b and c without indices. The 1-bit word is not subject to scrambling,
i.e., c = b . If the pairwise scrambling of the bits are performed according to the
truth table given in Table 4.1, no additional unit current sources are switched. In
Table 4.1, n denotes the sequence index and a(n) is a random binary sequence
whose complement is denoted a(n) . The function of the conditional scrambler
can be implemented with a simple finite state machine including only two D flip-
flops and a small number of logic gates, except for the generation of the random
sequence. The implementation of the conditional scrambler is straightforward
and is not further discussed here. This type of pairwise scrambling can be applied
123
Correction and Compensation of Errors
to any type of DAC architecture having several bits with equal weights. In the
special case of decomposition, the realization of the conditional scrambler can be
simplified by noting that the combination [ b l2, b l1 ] = [ 1, 0 ] cannot occur. Hence,
the values of c l2(n) and c l1(n) in the shaded rows of Table 4.1 can be replaced
with dont-care values.
2
N1 {bl } N1 {c2l }
1-layer decomposition encoder
1
N1 {bl } N1 {c1l }
Note that the proposed scrambling can only be applied to the 1-layer encoders in
the last layer. Applying scrambling to previous layers destroys the good glitch
properties of the decomposed architecture.
Simulation Results
In this section, we present simulation results from behavioral-level MATLAB
simulations. 14-bit DACs with different architectures are simulated. The errors
considered in the simulations are random, uncorrelated matching errors in the
unit current sources having a Gaussian distribution with a relative standard devia-
tion of 5 %. A full-scale sinusoidal test signal with 2 12 samples is used. The nor-
malized signal frequency of the test signal is
f signal
f N = --------------- 0.114 , (4.12)
fu
124
Dynamic Element Matching
0 0 0 0 0 0
0 0 0 1 a(n) a(n)
0 0 1 0 a(n) a(n)
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 1 a(n) a(n)
1 1 1 0 a(n) a(n)
1 1 1 1 1 1
Table 4.1 Truth table for pairwise conditional scrambling.
observed that the distortion is largely reduced when DEM is applied, to the cost
of a higher noise floor. The matching errors in the unit current sources used in the
simulations were identical in the two cases.
The spectra plotted in Fig. 4.4 are the results from a single stochastic outcome of
the matching errors. Due to the stochastic nature of the matching errors, the
results may differ considerably between different outcomes. Hence, one single
stochastic outcome does not provide sufficient information to base general con-
clusions upon. Therefore, simulations were performed for 10 3 different stochas-
tic outcomes and the SFDR was used as a metric for measuring the DAC
linearity. Five different cases were considered. Three DAC architectures without
scrambling are included as references. These are the binary-weighted architec-
125
Correction and Compensation of Errors
PSD [dB]
40 40
60 60
80 80
100 100
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Normalized frequency Normalized frequency
(a) (b)
Figure 4.4 Simulated output spectra for 14-bit 1-layer decomposed DACs (a) without and
(b) with conditional scrambling of the MSB.
ture, the 1-layer decompose architecture, and the 2-layer decomposed architec-
tures. The two other architectures are the 1-layer decomposed architecture with
conditional scrambling of the MSB and the 2-layer decomposed architecture with
conditional scrambling of the MSB applied to the 1-layer encoders in the last
layer. The yield vs. SFDR requirement is plotted in Fig. 4.5 for all five cases. The
difference between the unscrambled cases is small. The 2-layer decomposed
architecture is slightly better than the 1-layer decomposed architecture, which in
turn is slightly better than the binary-weighted architecture. A large improve-
ment, compared with the unscrambled cases, is obtained when the proposed
DEM technique is applied to 1-layer decomposition. The SFDR at 90 % yield is
74.7 dB, compared with 70.2 dB for the unscrambled 1-layer decomposed case.
It is also clear from the plot in that the spurious-tone reduction is much more effi-
cient when the DEM technique is applied in the 1-layer case than in the 2-layer
case. In the latter case, only a small SFDR improvement is obtained compared
with the unscrambled cases when a high yield is targeted.
The results presented so far indicate that applying the proposed DEM technique
to the 1-layer decomposed architecture yields the most efficient randomization.
Therefore, we focus on the 1-layer decomposed architecture and investigate the
influence of further randomization by introducing conditional scrambling of not
only the MSB but also of the bit with the second highest significance. The yield
vs. SFDR requirement for this case (referred to as 2-bit DEM) is plotted in
Fig. 4.6. Included in this plot are also the curves for the 1-layer decomposed
architectures without DEM and with conditional scrambling of the MSB
(referred to as 1-bit DEM). The spurious-tone reduction obtained using 2-bit
DEM is better than using 1-bit DEM. For example, the SFDR value at 90 % yield
using 2-bit DEM is 75.8 dB, which is 1.1 dB higher than the result obtained
126
Distributed Biasing
0.8
0.6
Yield
0.4
binary weighted
1-layer
0.2 1-layer DEM
2-layer
0 2-layer DEM
60 65 70 75 80 85 90
SFDR requirement
Figure 4.5 Yield plotted as a function of the SFDR requirement for different 14-bit DACs.
using 1-bit DEM. The SFDR values at 90 % and 99 % yield for the architectures
utilizing DEM considered in the simulations are given in Table 4.2. The hardware
overhead for the 1-layer decomposed architecture utilizing 2-bit DEM, which is
the best of these architectures, is only two small finite state machines performing
the operation described in Table 4.1 and the circuitry required for the random
number generation. Hence, the technique can be implemented at a low cost.
The performance of the 1-layer decomposed architecture can, of course, be fur-
ther improved by introducing conditional scrambling of more bits than two. Each
additional pair of bits that is scrambled requires an additional finite state
machine, i.e., the cost of the suggested hardware increases linearly with the num-
ber of scrambled bit pairs. However, the influence on the SFDR reduces with
decreasing bit weight. Hence, there is a trade-off between performance and hard-
ware cost and at some point, the improvement obtained by introducing condi-
tional scrambling of an additional pair of bits might be negligible and not worth
the cost of the additional hardware required.
127
Correction and Compensation of Errors
0.8
0.6
Yield
0.4
0.2 no DEM
1-bit DEM
0 2-bit DEM
60 65 70 75 80 85 90
SFDR requirement
Figure 4.6 Yield plotted as a function of the SFDR requirement for different types of 14-bit
DACs utilizing 1-layer decomposition.
W out
-I
I out, l = ----------- (4.13)
W in in
provided that the output transistors are operating in the saturation region and that
the transistors are perfectly matched. The transistors have the same length. W out
is the width of the output transistors and W in is the width of the input transistor.
In the following we discuss how current mirrors can be utilized for biasing cur-
rent sources and how the matching properties are affected.
In Fig. 4.8(a) we show an example where the current-source array is made of the
output transistors of a single multiple-output current mirror. Graded parameter
variations, discussed in Sec. 2.2.3, cause the output currents from the different
128
Modulation of Expected Errors
Vbias
current sources to vary over the array. The matching of the output currents can be
improved by partitioning the array of current sources into smaller parts, letting
each such part be an individual multiple-output current mirror, as indicated in
Fig. 4.8(b). This is because the bias voltage is set individually for each current
mirror. If the input transistors are located close to the output transistors, the bias
voltage is set to give the proper output current for the values of transistor param-
eters in the proximity of the input transistors, reducing the current variations over
the array due to graded parameter mismatch, compared with the approach in
Fig. 4.8(a). In order for the distributed biasing strategy to work, it is important
that the matching errors between the different bias currents are small. The biasing
strategy has no effect on the influence of random matching errors, so this prob-
lem remains.
129
Correction and Compensation of Errors
Ibias Ibias, 1
Ibias, 2
Ibias, K
(a) (b)
Figure 4.8 Arrays of unit current sources with (a) global bias voltage generation and (b)
distributed bias voltage generation.
STF(z) = 1 (4.14)
and
130
Modulation of Expected Errors
DAC input
x(n) DAC
Q model
e(n)
H(z)
131
Correction and Compensation of Errors
PSD [dBm/Hz]
30 30
40 40
50 50
60 60
70 70
80 80
90 90
100 100
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [MHz] Frequency [MHz]
(a) (b)
Figure 4.10 Measured output spectra from a DAC (a) without and (b) with the distortion
shaped using the proposed technique.
DAC. A suggestion for further investigation is to use a finer model with a larger
LUT than the model used in the example, perhaps also using the previous DAC
input to address the LUT as in Fig. 2.14. It is likely that this kind of model refine-
ment is required in order to make the compensation successful for larger signal
bandwidths than that used in the example. It would also be useful to use a multi-
carrier signal instead of a single-tone signal to avoid having the distortion appear-
ing outside of the signal band. If a multi-carrier signal is used, distortion appear
within the signal band due to intermodulation.
132
Modulation of Expected Errors
Proposed Technique
In a binary-weighted current-steering DAC, the largest DNL error due to current
source mismatch usually appears at the middle code transition [52], as discussed
in Sec. 2.2.2. In the approach presented in this section, we utilize this fact in two
DAC models with low computational complexity that may be integrated with the
DAC. Due to the low computational complexity of the models, the cost in terms
of circuit area and power consumption is negligible. The two models are illus-
trated in Fig. 4.11. The DNL errors in the models are nonzero only for the middle
code transition. In the model illustrated in Fig. 4.11(a), the DNL error in the mid-
dle code transition is 2a where a is a design parameter. The corresponding DNL
error for the model in Fig. 4.11(b) is 2a . The nominal transfer characteristics
for the DAC models are plotted with dashed lines in Fig. 4.11(a) and (b). As dis-
cussed in Sec. 2.1, there are alternative ways of choosing the nominal character-
istics. Commonly used choices are a straight line between the endpoints of the
actual characteristics and a best fit straight line using the least squares method
[11]. The latter is the approach used for evaluation of code domain metrics in this
thesis, as mentioned in Sec. 2.1. A possible benefit of using one of the other two
methods for selecting the nominal characteristics is that the absolute value of the
error e(n) on the average is lower than for the method used in this section.
Hence, the risk for instability in the feedback loop is reduced. However, the com-
plexity of calculating the error is somewhat higher for these other methods. With
the used method, the modeled error is simply either a or a depending on the
value of the MSB at the input of the DAC model.
After manufacturing, the performance of the DAC chips are evaluated without
error compensation, e.g., in terms of the SFDR. The chips that meet the given
specification can be used without error compensation. The chips that do not meet
the given specification are further evaluated using the spectral shaping technique
and the two DAC models. Some of these chips will meet the specification with
the error compensation using one of the two simple DAC models. Hence, the
yield can be improved. After testing, the chips require programming to set if error
compensation is required and, in that case, which of the two models should be
used. This programming can, e.g., be performed by burning a fuse inside the
chip. The usefulness of the technique is, of course, depending on whether or not
mismatch is the dominating error source and if oversampling can be afforded.
Simulation Results
The proposed strategy is evaluated through behavioral-level MATLAB simula-
tions on 14-bit binary-weighted DACs which include matching errors in the cur-
rent sources as the only error. The matching errors in the unit current sources are
observations of uncorrelated stochastic variables with Gaussian distribution hav-
133
Correction and Compensation of Errors
Model output
2a
0
0 middle code max code
Model input
(a)
2a
0
0 middle code max code
Model input
(b)
Figure 4.11 Illustration of DAC models with nonzero DNL errors at the middle code transi-
tion. The model in (a) has a positive DNL error and the model in (b) has a nega-
tive DNL error.
134
Modulation of Expected Errors
DAC input
DAC
x(n) error
model
e(n)
z1
(a)
a a
N N
MSB of DAC input
0 1
p/n
N
modeled error
(b)
Figure 4.12 Block diagrams for (a) the compensation circuit used in the simulations and (b)
the implementation of the DAC error model.
The test signal used in the simulations is a half-scale sinusoid with normalized
frequency
f sig 0.068
- ------------- ,
f N = -------- (4.16)
fu OSR
where f sig is the signal frequency, f u is the update frequency, and OSR is the
oversampling ratio. The SFDR evaluated within the signal band
f [ 0, f u ( 2 OSR ) ) is used as a performance metric in the simulations and is
for each stochastic outcome evaluated as the highest SFDR obtained from the dif-
ferent test cases.
135
Correction and Compensation of Errors
In Fig. 4.13, SFDR is plotted as a function of the parameter a for different values
of the OSR. The values for a = 0 are the values obtained without compensation.
The plotted values are the 90 % yield values, i.e., the SFDR requirement that is
fulfilled in 90 % of the stochastic outcomes. From the plots in Fig. 4.13, we con-
clude that for this particular simulation setup, a = 2 gives the best 90 % yield
value of the SFDR for considered values of the OSR. For a = 6 , the 90 % yield
value of the SFDR is practically the same as for the case a = 0 for all values of
OSR. This means that applying compensation with the parameter a set to 6
improves the performance only for a negligible number of the stochastic out-
comes. A better suppression of nonlinear distortion is obtained for higher values
of the OSR. This is hardly surprising, since the magnitude of the NTF for a first-
order modulator, which is [11]
NTF(z) = 1 z 1 (4.17)
is lower within the signal band for a high OSR than for a low OSR.
The simulation results for a = 2 are analyzed further since this parameter value
yields the best 90 % yield SFDR. As an example, we consider the case for which
OSR = 8 . The yield is plotted as a function of the SFDR requirement in
Fig. 4.14. A clear improvement of the yield using the proposed method is
observed. For example, an SFDR requirement of 73 dB results in a 89.7 % yield
without the proposed technique and a 99.7 % yield with the proposed technique.
The corresponding values for a 78 dB SFDR requirement is 56.6 % and 88.4 %,
respectively.
The simulation results presented in this section are merely illustrations of the
proposed method and should, of course, be used with care. Only one test signal
has been used for each value of OSR. For better performance estimation, several
different test signals relevant for the intended application should be used. More-
over, only static errors due to current source mismatch was considered. If
dynamic errors limit the DAC performance, it is likely that the benefit of using
the proposed technique is significantly less than indicated by the simulation
results presented in this section.
136
Modulation of Expected Errors
78 78
SFDR [dB]
SFDR [dB]
76 76
74 74
72 72
0 1 2 3 4 5 6 0 1 2 3 4 5 6
a a
(a) (b)
SFDR vs. a, OSR = 4 SFDR vs. a, OSR = 2
78 78
SFDR [dB]
SFDR [dB]
76 76
74 74
72 72
0 1 2 3 4 5 6 0 1 2 3 4 5 6
a a
(c) (d)
Figure 4.13 The 90 % yield value of SFDR as a function of the parameter a for different
values of the OSR.
137
Correction and Compensation of Errors
without compensation
with compensation
100
80
Yield [%]
60
40
20
0
65 70 75 80 85 90 95
SFDRreq [dB]
Figure 4.14 Yield vs. SFDR requirement with and without the proposed technique for
a = 2 and OSR = 8 .
138
5 Test-Chip
Implementations
Four different current-steering DACs implemented in CMOS technology have
been developed in this work to enable comparison between behavioral-level sim-
ulations and measurements on actual implementations and to provide platforms
for evaluation of different techniques for linearity improvement. In this chapter,
these four DAC chips are presented in chronological order. Design and measure-
ment issues that are common to all implementations are discussed in Sec. 5.1.
The first chip, a 14-bit DAC in a 0.35 m CMOS process, is presented in
Sec. 5.2. The same process was used for the implementation of a 14-bit PRDEM
DAC, which is presented in Sec. 5.3. The presentation includes comparisons
between measurement results and results from behavioral-level simulations. A
14-bit dual DAC (i.e., two DACs on the same chip) implemented in a 0.25 m
CMOS process is presented in Sec. 5.4. A configurable 12-bit DAC capable of
operating with different degrees of segmentation and decomposition was imple-
mented to enable comparisons between the different architectures. The circuit
was implemented in the same 0.35 m CMOS process as the DACs in Sec. 5.2
and Sec. 5.3 and is presented in Sec. 5.5.
139
Test-Chip Implementations
Floorplan
A DAC floorplan is outlined in Fig. 5.1. Starting from the left we have the digital
input entering the digital encoder. The type of encoding performed by the
encoder is different for different chips. All encoders have been implemented
using the complementary static CMOS logic style [75, 76, 77] to obtain a robust
design. The bits of the encoded data are applied to latches used for synchroniza-
tion and generation of control signals suitable for driving the current switches.
The current sources are placed in the block in the right part of Fig. 5.1, and the
output current wires are placed between the array and the switches.
digital input
latches
digital & current source array
encoder
switches
output
currents
140
Design and Measurement Strategies
output signal. With the layout strategy used in the implementations presented in
this chapter, the analog and digital parts are separated. Guard rings are used
around digital as well as analog parts to reduce the substrate noise in the analog
parts due to switching in the digital parts. Separate supply voltages are used for
digital and analog circuitry to reduce the amount of simultaneous switching noise
[78] induced in the analog signals.
Clock Distribution
Uncertainties in the timing of the switching signals, known as jitter, cause distor-
tion and noise in the DAC output. It is therefore important that the DAC is
updated at well-defined instants in time. In order to obtain that, it is required that
the clock net driving the switch signal generators is carefully designed. A sche-
matic of a clock net with a tree structure that has been used in the implementa-
tions is shown in Fig. 5.3. To avoid skew between the branches in the tree, it is
required that the loads present at the outputs of the buffers at the same level are
well matched. Therefore, the clock trees in the implemented DACs have been
designed with equal wire lengths for all wires present at the same level.
141
Test-Chip Implementations
D
Q+
Q
D
(a)
VDD
D D
VDD VDD
F F
Q Q+
(b)
Figure 5.2 Circuit solutions for switch signal generation. The circuit in (a) utilizes a cross-
coupled pair of NOR gates, whereas the circuit in (b) is a differential latch based
on the DCVS logic style.
142
Design and Measurement Strategies
Figure 5.3 Tree clock network for driving the switch signal generators.
A printed circuit board (PCB) for DAC measurement is outlined in Fig. 5.5. The
output currents from the DAC are directed into off-chip load resistors. An RF-
transformer is used to convert the differential signal to a single-ended signal,
denoted combined output in Fig. 5.5, that can be handled by the different mea-
surement instruments. In order to measure the individual single-ended outputs,
the transformer must be removed.
clock power
generator supply
oscilloscope
measurement
board DAC
spectrum
analyzer
GPIB
PC
controller
GPIB bus
143
Test-Chip Implementations
clock single-ended
outputs
combined
output
digital input
DAC
load RF
resistors transformer
digital supply analog supply
144
A 14-bit Segmented DAC in 0.35 m CMOS
Figure 5.6 Chip photograph of the 14-bit current-steering DAC implemented in a 0.35 m
CMOS process.
145
Test-Chip Implementations
PSD [dBm/Hz]
30 30
40 40
50 50
60 60
70 70
80 80
90 90
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10
(a) (b)
Output spectrum, fu = 20 MHz. Output spectrum, fu = 20 MHz.
0 0
10 10
20 20
PSD [dBm/Hz]
PSD [dBm/Hz]
30 30
40 40
50 50
60 60
70 70
80 80
90 90
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10
(c) (d)
Figure 5.7 Single-tone, full-scale measurements on 14-bit DAC in 0.35 m CMOS. For (a)
and (b), the update frequency is 5 MHz, and the signal frequencies are approxi-
mately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d), the update fre-
quency is 20 MHz, and the signal frequencies are approximately 2.55 MHz and
6.55 MHz, respectively.
The measurements were carried out for several signal frequencies, and the SFDR
was extracted from the spectra. SFDR is plotted as a function of signal frequency
in Fig. 5.9. Fig. 5.9(a) shows SFDR for the full-scale inputs, whereas Fig. 5.9(b)
shows SFDR for the half scale inputs.
The behavior of decreasing SFDR with increasing signal frequency observed in
the measurements agrees with observations made in simulations on the state-
space DAC model including finite output impedance in the current sources pre-
sented in Sec. 2.3.2.
146
A 14-bit PRDEM DAC in 0.35 m CMOS
PSD [dBm/Hz]
30 30
40 40
50 50
60 60
70 70
80 80
90 90
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10
(a) (b)
Output spectrum, fu = 20 MHz. Output spectrum, fu = 20 MHz.
0 0
10 10
20 20
PSD [dBm/Hz]
PSD [dBm/Hz]
30 30
40 40
50 50
60 60
70 70
80 80
90 90
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [Hz] 6 Frequency [Hz] 6
x 10 x 10
(c) (d)
Figure 5.8 Single-tone, half-scale measurements on a 14-bit DAC in 0.35 m CMOS. For
(a) and (b), the update frequency is 5 MHz, and the signal frequencies are
approximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d), the
update frequency is 20 MHz, and the signal frequencies are approximately
2.55 MHz and 6.55 MHz, respectively.
147
Test-Chip Implementations
SFDR [dB]
60 60
55 55
50 50
fu = 5 MHz fu = 5 MHz
45 fu = 20 MHz 45 fu = 20 MHz
40 5 6 7
40 5 6 7
10 10 10 10 10 10
Signal frequency [Hz] Signal frequency [Hz]
(a) (b)
Figure 5.9 SFDR vs. signal frequency for (a) full-scale signals and (b) half-scale signals.
5.3.1 Implementation
The PRDEM chip is designed with four layers of switching. The control signals
for the switches are generated off-chip to allow flexibility. The switching tree is
terminated with DAC banks consisting of one 1-bit DAC and one 10-bit DAC, as
was discussed in Sec. 4.1.2. The current sources and the current switches are both
of PMOS type, and no cascodes have been used in the current sources. A descrip-
tion of the design strategy used is given in [80]. A chip photograph of the
PRDEM DAC is shown in Fig. 5.10. The core area of the chip is approximately
6.3 mm2.
148
A 14-bit PRDEM DAC in 0.35 m CMOS
DAC bank
50 , is examined. The parameters used for the state-space model are given in
Table 5.1. The output without randomization is shown in Fig. 5.11(a). The SFDR
(59.6 dB) is determined by the third harmonic. When introducing switching in
the first layer (Fig. 5.11(b)) the SFDR is increased to 67.8 dB, an improvement of
8.2 dB corresponding to approximately one effective bit, to the cost of a some-
what higher noise floor. The SFDR is now limited by the second harmonic. When
introducing switching in all four layers (Fig. 5.11(c)) we can see some small dif-
ferences compared with Fig. 5.11(b) but the SFDR remains the same, hence we
do not gain any SFDR performance by having more than one switching layer.
This can be explained by observing the second harmonic in Fig. 5.11(a), (b) and
(c). The second harmonic is almost unaffected by the randomization, because it
arises from dynamic errors in the DAC and as soon as the third harmonic, arising
from mismatch, is suppressed below the second harmonic nothing is gained in
SFDR performance by using DEM.
149
Test-Chip Implementations
10
SFDR = 59.6 dB
20
30
PSD [dB/Hz]
40
50
60
70
80
90
100
0 1 2 3 4 5
Frequency [MHz]
(a)
Simulated With 1 Layer DEM Simulated With 4 Layer DEM
0 0
10 10
SFDR = 67.8 dB SFDR = 68.1 dB
20 20
30 30
PSD [dB/Hz]
PSD [dB/Hz]
40 40
50 50
60 60
70 70
80 80
90 90
100 100
0 1 2 3 4 5 0 1 2 3 4 5
Frequency [MHz] Frequency [MHz]
(b) (c)
Figure 5.11 Simulated spectra, 10 MHz update frequency, (a) without randomization, with
(b) one switching layer and (c) four layer switching.
150
A 14-bit PRDEM DAC in 0.35 m CMOS
Measurement Results
To enable comparisons between measurements and simulations, the implemented
DAC is measured with the update frequency f u = 10 MHz that was used for the
simulations. Fig. 5.12(a) and (b) show the measured output spectra without ran-
domization and with switching in one layer, respectively. The SFDR is increased
from 60.7 to 67.3 dB when one layer is switched, an improvement of 6.6 dB
which could be expected from the simulation results. When all four layers are
switched, which is the case for the spectrum shown in Fig. 5.12(c), the improve-
ment in SFDR compared with switching in only one layer is negligible.
Measured Spectrum Without DEM
0
10
SFDR = 60.7 dB
20
30
PSD [dB/Hz]
40
50
60
70
80
90
100
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency [MHz]
(a)
Measured With 1 Layer DEM Measured With 4 Layer DEM
0 0
10 10
SFDR = 67.3 dB SFDR = 68 dB
20 20
30 30
PSD [dB/Hz]
PSD [dB/Hz]
40 40
50 50
60 60
70 70
80 80
90 90
100 100
0.5 1 1.5 2 2.5 3 3.5 4 4.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Frequency [MHz] Frequency [MHz]
(b) (c)
Figure 5.12 Measured spectra, 10 MHz update frequency, (a) without randomization, (b)
with one switching layer, and (c) with four layer switching.
151
Test-Chip Implementations
and update frequency, f sig f u 1 8 , is held constant. The simulated and mea-
sured SFDR without randomization are compared in Fig. 5.13(a). The same com-
parison with switching in all four layers is shown in Fig. 5.13(b). From
Fig. 5.13(a) and Fig. 5.13(b) we find that the simulated and measured results are
similar, which indicates that the models used for the simulation are able to
describe the behavior of the implemented circuit.
Simulated and measured SFDR without DEM Simulated and measured SFDR with DEM
65
Measured 74 Measured 12
Simulated Simulated
71
62 10
68 11
Number of bits
Number of bits
SFDR [dB]
SFDR [dB]
65
59
62 10
56 9 59
56 9
53
53
1 5 10 30 1 5 10 30
Sampling Frequency [MHz] Sampling Frequency [MHz]
(a) (b)
Figure 5.13 Simulated and measured SFDR performance for different update frequencies
with (a) no randomization, and (b) switching in all layers.
152
A 14-bit Dual DAC in 0.25 m CMOS
(a)
(b)
Figure 5.14 (a) Chip photograph and (b) layout plot of the 14-bit dual DAC implemented in
a 0.25 m CMOS process.
153
Test-Chip Implementations
75
70
SFDR [dB]
65
60 fu = 5 MHz
fu = 10 MHz
55 fu = 25 MHz
50 6 7
10 10
Signal frequency [Hz]
A more adequate measure for DMT applications is the MTPR, which is defined
in Sec. 1.3.2. For this purpose, an ADSL-like input is used, which is quantized
values of
154
A 12-bit Configurable DAC in 0.35 m CMOS
255
j
x ( n ) = x dc + K a j sin 2n ------------f- + j , (5.1)
fu
j=1
missing tone
155
Test-Chip Implementations
5.5.1 Architecture
The analog part of the chip consists of a number of unit current sources (single
PMOS transistors) that are grouped (i.e., connected in parallel to a common
switch) to form the weighted current sources required for 4-layer decomposition.
By proper selection of control signals, these weighted current sources can in turn
be grouped to form the different weighted current sources required for a binary-
weighted converter, 1 to 4 layers of decomposition and 2 to 5 bits of segmenta-
tion. In Fig. 5.17(a)-(e), these different groupings are illustrated for a simpler
case, namely a 4-bit DAC operating in either binary-weighted, 2-bit segmented,
3-bit segmented, 1-layer decomposed, or 2-layer decomposed conversion mode.
The digital part of the chip consists of a configurable encoder, which is preceded
by a register used for synchronization of the input bits. In the interface between
the encoder and the switches, there are a number of clocked switch drivers (one
for each switch) of the type outlined in Fig. 5.2(b).
156
A 12-bit Configurable DAC in 0.35 m CMOS
(d) (e)
Figure 5.17 Connection of the unit current sources in a 4-bit DAC for (a) binary-weighted,
(b) 2-bit segmented, (c) 3-bit segmented, (d) 1-layer decomposed, and (e) 2-
layer decomposed conversion mode.
157
Test-Chip Implementations
Since design automation is not as well developed for analog circuits as for digital
circuits, designers are often forced to do full-custom designs. In order to obtain
reasonably short design times, it is important to use efficient design methodolo-
gies. In this section, we discuss a design methodology based on parameterized
cells for efficient layout generation. The design methodology has been used in
the design flow for the configurable DAC. This methodology is a further develop-
ment of the script-based approach used for the design of the DAC presented in
Sec. 5.4. The material presented in this section has previously been published in
[88].
Pcells
In this work, we have used the Cadence Virtuoso design environment, which has
built-in support for creation of parameterized cells, or Pcells with Cadence nota-
tion, using the SKILL programming language [89]. Often, some Pcells are pro-
vided by the process manufacturer in the design kit associated with a specific
process. These Pcells are usually simple primitive devices, e.g., transistors, resis-
tors, or parallel-plate capacitors. Typical parameters for a CMOS transistor are
length, width, number of fingers and Boolean parameters stating whether or not
drain/source contacts should be included. However, Pcells can be used for more
complex structures than primitive devices. For example, in deep sub-micron
CMOS processes, the parasitics in interconnects have a large impact on the cir-
cuit performance, and the behavior of a circuit may differ considerably from sim-
ulation results from the circuit schematic. Therefore, parasitics extracted from the
circuit layout are required for obtaining accurate simulation results. In [90],
SKILL Pcells were used for fast layout generation of operational amplifiers,
making it possible to include extracted parasitics in an amplifier optimization
process.
Pcells are used hierarchically in the design of the configurable DAC. Each sub
block is generalized in order to allow simple modification of the block parame-
ters. For example, if the width or the length of a transistor in an array is changed,
this also affects the placement and the routing, which should be handled by the
Pcell. This generalization of the circuit layout results in an increased design time,
compared with a manual layout with fixed transistor sizes, etc. However, it is usu-
ally required to iterate the circuit layout during the design process. Since this nor-
mally is the case, the Pcell approach with generalized building blocks is
favorable, since the regeneration of the layout is almost instantaneous. Further,
the use of general Pcells enables simpler design reuse, since the circuits can be
modified to match different specifications by changing the parameter values.
158
A 12-bit Configurable DAC in 0.35 m CMOS
There are, however, cases in which this approach is not feasible. For example,
when complex routing with good wire matching is required, a specialized tool
that optimizes the routing is preferred [86].
The structure of the SKILL code for a Pcell is shown in Fig. 5.18. The code starts
with a declaration of the Pcell, containing the name and location of the circuit in
the library hierarchy, followed by a list of parameters. The SKILL code defining
the placement of sub cells, routing of metal, poly, and diffusion layers, etc., is
placed after the parameter list. Even though there is an immense amount of vari-
ous SKILL commands, only a few commands, e.g., for instantiation of sub cells
and generation of paths and rectangles, are required for a successful design with
Pcells.
Figure 5.18 Structure of the SKILL code for a Pcell. Words in regular-weight font are
SKILL commands and words in bold font describe SKILL code to be inserted.
159
Test-Chip Implementations
(a)
(b)
(c)
Figure 5.19 Unit current source in (a) normal, (b) bias, and (c) dummy configuration. In (a)
and (b), the drains are connected to a routing channel above the transistor.
A number of unit current sources are connected in parallel to form weighted cur-
rent sources. A number of binary-weighted and 1-bit sub DACs are required in
the configurable DAC. Here, we have chosen to design the sub DACs from a
number of cells denoted current cells. Each current cell consists of two current
sources with different weights. Further, the current cells consist of a number of
unit sources in dummy and bias configuration. Input parameters to the current
cell are width and length for the unit current sources, the number of rows and col-
umns of unit current sources, the number of unit current sources in bias configu-
ration, and the widths of the metal wires that connects the current sources to the
outputs. The current cell is illustrated in Fig. 5.20, where the Pcell has been
instantiated with different parameter values for the number of rows.
160
A 12-bit Configurable DAC in 0.35 m CMOS
(a)
output bias
wires wire
(b)
Figure 5.20 The current cell Pcell consisting of 4 diode-connected transistors and current
sources with weights 8 and 4 implemented with (a) two and (b) four rows of
unit current sources.
Another basic building block in the current-steering DAC is the current switch.
The switch is implemented with two PMOS transistors with the sources con-
nected to a common node, i.e., the output node of a weighted current source, and
the drains connected to the differential outputs of the DAC. Each switch is iso-
lated with a guard ring to suppress the switching noise from the digital parts.
Parameters for the switch Pcell are lengths and widths for the switch transistors
and the height of the cell, which is required to determine the positions of the
guards. The switch is illustrated in Fig. 5.21, where the Pcell has been instanti-
ated with different parameter values.
Because the configurable DAC should be able to operate in a 4-layer decomposed
mode, 16 binary-weighted and 15 1-bit DACs are required. Therefore, a sub DAC
Pcell containing one binary-weighted and one 1-bit DAC was constructed. The
Pcell consists of a number of instantiations of the current cell Pcell with different
parameter values. The current cells are placed on top of each other, and a guard
ring is drawn around the resulting current source array. The required number of
current switches are placed to the left of the current source array. The Pcell is
illustrated in Fig. 5.22(a) and (b), where a sub DAC with an 8-bit binary-
weighted DAC is implemented with 4 and 8 rows of unit current sources per cur-
rent cell, respectively. Other parameters in the Pcell are, e.g., transistor widths
and lengths, wire widths, number of bits in the binary-weighted DAC, and num-
ber of columns in the current source array.
Configurable Encoder
A configurable encoder is required to allow the DAC to operate in the different
modes. Since the encoder is a digital block, it could have been implemented
using an automated design flow including logic synthesis and automatic place-
161
Test-Chip Implementations
(a)
output wires
guards
switch transistors
(b)
(c)
Figure 5.21 The switch Pcell instantiated with parameter values (a) transistor length
l = 0.7 m , transistor width w = 5 m , and cell height h = 10 m , (b)
l = 0.7 m , w = 5 m , and h = 15 m , and (c) l = 0.7 m ,
w = 10 m , and h = 10 m . The widths of the output wires are 10 m .
ment and routing. However, the encoder is easy to implement using full-custom
design. Therefore, a Pcell-based approach was used also for the encoder. A few
simple logic gates were required, and these were laid out manually. The encoder
is implemented as a tree of 1-layer encoders, which in turn are implemented as
Pcells, where the main input parameter is the number of input bits. The whole
162
A 12-bit Configurable DAC in 0.35 m CMOS
(a)
(b)
Figure 5.22 Instantiations of the Pcell for a sub DAC containing one binary-weighted DAC
and one 1-bit DAC. Each current cell in the sub DACs occupies (a) 4 rows and
(b) 8 rows. In both (a) and (b), the number of input bits to the binary-weighted
DAC is 8.
encoder itself is also a Pcell, where the main parameters are the number of input
bits and the number of layers. The Pcell is illustrated in Fig. 5.23. In Fig. 5.23(a),
the Pcell is instantiated with 5 input bits and 2 layers, and in Fig. 5.23(b), the
Pcell is instantiated with 12 input bits and 4 layers. The encoder shown in
Fig. 5.23(b) is the one that was used in the chip that was fabricated. It has 8 con-
trol signals, two for each layer, to control the DACs mode of operation. These
control signals are denoted configuration bits in Fig. 5.23(a).
Configurable DAC
The chip photograph of the configurable 12-bit DAC is shown in Fig. 5.24. It is
composed of 16 sub DACs, each containing one 8-bit DAC and one 1-bit DAC,
and the encoder shown in Fig. 5.23(b). Since only 15 1-bit DACs are required,
the output of one of the 1-bit DACs is connected to the supply voltage. Each of
the sub DACs has its own bias circuit, which is driven by a bias current generated
in a global bias circuit. In the interface between the encoder and the sub DACs,
there are a number of switch drivers of the type outlined in Fig. 5.2(b), that gen-
erate proper differential signals for controlling the current switches. The manual
163
Test-Chip Implementations
input
configuration bits
configuration bits
output
(a)
(b)
Figure 5.23 Layout of a configurable encoder with (a) 5 input bits and 2 layers and (b) 12
input bits and 4 layers.
layout work in the assembly of the chip is limited to the pad frame, routing of
wires from the core to the pad frame, routing of the power supply and ground
wires from the pad frame to the core, and some minor inter-cell routing. The core
area and the total chip area are approximately 2.5 mm2 and 6.7 mm2, respec-
tively.
Due to the extensive use of Pcells, it is easy to reuse the blocks. For example, if
measurements show that the distortion caused by transistor mismatch is too large,
and that the area of the unit current source should be made larger, a modified lay-
out of the DAC core can be generated in a few seconds by changing the parame-
ter that needs to be modified. Further, since the blocks were parameterized, the
164
A 12-bit Configurable DAC in 0.35 m CMOS
layout of the circuit could be started before the transistor sizing was finished.
Hence, using the design approach discussed in this section enables parallelization
of the design flow, which has a potential of reducing the overall design time.
165
Test-Chip Implementations
not included, and transistor mismatch was not taken into account. For accurate
performance estimation, these parameters should be included and more realistic
test vectors, e.g., multi-tone signals, should be used. However, the simulations
are time consuming (each ramp takes more than three days to simulate). There-
fore, measurements are used to evaluate the performance of the circuit in the dif-
ferent modes of operation. Nevertheless, the simulated ramp responses give an
indication of the differences in glitch behavior between the different modes.
The simulated ramp responses for binary-weighted mode, 5-bit segmented mode,
and 4-layer decomposed mode are shown in Fig. 5.25(a), (b), and (c), respec-
tively. The magnitudes of the glitches shown in these plots are quite large. How-
ever, if parasitic capacitances had been included in the simulations, the outputs
would have been lowpass filtered and the glitch magnitudes reduced. Moreover,
image rejection filters are used in actual applications to remove the spectral
images of the signal that appears at multiples of the update frequency. These fil-
ters also reduce the glitch magnitudes. The relative differences between the dif-
ferent modes of operation shown in Fig. 5.25 is, however, preserved. From the
plots in Fig. 5.25, it is obvious that the binary-weighted mode suffers from larger
glitches than the segmented and decomposed modes. Enlarged plots around the
middle code transition are included in Fig. 5.25(b) and (c) in order to compare
the glitch behavior between segmented and decomposed modes. The glitch in the
middle code transition is much smaller in the decomposed mode than in the seg-
mented mode. This is not only true for this particular code transition, but also for
14 additional code transitions. For the remaining code transitions in the ramp, the
two modes have the same number of switched unit current sources, and, hence,
approximately the same glitch behavior.
166
A 12-bit Configurable DAC in 0.35 m CMOS
Binary-weighted DAC
1
0
0.1 0.2 0.3 0.4
Time [ms]
(a)
5-bit segmented DAC 4-layer decomposed DAC
1 1
Output voltage [V]
0.5 0.5
0.5 0.5
0.49 0.49
(b) (c)
Figure 5.25 Simulated single-ended ramp responses for the test chip in (a) binary-weighted,
(b) 5-bit segmented, and (c) 4-layer decomposed modes. The update frequency
is 10 MHz.
Binary weighted
20
30
PSD, dBm/Hz
40
50
60
70
80
90
0 1 2 3 4 5
Frequency, MHz
Figure 5.26 Measured dual-tone output spectrum for one of the DACs in binary-weighted
mode.
167
Test-Chip Implementations
observed from Fig. 5.27. For this particular chip, the nonlinear distortion is actu-
ally worse in the 4-bit segmented mode than in the 3-bit segmented mode. This is
due to the stochastic nature of the matching errors. For this particular outcome
(i.e., chip), the matching errors gave less distortion in the 3-bit segmented mode
than in the 4-bit segmented mode. Seen over a large number of chips, however, 4-
bit segmentation yields less distortion than 3-bit segmentation.
PSD, dBm/Hz
40 40
50 50
60 60
70 70
80 80
90 90
0 1 2 3 4 5 0 1 2 3 4 5
Frequency, MHz Frequency, MHz
(a) (b)
4-bit segmented 5-bit segmented
20 20
30 30
PSD, dBm/Hz
PSD, dBm/Hz
40 40
50 50
60 60
70 70
80 80
90 90
0 1 2 3 4 5 0 1 2 3 4 5
Frequency, MHz Frequency, MHz
(c) (d)
Figure 5.27 Measured dual-tone output spectra for one of the DACs in (a) 2-bit segmented,
(b) 3-bit segmented, (c) 4-bit segmented, and (d) 5-bit segmented mode.
The same chip was also measured in the different available decomposed modes.
The resulting output spectra are shown in Fig. 5.28. Using decomposition also
shows a clear improvement in linearity compared with the binary-weighted case.
For the decomposed mode, we find that the distortion is actually worse for the 2-
layer decomposed mode than for the 1-layer decomposed mode. This is similar to
the nonintuitive behavior for the segmented mode and is due to the same statisti-
cal variation. Seen over a large number of chips, 2-layer decomposition results in
168
A 12-bit Configurable DAC in 0.35 m CMOS
PSD, dBm/Hz
40 40
50 50
60 60
70 70
80 80
90 90
0 1 2 3 4 5 0 1 2 3 4 5
Frequency, MHz Frequency, MHz
(a) (b)
3-layer decomposed 4-layer decomposed
20 20
30 30
PSD, dBm/Hz
PSD, dBm/Hz
40 40
50 50
60 60
70 70
80 80
90 90
0 1 2 3 4 5 0 1 2 3 4 5
Frequency, MHz Frequency, MHz
(c) (d)
Figure 5.28 Measured dual-tone output spectra for one of the DACs in (a) l-layer decom-
posed, (b) 2-layer decomposed, (c) 3-layer decomposed, and (d) 4-layer decom-
posed modes.
The measured SNDR is limited by the noise floor of the spectrum analyzer, so the
SNDR does not vary more than a few dB between the different modes. Therefore,
we instead use the signal-to-distortion ratio (SDR) as a performance metric. We
define SDR as
169
Test-Chip Implementations
P signal
SDR = ---------------
-, (5.2)
Pd
where P signal is the signal power and P d is the total power for all spurious tones
visible above the noise floor of 85 dBm/Hz. SDR values for M -layer decom-
posed and ( M + 1 )-bit segmented modes are plotted as a function of M in
Fig. 5.29. The plotted SDR values are the average values over three different
chips (the averages are computed in linear scale, but plotted in dB scale). Natu-
rally, a more relevant measure than the average SDR would be to use a value of
an SDR specification that results in a specific (e.g., 90 %) yield, as was the case
for the behavioral-level simulations presented in Chapter 3. However, only three
different chips have been characterized, which is too small a number to allow
reliable yield calculations. From Fig. 5.29, it can be concluded that the decom-
posed architecture suffers from less nonlinear distortion than the segmented
architecture, especially for small values of M . Qualitatively, this agrees well with
the behavioral-level simulation results presented in Chapter 3. The measurement
results indicate that the results from the behavioral-level simulations presented in
Chapter 3 are reasonable and that the decomposed DAC architecture is a viable
alternative to the traditional segmented architecture. As mentioned in Chapter 3,
designers should be aware of the different hardware complexities for the different
architectures and take this into account when choosing the proper architecture for
specific cases.
44
42
40
38 M-layer decomposed
36 (M+1)-bit segmented
34
0 1 2 3 4
M
Figure 5.29 Measured dual-tone signal-to-distortion ratio for M -layer decomposed and
( M + 1 )-bit segmented modes plotted as a function of M .
170
6 Conclusions
Selected aspects related to modeling, error correction, and implementation of
current-steering DACs implemented in CMOS technology were discussed in the
work presented in this thesis. Target applications considered were telecommuni-
cation applications such as the different DSL applications. As outlined in the the-
sis, the requirements on linearity for components in the transmit and receive
paths are hard in such applications. Therefore, the linearity properties of current-
steering DACs were of special importance in the presented work.
Behavioral-level models of different nonideal properties of a current-steering
DAC were discussed. Two different models with different computational com-
plexity of signal-dependent settling errors due to finite output impedance in cur-
rent sources were developed. Another dynamic error modeled in this work was
glitches due to asymmetry in the settling behavior when switching on and off a
current source. Further, a method for estimating the behavior of the modeled
glitches in the frequency domain was developed. Well-known models of static
errors, such as matching errors and the static nonlinearity caused by finite output
resistance in the current sources were also discussed.
The encoding used for the digital control word in a current-steering DAC has a
large influence on the circuit performance, e.g., in terms static linearity and
glitches. Two DAC architectures were developed related to this aspect. These
were denoted the decomposed and partially decomposed architectures and uti-
lized encoding strategies aiming at a high circuit performance by avoiding unnec-
essary switching of current sources. The developed architectures were compared
with the well-known binary-weighted and segmented architectures using behav-
ioral-level simulations. The number of bits in the control word was used as a sim-
ple measure of hardware complexity in the presented comparisons. Using this
measure, the simulation results indicated that the decomposed and partially
171
Conclusions
172
sources. The simulation results and the measurement results showed good agree-
ment and illustrated the limited efficiency of DEM techniques for situations
where dynamic errors dominate. The third circuit presented was a 14-bit dual
DAC with a doubly segmented architecture. The use of distributed biasing effi-
ciently suppressed the influence of linearly graded matching errors and a good
static linearity was obtained. The last chip presented was a 12-bit configurable
DAC capable of operating with different degrees of segmentation and decompo-
sition. This circuit enabled comparisons between the segmented and decomposed
architectures. Measurements performed on the configurable DAC showed the
same trends as the behavioral-level simulations presented earlier in the thesis and
indicated that the decomposed architecture is a viable alternative to the tradi-
tional segmented architecture.
173
Conclusions
174
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