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Proceedings of the 7th WSEAS International Conference on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL and SIGNAL PROCESSING (CSECS'08)

A 0.18m 3GHz True Single Phase Clocking Divider-by-3 Circuit


MASAYUKI IKEBE, JUNICHI MOTOHISA, and EIICHI SANO
Hokkaido University, Graduate School of Hokkaido University, Research Center For
Information Science and Technology Integrated Quantum Electronics
Kita-ku, Kita 14, Nishi 9, Sapporo Kita-ku, Kita 13, Nishi 8, Sapporo
JAPAN JAPAN

Abstract: We evaluated the use of a true single phase clocking (TSPC) circuit as a high-frequency divider-by-3
circuit. This divider consists of two TSPC D-flip-flops (D-FFs) with NOR gate logic circuitry. To achieve high-
speed operations as well as downsize the curcuit, the NOR functions are implemented into the TSPC D-FF. We
designed the divider using a 0.18-m RF CMOS process; the circuit is 100 200 m2 . In the measurements, we
confirmed the frequency divided by 3 at less than 3.14 GHz clock with 2.34 W.

KeyWords: SCL, TSPC, High frequency divider, Divider-by-3 circuit, High speed operation.

1 Introduction VDD

The field of broadband communications has been


rapidly expanding as the information society contin- QB
Q
ues to grow. Relatively large amounts of data can now
be handled with ease, and the exchange of image and D DB
music data is commonplace. In both wired and wire-
less communications, synchronous technology is in-
dispensable, and this technology is used on various :clk :clk
levels, such as the protocol and circuit levels. A di-
vider generates a fraction of the reference frequency,
and is used for a clock generator, a frequency synthe-
sizer, and other operations. (a) SCL circuit
An ordinary high frequency divider in a CMOS
process consists of source coupled logic- (SCL-)[1] D D Q D Q Q
D-flipflops (D-FFs). Since the SCL uses a differen- DB DB
SCL
QB DB
SCL
QB QB
tial operation, this circuit can perform high-speed op-
:clk :clk :clk :clk
erations at low amplitudes (Fig. 1). However, for a
:clk
divider-by-2 circuit, a D-FF with two SCL circuits is
required[2]. Moreover, the circuit configuration of :clk
the divider-by-3 circuit needs two D-FFs and addi- (b) SCL D-FF
tional logic circuits. Therefore, it has been difficult to
produce a high frequency divider with a small circuit
composition. Figure 1: Source-coupled logic circuit.
To overcome this problem, we propose new cir-
cuitry for high frequency division by 3 that has a
TSPC architecture that can be used for various appli- ing between CMOS devices. Like a dynamic logic cir-
cations. cuit that alternately performsPre-chargeandEval-
uate operations in parasitic capacitance, the TSPC
circuit operates a data fetch by using the pre-charge
2 True Single Phase Clocking divider and data hold performed by the high impedance
switching at the clock-signal timing[3, 4].
2.1 Operation of TSPC logic circuit Figure 2 shows the D-FF operation of a TSPC cir-
A TSPC logic circuit alternately generates Data- cuit. When = L, the parasitic capacitance of the in-
through state and Hold state operations by switch- put part is pre-charged along with the Data[t+1]. The

ISSN: 1790-5117 110 ISBN: 978-960-474-035-2


Proceedings of the 7th WSEAS International Conference on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL and SIGNAL PROCESSING (CSECS'08)

VDD as shown in Fig. 3 performes frequency dividing by 3.


In the circuit configuration, the cascade connec-

tion between the D-FF and the AND gate degrades
Q the frequency characteristic by adding additional de-
D lay to the circuitry. Therefore, the NOR function was
implemented into the TSPC D-FF without using the
optional AND gate circuit. A differential output is
achieved by using an additional inverter.

(a) TSPC circuit


3 Circuit Design and its Simulation
=L
VDD
We designed the divider by using a 0.18-m mixed
signal/RF CMOS process with one poly and six metal

D[t] layers. In this design, the output-impedance matching
was not set to 50 terminated, because we assume
D[t+1] D[t+1]
that the next stage circuit is a conventional logic cir-
cuit that has a high input impedance. The ratio of the
size of the p- and n-MOSFET was set to 3:1 due to the

mobility of the MOSFETs, but the actual sizes were
determined by the operating frequency. By the MOS-
> FETs size of the additional output inverter, we control
VDD the signal duty.
Figure 4 shows the size depending on the oper-
ating frequency. The power dissipation for a 3-GHz
D[t+1]
operation was 2.7 mW under typical conditions. We
D[t+1] D[t+1] confirmed that we could convert the frequency from 3

GHz into 1 GHz. The result of transition simulation is
shown in Fig. 5.
Based on the measurement setup, we also include
the result for 50 terminated configuration. We were
(b) D-FF operation able to confirm division operations up to 3.6 GHz us-
ing our design by conducting circuit simulations un-
der typical conditions. Figure 6 shows the layout of
Figure 2: True-single-phase-clocking circuit. the circuit When compared to a standard SCL config-
uration, we decreased the circuit area by 50% using
the SCL D-FF basis. Our circuit was 100 120 m2 .
n- and p-MOSFET in the output part simultaneously
turn off, and Date[t] is held in the parasitic capaci-
tance of the output line. When H, the state of 4 Measurement result
Data[t + 1] is determined and then the circuit outputs
it. The TSPC circuit runs as a D-FF which repeats the Figure 7 shows the measurement setup. One of the
above-mentioned operations. fabricated chips was placed on a probe station. The
transition characteristic was measured with an oscil-
2.2 TSPC divider-by-3 circuit loscope. The signal generator port was connected to
the divider input.
The proposed divider-by-3 circuit consists of sequen-
tial circuits based on the TSPC D-FFs and 2-AND
gate logic. Figure 3 shows the proposed circuit and In this measurement, an input signal with 7 dBm
its truth table. was applied to the divider through a cable with 50 -
This circuit achieves frequency division by using characteristic-impedance configuration. The mea-
logic operations. By AND logic, when only Q1[t] = 1 sured results are shown in Fig. 8 and 9. We confirmed
and Q2[t] = 0, Q2[t + 1] becomes 1. In other con- the operation of dividing by 3 at less than 3.14 GHz
dition, Q2[t + 1] becomes 0. Therefore the circuit with 2.34-mW. Moreover, when supply voltage VDD

ISSN: 1790-5117 111 ISBN: 978-960-474-035-2


Proceedings of the 7th WSEAS International Conference on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL and SIGNAL PROCESSING (CSECS'08)

Q1[t]=0 Q2[t]=0
D Q1 2AND D Q2
Q1[t+1]=1 Q2[t+1]=0
TSPC TSPC
Q1B Q2B
Q1[t+2]=1 Q2[t+2]=1
:clk :clk
Q1[t+3]=0 Q2[t+3]=0
:clk
(a) TSPC-divider-by-3 circuitry

VDD


Q1 Q2
Q2

Q2

Output buffer

(b) Actual TSPC-divider-by-3 circuit


Figure 3: TSPC-divider-by-3 circuit.

4.3
6 mA
5 Conclusion
4.2 We designed a high-frequency-TSPC divider-by-3 cir-
5 mA
4.1 cuit. This divider, which has two TSPC D-FFs, con-
Frequency (GHz)

4 mA verted a 3-GHz reference signal into a 1 GHz one


4 with only a 2.7 mW. The circuit was 100 120 m2
2.5 mA
3.9 and was constructed using a 0.18-m mixed signal/RF
CMOS process. We fabricated and measured the de-
3.8
signed divider. A 3-GHz operation of dividing by 3
1.5 mA: current
3.7 with 2.34 mW was confirmed by measurement.
3.6 Acknowledgements: This work is supported by
0 1 2 3 4 5 6
Scale factor VLSI Design and Education Center (VDEC), the Uni-
versity of Tokyo in collaboration with Cadence De-
sign Systems, Inc. and Agilent Technologies Japan,
Figure 4: Operating frequency vs. MOSFET size for Ltd.
current dissipation of proposed divider.

References:
[1] Sayfe Kiaei, San-Hwa Chee and Dave All-
stot, CMOS Source-Coupled Logic for Mixed-
= 2.3 V was given, operation frequency increased upto Mode VLSI, 1990 IEEE International Sympo-
4 GHz with 4.16 mW. sium on Circuits and Systems, vol. 2, pg. 1608-
1611, IEEE, 1990.
Since the measurement setup was a 50 - termi- [2] Behzad Razavi, Kwing F. Lee, and Ran H. Yan,
nation, the output amplitude was small. This result Design of High-Speed, Low-Power Frequency
was same as that in simulation one. However, during Dividers and Phase-Locked Loops in Deep Sub-
the measurement, when an input signal of more than micron CMOS IEEE Journal of Solid-State Cir-
3.14 GHz was given to the circuit, it worked as a di- cuits, VOL. 30, NO. 2, pp. 101-109, 1995
vider by 4. The main reason for this unusual operation [3] Y. Ji-ren, I. Karsson, and C. Svenson A
is the parasitic capacitance of the feedback line. If a True Single-Phase-Clock Dynamic CMOS Cir-
signal delay occurs, the updating of the next stage also cuit Tectilque, IEEE Journal of Solid-State Cir-
falls behind. cuits, VOL. SC-22,NO. 5, pp. 899-901, 1987.

ISSN: 1790-5117 112 ISBN: 978-960-474-035-2


Proceedings of the 7th WSEAS International Conference on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL and SIGNAL PROCESSING (CSECS'08)

[4] R. Sundblad and C. Svensson, A True Single-


1.8 Phase-Clock Dynamic CMOS Circuit Tec-
tilque, IEEE Trans. Computer-A zded Des., vol.
CAD-6, pp. 282-289, 1987.
Voltage (V)

Probe
Signal station
Oscilloscope
generator
50 50
DUT
0
2.0 2.1 2.2
Time (nsec)
Figure 7: Measurement setup.
(a) Open

0.5
1.8

AC voltage (V)
Voltage (V)

2.0 2.1 2.2


Time (nsec) -0.5
(b) 50 terminated. 0 1.0 2.0
Time (nsec)

Figure 5: Transition simulation results.


Figure 8: Measurement results of proposed circuit.

VDD VDD
4.2

4
2.08 mA
3.8
100 m 1.86 mA
3.6
1.68 mA
120 m

CLK 3.4 1.34 mA


OUT 1.58 mA
3.2
1.29 mA: current
3
1.7 1.9 2.1 2.3
Supply voltage (V)

Figure 9: Maximum Operating frequency vs. supply


Figure 6: Layout of proposed divider. voltage for current dissipation.

ISSN: 1790-5117 113 ISBN: 978-960-474-035-2