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EE Dept, IIT Bombay

EE 712 Embedded Systems Design
Spring 2010 / Mid-semester Examination
Saturday, 20.Feb.2009, 1730 -- 1930
Note: Answer all the FOUR questions. Marks: 5 + 5 + 10 +10 = 30.

Q.1 A) Briefly compare the merits and demerits of single-ended and differential
signal interconnections.
B) How should an unused CMOS input be connected and why?
C) Briefly compare the uses of the I/O pins with open drain, internal passive
pull-up, and tri-state outputs.
D) Give the circuit for interfacing a key, with hardware debouncing, to a CMOS
input. The input should be low when the switch is closed. Assume that bounce
can last up to 5 ms. Taking a 10 F capacitor, find the appropriate value of
[1+1+1+2 = 5 marks]
Q.2 A) An array of 8 LED's is to be interfaced to output pins which can source as
well as sink current. Show the circuit for scanned interfacing, with first priority
to minimize the number of pins and the second priority to minimize the number
of resistors. Select the appropriate value of the current limiting resistors,
assuming an average current of 5 mA for a properly lit LED.
B) Redraw the circuit for the above LED interfacing, assuming all the outputs to
be open drain type. While the first priority remains minimizing the number of
output pins, the second priority is to minimize the external transistors.
C) Briefly describe the key advantages and challenges in RISC architecture.
[2+2+1 = 5 marks]
Q.3 Explain the following with illustrative examples for the ARM architecture:
A) What is the advantage of using PC relative addressing for loading a constant
in a register from a literal pool? Illustrate by an assembly language example. (No
pseudo instructions are to be used).
B) How are calls and returns managed in an ARM based system? Explain with
the example of a main routine calling a subroutine, which then calls another
subroutine. Show how the return addresses can be saved in a stack using load
and store instructions. (Assume that we want to use a pre-decrement, post-
increment kind of stack).
C) Describe the sequence of events which take place after an FIQ interrupt
occurs. How does the interrupt handler return control to the program which was
running when the interrupt occurred? What are the facilities available in FIQ
mode which are not there in the ordinary interrupt mode?
D) Suppose an ARM based system is running in the Thumb state when an
interrupt occurs. The interrupt service routine uses the ARM instruction set.
Explain how the change over occurs between the two instruction sets as we enter
the interrupt service routine and when we return from it.
[2+3+2+3 = 10 marks]
Q.4 In an application, the user can take any of the following actions:
(a) define parameter 1,
(b) define parameter 2,
(c) calculate a value which depends on these two parameters.
The parameters can be defined in any order. If the user asks for a calculation
without defining both parameters, an error message is issued. If both parameters
were defined, asking for a calculation prints the results and makes both
parameters undefined. Defining a parameter again before asking for a
calculation overwrites the previous value of the parameter with the new one.
Construct a state diagram for this application, assuming user actions (a), (b) or
(c) to be the external inputs. The state diagram should use tests and actions,
which conform to the following restrictions:
Each state is associated with a unique test.
A test can return only a yes or no answer.
Associated with either answer is an action and a next state
Give only the state diagram and the associated data structure. No program needs
to be written.
[10 Marks]


ARM Data Processing Instructions:

Instr{Cond.}{S} Rd, {Rn,} OP2: OP2 through shifter
MOV (move), MVN (move not),
BIC (Bit Clear- Rd=Rn AND NOT OP2
RSB (Reverse Subtract), RSC (Rev. Subtr with carry)
TST (AND to set flags, discard result)
TEQ(EOR to set flags, discard result)
CMP (Subtract to set flags, discard result)
CMN (Add to set flags, discard result)
Multiply: 32bit
MUL{Con}{S} Rd, Rm, Rs : (Rd=Rm*Rs)
MLA{Con}{S} Rd, Rm, Rs, Rn : (Rd=Rn+Rm*Rs)
Long Multiply:
SMULL (signed mult), SMLAL (signed multiply accumulate), UMULL (unsigned mult),
(unsigned multiply accumulate).
Status Register Access:
MRS{Con} Rd, SR : (Status reg to reg),
MRS{Con} SR, Rd : (reg to status reg),
where status reg SR is either CPSR or SPSR.
Load-Store Instructions:
LDR, STR with and without pointer update
LDM, STM (Load Store Multiple).
LDR R2, [R5,# 8] : Load R2 from address R5+8
STR R2, [R5] # 8 : Store R2 at address R5, then R5=R5+8
LDR R2, [R5, #-1]! : R5=R5-1, load R2 from address=updated R5

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