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EE477L
MOS VLSI Circuit Design
Introduction
System-on-Chip, 2002
20 to 30 million transistors
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
First transistor
Bell Labs, 1947
Bipolar logic
1960s
1971
1000 transistors
1 MHz operation
A B
Voltage B
Voltage
Source
Source
L = A and B L = A or B
X Y Z F
0 0 0 0
X Y F 0 0 1 0
0 1 0 0
X 0 0 0 X
F F 0 1 1 0
Y 0 1 0 Y
1 0 0 0
1 0 0
F=XY Z
F=XYZ 1 0 1 0
1 1 1 1 1 0 0
1 1 1 1
X Y Z F
0 0 0 0
X Y F 0 0 1 1
X 0 1 0 1
0 0 0 X
F F 0 1 1 1
Y 0 1 1 Y
1 0 0 1
1 0 1 Z
F=X+Y F=X+Y+Z 1 0 1 1
1 1 1 1 1 0 1
1 1 1 1
2-input OR 3-input OR
Shahin Nazarian/EE477L/Fall 2012 13
NOT Gate
X F
1 0
X F
0 1
F=X
X X
Z Z
Y Y
NAND NOR
Z X Y Z X Y
X Y Z X Y Z X Y Z X Y Z
0 0 0 0 0 1 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 1 0 0
1 1 1 1 1 0 1 1 1 1 1 0
AND NAND OR NOR
True if NOT ALL True if NOT ANY
inputs are true input is true
X X
Z Z
Y Y
XOR XNOR
Z X Y Z X Y
X Y Z X Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
True if an odd # of inputs are true True if an even # of inputs are true
= True if inputs are ___________ = True if inputs are ___________
0 0 0 0 1
0 0 1 1 1
Inputs Logic Outputs
Circuit
1 1 1 0 0
Cout Cin 0 1
110 X Y
0110 = X
1 Cout Full Cin 0
Adder
+ 0111 = Y S
1101
Shahin Nazarian/EE477L/Fall 2012 0 19
Functions & Logic Networks
X Y Ci Co
0 0 0 0 X
0 0 1 0 Y
0 1 0 0
0 1 1 1 Co
Ci
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1 Level 1 Level 2
X Y Ci Co XY XCi YCi
0 0 0 0 0 0 0 X
0 0 1 0 0 0 0 Y
0 1 0 0 0 0 0
0 1 1 1 0 0 1 Co
Ci
1 0 0 0 0 0 0
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 1 1 Level 1 Level 2
A3A2A1A0 = A A3 B3 A2 B2 A1 B1 A0 B0
To build a Mux
Decode the _______ bits and include the
corresponding data input
Finally _______ all the first level outputs
together
0 1
1 0
I1 I0
1 0
1 0
Initial Values
1 P
0 C 0
1
1 P 0
0 0
1 R
1 V 0
0 B
0 T
1 P
1
0 C 0
1
1 P 1 0
0 1 0
1 R
0 1 V 1 0
0 B 4 Levels of Logic
0 T
0
1 P 1 1
0 C 0
0 0
1
1 P 0
0 0
1 R
1 V 0
0 B 2 Levels of Logic
0 T
X Y X Y X Y X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
1 1 1 1
Shahin Nazarian/EE477L/Fall 2012 29
Delay Example (Cont.)
1 0 1 0 1 0 1 1
X Y X Y X Y X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
1 1 1 1
Shahin Nazarian/EE477L/Fall 2012 30
Delay Example (Cont.)
The first adder updates its carry and sum but
meanwhile other adders output incorrect values due to
the lack of correct carries
New inputs: 1 _
1111 = X Time
+ 0001 = Y 1
0000
Old inputs:
1 0 1 0 1 0 1 1
X Y X Y X Y 1 X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
1 1 1
0 0 0 0
Shahin Nazarian/EE477L/Fall 2012 31
Delay Example (Cont.)
X Y X Y 1 X Y 1 X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
0 1
1 1
0 0 0 0
Shahin Nazarian/EE477L/Fall 2012 32
Delay Example (Cont.)
X Y 1 X Y 1 X Y 1 X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
0 1 0 1
1
0 0 0 0
Shahin Nazarian/EE477L/Fall 2012 33
Delay Example (Cont.)
New inputs: 1 _
1111 = X Time
+ 0001 = Y 4
0000
Old inputs:
1 0 1 0 1 0 1 1
1 X Y 1 X Y 1 X Y 1 X Y
0 0 0 0
Cout Full Cin Cout Full Cin Cout Full Cin Cout Full Cin 0
Adder Adder Adder Adder
S S S S
0 1 0 1 0 1
0 0 0 0
Shahin Nazarian/EE477L/Fall 2012 34
Sequential Devices (Registers)
___________ outputs are only a function of the
current inputs
Outputs only depend on what the inputs are right
now, not one second ago
This implies they have no memory (cant remember
a value)
_________ logic devices provide the ability to retain or
remember a value by itself (even after the input is
changed or removed)
Usually have a controlling signal that indicates when
the device should update the value it is
remembering vs. when it should simply remember
that value
This controlling signal is usually the _____ signal
Shahin Nazarian/EE477L/Fall 2012 35
Clock Signal
Alternating high/low voltage
pulse train
Clock Signal
2.8 GHz
= 2.8*109 cycles per second
Cycle measurement = 0.357 ns/cycle
Processor
# of cycles per second (e.g.
2.8 GHz = 2.8 * 109 cycles
per second)
clk
d(t) D Q q(t)
d(t)
D-FF
Clock Signal
CLK q(t)
CLK
CLR
register to be initialized to D1 D
SET
Q Q1
0s CLR
CLR
1
CLK /AR Di Qi*
SET
D3 D Q Q3
X 0 X 0
CLR
1,0 1 X Qi
1 0 0 /AR
CLK
1 1 1
4-bit Register
Shahin Nazarian/EE477L/Fall 2012 39
Registers
CLK
/AR
D[3 :0 ] 0010 0011 0100 0101 0110 0111 1000 1001 1010
Inputs
Sequential Logic
Sequential Logic
Register
Inputs
Combo Combo Combo
Logic Logic Logic
Combinational Sequential
Logic CLK Logic CLK CLK
Manipulates Synchronizes &
(Processes) Data Save Data
Stage 1 Stage 2
Stage 1 Stage 2
Clock 0 A[0] + B[0]
Clock 1 A[1] + B[1] (A[0] + B[0]) / 4
Clock 2 A[2] + B[2] (A[1] + B[1]) / 4
Shahin Nazarian/EE477L/Fall 2012 43
Need for Registers
5 ns
Signal i
Register
Register
Signal j
2 ns
CLK CLK
Adder (+)
Register
Q
CLK
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Shahin Nazarian/EE477L/Fall 2012 49
Evolution of Memory Capacity
1,000,000 10,000,000
Productivity
58%/Yr. compounded
10,00010 Complexity growth rate
100
100,000
1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
x x Productivity growth rate
x
0.01
10 0.1
100
0.001
1 0.01
10
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Source: Sematech
Single die
Wafer
Going up to 12 (30cm)
From http://www.amd.com
Shahin Nazarian/EE477L/Fall 2012 55
Cost per Transistor
cost:
-per-transistor
1
0.1 Fabrication capital cost per transistor (Moores law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
defects per unit area die area
die yield 1
is approximately 3
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave p(t )dt isupply t dt
T t T t
Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK
vAinN CVLout
CL
NMOS
NETWORK
T T Vdd
E 0 1 = P t dt = V dd i sup ply t dt = Vdd CL dV out = C L V dd 2
0 0 0
T T Vdd
1 2
E ca p = P cap t dt = V out i ca p t dt = C L Vout dVout = --- C V dd
2 L
0 0 0
v( t) VDD
i( t)