Basic HDL Coding

Techniques
Part 1

NOTES

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 Printable Content
You can download a printable PDF version of this module from:
ftp://ftp.xilinx.com/pub/documentation/education/fpga23001-rel-print.zip

Basic HDL Coding Techniques - 2 2008 Xilinx, Inc. All Rights Reserved

NOTES
Remember, you can download a printable PDF version of this module from the FTP site
noted here.

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 Objectives
After completing this module, you will be able to:
Specify Xilinx resources that may need to be instantiated
Identify some basic design guidelines that successful FPGA designers follow
Select a proper HDL coding style for fast, efficient circuits, including:
Combinatorial functions
Register functions

Note: The guidelines in this module are not specific to any particular synthesis
tool or Xilinx FPGA family

Basic HDL Coding Techniques - 3 2008 Xilinx, Inc. All Rights Reserved

NOTES
By the completion of this module, you will be able to list at least two uses for the
Architecture Wizard, identify two features of the Floorplan Editor, and create quality pin
assignments for your Xilinx FPGA.

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 Outline

Achieving Breakthrough Performance

Basic Design Guidelines
Coding for Combinatorial Logic
Register Inference
Summary

Basic HDL Coding Techniques - 4 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Breakthrough Performance
Three steps to achieve breakthrough performance
1. Utilize embedded (dedicated) resources
Dedicated resources are faster than a LUT/flip-flop
implementation and consume less power
Typically built with the CORE Generator tool and
instantiated Virtex
Virtex-5 FPGA
Virtex-5 FPGA
DSP48, FIFO, block RAM, ISERDES, OSERDES,
PowerPC processor, EMAC, and MGT, for example
2. Write code for performance Performance Meter
Use synchronous design methodology
Ensure the code is written optimally for critical paths
Pipeline
3. Drive your synthesis tool
Try different optimization techniques
Add critical timing constraints in synthesis
Preserve hierarchy
Apply full and correct constraints
Use High effort

Basic HDL Coding Techniques - 5 2008 Xilinx, Inc. All Rights Reserved

NOTES
Applying full and correct constraints refers to applying constraints for all clocks in the
design. Additionally, false paths and multicycle paths should be correctly constrained, as
should the I/O.
The timing closure flow chart was created to help achieve breakthrough performance.

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 Use Embedded Blocks
Embedded block timing is correct by construction
Not dependent on programmable routing
Offers as much as 3x the performance
of soft implementations XtremeDSP Solution
Slice
Uses less power
Examples
FIFO at 500 MHz
DSP slices at 500 MHz
Smart RAM FIFO
PowerPC processor at
702 DMIPS
PowerPC Processor

Basic HDL Coding Techniques - 6 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Timing Closure

Basic HDL Coding Techniques - 7 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Outline

Achieving Breakthrough Performance

Basic Design Guidelines
Coding for Combinatorial Logic
Register Inference
Summary

Basic HDL Coding Techniques - 8 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Instantiation versus
Inference
Instantiate a component when you must dictate exactly which resource is
needed
The synthesis tool is unable to infer the resource
The synthesis tool fails to infer the resource
Xilinx recommends inference whenever possible
Inference makes your code more portable
Xilinx recommends using the CORE Generator software to create
functions such as Arithmetic Logic Units (ALUs), fast multipliers, and
Finite Impulse Response (FIR) filters for instantiation
Xilinx recommends using the Architecture Wizard utility to create DCM,
PLL, and BUFG instantiations

Basic HDL Coding Techniques - 9 2008 Xilinx, Inc. All Rights Reserved

NOTES
Instantiation: Directly referencing a library primitive or macro in your HDL.
Inference: Writing a Register Transfer Level (RTL) description of circuit behavior that the
synthesis tool converts into library primitives.

Why instantiate?
Instantiation is useful when you cannot infer the component. For example, inferring the
DCM component of the Virtex-II FPGA is not possible; hence, instantiating the DCM
block is the only way to use it.

Components that must be instantiated are listed later in this module.

Appendix C contains examples of inferring various Xilinx resources. (The appendixes are
not included in the printed workbook, but are available via
ftp://ftp.xilinx.com/pub/documentation/education/fpga23000-9-rev1-xlnx_lab_files.zip.)

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 FPGA Resources
Can be inferred by all synthesis Can be inferred by some synthesis
tools tools
Shift register LUT (SRL16/ Memories
SRLC16) Global clock buffers (BUFGCE,
F5, F6, F7, and F8 multiplexers BUFGMUX, BUFGDLL)
Carry logic Some complex DSP functions
MULT_AND Cannot be inferred by any synthesis
Multipliers and counters using the tools
DSP48 SelectIO (differential) interface
Global clock buffers (BUFG) Output DDR registers
SelectIO (single-ended) interface DCM / PLL
I/O registers (single data rate) Local clock buffers (BUFIO, BUFR)
Input DDR registers

Basic HDL Coding Techniques - 10 2008 Xilinx, Inc. All Rights Reserved

NOTES
Appendix C contains information for specific synthesis tools. (The appendixes are not
included in the printed workbook, but are available via
ftp://ftp.xilinx.com/pub/documentation/education/fpga23000-9-rev1-xlnx_lab_files.zip.)

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 Suggested Instantiation
Xilinx recommends that you instantiate the following elements
Memory resources
Block RAMs specifically (use the CORE Generator software to build large
memories)
SelectIO interface resources
Clocking resources
DCM, PMCD (use the Architecture Wizard)
IBUFG, BUFGMUX, BUFGCE
BUFIO, BUFR

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NOTES

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 Suggested Instantiation
Why does Xilinx suggest
this? START
Xilinx wrapper top_xlnx
UP

Easier to port your HDL OBUF _GTL

to other and newer IBUFG DCM BUFG
Top-Level
Top-Level
technologies OBUF _GTL

Block
Block
Fewer synthesis IBUF _SSTL2_I
OBUF _GTL

constraints and
attributes to pass on
Keeping most of the
attributes and constraints in the Xilinx User Constraints File (UCF) keeps it simpleone file
contains critical information
Create a separate hierarchical block for instantiating these resources
Above the top-level block, create a Xilinx wrapper with instantiations specific to Xilinx
Instead use VHDL configuration statements or put wrappers around each instantiation
This maintains hierarchy and makes it easy to swap instantiations

Basic HDL Coding Techniques - 12 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Hierarchy Management
Synplify, Precision, and XST software
The basic settings are
Flatten the design: Allows total combinatorial optimization across all
boundaries
Maintain hierarchy: Preserves hierarchy without allowing optimization of
combinatorial logic across boundaries
If you have followed the synchronous design guidelines, use the setting
-maintain hierarchy
If you have not followed the synchronous design guidelines, use the
setting -flatten the design.
Consider using the keep attribute to preserve nodes for testing
Your synthesis tool may have additional settings
Refer to your synthesis documentation for details on these settings

Basic HDL Coding Techniques - 13 2008 Xilinx, Inc. All Rights Reserved

NOTES
To access hierarchy control:
Synplify software: SCOPE Constraints Editor
Synplify also has an additional setting: Maintain hierarchy but allow optimization. This
setting allows combinatorial logic to be optimized while maintaining hierarchy in the netlist
(setting in Synplify is firm).
Precision software: After compiling the design, right-click Modules in the Design Hierarchy
window and select Preserve Hierarchy or Flatten Hierarchy.
XST: Turn on the Advanced Property Display level in the Edit Preferences dialog box.
Then look under Properties for the Synthesize process Synthesis Options tab Keep
Hierarchy.

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 Hierarchy Preservation
Benefits
Easily locate problems in the code based on the hierarchical instance
names contained within static timing analysis reports
Enables floorplanning and incremental design flow
The primary advantage of flattening is to optimize combinatorial logic
across hierarchical boundaries
If the outputs of leaf-level blocks are registered, there is generally no need
to flatten

Basic HDL Coding Techniques - 14 2008 Xilinx, Inc. All Rights Reserved

NOTES
Registering outputs of each leaf-level block is part of the synchronous design techniques
methodology. Registering the output boundaries helps because you know the delays from
one block to the next. That is, the delays are not variable based on combinatorial outputs.
Logic cannot be optimized across a registered boundary. Therefore, if you do register
outputs, you know the delay is minimized from one hierarchical or functional block to the
next and you also know that no logic optimization can occur across hierarchical domains.
In addition to the benefits listed above, preserving hierarchy has the added benefit of
limiting name changes to registersthus, the element names used in a UCF will generally
not change. If you flatten the design, the register and element names and hierarchical path
and references in a flattened design can change from one iteration to the next. In this case,
maintaining the UCF can be quite a burden.
However, preserving hierarchy can prevent register balancing (retiming) and register
duplication. Nevertheless, the benefits of preserving hierarchy generally outweigh the
benefits of flattening except when you have combinatorial outputs.
And in general, preserve hierarchy for large designs. For smaller designs, preserve the
hierarchy if you registered leaf-level outputs; otherwise, you might consider flattening the
design. If you flatten the design, remember the extra burdens of name changes (UCF and
static timing analysis) from one iteration to the next and the limits on floorplanning.

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 Outline

Achieving Breakthrough Performance

Basic Design Guidelines
Coding for Combinatorial Logic
Register Inference
Summary

Basic HDL Coding Techniques - 15 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Multiplexers
Multiplexers are generated from IF and CASE statements
IF/THEN statements generate priority encoders
Use a CASE statement to generate complex encoding
There are several issues to consider with a multiplexer
Delay and size
Affected by the number of inputs and number of nested clauses to an IF/THEN
or CASE statement
Unintended latches or clock enables
Generated when IF/THEN or CASE statements do not cover all conditions
Review your synthesis tool warnings
Check by looking at the component with a schematic viewer

Basic HDL Coding Techniques - 16 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 IF/THEN Statement Answer
Priority Encoder
Most critical input listed first
Lease critical input listed last

do_e 0
0
do_c 1 0
do_b 1 0 oput
do_a 1
IF (crit_sig) THEN oput <= do_d ; cond_c do_d 1
cond_b
ELSIF cond_a THEN oput <= do_a; cond_a
crit_sig
ELSIF cond_b THEN oput <= do_b;
ELSIF cond_c THEN oput <= do_c;
ELSE oput <= do_e;
END IF;

Basic HDL Coding Techniques - 17 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Avoid Nested IF and IF/ELSE
Statements
Nested IF or IF/THEN/ELSE statements form priority encoders
CASE statements do not have priority
If nested IF statements are necessary, put critical input signals on the
first IF statement
The critical signal ends up in the last logic stage

Basic HDL Coding Techniques - 18 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 CASE Statements
CASE statements in a combinatorial process (VHDL) or always
statement (Verilog)
Latches are inferred if outputs are not defined in all branches
Use default assignments before the CASE statement to prevent latches
CASE statements in a sequential process (VHDL) or always statement
(Verilog)
Clock enables are inferred if outputs are not defined in all branches
This is not wrong, but might generate a long clock enable equation
Use default assignments before CASE statement to prevent clock enables

Basic HDL Coding Techniques - 19 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 CASE Statements
Register the select inputs if possible (pipelining)
Can reduce the number of logic levels between flip-flops
Consider using one-hot select inputs
Eliminating the select decoding can improve performance
Determine how your synthesis tool synthesizes the order of the select
lines
If there is a critical select input, this input should be included last in the
logic for fastest performance

Basic HDL Coding Techniques - 20 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 CASE Statement
module case_binary (clock, sel, data_out, in_a,
in_b, in_d, in_c, in_e, in_f) ;
This Verilog code describes a 6:1
multiplexer with binary-encoded input clock ;
input [2:0] sel ;
select inputs input in_a, in_b, in_c, in_d, in_e, in_f ;
output data_out ;
This synthesized to 3 LUTs and 2 reg data_out;
F5 muxes
always @(posedge clock)
Longest path = 1 LUT + 2 F5 begin
case (sel)
The advantage of using the dont 3'b000 : data_out <= in_a;
care for the default, is that the 3'b001 : data_out <= in_b;
3'b010 : data_out <= in_c;
synthesizer will have more flexibility 3'b011 : data_out <= in_d;
to create a smaller, faster circuit 3'b100 : data_out <= in_e;
3'b101 : data_out <= in_f;
How could the code be changed default : data_out <= 1'bx;
endcase
to use one-hot select inputs? end
endmodule

Basic HDL Coding Techniques - 21 2008 Xilinx, Inc. All Rights Reserved

NOTES

VHDL version (entity declaration omitted):

process (clock)
begin
if (clockevent and clock = 1) then
case (sel) is
when 000 => data_out <= in_a;
when 001 => data_out <= in_b;
when 010 => data_out <= in_c;
when 011 => data_out <= in_d;
when 100 => data_out <= in_e;
when 101 => data_out <= in_f;
when others => data_out <= X;
end case;
end if;
end process;

This synthesized to (3) LUTs and (2) Mux F5 with only 3 logic level delay (1 Lut + 2 F5).

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 CASE Statement
module case_onehot (clock, sel, data_out, in_a,
in_b, in_d, in_c, in_e, in_f) ;
This is the same code with one-hot
input clock ;
select inputs input [5:0] sel ;
This synthesized to 8 LUTs and 1 input in_a, in_b, in_c, in_d, in_e, in_f ;
output data_out ;
F5 mux reg data_out;
Longest path = 2 LUTs + 1 F5 always @(posedge clock)
This yields no benefit for 6-1 mux, begin
case (sel)
but when you get larger the benefit 6'b000001 : data_out <= in_a;
is significant 6'b000010 : data_out <= in_b;
6'b000100 : data_out <= in_c;
Enumerated types allow you to 6'b0010 00: data_out <= in_d;
6'b010000 : data_out <= in_e;
quickly test different encoding 6'b100000 : data_out <= in_f;
and makes simulation more default : data_out = 1'bx;
endcase
readable end
endmodule

Basic HDL Coding Techniques - 22 2008 Xilinx, Inc. All Rights Reserved

NOTES

VHDL version (entity declaration omitted):

process (clock)
begin
if (clockevent and clock = 1) then
case (sel) is
when 000001 => data_out <= in_a;
when 000010 => data_out <= in_b;
when 000100 => data_out <= in_c;
when 001000 => data_out <= in_d;
when 010000 => data_out <= in_e;
when 100000 => data_out <= in_f;
when others => data_out <= X;
end case;
end if;
end process;

This implementation synthesizes to (8) LUTs and (1) mux F5. The worst case path includes
(2) LUTs and (1) mux F5. This is a slower implementation than the binary version (previous
slide) but try this as a 20-to-1 mux. Then you will see significant performance improvement
over
Basic the Coding
HDL OHE. Techniques www.xilinx.com 22
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 Other Basic Performance Tips

Avoid high-level loop constructs

Synthesis tools may not produce optimal results
Order and group arithmetic and logical functions and operators
A <= B + C + D + E; should be: A <= (B + C) + (D + E)
Use synchronous reset
Better system control

Basic HDL Coding Techniques - 23 2008 Xilinx, Inc. All Rights Reserved

NOTES
Avoiding inadvertent latch inference can easily be accomplished with default assignments.

// Default assignments before if-then-else or case statement

// Now, all outputs are assigned in every branch avoiding
// inadvertent latch inference
out1 = 1b0;
out2 = input2;
out3 = out3_registered;
if (a = b)
out1 = a;
else if (a = c)
out2 = b;
else if (a = d)
out3 = c;

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 Synchronous Design
Rewards
Always make your design synchronous
Recommended for all FPGAs
Failure to use synchronous design can potentially
Waste device resources
Not using a synchronous element will not save silicon and it wastes money
Waste performance
Reduces capability of end products; higher speed grades cost more
Lead to difficult design process
Difficult timing specifications and tool-effort levels
Cause long-term reliability issues
Probability, race conditions, temperature, and process effects
Synchronous designs have
Few clocks
Synchronous resets
No gated clocks; instead, clock enables

Ken Chapman
Basic HDL Coding Techniques - 24 2008 Xilinx, Inc. All Rights Reserved (Xilinx UK) 2003

NOTES
The Spartan devices have been designed with the idea that synchronous design techniques
should be used. Synchronous design techniques will also help the software tools and lead to
higher performance implementations in lower speed grade (lower cost) devices.

All the challenging silicon design problems of balanced (near zero skew) clock trees and
synchronous elements have already been solved by Xilinx when it manufactures the devices.
Because the clock networks exist, and every block can (or has to) be synchronous, make the
most of the device and design synchronously.

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 Outline

Achieving Breakthrough Performance

Basic Design Guidelines
Coding for Combinatorial Logic
Register Inference
Summary

Basic HDL Coding Techniques - 25 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Inferred Register Examples
Ex 1 D Flip-Flop Ex 2. D Flip-Flop with Asynch Preset
always @(posedge CLOCK)
always @(posedge CLOCK or
Q = D_IN; posedge PRESET)
if (PRESET)
Q = 1;
else
Q = D_IN;
Ex 3. D Flip-Flop with Asynch Reset Ex 4. D Flip-Flop with Synch Reset

always @(posedge CLOCK always @(posedge CLOCK)

or posedge RESET) if (RESET)
if (RESET) Q = 0;
Q = 0; else
else Q = D_IN;
Q = D_IN;

Basic HDL Coding Techniques - 26 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Clock Enables
Coding style will determine if clock enables are used

VHDL Verilog
FF_AR_CE: process(ENABLE,CLK) always @(posedge CLOCK)
begin if (ENABLE)
if (CLKevent and CLK = 1) then Q = D_IN;
if (ENABLE = 1) then
Q <= D_IN;
end if;
end if;
end process

Basic HDL Coding Techniques - 27 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Outline

Achieving Breakthrough Performance

Basic Design Guidelines
Coding for Combinatorial Logic
Register Inference
Summary

Basic HDL Coding Techniques - 28 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Apply Your Knowledge
What is the approach presented here for obtaining breakthrough
performance?

Compare CASE and IF/THEN statements when creating multiplexers

What problem occurs with nested CASE and IF/THEN statements?

Basic HDL Coding Techniques - 29 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Answers
What is the approach presented here for obtaining breakthrough
performance?
Three steps to achieve breakthrough performance
1. Utilize embedded (dedicated) resources
Performance by construction
DSP48, FIFO, block RAM, ISERDES, OSERDES, PowerPC processor,
EMAC, and MGT, for example
2. Write code for performance
Pipeline
Xilinx FPGAs have abundant registers: one register per LUT
3. Drive your synthesis tool
Apply full and correct constraints
Utilize optional settings
Use High effort

Basic HDL Coding Techniques - 30 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Answers
Compare CASE and IF/THEN statements when creating multiplexers
Both types of statements produce multiplexers
CASE statements produce smaller/faster circuits in general
IF/THEN statements are more flexible but create a priority encoder
IF/THEN statements may be faster for late arriving signals
What problem occurs with nested CASE and IF/THEN statements?
Nested CASE and IF/THEN statements can generate long delays due to
cascaded functions

Basic HDL Coding Techniques - 31 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Summary
Use as much of the dedicated hardware resources as possible to ensure
optimum speed and device utilization
Plan on instantiating clocking and memory resources
Try to use the Core Generator tool to create optimized components that
target dedicated FPGA resources (BRAM, DSP48, and FIFO)
Maintain your design hierarchy to make debugging, simulation, and
report generation easier

Basic HDL Coding Techniques - 32 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Summary
CASE and IF/THEN statements produce different types of multiplexers
CASE statements tend to build logic in parallel while IF/THEN statements
tend to build priority encoders
Avoid nested CASE and IF/THEN statements
You should always build a synchronous design for your FPGA
Inferring many types of flip-flops from HDL code is possible
Synchronous sets/resets are preferred

Basic HDL Coding Techniques - 33 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Where Can I Learn More?
Synthesis & Simulation Design Guide
www.xilinx.com/support Documentation Search for Synthesis &
Simulation Design Guide
User guides
www.xilinx.com/support Documentation Search for User Guides
XST User Guide
www.xilinx.com/support Documentation Search for XST
This guide has example inferences of many architectural resources
ISE online help
Start Xilinx ISE 10.1i Documentation Software Manuals

Basic HDL Coding Techniques - 34 2008 Xilinx, Inc. All Rights Reserved

NOTES

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 Printable Content
You can download a printable PDF version of this module from:
ftp://ftp.xilinx.com/pub/documentation/education/fpga23001-rel-print.zip

Basic HDL Coding Techniques - 35 2008 Xilinx, Inc. All Rights Reserved

NOTES
Remember, you can download a printable PDF version of this module from the FTP site
noted here. Note that this module is also included in the appendix of the workbook for the
Designing for Performance course.

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1-877-XLX-CLAS
 Give Us Your Feedback
Thank you for viewing this recorded e-Learning (REL)
Please give us your feedback on this module, while you are still thinking
about this recording
Go to www.xilinx.com/training/eval-rel
Simply follow the instructions and submit the evaluation
This will only take a couple of minutes

Basic HDL Coding Techniques - 36 2008 Xilinx, Inc. All Rights Reserved

NOTES
Please give us your feedback on this module. Simply follow the instructions you see here.
Finally, thanks for listening to this recorded e-Learning on the Architecture Wizard and the
Floorplan Editor. I hope you found this worthwhile. My name is Frank Nelson. I look
forward to meeting you in the Fundamentals of FPGA Design course

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