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Version D-2010.03-SP1 for sparcOS5 -- Apr 26, 2010
Copyright (c) 1988-2010 by Synopsys, Inc.
ALL RIGHTS RESERVED
This software and the associated documentation are confidential and
proprietary to Synopsys, Inc. Your use or disclosure of this software
is subject to the terms and conditions of a written license agreement
between you, or your company, and Synopsys, Inc.
The above trademark notice does not imply that you are licensed to use
all of the listed products. You are licensed to use only those products
for which you have lawfully obtained a valid license key.
Initializing...
set link_library *
*
set target_library [list /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class
.db]
/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db
set synthetic_library [list /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/cl
ass.sdb ]
/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb
set link_library [concat $link_library $synthetic_library $target_library]
* /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb /opt/CAD/Synopsys/
Current/Synthesis/libraries/syn/class.db
######################### ADD SCAN CHAIN SCRIPT ##############################
#
################################################################################
#
# Read in the RTL Design
################################################################################
#
analyze -format vhdl bigapple.vhd
Running PRESTO HDLC
Compiling Entity Declaration MUX
Compiling Architecture MUX_ARC of MUX
Warning: ./bigapple.vhd:20: The architecture mux_arc has already been analyzed.
It is being replaced. (VHD-4)
Compiling Entity Declaration COMPARATOR
Compiling Architecture COMPARATOR_ARC of COMPARATOR
Warning: ./bigapple.vhd:48: The architecture comparator_arc has already been an
alyzed. It is being replaced. (VHD-4)
Compiling Entity Declaration SUBTRACTOR
Compiling Architecture SUBTRACTOR_ARC of SUBTRACTOR
Warning: ./bigapple.vhd:79: The architecture subtractor_arc has already been an
alyzed. It is being replaced. (VHD-4)
Compiling Entity Declaration REGIS
Compiling Architecture REGIS_ARC of REGIS
Warning: ./bigapple.vhd:113: The architecture regis_arc has already been analyz
ed. It is being replaced. (VHD-4)
Compiling Entity Declaration FSM
Compiling Architecture FSM_ARC of FSM
Warning: ./bigapple.vhd:141: The architecture fsm_arc has already been analyzed
. It is being replaced. (VHD-4)
Compiling Entity Declaration GCD
Compiling Architecture GCD_ARC of GCD
Warning: ./bigapple.vhd:253: The architecture gcd_arc has already been analyzed
. It is being replaced. (VHD-4)
Compiling Entity Declaration GCD_BSD
Compiling Architecture GCD_BSD_ARC of GCD_BSD
Warning: ./bigapple.vhd:334: The architecture gcd_bsd_arc has already been anal
yzed. It is being replaced. (VHD-4)
Presto compilation completed successfully.
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb'
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db'
1
elaborate gcd
Loading db file '/opt/CAD/Synopsys/Current/syn/libraries/syn/gtech.db'
Loading db file '/opt/CAD/Synopsys/Current/syn/libraries/syn/standard.sldb'
Loading link library 'class'
Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'gcd'.
Information: Building the design 'fsm'. (HDL-193)
Statistics for case statements in always block at line 156 in file
'./bigapple.vhd'
===============================================
| Line | full/ parallel |
===============================================
| 158 | auto/auto |
===============================================
Inferred memory devices in process
in routine fsm line 147 in file
'./bigapple.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| cState_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'mux'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'regis'. (HDL-193)
Inferred memory devices in process
in routine regis line 115 in file
'./bigapple.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| output_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'comparator'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'subtractor'. (HDL-193)
Presto compilation completed successfully.
1
check_design -multiple_designs
Warning: In design 'comparator', cell 'C38' does not drive any nets. (LINT-1)
Warning: In design 'subtractor', cell 'C73' does not drive any nets. (LINT-1)
Warning: In design 'subtractor', cell 'C76' does not drive any nets. (LINT-1)
Information: Design 'mux' is instantiated 2 times. (LINT-45)
Cell 'X_MUX' in design 'gcd'
Cell 'Y_MUX' in design 'gcd'
Information: Design 'regis' is instantiated 3 times. (LINT-45)
Cell 'X_REG' in design 'gcd'
Cell 'Y_REG' in design 'gcd'
Cell 'OUT_REG' in design 'gcd'
1
################################################################################
#
# Apply Additional Optimization Constraints
################################################################################
#
# Prevent assignment statements in the Verilog netlist.
set_fix_multiple_port_nets -all -buffer_constants
1
################################################################################
#
# Compile the Design
################################################################################
#
compile -scan
Information: Choosing a test methodology will restrict the optimization of seque
ntial cells. (UIO-12)
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | D-2010.03-DWBB_1004 | * |
| Licensed DW Building Blocks | | |
| class.sdb | | |
============================================================================

Information: There are 3 potential problems in your design. Please run 'check_de
sign' for more information. (LINT-99)

Beginning Pass 1 Mapping

------------------------
Processing 'regis_0'
Processing 'subtractor'
Processing 'comparator'
Processing 'mux_0'
Processing 'fsm'
Processing 'gcd'
Updating timing information
Information: Updating design information... (UID-85)
Information: Design 'gcd' has no optimization constraints set. (OPT-108)
Beginning Implementation Selection
----------------------------------
Processing 'subtractor_DW02_mult_0'
Processing 'subtractor_DW02_mult_1'
Beginning Mapping Optimizations (Medium effort)
-------------------------------
Structuring 'regis_2'
Mapping 'regis_2'
Structuring 'regis_1'
Mapping 'regis_1'
Structuring 'mux_1'
Mapping 'mux_1'
Structuring 'subtractor'
Mapping 'subtractor'
Structuring 'comparator'
Mapping 'comparator'
Structuring 'regis_0'
Mapping 'regis_0'
Structuring 'mux_0'
Mapping 'mux_0'
Structuring 'fsm'
Mapping 'fsm'
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0

Beginning Delay Optimization Phase

----------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0

Beginning Area-Recovery Phase (cleanup)

-----------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
 --------- --------- --------- --------- --------- -------------------------
0:00:08 372.0 0.00 0.0 0.0
0:00:08 372.0 0.00 0.0 0.0
0:00:08 370.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
0:00:08 369.0 0.00 0.0 0.0
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db'
Optimization Complete
---------------------
1
# Save gate level synthesis
change_names -rules verilog -hierarchy
1
write -f verilog -hierarchy -output gcd_syn.v
Writing verilog file '/home/carsondk/work/test/gcd_syn.v'.
1
################################################################################
#
# DFT Compiler Optimization Section
################################################################################
#
#############################################################################
# DFT Signal Type Definitions
#############################################################################
create_port test_so -direction out
Creating port 'test_so' in design 'gcd'.
1
create_port test_si -direction in
Creating port 'test_si' in design 'gcd'.
1
create_port test_se -direction in
Creating port 'test_se' in design 'gcd'.
1
set_dft_signal -view spec -type ScanDataOut -port test_so
Accepted dft signal specification for modes: all_dft
1
set_dft_signal -view spec -type ScanDataIn -port test_si
Accepted dft signal specification for modes: all_dft
1
set_dft_signal -view spec -type ScanEnable -port test_se
Accepted dft signal specification for modes: all_dft
1
set_dft_signal -view existing_dft -type ScanClock -port [list clk] -timing {45 5
5}
Accepted dft signal specification for modes: all_dft
1
set_dft_signal -view existing_dft -type Reset -port rst -active 1
Accepted dft signal specification for modes: all_dft
1
set_scan_path chain0 -view spec -scan_enable scan_en
Warning: Can't find object 'scan_en' in design 'gcd'. (UID-95)
Accepted scan path specification for mode: Internal_scan
1
set_scan_path chain0 -view spec -scan_data_in scan_in
Warning: Can't find object 'scan_in' in design 'gcd'. (UID-95)
Error: Value for list '-scan_data_in' must have 1 elements. (CMD-036)
0
#############################################################################
# DFT Configuration
#############################################################################
set_dft_insertion_configuration -preserve_design_name true
Accepted insert_dft configuration specification.
1
# Do not run incremental compile as a part of insert_dft
set_dft_insertion_configuration -synthesis_optimization none
Accepted insert_dft configuration specification.
1
set_scan_register_type -type -exact {FD1S FD2S FD4S}
Warning: Can't find object 'FD1S' in design 'gcd'. (UID-95)
Warning: Can't find object 'FD2S' in design 'gcd'. (UID-95)
Warning: Can't find object 'FD4S' in design 'gcd'. (UID-95)
Error: Unable to find example flip flop '-exact'. (UID-904)
0
set_scan_configuration -style multiplexed_flip_flop -chain_count 1 -create_dedic
ated_scan_out_ports true
Accepted scan configuration for modes: all_dft
1
#############################################################################
# DFT Test Protocol Creation
#############################################################################
# "-capture_procedure multi_clock" is default for "create_test_protocol"
# since the B-2008.09-SP2 release. This is the recommended value.
# If necessary, you can use the "-capture_procedure single_clock" option.
create_test_protocol -infer_async -infer_clock
Information: Generating Multi-clock protocol. The default value of '-capture_pro
cedure' has changed to 'multi_clock'.
In mode: all_dft...
Information: Starting test protocol creation. (TEST-219)
...inferring clock signals...
Information: Inferred system/test clock port clk (45.0,55.0). (TEST-260)
...inferring asynchronous signals...
Information: Inferred active high asynchronous control port rst. (TEST-261)
1
#############################################################################
# DFT Scan Chain Insertion
#############################################################################
# Use the -verbose version of dft_drc to assist in debugging if necessary
dft_drc
In mode: all_dft...
Pre-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
...checking pre-dft rules...
-----------------------------------------------------------------
Begin Pre-DFT violations...
Warning: Clock rst connects to data input (D) of DFF TOFSM/cState_reg_0_. (D10-
1)
Information: There are 14 other cells with the same violation. (TEST-171)
Pre-DFT violations completed...
-----------------------------------------------------------------
-----------------------------------------------------------------
DRC Report
Total violations: 15
-----------------------------------------------------------------
15 PRE-DFT VIOLATIONS
15 Clock feeding data input violations (D10)

Warning: Violations occurred during test design rule checking. (TEST-124)

-----------------------------------------------------------------
Sequential Cell Report
0 out of 15 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 15 cells are valid scan cells
Information: Test design rule checking completed. (TEST-123)
1
dft_drc -verbose
In mode: all_dft...
Pre-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking for scan equivalents...
...checking vector rules...
...checking pre-dft rules...
-----------------------------------------------------------------
Begin Pre-DFT violations...
Warning: Clock rst connects to data input (D) of DFF TOFSM/cState_reg_0_. (D10-
1)
Warning: Clock rst connects to data input (D) of DFF TOFSM/cState_reg_2_. (D10-
2)
Warning: Clock rst connects to data input (D) of DFF TOFSM/cState_reg_1_. (D10-
3)
Warning: Clock rst connects to data input (D) of DFF X_REG/output_reg_3_. (D10-
4)
Warning: Clock rst connects to data input (D) of DFF X_REG/output_reg_2_. (D10-
5)
Warning: Clock rst connects to data input (D) of DFF X_REG/output_reg_1_. (D10-
6)
Warning: Clock rst connects to data input (D) of DFF X_REG/output_reg_0_. (D10-
7)
Warning: Clock rst connects to data input (D) of DFF OUT_REG/output_reg_3_. (D1
0-8)
Warning: Clock rst connects to data input (D) of DFF OUT_REG/output_reg_2_. (D1
0-9)
Warning: Clock rst connects to data input (D) of DFF OUT_REG/output_reg_1_. (D1
0-10)
Warning: Clock rst connects to data input (D) of DFF OUT_REG/output_reg_0_. (D1
0-11)
Warning: Clock rst connects to data input (D) of DFF Y_REG/output_reg_3_. (D10-
12)
Warning: Clock rst connects to data input (D) of DFF Y_REG/output_reg_2_. (D10-
13)
Warning: Clock rst connects to data input (D) of DFF Y_REG/output_reg_1_. (D10-
14)
Warning: Clock rst connects to data input (D) of DFF Y_REG/output_reg_0_. (D10-
15)
Pre-DFT violations completed...
-----------------------------------------------------------------
-----------------------------------------------------------------
DRC Report
Total violations: 15
-----------------------------------------------------------------
15 PRE-DFT VIOLATIONS
15 Clock feeding data input violations (D10)

Warning: Violations occurred during test design rule checking. (TEST-124)

-----------------------------------------------------------------
Sequential Cell Report
0 out of 15 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 15 cells are valid scan cells
TOFSM/cState_reg_0_
TOFSM/cState_reg_2_
TOFSM/cState_reg_1_
X_REG/output_reg_3_
X_REG/output_reg_2_
X_REG/output_reg_1_
X_REG/output_reg_0_
OUT_REG/output_reg_3_
OUT_REG/output_reg_2_
OUT_REG/output_reg_1_
OUT_REG/output_reg_0_
Y_REG/output_reg_3_
Y_REG/output_reg_2_
Y_REG/output_reg_1_
Y_REG/output_reg_0_
Information: Test design rule checking completed. (TEST-123)
1
report_constraint -all_violators
****************************************
Report : constraint
-all_violators
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:34 2010
****************************************
This design has no constraints.
1
report_scan_configuration
****************************************
Report : Scan configuration
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:34 2010
****************************************
========================================
TEST MODE: all_dft
VIEW : Specification
========================================
Chain count: 1
Scan Style: Multiplexed flip-flop
Maximum scan chain length: Undefined
Exact scan chain length: Undefined
Physical Partitioning: Horizontal
Replace: True
Preserve multibit segments: True
Clock mixing: No mix
Internal clocks: none
Add lockup: True
Lockup type: latch
Insert terminal lockup: False
Create dedicated scan out ports: True
Shared scan in: 0
Bidirectional mode: No bidirectional type
Internal Clock Mixing: False
Test Clocks by System Clocks: False
Hierarchical Isolation: False
Multiple Scan Enable: Disable
Pipeline Scan Enable: Disable
Voltage Mixing: False
Identify Shift Register: False
Power Domain Mixing: False
Reuse MV Isolation Cells: True
1
report_dft_insertion_configuration
****************************************
Report : insert_dft configuration
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:34 2010
****************************************
Options Status
------- --------
Map_effort Medium
Preserve_design_name True
Route_scan_enable True
Route_scan_clock True
Route_scan_serial True
Synthesis_optimization None
Unscan False
1
# Use the -show all version to preview_dft for more detailed report
preview_dft
Information: Using test design rule information from previous dft_drc run.
Architecting Scan Chains
****************************************
Preview_dft report
For : 'Insert_dft' command
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:34 2010
****************************************
Number of chains: 1
Scan methodology: full_scan
Scan style: multiplexed_flip_flop
Clock domain: no_mix
Scan enable: test_se (no hookup pin)

Scan chain 'chain0' (test_si --> test_so) contains 15 cells

************ Test Point Plan Report ************

Total number of test points : 0
Number of Autofix test points: 0
Number of Wrapper test points: 0
Number of test modes : 0
Number of test point enables : 0
Number of data sources : 0
Number of data sinks : 0
**************************************************
1
preview_dft -show all -test_points all
Information: Using test design rule information from previous dft_drc run.
Architecting Scan Chains
****************************************
Preview_dft report
For : 'Insert_dft' command
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:34 2010
****************************************
Number of chains: 1
Scan methodology: full_scan
Scan style: multiplexed_flip_flop
Clock domain: no_mix
Scan enable: test_se (no hookup pin)
(l) shows cell scan-out drives a lockup latch
(s) shows cell is a scan segment
(t) shows cell has a true scan attribute
(w) shows cell scan-out drives a wire

Scan chain 'chain0' (test_si --> test_so) contains 15 cells:

OUT_REG/output_reg_0_ (clk, 45.0, rising)
OUT_REG/output_reg_1_
OUT_REG/output_reg_2_
OUT_REG/output_reg_3_
TOFSM/cState_reg_0_
TOFSM/cState_reg_1_
TOFSM/cState_reg_2_
X_REG/output_reg_0_
X_REG/output_reg_1_
X_REG/output_reg_2_
X_REG/output_reg_3_
Y_REG/output_reg_0_
Y_REG/output_reg_1_
Y_REG/output_reg_2_
Y_REG/output_reg_3_
Scan signals:
test_scan_in: test_si (no hookup pin)
test_scan_out: test_so (no hookup pin)

****************************************
No user-defined segments

No multibit segments

****************************************
No cells have scan true
No cells have scan false

No tristate nets.
No bidirectionals.

************ Test Point Plan Report ************

Total number of test points : 0
Number of Autofix test points: 0
Number of Wrapper test points: 0
Number of test modes : 0
Number of test point enables : 0
Number of data sources : 0
Number of data sinks : 0
**************************************************
No test points.
1
insert_dft
Information: Using test design rule information from previous dft_drc run.
Architecting Scan Chains
Routing Scan Chains
Routing Global Signals
Mapping New Logic
Resetting current test mode
1
################################################################################
#
# DFT Incremental Compile
################################################################################
#
compile -incremental -scan
Information: Choosing a test methodology will restrict the optimization of seque
ntial cells. (UIO-12)

Beginning Pass 1 Mapping (Incremental)

------------------------
Updating timing information
Information: Updating design information... (UID-85)
Information: Design 'gcd' has no optimization constraints set. (OPT-108)
Beginning Mapping Optimizations (Medium effort) (Incremental)
-------------------------------
Beginning Incremental Implementation Selection
----------------------------------------------
Beginning Delay Optimization Phase
----------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:00 369.0 0.00 0.0 0.0
0:00:01 369.0 0.00 0.0 0.0
0:00:01 369.0 0.00 0.0 0.0
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db'
Optimization Complete
---------------------
1
################################################################################
#
# Write Out Final Design and Reports (without BSD)
################################################################################
#
uniquify -force
Removing uniquified design 'fsm'.
Removing uniquified design 'regis_0'.
Removing uniquified design 'comparator'.
Removing uniquified design 'subtractor'.
Removing uniquified design 'mux_0'.
Removing uniquified design 'regis_1'.
Removing uniquified design 'regis_2'.
Removing uniquified design 'mux_1'.
Uniquified 1 instances of design 'fsm'.
Uniquified 1 instances of design 'regis_0'.
Uniquified 1 instances of design 'comparator'.
Uniquified 1 instances of design 'subtractor'.
Uniquified 1 instances of design 'mux_0'.
Uniquified 1 instances of design 'regis_1'.
Uniquified 1 instances of design 'regis_2'.
Uniquified 1 instances of design 'mux_1'.
1
change_names -rules verilog -hierarchy
1
report_constraint -all_violators
Information: Updating graph... (UID-83)
Information: Updating design information... (UID-85)
****************************************
Report : constraint
-all_violators
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:37 2010
****************************************
This design has no constraints.
1
dft_drc -verbose -coverage_estimate
In mode: Internal_scan...
Design has scan chains in this mode
Design is scan routed
Post-DFT DRC enabled
Information: Starting test design rule checking. (TEST-222)
Loading test protocol
...basic checks...
...basic sequential cell checks...
...checking vector rules...
...checking clock rules...
...checking scan chain rules...
...checking scan compression rules...
...checking X-state rules...
...checking tristate rules...
...extracting scan details...
-----------------------------------------------------------------
Begin Clock violations...
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (TOFSM/cState_reg_0_). (C26-1)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (TOFSM/cState_reg_2_). (C26-2)
 Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (TOFSM/cState_reg_1_). (C26-3)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (X_REG/output_reg_3_). (C26-4)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (X_REG/output_reg_2_). (C26-5)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (X_REG/output_reg_1_). (C26-6)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (X_REG/output_reg_0_). (C26-7)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (Y_REG/output_reg_3_). (C26-8)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (Y_REG/output_reg_2_). (C26-9)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (Y_REG/output_reg_1_). (C26-10)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (Y_REG/output_reg_0_). (C26-11)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (OUT_REG/output_reg_3_). (C26-12)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (OUT_REG/output_reg_2_). (C26-13)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (OUT_REG/output_reg_1_). (C26-14)
Warning: Clock rst used as data is different than capture clock clk for inputs
CP/D of stable DFF (OUT_REG/output_reg_0_). (C26-15)
Clock violations completed...
-----------------------------------------------------------------
-----------------------------------------------------------------
DRC Report
Total violations: 15
-----------------------------------------------------------------
15 CLOCK VIOLATIONS
15 Clock as data different from capture clock for stable cell violations (C2
6)

Warning: Violations occurred during test design rule checking. (TEST-124)

-----------------------------------------------------------------
Sequential Cell Report
0 out of 15 sequential cells have violations
-----------------------------------------------------------------
SEQUENTIAL CELLS WITHOUT VIOLATIONS
* 15 cells are valid scan cells
TOFSM/cState_reg_0_
TOFSM/cState_reg_2_
TOFSM/cState_reg_1_
X_REG/output_reg_3_
X_REG/output_reg_2_
X_REG/output_reg_1_
X_REG/output_reg_0_
 Y_REG/output_reg_3_
Y_REG/output_reg_2_
Y_REG/output_reg_1_
Y_REG/output_reg_0_
OUT_REG/output_reg_3_
OUT_REG/output_reg_2_
OUT_REG/output_reg_1_
OUT_REG/output_reg_0_
....Inferring feed-through connections....
Information: Test design rule checking completed. (TEST-123)
Running test coverage estimation...
1016 faults were added to fault list.
ATPG performed for stuck fault model using internal pattern source.
----------------------------------------------------------
#patterns #faults #ATPG faults test process
stored detect/active red/au/abort coverage CPU time
--------- ------------- ------------ -------- --------
Begin deterministic ATPG: #uncollapsed_faults=880, abort_limit=10...
0 772 108 0/0/0 89.37% 0.00
0 63 33 5/4/0 96.04% 0.01
0 20 0 8/11/0 98.61% 0.02

Pattern Summary Report

-----------------------------------------------
#internal patterns 0
-----------------------------------------------

Uncollapsed Stuck Fault Summary Report

-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 991
Possibly detected PT 0
Undetectable UD 11
ATPG untestable AU 14
Not detected ND 0
-----------------------------------------------
total faults 1016
test coverage 98.61%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.
1
report_scan_path -view existing -chain all
****************************************
Report : Scan path
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:39 2010
****************************************
========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================
========================================
AS SPECIFIED BY USER
========================================

========================================
AS BUILT BY insert_dft
========================================
Scan_path Len ScanDataIn ScanDataOut ScanEnable MasterClock SlaveClock
----------- ----- ----------- ----------- ----------- ----------- -----------
I chain0 15 test_si test_so test_se clk -
1
report_cell
****************************************
Report : cell
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:39 2010
****************************************
Attributes:
b - black box (unknown)
h - hierarchical
n - noncombinational
r - removable
u - contains unmapped logic
Cell Reference Library Area Attributes
--------------------------------------------------------------------------------
OUT_REG regis_4 57.000000 h, n
TOFSM fsm_0 57.000000 h, n
U_COMP comparator_0 28.000000 h
X_MUX mux_2 15.000000 h
X_REG regis_3 57.000000 h, n
X_SUB subtractor_0 83.000000 h
Y_MUX mux_3 15.000000 h
Y_REG regis_5 57.000000 h, n
--------------------------------------------------------------------------------
Total 8 cells 369.000000
1
write_test_protocol -output ./src/gcd_scan_syn.spf
Writing test protocol file '/home/carsondk/work/test/src/gcd_scan_syn.spf' for m
ode 'Internal_scan'...
1
write -f verilog -hierarchy -output ./src/gcd_scan_syn.v
Writing verilog file '/home/carsondk/work/test/src/gcd_scan_syn.v'.
1
################################################################################
#
# Write Out Final Design and Reports (without BSD)
################################################################################
#Information: Defining new variable 'hlo_collapse_intermediate_hardware_alts'. (
CMD-041)
Information: Defining new variable 'compile_group_pull_control_logic'. (CMD-041)
Information: Defining new variable 'test_enable_dft_drc'. (CMD-041)
design_vision> Current design is 'gcd'.
Current design is 'gcd'.
design_vision> design_vision> exit
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Information: Defining new variable
Thank you...
'tixComboBox'. (CMD-041)
'tixScrolledListBox'. (CMD-041)
'tixLabelWidget'. (CMD-041)
'v'. (CMD-041)
'tixEvent'. (CMD-041)
'tixControl'. (CMD-041)
'tixFloatEntry'. (CMD-041)
'tk_strictMotif'. (CMD-041)
'tixPrimOpt'. (CMD-041)
'tix'. (CMD-041)
'_tix_event_flags'. (CMD-041)
'no_gui'. (CMD-041)
'tk_patchLevel'. (CMD-041)
'widget_geom'. (CMD-041)
'tix_library'. (CMD-041)
'tix_version'. (CMD-041)
'tix_release'. (CMD-041)
'tixScrolledGrid'. (CMD-041)
'tix_priv'. (CMD-041)
'tixLabelEntry'. (CMD-041)
'tixButtonBox'. (CMD-041)
'tix_patchLevel'. (CMD-041)
'tixAppContext'. (CMD-041)
'tixScrolledWidget'. (CMD-041)
'tkPriv'. (CMD-041)
'tixPrimitive'. (CMD-041)
'opt'. (CMD-041)
'tixOption'. (CMD-041)
'tk_library'. (CMD-041)
'tk_version'. (CMD-041)