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A B C D E

1 1

2
Compal Confidential 2

G400/G500 UMA M/B Schematics Document


Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

2013-02-27
3 3

LA-9632P
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 1 of 60
A B C D E
A B C D E

Compal confidential
Project Name : VIWGP (14") / VIWGR (15")

1
Chief River 1

Intel Memory Bus 204pin DDRIII-SO-DIMM X2


Processor Dual Channel BANK 0, 1, 2 Page 12, 13
1600MHz
DDR3
Ivy Bridge 1333MHz
DDR3
1066MHz
DDR3
rPGA989
37.5mm x 37.5mm
Page 5~11

FDI *8 DMI2 *4
2.7GT/s 5GT/s

2 LVDS Conn. Left USB3.0 x2 Right USB2.0 Int. Camera


2

Page 23
USB30 x2 USB30 Port 0,1 USB20 Port 9 USB20 Port 3
Page 35 Page 35 Page 23

HDMI Conn. USB20 x6 Touch Screen Card Reader


Page 25
Realtek RTS5170
USB20 Port 2
Page 35 USB20 Port 11 page 28
CRT Conn. Intel
Page 24
PCH
LAN Panther Point SATA Gen3 HDD Conn.
PCIe Port 0 PCIe x1
RJ45 Conn. Atheros SATA Port 0
Page 28 Page 30
AR8162/QCA8172(10/100)
Page 27
FCBGA 989Balls
25mm x 25mm SATA ODD Conn.
SATA Port 2
Page 30
3 PCIe Mini Card PCIe x1
3

WLAN Audio Codec


PCIe Port 1
Page 26 AZALIA CONEXANT
CX20757
Page 31

Page 14~22

Int. MIC Conn. Int. Speaker Conn. Audio Combo Jacks


Sub-borad Page 31 Page 31
HP & MIC Page 31

SPI ROM EC
15" 2MB + 4MB ENE KB9012
14" Page 14 Page 32

Power/B
(LID)
LS9631
4 4

USB/B ODD/B Thermal Sensor Touch Pad Int. KBD


Page 29 Page 33 Page 33

LS9632 LS9634

IO/B Switch/B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
(Card Reader) (LED, LID) MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LS9633 LS9635 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 2 of 60
A B C D E
A B C D E

Voltage Rails BOARD ID Table


SIGNAL
Board ID PCB Revision STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

+5VS
0 0.1 Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+3VS
1
power 2 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +1.5VS
+V1.05S_VCCP
3
1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+5VALW +1.5V +VCC_CORE


4
5 S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B +VGA_CORE
+3VALW +VCC_GFXCORE_AXG
6
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
7
State +0.75VS
+1.05VS
Vcc 3.3V
Board ID / SKU ID Table for AD channel
R694 100K +/- 1%
Board ID R695 VAD_BID min V AD_BID typ VAD_BID max EC AD
0 0 0 V 0 V 0 V 0x00 - 0x0B MP
1 12K +/- 1% 0.347V 0.354V 0.360V 0x0C - 0x1C PVT
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1D - 0x26 DVT
S0
O O O O 3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30 EVT

S3
O O O X
2 2

S5 S4/AC
O O X X USB Port Table BOM Structure Table
S5 S4/ Battery only 3 External Item BOM Structure
O X X X USB 2.0 Port USB Port VIWGP (14") 14@
S5 S4/AC & Battery 0 USB Port (Left Side)USB3.0 VIWGR (15") 15@
don't exist X X X X UHCI0
1 USB Port (Left Side)USB3.0 HDMI Logo 45@
2 Touch Screen LAN 10/100 8162@
UHCI1
3 Camera LAN 10/100 8172@
EHCI1
4 LAN Switch mode SWR@
UHCI2
5 LAN LDO Mode LDO@
EC SM Bus1 address EC SM Bus2 address 6 LAN Gas tube GAS@
UHCI3
7 Camera CMOS@
Device Address Device Address
8 HDMI HDMI@
Smart Battery 0001 011x Thermal Sensor 0100 1100 UHCI4
9 USB Port (Right Side USB-BD) PCH is HM76 HM76@
10 Mini Card(WLAN) PCH is HM70 HM70@
PCH SM Bus address AMD-GPU SM Bus address EHCI2 UHCI5
3 11 Card Reader PCH is NM70 NM70@ 3

12 VGA is Mars XT Mars@


Device Address Device Address UHCI6
DDR_JDIMM1 1010 000x A0h Internal thermal sensor 0100 0001 41h
13 VGA is Sun Pro Sun@
DDR_JDIMM2 1010 010x A4h
For VGA PX@
For VRAM and Strap X76@
For UMA Strap UMA@
Microphone MIC@
Touch Screen TS@
SMBUS Control Table Connector ME@
Board ID for EVT EVT@
Board ID for DVT DVT@
Thermal
SOURCE VGA BATT KB9012 SODIMM WLAN Sensor PCH Board ID for PVT PVT@
For USB2.0 (All PCH) USB2@
SMB_EC_CK1
SMB_EC_DA1
KB9012 X V
+3VALW
X X X X X For USB3.0 (HM76,HM70) USB3@
+3VALW
For share ROM SROM@
SMB_EC_CK2
SMB_EC_DA2
KB9012 V
+3VGS
X X X X +3VS
V V
+3VALW
For non-share ROM NOSROM@
+3VS
PCH_SMBCLK
X X X V V X X
4 4

PCH
PCH_SMBDATA +3VALW +3VS +3VS
PCH_SML0CLK
PCH
PCH_SML0DATA +3VALW
X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VGS
X V
+3VS
X X +3VS
V X Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 3 of 60
A B C D E
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

ZZZ1 14@ ZZZ2 15@

PEG_ICOMPI and RCOMPO signals should be


shorted and routed
14"_UMA_PCB_LA9632P 15"_UMA_PCB_LA9632P
with - max length = 500 mils - typical
DA6000WP000 DA6000WP100 +V1.05S_VCCP impedance = 43 mohms
PCB 0Y0 LA-9632P REV0 M/B UMA 3 PCB 0Y0 LA-9632P REV0 M/B UMA 5
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
D
24.9_0402_1% - typical impedance = 14.5 mohms D

JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI J21
B27 PEG_ICOMPO H22
<16> DMI_CRX_PTX_N0 DMI_RX#[0] PEG_RCOMPO PEG Static Lane Reversal - CFG2 is for the 16x
<16> DMI_CRX_PTX_N1 B25
A25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 DMI_RX#[2]
<16> DMI_CRX_PTX_N3 B24 K33 1: Normal Operation; Lane # definition matches
DMI_RX#[3] PEG_RX#[0] M35
PEG_RX#[1] CFG2 socket pin map definition
<16> DMI_CRX_PTX_P0 B28 L34
B26 DMI_RX[0] PEG_RX#[2] J35
<16> DMI_CRX_PTX_P1 DMI_RX[1] PEG_RX#[3]
A24 J32 0:Lane Reversed
<16> DMI_CRX_PTX_P2
*

DMI
B23 DMI_RX[2] PEG_RX#[4] H34
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H31
G21 PEG_RX#[6] G33
<16> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
E22 G30
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35
<16> DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34
<16> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D33
<16> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31
<16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
F20 B33
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS


C21 C32
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33
PEG_RX[0] L35
PEG_RX[1] K34
A21 PEG_RX[2] H35
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
C H19 H32 C
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34
<16> FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33
<16> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30
<16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33
<16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32
PEG_RX[11] D34
A22 PEG_RX[12] E31
<16> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33
<16> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32
<16> FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
G18
<16> FDI_CTX_PRX_P3 FDI0_TX[3]
B20 M29
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
J18 PEG_TX#[4] K31
+V1.05S_VCCP <16> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
<16> FDI_FSYNC1
J17 K28
FDI1_FSYNC PEG_TX#[6] J30
H20 PEG_TX#[7] J28
<16> FDI_INT FDI_INT PEG_TX#[8] H29
PEG_TX#[9]
1

<16> FDI_LSYNC0 J19 G27


R7 H17 FDI0_LSYNC PEG_TX#[10] E29
<16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
24.9_0402_1% F27
PEG_TX#[12] D28
PEG_TX#[13] F26
2

PEG_TX#[14] E25
EDP_COMP A18 PEG_TX#[15]
B
A17 eDP_COMPIO M28 B
eDP_COMPIO and ICOMPO signals eDP_ICOMPO PEG_TX[0]
eDP_HPD B16 M33
should be shorted near balls eDP_HPD# PEG_TX[1] M30
PEG_TX[2] L31
and routed with typical PEG_TX[3]
C15 L28
impedance <25 mohms D15 eDP_AUX PEG_TX[4] K30
eDP_AUX# PEG_TX[5] K27
eDP

PEG_TX[6] J29
C17 PEG_TX[7] J27
F16 eDP_TX[0] PEG_TX[8] H28
C16 eDP_TX[1] PEG_TX[9] G28
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
C18 PEG_TX[12] D27
E16 eDP_TX#[0] PEG_TX[13] E26
D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15]
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 5 of 60
5 4 3 2 1
5 4 3 2 1

JCPU1B
D D

A28
C26 BCLK A27 CLK_CPU_DMI <15>

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>

AN34
SKTOCC# A16 2 R12 1 1K_0402_5%
+V1.05S_VCCP DPLL_REF_CLK A15 2 R13 1 1K_0402_5%
DPLL_REF_CLK# +V1.05S_VCCP

T48 H_CATERR# AL33


CATERR#
R9 1
62_0402_5%

THERMAL
AN33 R8 H_DRAMRST#
<32> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15 +V1.05S_VCCP

DDR3
MISC
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 2 R16 1 140_0402_1%
<32,36,37,43> H_PROCHOT# PROCHOT# SM_RCOMP[0] A5 SM_RCOMP1 2 R17 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP2 2 R18 1 200_0402_1%
SM_RCOMP[2]
AN32 DDR3 Compensation Signals
<19> H_THRMTRIP# THERMTRIP#

RP13
XDP_TRST# 8 1
AP29 XDP_PRDY# XDP_TDI 7 2
PRDY# AP27 XDP_PREQ# XDP_TMS 6 3
PREQ# XDP_TCK 5 4

1
AR26 XDP_TCK
C TCK AR27 XDP_TMS 51_0804_8P4R_5% C46 C

PWR MANAGEMENT
TMS

JTAG & BPM


AM34 AP30 XDP_TRST# 100P_0402_50V8J
<16> H_PM_SYNC

2
PM_SYNC TRST#
@
AR28 XDP_TDI
TDI AP26 XDP_TDO
AP33 TDO
<19> H_CPUPWRGD UNCOREPWRGOOD
ESD
2

R29 AL35 XDP_DBRESET# R28 2 1 1K_0402_5%


DBR# +3VS
1 R27 1 2 PM_DRAM_PWRGD_R V8
C549 130_0402_5% SM_DRAMPWROK
10K_0402_5%

1
AT28 XDP_BPM#0
22P_0402_50V8J BPM#[0] AR29 XDP_BPM#1 C45
1

2 BPM#[1] AR30 XDP_BPM#2 47P_0402_50V8J

2
BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3
RESET# BPM#[3] AP32 XDP_BPM#4
BPM#[4] AR31 XDP_BPM#5
BPM#[5] AT31 XDP_BPM#6
ESD BPM#[6] AR32 XDP_BPM#7 ESD
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
+3VALW
ME@

Buffered reset to CPU


+1.5V_CPU_VDDQ
+3VS
B B
1

R30
U1 200_0402_5% +V1.05S_VCCP
5

1 R161 2 1
P

+3VS B
10K_0402_5% 4 PM_SYS_PWRGD_BUF R32
2 O 75_0402_5%
<16> PM_DRAM_PWRGD A
G

5
74AHC1G09GW_TSSOP5 R34 U2
3

43_0402_1% 1 3V

P
BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
Y 2 PCH_PLTRST#
A PCH_PLTRST# <18>

G
SN74LVC1G07DCKR_SC70-5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

JCPU1C JCPU1D
<13> DDR_B_D[0..63]

AB6 AE2
<12> DDR_A_D[0..63] SA_CLK[0] AA6 M_CLK_DDR0 <12> SB_CLK[0] AD2 M_CLK_DDR2 <13>
DDR_A_D0 C5 SA_CLK#[0] V9 M_CLK_DDR#0 <12> DDR_B_D0 C9 SB_CLK#[0] R9 M_CLK_DDR#2 <13>
D5 SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> A7 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D1 DDR_B_D1
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
C6 SA_DQ[4] SA_CLK[1] AB5 M_CLK_DDR1 <12> A8 SB_DQ[4] SB_CLK[1] AD1 M_CLK_DDR3 <13>
DDR_A_D5 DDR_B_D5
C2 SA_DQ[5] SA_CLK#[1] V10 M_CLK_DDR#1 <12> D9 SB_DQ[5] SB_CLK#[1] R10 M_CLK_DDR#3 <13>
DDR_A_D6 DDR_B_D6
D C3 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> D8 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13> D
DDR_A_D7 DDR_B_D7
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
DDR_A_D23 K2 SA_DQ[22] SA_CS#[0] AL3 DDR_CS0_DIMMA# <12> DDR_B_D23 K7 SB_DQ[22] SB_CS#[0] AE3 DDR_CS2_DIMMB# <13>
DDR_A_D24 M8 SA_DQ[23] SA_CS#[1] AG1 DDR_CS1_DIMMA# <12> DDR_B_D24 M5 SB_DQ[23] SB_CS#[1] AD6 DDR_CS3_DIMMB# <13>
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
DDR_A_D30 N9 SA_DQ[29] SA_ODT[0] AG3 M_ODT0 <12> DDR_B_D30 M2 SB_DQ[29] SB_ODT[0] AD4 M_ODT2 <13>
M_ODT1 <12> M_ODT3 <13>

DDR SYSTEM MEMORY B


DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A


DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <13>
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
C DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2 C
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
DDR_A_D49 AN11 SA_DQ[48] D4 DDR_A_DQS0 DDR_A_DQS[0..7] <12> DDR_B_D49 AJ11 SB_DQ[48] C7 DDR_B_DQS0 DDR_B_DQS[0..7] <13>
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
DDR_A_D60 AL14 SA_DQ[59] DDR_B_D60 AT12 SB_DQ[59]
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_A_MA[0..15] <12> DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <13>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
<12> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 DDR_A_MA8 <13> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 DDR_B_MA8
<12> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 DDR_A_MA9 <13> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3 DDR_B_MA9
B <12> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 B
DDR_A_MA10 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<12> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <13> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<12> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <13> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<12> DDR_A_WE# SA_WE# SA_MA[15] <13> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE


ME@

+1.5V ME@
1

R37
1K_0402_5%
R38
1K_0402_5%
2

3 1 1 2
S

H_DRAMRST# DDR3_DRAMRST#_R
<6> H_DRAMRST# DDR3_DRAMRST# <12,13>
2

Q2
R39 LBSS138LT1G_SOT-23-3
G
2

4.99K_0402_1%
1

@
A 1 R48 2 DRAMRST_CNTRL_PCH_R A
<10,15> DRAMRST_CNTRL_PCH
0_0402_5%

1
C35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
0.047U 16V K X7R 0402
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
Eiffel used 0.01u AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
Module design used 0.047u DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 7 of 60

5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor

D D

Interl request AH26 short GND


JCPU1E check on EVT phase PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches


AH27 PAD T13 CFG2
AK28 VCC_DIE_SENSE AH26 socket pin map definition
AK29 CFG[0] VSS_DIE_SENSE
AL26 CFG[1]
0:Lane Reversed
CFG4
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4] RSVD28
L7
AG7
* CFG4
AL30 CFG[5] RSVD29 AE7
CFG[6] RSVD30

1
AM31 AK2
AM32 CFG[7] RSVD31
AM30 CFG[8] W8 @ R42

CFG
AM28 CFG[9] RSVD32 1K_0402_1%
+VCC_GFXCORE_AXG AM26 CFG[10]

2
AN28 CFG[11] AT26
+VCC_CORE AN31 CFG[12] RSVD33 AM33
AN26 CFG[13] RSVD34 AJ27
CFG[14] RSVD35
2

@ AM27
R252 AK31 CFG[15]
AN29 CFG[16]
49.9_0402_1% CFG[17]
2

@ Display Port Presence Strap


R253
1

49.9_0402_1% T8
C RSVD37 J16 C
1 : Disabled; No Physical Display Port
VCC_AXG_VAL_SENSE AJ31 RSVD38 H16 CFG4 * attached to Embedded Display Port
1

R82 1 @ 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 VAXG_VAL_SENSE RSVD39 G16


VCC_VAL_SENSE AJ33 VSSAXG_VAL_SENSE RSVD40
R88 1 2 100_0402_1% VSS_VAL_SENSE AH33 VCC_VAL_SENSE
@
VSS_VAL_SENSE 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26 AR35
RSVD5 RSVD_NCTF1 AT34

RESERVED
RSVD_NCTF2 AT33
VSS_AXG_VAL_SENSE RSVD_NCTF3 AP35
RSVD_NCTF4 AR34
RSVD_NCTF5
VSS_VAL_SENSE
F25
F24 RSVD8
RSVD9
2

@ @ F23
R255 R257 D24 RSVD10 B34
G25 RSVD11 RSVD_NCTF6 A33
49.9_0402_1% 49.9_0402_1% RSVD12 RSVD_NCTF7
G24 A34
E23 RSVD13 RSVD_NCTF8 B35
1

D23 RSVD14 RSVD_NCTF9 C35


C30 RSVD15 RSVD_NCTF10
A31 RSVD16
B30 RSVD17
B29 RSVD18
D30 RSVD19 AJ32
B31 RSVD20 RSVD51 AK32
RSVD21 RSVD52 PCIE Port Bifurcation Straps
A30
C29 RSVD22
RSVD23
11: (Default) x16 - Device 1 functions 1 and 2 disabled
AN35
B J20 BCLK_ITP AM35 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B18 RSVD24
RSVD25
BCLK_ITP#
* disabled
01: Reserved - (Device 1 function 1 disabled ; function
J15 AT2 2 enabled)
RSVD27 RSVD_NCTF11 AT1
RSVD_NCTF12 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
AR1
RSVD_NCTF13

B1
KEY

TYCO_2013620-2_IVY BRIDGE

ME@

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB


CFG7 de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 8 of 60
5 4 3 2 1
5 4 3 2 1

JCPU1F POWER +V1.05S_VCCP


+VCC_CORE

QC=94A 8.5A
DC=53A
AG35
AG34 VCC1 AH13
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
D AG31 VCC4 VCCIO3 AC10 D
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
AF34 VCC11 VCCIO10 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12

PEG AND DDR


AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
AC32 VCC33 VCCIO31 C12
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
C AC29 VCC36 VCCIO34 B12 C
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44 +V1.05S_VCCP
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY

Y34 VCC51
Y33 VCC52
Y32 VCC53
VCC54

1
Y31
Y30 VCC55 R46
Y29 VCC56
VCC57 75_0402_5%
Y28
Y27 VCC58
VR_SVID_CLK series-resistors close to VR

2
Y26 VCC59
V35 VCC60
V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 R47 2 43_0402_5%
SVID

V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <43>


V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <43>
V31 VCC64 VIDSOUT VR_SVID_DAT <43>
V30 VCC65
V29 VCC66 2 1 130_0402_5%
VCC67
R50 +V1.05S_VCCP 0.1uF on power side
V28
B V27 VCC68 B
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U27 VCC78
U26 VCC79
R35 VCC80 +VCC_CORE
R34 VCC81
R33 VCC82
VCC83

1
R32
R31
R30
VCC84
VCC85
Trace Impedance =27-33 ohm R51

R29
R28
VCC86
VCC87
Trace Length Matc < 25 mils 100_0402_1%
SENSE LINES

2
R27 VCC88 AJ35
R26 VCC89 VCC_SENSE AJ34 VCCSENSE <43>
P35 VCC90 VSS_SENSE VSSSENSE <43>
P34 VCC91
VCC92

1
P33
P32 VCC93 B10 R54
P31 VCC94 VCCIO_SENSE A10 1 VCCIO_SENSE <42>
VSSIO_SENSE_L R74 2VSSIO_SENSE 100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO 10_0402_1%
P29 VCC96

2
P28 VCC97
VCC98 R74 & R79 put together +V1.05S_VCCP
P27
P26 VCC99 R79
A VCC100 2 1 A
VSSIO_SENSE_L <42>
10_0402_1%

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE Security Classification Compal Secret Data


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 9 of 60
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ
Q6

1
D LBSS138LT1G_SOT-23-3
2
+VREF_DQ_DIMMA G DRAMRST_CNTRL_PCH <15,7>
+VREF_DQ_DIMMB S

3
<35> SUSP +V_DDR_REFA_R
+V_DDR_REFB_R
U3
DMN3030LSS-13_SOP8L-8
B+ 8 1 AP4800

1
7 2 D
D 6 3 Id=9.6A DRAMRST_CNTRL_PCH 2 D

1
5 G
R56 S

3
82K_0402_5% Q9

4
LBSS138LT1G_SOT-23-3

2
R885 R02 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
RUN_ON_CPU1.5VS3 1 2

1
15K_0402_1% 1

1
D +VCC_GFXCORE_AXG
2 Q4 R57 C97
G 2N7002H_SOT23-3 330K_0402_5% 0.047U_0603_25V7K

1
S @ 2

2
R616
10_0402_1%

2
+VCC_GFXCORE_AXG JCPU1G
POWER VCC_AXG_SENSE <43>

AT24 AK35

SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 +1.5V_CPU_VDDQ
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <43>
AT21
VAXG3

1
AT20
AT18 VAXG4 R626
VAXG5

1
AT17 10_0402_1%
AR24 VAXG6
AR23 VAXG7 R67
+V_SM_VREF should

2
AR21 VAXG8 1K_0402_1%
AR20 VAXG9 have 20 mil trace width

2
AR18 VAXG10 AL1 +V_SM_VREF_CNT
C
AR17 VAXG11 SM_VREF C
VAXG12

1
AP24 1

VREF
AP23 VAXG13
AP21 VAXG14 C98 R78
AP20 VAXG15 B4 +V_DDR_REFA_R .1U_0402_16V7K 1K_0402_1%
AP18 VAXG16 SA_DIMM_VREFDQ D1 +V_DDR_REFB_R 2

2
AP17 VAXG17 SB_DIMM_VREFDQ
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
AN20 VAXG21 +1.5V_CPU_VDDQ
AN18 VAXG22

DDR3 -1.5V RAILS


AN17 VAXG23
AM24 VAXG24 AF7

GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1
AM20 AC7 1 1 1 1
VAXG28 VDDQ4

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C122
AM18 AC4 @ + C123
AM17 VAXG29 VDDQ5 AC1 220U_6.3V_M
AL24 VAXG30 VDDQ6 Y7
AL23 VAXG31 VDDQ7 Y4 2 2 2 2 2
AL21 VAXG32 VDDQ8 Y1
AL20 VAXG33 VDDQ9 U7
AL18 VAXG34 VDDQ10 U4
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
AJ20 VAXG45 +VCCSA
B B
AJ18 VAXG46
AJ17 VAXG47 M27 +VCCSA
AH24 VAXG48 VCCSA1 M26
SA RAIL

VAXG49 VCCSA2 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126
AH23 L26
AH21 VAXG50 VCCSA3 J26 + C128 @
AH20 VAXG51 VCCSA4 J25 330U_D2_2.5VY_R9M
AH18 VAXG52 VCCSA5 J24 2 2 2
AH17 VAXG53 VCCSA6 H26 2
VAXG54 VCCSA7 H25
VCCSA8
1.8V RAIL

H23
+1.8VS VCCSA_SENSE +VCCSA_SENSE <41>
R69 0_0805_5% 1.5A
1 2 +1.8VS_VCCPLL B6
A6 VCCPLL1 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <41>


22U_0805_6.3V6M
C345

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C132

@ 1 1 1 A2 C24
VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 <41>

@
2 2 2 A19
VCCIO_SEL

TYCO_2013620-2_IVY BRIDGE

ME@

A IVY Bridge drives VCCIO_SEL low A

VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1

Security Classification Compal Secret Data


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 10 of 60
5 4 3 2 1
5 4 3 2 1

JCPU1H JCPU1I

AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24
AT16 VSS7 VSS87 AJ3 T30 VSS165 VSS238 E21
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15
D D
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3
AR7 VSS19 VSS100 AH16 N34 VSS177 VSS250 E2
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35
AP34 VSS22 VSS103 AG9 N31 VSS180 VSS253 D32
AP31 VSS23 VSS104 AG8 N30 VSS181 VSS254 D29
AP28 VSS24 VSS105 AG4 N29 VSS182 VSS255 D26
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20
AP22 VSS26 VSS107 AF5 N27 VSS184 VSS257 D17
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28
AP10 VSS30 VSS111 AE34 L30 VSS188 VSS261 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10
C
AN30 VSS34 VSS115 AE30 L6 VSS192 VSS265 C1 C
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9
AN7 VSS42 VSS123 AC8 K29 VSS200 VSS273 B8
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35
AM16 VSS48 VSS129 AB34 H27 VSS206 VSS279 A32
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285
AM1 VSS55 VSS136 AB27 H9 VSS213
AL34 VSS56 VSS137 AB26 H8 VSS214
AL31 VSS57 VSS138 Y9 H7 VSS215
AL28 VSS58 VSS139 Y8 H6 VSS216
B B
AL25 VSS59 VSS140 Y6 H5 VSS217
AL22 VSS60 VSS141 Y5 H4 VSS218
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220
AL13 VSS63 VSS144 W35 H1 VSS221
AL10 VSS64 VSS145 W34 G35 VSS222
AL7 VSS65 VSS146 W33 G32 VSS223
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226
AK30 VSS69 VSS150 W29 G20 VSS227
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232
AK13 VSS75 VSS156 U6 VSS233
AK10 VSS76 VSS157 U5
AK7 VSS77 VSS158 U3
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80

A A
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ Security Classification CompalME@


Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 11 of 60
5 4 3 2 1
5 3 2 1

+VREF_DQ_DIMMA +1.5V
3A@1.5V
<7> DDR_A_D[0..63]
DDR3 SO-DIMM A <7> DDR_A_DQS[0..7]
JDIMM1
<7> DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4 <7> DDR_A_MA[0..15]

2.2U_0603_6.3V4Z

.1U_0402_16V7K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C134

C133
1 1 DDR_A_D1 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0
DDR_A_DM0 11 VSS4 DQS#0 12 DDR_A_DQS0
13 DM0 DQS0 14
D 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6 +1.5V D
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20 RP15
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 8 1
DQ8 DQ12 +VREF_DQ_DIMMA
DDR_A_D9 23 24 DDR_A_D13 7 2
25 DQ9 DQ13 26 6 3
VSS9 VSS10 +VREF_DQ_DIMMB
@ DDR_A_DQS#1 27 28 DDR_A_DM1 5 4
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <13,7>
31 32 1K_0804_8P4R_1%
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 +1.5V
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44 RP16
DDR_A_DQS#2 45 VSS15 VSS16 46 DDR_A_DM2 8 1
DQS#2 DM2 +VREF_CA
DDR_A_DQS2 47 48 7 2
49 DQS2 VSS17 50 DDR_A_D22 6 3
VSS18 DQ22 +VREF_CB
DDR_A_D18 51 52 DDR_A_D23 5 4
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28 1K_0804_8P4R_1%
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
DDR_A_DM3 63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

C DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<7> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
<7> M_CLK_DDR0 M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1 OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <7>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
Layout Note: (10uF_0603_6.3V)*8
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
DDR_A_RAS# <7>
Place near DIMM
111 BA0 RAS# 112
<7> DDR_A_WE# DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# (0.1uF_402_10V)*4
WE# S0# DDR_CS0_DIMMA# <7>
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
A13 ODT1 M_ODT1 <7> +VREF_CA
DDR_CS1_DIMMA# 121 122
<7> DDR_CS1_DIMMA# S1# NC2 +1.5V
123 124
125 VDD17 VDD18 126 +VREF_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

.1U_0402_16V7K

2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

C135

C136
DDR_A_D33 131 132 DDR_A_D37 1 1 1
DQ33 DQ37

10U_0603_6.3V6M
C139

10U_0603_6.3V6M
C140

10U_0603_6.3V6M
C141

10U_0603_6.3V6M
C142

10U_0603_6.3V6M
C143

10U_0603_6.3V6M
C144

.1U_0402_16V7K
C145

.1U_0402_16V7K
C146

.1U_0402_16V7K
C147

.1U_0402_16V7K
C148
133 134 1 1 1 1 1 1 1 @ 1 1 1
DDR_A_DQS#4 135 VSS29 VSS30 136 DDR_A_DM4 + C149 @
B DDR_A_DQS4 137 DQS#4 DM4 138 220U_6.3V_M B
139 DQS4 VSS31 140 DDR_A_D38 2 2
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2 2 2 2 2 2 2 2 2 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45 @
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
DDR_A_DM5 153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
VSS37 VSS38 VDDQ(1.5V) =
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
DQ43 DQ47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DQ48 DQ52 6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168 Place near DIMM
DDR_A_DQS#6 169 VSS41 VSS42 170 DDR_A_DM6
DQS#6 DM6 VTT(0.75V) =
DDR_A_DQS6 171 172 7/28 Update connect GND directly
173 DQS6 VSS43 174 DDR_A_D54
VSS44 DQ54 3*0805 10uf 4*0402 1uf
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178 +0.75VS
DQ51 VSS45 VREF =
179 180 DDR_A_D60 DDR_A_DM0
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 DDR_A_DM1
DQ56 DQ61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 183 184 DDR_A_DM2
185 DQ57 VSS47 186 DDR_A_DQS#7 DDR_A_DM3
VSS48 DQS#7 VDDSPD (3.3V)=

1U_0402_6.3V6K
C150

1U_0402_6.3V6K
C152
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM4
189 DM7 DQS7 190 DDR_A_DM5
VSS49 VSS50 1*0402 0.1uf 1*0402 2.2uf 1 1
DDR_A_D58 191 192 DDR_A_D62 DDR_A_DM6
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DDR_A_DM7
195 DQ59 DQ63 196
197 VSS51 VSS52 198 2 2
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,26> Layout Note:
2.2U_0603_6.3V4Z

.1U_0402_16V7K

A 201 202 SMB_CLK_S3 A


SA1 SCL SMB_CLK_S3 <13,15,26>
Place near DIMM
C155

C156

1 1 203 204 +0.75VS


VTT1 VTT2
205 206 0.65A@0.75V
G1 G2
2 2 LCN_DAN06-K4806-0103

ME@ Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 12 of 60
5 4 3 2 1
5 4 3 2 1

+VREF_DQ_DIMMB 3A@1.5V
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]

<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB
DDR_B_D4
<7> DDR_B_MA[0..15]
DDR_B_D0 DDR_B_D5
DDR_B_D1
DDR_B_DQS#0
DDR_B_DM0 DDR_B_DQS0

D DDR_B_D2 DDR_B_D6 D
DDR_B_D3 DDR_B_D7

DDR_B_D8 DDR_B_D12
DDR_B_D9 DDR_B_D13

DDR_B_DQS#1 DDR_B_DM1
DDR_B_DQS1 DDR3_DRAMRST#
DDR3_DRAMRST# <12,7>

For Arranale only +VREF_DQ_DIMMB DDR_B_D10 DDR_B_D14


DDR_B_D11 DDR_B_D15
supply from a external 1.5V voltage divide
DDR_B_D16 DDR_B_D20
circuit. DDR_B_D17 DDR_B_D21

DDR_B_DQS#2 DDR_B_DM2
DDR_B_DQS2
DDR_B_D22
DDR_B_D18 DDR_B_D23
DDR_B_D19
DDR_B_D28
DDR_B_D24 DDR_B_D29
DDR_B_D25
DDR_B_DQS#3
DDR_B_DM3 DDR_B_DQS3

DDR_B_D26 DDR_B_D30
DDR_B_D27 DDR_B_D31

C DDR_CKE2_DIMMB DDR_CKE3_DIMMB C
<7> DDR_CKE2_DIMMB DDR_CKE3_DIMMB <7>
DDR_B_MA15
<7> DDR_B_BS2 DDR_B_BS2 DDR_B_MA14

DDR_B_MA12 DDR_B_MA11
DDR_B_MA9 DDR_B_MA7

DDR_B_MA8 DDR_B_MA6
DDR_B_MA5 DDR_B_MA4

DDR_B_MA3 DDR_B_MA2
DDR_B_MA1 DDR_B_MA0

<7> M_CLK_DDR2 M_CLK_DDR2 M_CLK_DDR3


M_CLK_DDR3 <7>
<7> M_CLK_DDR#2 M_CLK_DDR#2 M_CLK_DDR#3
M_CLK_DDR#3 <7>
DDR_B_MA10 DDR_B_BS1
Layout Note: (10uF_0603_6.3V)*8
DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 DDR_B_RAS#
DDR_B_RAS# <7>
Place near DIMM
<7> DDR_B_WE# DDR_B_WE# DDR_CS2_DIMMB# (0.1uF_402_10V)*4
DDR_CS2_DIMMB# <7>
<7> DDR_B_CAS# DDR_B_CAS# M_ODT2
M_ODT2 <7>
DDR_B_MA13 M_ODT3
M_ODT3 <7> +VREF_CB
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB#
+1.5V
+VREF_CB

DDR_B_D32 DDR_B_D36
DDR_B_D33 DDR_B_D37

DDR_B_DQS#4 DDR_B_DM4
B DDR_B_DQS4 B
DDR_B_D38
DDR_B_D34 DDR_B_D39
DDR_B_D35
DDR_B_D44
DDR_B_D40 DDR_B_D45
DDR_B_D41
DDR_B_DQS#5
DDR_B_DM5 DDR_B_DQS5 VDDQ(1.5V) =
DDR_B_D42 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DDR_B_D47
6*0603 10uf (PER CONNECTOR) Layout Note:
DDR_B_D48 DDR_B_D52
DDR_B_D49 DDR_B_D53 Place near DIMM
VTT(0.75V) =
DDR_B_DQS#6 DDR_B_DM6
DDR_B_DQS6 3*0805 10uf 4*0402 1uf
DDR_B_D54
DDR_B_D50 DDR_B_D55 +0.75VS
DDR_B_D51
DDR_B_D60 1*0402 0.1uf 1*0402 2.2uf DDR_B_DM0
DDR_B_D56 DDR_B_D61 DDR_B_DM1
DDR_B_D57 VDDSPD (3.3V)= DDR_B_DM2
DDR_B_DQS#7 DDR_B_DM3
DDR_B_DM7 DDR_B_DQS7 1*0402 0.1uf 1*0402 2.2uf DDR_B_DM4
DDR_B_DM5
DDR_B_D58 DDR_B_D62 DDR_B_DM6
DDR_B_D59 DDR_B_D63 DDR_B_DM7

+3VS SMB_DATA_S3
A SMB_DATA_S3 <12,15,26> A
SMB_CLK_S3 Layout Note:
+3VS SMB_CLK_S3 <12,15,26>
+0.75VS
0.65A@0.75V Place near DIMM

Title

Size Document Number Rev

5 4 3 2 1
5 4 3 2 1

PCH_RTCX1
CLRP2 CMOS setting
W=20mils W=20mils Shunt Clear CMOS
1 2 PCH_RTCX2
+RTCVCC +RTCBATT R98 10M_0402_5% Open Keep CMOS

2
R99 @
1K_0402_5% R104 CLRP3 TPM setting
1 2 0_0402_5%
Y1 Shunt Clear ME RTC Registers

1
1 1 2
C179 32.768KHZ_12.5PF_CM31532768DZFT Open Keep ME RTC Registers
1U_0603_10V4Z 1 1
C181
2 C180 18P_0402_50V8J
D 18P_0402_50V8J D
2 2

CMOS U4A

SHORT PADS
CLRP2
+RTCVCC @
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <32>

1
R101 1 2 1M_0402_5% SM_INTRUDER# A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <32>

LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 <32>
R102 1 2 330K_0402_5% PCH_INTVRMEN 1U_0603_10V4Z C37 LPC_AD3

2
1 2 2 D20 FWH3 / LAD3 LPC_AD3 <32>
PCH_RTCRST#
R103 20K_0402_5% RTCRST# D36 LPC_FRAME#
INTVRMEN 1 2 PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# <32>
SRTCRST# E36
Integrated VRM enable
H R100 20K_0402_5%
* 1 LDRQ0#

1
SHORT PADS
CLRP3
Integrated VRM disable SM_INTRUDER# K22 K36

RTC
L @
INTRUDER# LDRQ1# / GPIO23
C182
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <32>

2
2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <30>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <30>
AP7 SATA_ITX_C_DRX_N0 HDD

SATA 6G
SATA0TXN SATA_ITX_C_DRX_N0 <30>
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 <30>
HDA_SYNC SATA0TXP
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10
<31> HDA_SPKR SPKR SATA1RXN AM8
LOW= Disable (Default)
* HDA_RST# K34
HDA_RST#
SATA1RXP
SATA1TXN
AP11
AP10
SATA1TXP
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<31> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <30>
AD5 SATA_DTX_C_IRX_P2 ODD
SATA2RXP SATA_DTX_C_IRX_P2 <30>
R106 2 @ 1 1K_0402_5% ME_FLASH G34 AH5 SATA_ITX_C_DRX_N2
HDA_SDIN1 SATA2TXN AH4 SATA_ITX_C_DRX_N2 <30>
SATA_ITX_C_DRX_P2
SATA2TXP SATA_ITX_C_DRX_P2 <30>
Low = Disabled (Default) C34
* HDA_SDIN2 AB8

IHDA
High = Enabled [Flash Descriptor Security Overide] A34 SATA3RXN AB10
HDA_SDIN3 SATA3RXP AF3
SATA3TXN AF1
ME_FLASH A36 SATA3TXP
+3V_PCH <32> ME_FLASH HDA_SDO Y7

SATA
SATA4RXN Y5
R108 2 1 1K_0402_5% HDA_SYNC PCH_GPIO33 C36 SATA4RXP AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
PCH_GPIO13 N32 SATA4TXP
HDA_DOCK_RST# / GPIO13 Y3
This signal has a weak internal pull-down
SATA5RXN Y1
On Die PLL VR is supplied by SATA5RXP
1.5V when smapled high AB3
PCH_JTAG_TCK J3 SATA5TXN AB1
* 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 R111
JTAG_TMS SATAICOMPO +V1.05S_VCCP

JTAG
37.4_0402_1%
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
+5VS JTAG_TDI SATAICOMPI
PCH_JTAG_TDO H1
JTAG_TDO AB12 R113 +V1.05S_VCCP
HDA_BIT_CLK SATA3RCOMPO
<31> HDA_BITCLK_AUDIO For EMI 49.9_0402_1%
2
G

Q10 AB13 SATA3_COMP 1 2


RP12 LBSS138LT1G_SOT-23-3 SATA3COMPI
8 1 HDA_SYNC_R 3 1 HDA_SYNC
<31> HDA_SYNC_AUDIO
7 2 SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2
S

6 3 SPI_CLK SATA3RBIAS R115


2

B 5 4 HDA_RST# SPI_SB_CS0# Y14 750_0402_1% B


<31> HDA_RST_AUDIO# SPI_CS0#
R878
33_0804_8P4R_5% 1M_0402_5% T1
SPI_CS1#
SPI

ME_FLASH P3 SATALED#
<31> HDA_SDOUT_AUDIO SATALED#
Share ROM
1

SPI_SI V4 V14 PCH_GPIO21


SPI_MOSI SATA0GP / GPIO21 @
SPI_SO_R U3 P1 BBS_BIT0_R RP2
check with vender SPI_MISO SATA1GP / GPIO19 SPI_SO_R 1 8 EC_SPI_SO
2 7 EC_SPI_SO <32>
Del Q10 check with codec SPI_SI EC_SPI_SI
EC_SPI_SI <32>
PANTHER-POINT_FCBGA989 SPI_CLK_PCH_R 3 6 EC_SPI_CLK
VDDIO using 3VALW HM76@ SPI_SB_CS0# 4 5 EC_SPI_CS#
EC_SPI_CLK <32>
EC_SPI_CS# <32>
SA00005FH70
S IC BD82HM76 SLJ8E C1 BGA 989P PCH C38! 0_0804_8P4R_5%
SPI_CLK_PCH_R
U4 HM70@ +3V_ROM
Share ROM
1

R124
33_0402_5% R127 1 2 SPI_WP# +3V_ROM
@ 3.3K_0402_5%
SA00005MQ80
2

IC BD82HM70 SJTNV C1 BGA 989P PCH C38! R129 1 2 SPI_HOLD# U5


3.3K_0402_5% SPI_SB_CS0# 1 8
SPI_SO_R 1 R131 2 SPI_SO_L 2 CS# VCC 7 SPI_HOLD#
DPDG1.1 C190 For EMI U4 NM70@
SO HOLD#
22P_0402_50V8J 0_0402_5% SPI_WP# 3 6 SPI_CLK_1 1 R133 2 SPI_CLK_PCH_R
@ 4 WP# SCLK 5 0_0402_5% SPI_SI
+3VS @ GND SI
For EMI @
RP17 W25Q64FVSSIQ_SO8 For EMI
BBS_BIT0_R 8 1 SA000039A30
R124;c190 close to U4.T3 pin SA00005WU60 SATALED# 7 2 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
S IC BD82NM70 SLJTA C1 BGA 989P PCH C38! PCH_GPIO16 6 3
A <19> PCH_GPIO16 SERIRQ 5 4 A

10K_0804_8P4R_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 06, 2013 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1

U4B
Q60A
2N7002DW-T/R7_SOT363-6
PCIE_PRX_DTX_N1 BG34 6 1 SMB_CLK_S3
<27> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,26>
LAN PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPI011 2 R134 1 10K_0402_5%
<27> PCIE_PRX_DTX_P1 PERP1 SMBALERT# / GPIO11 +3V_PCH
C192 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N1 AV32
<27> PCIE_PTX_C_DRX_N1
C193 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P1 AU32 PETN1 H14 PCH_SMBCLK DIMM1

2
<27> PCIE_PTX_C_DRX_P1 PETP1 SMBCLK

<26> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA
C9 PCH_SMBDATA
+3VS DIMM2

5
PCIE_PRX_DTX_P2 BF34
WLAN
<26> PCIE_PRX_DTX_P2
<26> PCIE_PTX_C_DRX_N2
C194 1 2 .1U_0402_16V7K PCIE_PTX_DRX_N2 BB32 PERP2
PETN2
Mini Card
C195 1 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<26> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,26>

SMBUS
A12 DRAMRST_CNTRL_PCH
BG36 SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <10,7>
2N7002DW-T/R7_SOT363-6
BJ36 PERN3 C8 PCH_SML0CLK
PERP3 SML0CLK Q60B
D AV34 2 R139 1 D
PETN3 +3V_PCH
AU34 G12 PCH_SML0DATA 1K_0402_5%
PETP3 SML0DATA Q61A
BF36 PCH_HOT# 2 R140 1 10K_0402_5% 2N7002DW-T/R7_SOT363-6
PERN4 +3V_PCH
BE36 6 1 EC_SMB_CK2
AY34 PERP4 C13 EC_SMB_CK2 <29,32>
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 SML1CLK VGA

2
BG37 SML1CLK / GPIO58

PCI-E*
BH37 PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3VS EC

5
AY36
BB36 PETN5
PETP5
Thermal Sensor
3 4 EC_SMB_DA2
BJ38 EC_SMB_DA2 <29,32>
BG38 PERN6 2N7002DW-T/R7_SOT363-6
AU36 PERP6 M7

Controller
PETN6 CL_CLK1 Q61B
AV36 +3V_PCH
PETP6 +3V_PCH

Link
BG40 T11
PERN7 CL_DATA1

2
BJ40
AY40 PERP7
PETN7

2
BB40 P10 R143
PETP7 CL_RST1# R544 R545
10K_0402_5%
BE38 2.2K_0402_5% 2.2K_0402_5%

1
BC38 PERN8
AW38 PERP8

1
AY38 PETN8 PCH_SML0CLK
PETP8
M10 1 R145 2 10K_0402_5% PCH_SML0DATA
R153 1 @ 2 0_0402_5% CLK_PCIE_LAN#_R Y40 PEG_A_CLKRQ# / GPIO47 @
<27> CLK_PCIE_LAN# CLKOUT_PCIE0N
LAN R154 1 @ 2 0_0402_5% CLK_PCIE_LAN_R Y39
<27> CLK_PCIE_LAN CLKOUT_PCIE0P AB37
C
For EMI CLKOUT_PEG_A_N C
J2 AB38

CLOCKS
<27> CLKREQ_LAN# 2 1 10K_0402_5% PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
+3V_PCH R152
+3V_PCH
R156 1 @ 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
<26> CLK_PCIE_WLAN1# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <6> +3VS
R165 1 @ 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
<26> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN For EMI RP23
M1 SML1DATA 8 1
<26> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
+3VS R158 2 1 10K_0402_5% AM12 EC_SMB_DA2 7 2
CLKOUT_DP_N AM13 SML1CLK 6 3
AA48 CLKOUT_DP_P EC_SMB_CK2 5 4
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5% 2.2K_0804_8P4R_5%
PCH_GPIO20 V10 CLKIN_DMI_N BE18 CLK_BUF_CPU_DMI R157 1 2 10K_0402_5%
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P +3V_PCH

Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5% +3VS


Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_DMI2 R160 1 2 10K_0402_5% RP24
CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 8 1
PCH_GPIO25 A8 SMB_CLK_S3 7 2
PCIECLKRQ3# / GPIO25 G24 CLK_BUF_DREF_96M# R162 1 2 10K_0402_5% PCH_SMBDATA 6 3
CLKIN_DOT_96N E24 CLK_BUF_DREF_96M R163 1 2 10K_0402_5% SMB_DATA_S3 5 4
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N 2.2K_0804_8P4R_5%
CLKOUT_PCIE4P AK7 CLK_BUF_PCIE_SATA# R164 1 2 10K_0402_5%
PCH_GPIO26 L12 CLKIN_SATA_N AK5 CLK_BUF_PCIE_SATA R166 1 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%


V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B B
AB42 V47 XTAL25_IN
AB40 CLKOUT_PEG_B_N XTAL25_IN V49 XTAL25_OUT
CLKOUT_PEG_B_P XTAL25_OUT
PCH_GPIO56 E6 R171 +V1.05S_VCCP
PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
V40 XCLK_RCOMP
V42 CLKOUT_PCIE6N
CLKOUT_PCIE6P XTAL25_IN
PCH_GPIO45 T13
PCIECLKRQ6# / GPIO45 27M_SSC XTAL25_OUT 1 2
V38 K43 R169 1M_0402_5%
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P F47 3 4
PCH_GPIO46 K12 CLKOUTFLEX1 / GPIO65 OSC NC
PCIECLKRQ7# / GPIO46 H47 2 1
AK14 CLKOUTFLEX2 / GPIO66 NC OSC
PCIE_CLK_8N AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67 Y2
PCIE_CLK_8P CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 PCH_GPIO67 <19>
1 25MHZ_10PF_7V25000014 1
BIOS Request SKU ID C196 C197
PANTHER-POINT_FCBGA989 12P_0402_50V8J 12P_0402_50V8J
2 2
HM76@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 15 of 60
5 4 3 2 1
5 4 3 2 1

+RTCVCC

DSWODVREN R179 2 1 330K_0402_5%

R183 2 @ 1 330K_0402_5%
D D
DSWODVREN - On Die DSW VR Enable
U4C * HEnable
LDisable

@ DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0


<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
U15 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
3

DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3


<5> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <5>
1 BC12 FDI_CTX_PRX_N4
G

<32,43> VGATE A FDI_RXN4 FDI_CTX_PRX_N4 <5>


4 SYS_PWROK DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
Y <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
PCH_PWROK 2 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
B <5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
P

DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7


<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3
5

DMI3RXP
1

@ BG14 FDI_CTX_PRX_P0
FDI_RXP0 FDI_CTX_PRX_P0 <5>
R180 DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <5>
10K_0402_5% DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
+3VS DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3
<5> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <5>
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4
FDI_CTX_PRX_P4 <5>
2

<5> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 AU18 DMI2TXP
DMI_CRX_PTX_P3
<5> DMI_CRX_PTX_P3 DMI3TXP AW16 FDI_INT
FDI_INT FDI_INT <5>
+V1.05S_VCCP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
R177 49.9_0402_1%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
R178 750_0402_1%
4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
A18 DSWODVREN
DSWVRMEN
SUSACK# is only used on platform
that support the Deep Sx state.

System Power Management


C12 E22 EC_RSMRST#
SUSACK# DPWROK

SYS_RST# K3 B9
<19> SYS_RST# SYS_RESET# WAKE# PCIE_WAKE# <26>

SYS_PWROK P12 N3 PM_CLKRUN#


<32> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32
R299 10K_0402_5%
L22 G8 SUS_STAT# 2 1
<32> PCH_PWROK PWROK SUS_STAT# / GPIO61

PCH_PWROK L10 N14


APWROK SUSCLK / GPIO62 SUSCLK <32>

PM_DRAM_PWRGD B13 D10


<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <32>

C21 H4
<32> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <32>
+3V_PCH
SUSWARN# K16 F4
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <32>
2 R192 1 300_0402_5% PM_DRAM_PWRGD
B E20 G10 Can be left NC when IAMT is not support on the platfrom B
<32> PBTN_OUT# PWRBTN# SLP_A#
R194 2 1 10K_0402_5% SUSWARN#

D29 1 2 AC_PRESENT_R H20 G16


<32,36,38> ACIN ACPRESENT / GPIO31 SLP_SUS#
CH751H-40PT_SOD323-2
R197 2 1 10K_0402_5% EC_RSMRST# PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
@
RI# A10 K14 Can be left NC if no use integrated LAN.
RI# SLP_LAN# / GPIO29

PANTHER-POINT_FCBGA989

HM76@
+3V_PCH

R309 1 2 200K_0402_5% AC_PRESENT_R

+3V_PCH

RP25
8 1 PCIE_WAKE#
A 7 2 RI# A
6 3 EC_SMI#
5 4 EC_SMI# <19,32>

10K_0804_8P4R_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 16 of 60
5 4 3 2 1
5 4 3 2 1

U4D
R438
D 2 1 ENBKL J47 AP43 D
<32> ENBKL L_BKLTEN SDVO_TVCLKINN
M45 AP45
<23> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
100K_0402_1% P45 AM42
<23> PCH_PWM L_BKLTCTL SDVO_STALLN AM40
EDID_CLK T40 SDVO_STALLP
<23> EDID_CLK K47 L_DDC_CLK AP39
EDID_DATA
<23> EDID_DATA L_DDC_DATA SDVO_INTN AP40
CTRL_CLK T45 SDVO_INTP
CTRL_DATA P39 L_CTRL_CLK
+3VS L_CTRL_DATA
2 R206
2.37K_0402_1% 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <25>
AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <25>
RP14 LVD_VREF AE48
8 1 EDID_DATA AE47 LVD_VREFH AT49
7 2 EDID_CLK LVD_VREFL DDPB_AUXN AT47
6 3 CTRL_DATA DDPB_AUXP AT40
DDPB_HPD TMDS_B_HPD# <25>
5 4 CTRL_CLK AK39
<23> LVDS_ACLK# LVDSA_CLK#

LVDS
AK40 AV42 TMDS_B_DATA2#_PCHHDMI@ C200 1 2 .1U_0402_16V7K
<23> LVDS_ACLK LVDSA_CLK DDPB_0N HDMI_TX2-_CK <25>
2.2K_0804_8P4R_5% AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 .1U_0402_16V7K HDMI D2
AN48 DDPB_0P AV45 TMDS_B_DATA1#_PCHHDMI@ 1 2 HDMI_TX2+_CK <25>
C202 .1U_0402_16V7K
<23> LVDS_A0# AM47 LVDSA_DATA#0 DDPB_1N AV46 TMDS_B_DATA1_PCH HDMI@ 1 2 HDMI_TX1-_CK <25>
C203 .1U_0402_16V7K HDMI D1
<23> LVDS_A1# LVDSA_DATA#1 DDPB_1P HDMI_TX1+_CK <25>

Digital Display Interface


AK47 AU48 TMDS_B_DATA0#_PCHHDMI@ C204 1 2 .1U_0402_16V7K HDMI
C <23> LVDS_A2# AJ48 LVDSA_DATA#2 DDPB_2N AU47 TMDS_B_DATA0_PCH HDMI@ 1 2 HDMI_TX0-_CK <25> C
C205 .1U_0402_16V7K HDMI D0
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <25>
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 .1U_0402_16V7K
AN47 DDPB_3N AV49 TMDS_B_CLK_PCH 1 2 HDMI_CLK-_CK <25>
HDMI@ C207 .1U_0402_16V7K HDMI CLK
<23> LVDS_A0 AM49 LVDSA_DATA0 DDPB_3P HDMI_CLK+_CK <25>
<23> LVDS_A1 LVDSA_DATA1
AK49
<23> LVDS_A2 AJ47 LVDSA_DATA2 P46
LVDSA_DATA3 DDPC_CTRLCLK CAP move on Conn, side
P42
RP20 DDPC_CTRLDATA
8 1 DAC_BLU AF40
7 2 DAC_GRN AF39 LVDSB_CLK# AP47
6 3 DAC_RED LVDSB_CLK DDPC_AUXN AP49
5 4 AH45 DDPC_AUXP AT38
AH47 LVDSB_DATA#0 DDPC_HPD
150_0804_8P4R_1% AF49 LVDSB_DATA#1 AY47
AF45 LVDSB_DATA#2 DDPC_0N AY49
Max = 800 mils LVDSB_DATA#3 DDPC_0P
DDPC_1N
AY43
AH43 AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
DAC_BLU LVDSB_DATA3 DDPC_3N BB49
<24> DAC_BLU DDPC_3P
DAC_GRN
<24> DAC_GRN N48 M43
B B
DAC_RED P49 CRT_BLUE DDPD_CTRLCLK M36
<24> DAC_RED T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
AT45
DDPD_AUXN

CRT
CRT_DDC_CLK T39 AT43
<24> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
CRT_DDC_DATA M40 BH41
<24> CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD
BB43
+3VS M47 DDPD_0N BB45
<24> CRT_HSYNC M49 CRT_HSYNC DDPD_0P BF44
<24> CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
DDPD_2N
1

CRT_IREF T43 BE42


R559 R524 T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N
1

2.2K_0402_5% 2.2K_0402_5% BG42


R211 DDPD_3P
1K_0402_1% PANTHER-POINT_FCBGA989
2

CRT_DDC_CLK
2

CRT_DDC_DATA HM76@

A A

Security Classification Compal Secret Data


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 17 of 60
5 4 3 2 1
5 4 3 2 1

+3VS
RP1
PCI_PIRQA# 1 10
PCI_PIRQD# 2 9 PCH_GPIO2 U4E
PCI_PIRQC# 3 8 DGPU_PWR_EN AY7
PCI_PIRQB# 4 7 PCH_GPIO4 RSVD1 AV7
5 6 PCH_GPIO3 BG26 RSVD2 AU3
+3VS BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
8.2K_1206_10P8R_5% BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8
AH38 TP5 RSVD6
D TP6 D
AH37 AU2
AK43 TP7 RSVD7 AT4
+3VS AK45 TP8 RSVD8 AT3
RP7 C18 TP9 RSVD9 AT1
8 1 DGPU_HOLD_RST# N30 TP10 RSVD10 AY3
7 2 PCH_WL_OFF# H3 TP11 RSVD11 AT5
6 3 PCH_GPIO5 AH12 TP12 RSVD12 AV3
5 4 PCH_GPIO52 AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
8.2K_0804_8P4R_5% Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
Pull-up resistors are not required TP17 RSVD17
L24 BB3
on these signals AB46 TP18 RSVD18 BB7
R292 1 @ 2 8.2K_0402_5% PCH_GPIO51 AB45 TP19 RSVD19 BE8
TP20 RSVD20

RSVD
BD4
R557 1 @ 2 8.2K_0402_5% PCH_GPIO53 RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
TP24 RSVD25
AY5
RSVD26 BA2
USB3_RX1_N BE28 RSVD27
<34> USB3_RX1_N USB3Rn1
<34> USB3_RX2_N USB3_RX2_N BC30 AT12
USB3_RX3_N BE32 USB3Rn2 RSVD28 BF3
C USB3Rn3 RSVD29 C
Boot BIOS Strap bit1 BBS1 USB3_RX4_N BJ32
USB3_RX1_P BC28 USB3Rn4
<34> USB3_RX1_P USB3Rp1
Boot BIOS <34> USB3_RX2_P USB3_RX2_P BE30 USB Debug Port = Port1 and Port9
USB3_RX3_P BF32 USB3Rp2
Bit11 Bit10 Destination USB3_RX4_P BG32 USB3Rp3
USB3Rp4 USBP0N
C24 USB20_N0
USB20_N0 <34>
USB3_TX1_N AV26 A24 USB20_P0 LEFT USB
<34> USB3_TX1_N USB3Tn1 USBP0P USB20_P0 <34>
0 1 Reserved USB3_TX2_N BB26 C25 USB20_N1 (USB 3.0)
<34> USB3_TX2_N USB3Tn2 USBP1N USB20_N1 <34>
GNT1#/ USB3_TX3_N AU28 B25 USB20_P1 LEFT USB
USB3Tn3 USBP1P USB20_P1 <34>
1 0 Reserved USB3_TX4_N AY30 C26 USB20_N2
GPIO51 USB3_TX1_P AU26 USB3Tn4 USBP2N A26 USB20_P2
USB20_N2 <34>
<34> USB3_TX1_P
USB3_TX2_P AY26 USB3Tp1 USBP2P K28 USB20_N3
USB20_P2 <34> Touch Screen
1 1 SPI (Default)
* <34> USB3_TX2_P
USB3_TX3_P AV28 USB3Tp2
USB3Tp3
USBP3N
USBP3P
H28 USB20_P3
USB20_N3
USB20_P3
<23>
<23> USB Camera
0 0 LPC USB3_TX4_P AW30 E28
USB3Tp4 USBP4N D28
USBP4P C28
USBP5N A28
USBP5P C29
USBP6N B29
PCI_PIRQA# K40 USBP6P N28
PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# G38 PIRQC# USBP8N K30
PIRQD# USBP8P G30 USB20_N9
USBP9N USB20_N9 <34>
DGPU_HOLD_RST# C46 E30 USB20_P9 RIGHT USB
REQ1# / GPIO50 USBP9P USB20_P9 <34>

USB
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <26>
E40 A30 USB20_P10 WLAN
<32> DGPU_PWR_EN REQ3# / GPIO54 USBP10P USB20_P10 <26>
B L32 USB20_N11 B
USBP11N USB20_N11 <33>
PCH_GPIO51 D47 K32 USB20_P11 CARD READER
GNT1# / GPIO51 USBP11P USB20_P11 <33>
PCH_GPIO53 E42 G32
PCH_WL_OFF# F46 GNT2# / GPIO53 USBP12N E32
<26> PCH_WL_OFF# GNT3# / GPIO55 USBP12P C32
USBP13N A32
PCH_GPIO2 G42 USBP13P
GPIO55 PIRQE# / GPIO2
PCH_GPIO3 G40
PCH_WL_OFF# R215 1 @ 2 1K_0402_5% PCH_GPIO4 C42 PIRQF# / GPIO3 C33 USBRBIAS 1 R218 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# 22.6_0402_1%
PIRQH# / GPIO5
B33
Within 500 mils
PCI_PME# K10 USBRBIAS
A16 swap overide Strap/Top-Block PME#
Swap Override jumper For LEFT USB3.0 Port
PCH_PLTRST# C6 A14 USB_OC0#
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# <34>
Low=A16 swap K20 USB_OC1#
OC1# / GPIO40 B17 USB_OC2#
override/Top-Block OC2# / GPIO41
PCI_GNT3# Swap Override enabled 22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
High=Default 22_0402_5% 1 2 R220 CLK_PCI_EC_R H43 L16 USB_OC4#
* <32> CLK_PCI_EC
CLK_PCI_DB_R J48 CLKOUT_PCI1
CLKOUT_PCI2
OC4# / GPIO43
OC5# / GPIO9
A16 USB_OC5#
USB_OC4# <34>
+3V_PCH
For EMI K42 D14 USB_OC6# For RIGHT USB2.0 Port
CLKOUT_PCI3 OC6# / GPIO10 RP18
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14 USB_OC0# 1 10
USB_OC1# 2 9 USB_OC4#
PANTHER-POINT_FCBGA989 USB_OC2# 3 8 USB_OC5#
USB_OC3# 4 7 USB_OC6#
HM76@ 5 6 USB_OC7#
+3V_PCH
A A

@ R222 10K_1206_10P8R_5%
1 2 PCH_PLTRST#
<26,27,32> PLT_RST#
0_0402_5%
Security Classification Compal Secret Data
1

1
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
C208 @ R223
1U_0402_6.3V6K
2
100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 18 of 60
5 4 3 2 1
5 4 3 2 1

+3VS +3VS +3VS

PCH_GPIO69 PCH_GPIO70 Function

2
10K_0402_5%

10K_0402_5%

10K_0402_5%
NM70@ NM70@ HM70@ Mars@

1 1 NM70 R702 R703 R703 PCH_GPIO71 Function R704


10K_0402_5%

1
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71
Reserved 1 Mars XT
1 0

2
10K_0402_5%

10K_0402_5%
0 Sun Pro R706
HM70@ HM76@ HM76@
D
0 1 HM70 R707 R707 R705
200K_0402_5%
Sun@
D
10K_0402_5%

1
0 0 HM76

U4F

PCH_GPIO0 T7 C40 PCH_GPIO68


BMBUSY# / GPIO0 TACH4 / GPIO68
PCH_GPIO1 A42 B41 PCH_GPIO69
GPIO28 TACH1 / GPIO1 TACH5 / GPIO69
On-Die PLL Voltage Regulator PCH_GPIO6 H36 C41 PCH_GPIO70 +3VS
TACH2 / GPIO6 TACH6 / GPIO70
This signal has a weak internal pull up
EC_SCI# E38 A40 PCH_GPIO71
<32> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71

2
HOn-Die voltage regulator enable
* LOn-Die PLL Voltage Regulator disable <16,32> EC_SMI#
EC_SMI# C10
GPIO8
R236
10K_0402_5%
R240 1 @ 2 1K_0402_5% PCH_GPIO28 PCH_GPIO12 C4
+3V_PCH LAN_PHY_PW R_CTRL / GPIO12

1
1 R230 2 1K_0402_5% EC_LID_OUT# G2 P4 +3VS
GPIO15 A20GATE GATEA20 <32>
<32> EC_LID_OUT# AU16
PCH_GPIO16 U2 PECI
<14> PCH_GPIO16 SATA4GP / GPIO16 P5 KBRST# KBRST# R226 1 2 10K_0402_5%
* PCH_GPIO27 (Have internal Pull-High) RCIN# KBRST# <32>

GPIO
DGPU_PWROK D40 AY11
High: VCCVRM VR Enable TACH0 / GPIO17 PROCPW RGD H_CPUPWRGD <6>

CPU/MISC
Low: VCCVRM VR Disable PCH_BT_ON# T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
H_THRMTRIP# <6>
C
SCLOCK / GPIO22 THRMTRIP# R239 390_0402_5% C
1 2 10K_0402_5% <26> PCH_BT_ON# E8 T14
R245 @ PCH_GPIO27 ODD_EN
+3V_PCH <30> ODD_EN GPIO24 INIT3_3V#
PCH_GPIO27 E16 AY1
R241 GPIO27 DF_TVS INIT3_3V
1 2 10K_0402_5% PCH_GPIO28 P8 This signal has weak internal PU,can't pull low
GPIO28 AH8
1 R242 2 10K_0402_5% K1 TS_VSS1
GPIO36, 37 +3VS
INTEL_BT_OFF#
STP_PCI# / GPIO34 +1.8VS
AK11
+3VS When Unused as GPIO or SATA*GP PCH_GPIO35 K4 TS_VSS2
+3VS <26> INTEL_BT_OFF# GPIO35
Use 8.2K-10K pull-down to ground. TS_VSS3
AH10 DMI Termination Voltage
PCH_GPIO36 V8
SATA2GP / GPIO36
1

1
AK10 Set to Vcc when HIGH
M5 TS_VSS4
R244 @ R250 @ PCH_GPIO37
SATA3GP / GPIO37
NV_CLE
10K_0402_5% 10K_0402_5% Set to Vss when LOW R216
PCH_GPIO38 N2 P37 2.2K_0402_5%
SLOAD / GPIO38 NC_1
2

2
PCH_GPIO37 PCH_GPIO36 PCH_GPIO39 M3 NV_CLE 2 1
SDATAOUT0 / GPIO39 H_SNB_IVB# <6>
R217 1K_0402_5%
1

PCH_GPIO48 V13 BG2 Weak internal CLOSE TO THE BRANCHING POINT


SDATAOUT1 / GPIO48 VSS_NCTF_15
1

PU,Do not pull low


R881 PCH_GPIO49 V3 BG48
10K_0402_5% R547 @ SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
10K_0402_5% PCH_GPIO57 D6 BH3
2

GPIO57 VSS_NCTF_17
2

BH47
@ VSS_NCTF_18
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
A44 BJ44
B VSS_NCTF_2 VSS_NCTF_20 B
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
+3VS VSS_NCTF_4 VSS_NCTF_22
BIOS Request SKU ID
A5 BJ5
RP10 VSS_NCTF_5 VSS_NCTF_23
+3VS 8 1 PCH_GPIO39 A6 BJ6
7 2 SYS_RST# VSS_NCTF_6 VSS_NCTF_24
SYS_RST# <16>
6 3 PCH_BT_ON# B3 C2
5 4 PCH_GPIO35 VSS_NCTF_7 VSS_NCTF_25
B47 C48
10K_0804_8P4R_5% VSS_NCTF_8 VSS_NCTF_26
2

1
10K_0402_5%

10K_0402_5%

BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 D49
R711 R246 VSS_NCTF_10 VSS_NCTF_28
UMA@ UMA@ BE1 E1
1

VSS_NCTF_11 VSS_NCTF_29
PCH_GPIO38 BE49 E49
VSS_NCTF_12 VSS_NCTF_30
PCH_GPIO67 BF1 F1
PCH_GPIO67 <15> VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32
2

1
10K_0402_5%

10K_0402_5%

R708 R298 PANTHER-POINT_FCBGA989


PX@ PX@
PCH_GPIO38 PCH_GPIO67 Function HM76@
1

A A

0 0 SG(Optimus / PX)
0 1 Reserved Security Classification Compal Secret Data
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
1 0 DIS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 19 of 60
5 4 3 2 1

Compal Electronics, Inc.


5 4 3 2 1

L1 Change to 1 ohm P/N


+V1.05S_VCCP U4G POWER S RES 1/10W 1 +-1% 0603
+3VS PCH Power Rail Table
Near AA23
1300mA L1 1_0603_1% Refer to CPU EDS R1.5
AA23 U48 +VCCADAC 2 1
AC23 VCCCORE[1] 1mA VCCADAC
VCCCORE[2] 1 1 1 1 S0 Iccmax

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395@ Voltage Rail Voltage Current (A)

CRT
VCCCORE[3]

10U_0603_6.3V6M
C209
AD23 U47 C213 C214 C215 10U_0603_6.3V6M
AF21 VCCCORE[4] VSSADAC 0.01U_0402_16V7K .1U_0402_16V7K 10U_0603_6.3V6M

VCC CORE
AF23 VCCCORE[5] 2 2 2 2
VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 AG21 +3VS D
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36
VCCCORE[9] 1mA VCCALVDS V5REF 5 0.001
AG26
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]

LVDS
AJ26 AM37 L2
AJ27 VCCCORE[14] VCCTX_LVDS[1]
VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
AJ31 VCCCORE[16] VCCTX_LVDS[2]
1 1 1 0.1uH inductor, 200mA
VCCCORE[17] AP36
+V1.05S_VCCP
60mA VCCTX_LVDS[3] VccADAC 3.3 0.001
C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
AN19 VCCTX_LVDS[4] 2 2 2
VCCIO[28]
VccADPLLA 1.05 0.075

+VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.075


VCCAPLLEXP Near V33
This pin can be left as no connect in V33
AN16 VCC3_3[6]

HVCMOS
VccCore 1.05 1.3
On-Die VR enabled mode (default). VCCIO[15]
1
AN17
VCCIO[16] V34
VCC3_3[7]
C219 VccDMI 1.05 0.042
.1U_0402_16V7K
AN21 2
VCCIO[17]
VccIO 1.05 3.709
AN26 +1.5VS
VCCIO[18]
AN27 3711mA AT16 VccASW 1.05 0.903
VCCIO[19] VCCVRM[3]
+V1.05S_VCCP AP21 +V1.05S_VCCP
C
Near AN16 VCCIO[20] Near AT20 C
VccSPI 3.3 0.01
AP23 AT20
VCCIO[21] VCCDMI[1]
1
+V1.05S_VCCP
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 Near AB36 VccDSW 3.3 0.001
VCCIO[22]
10U_0603_6.3V6M
C221

VCCIO
C220
AP26 AB36 1U_0402_6.3V6K
VCCIO[23] 20mA VCCCLKDMI 2
1 VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
AN34 AG16 VccSus3_3 3.3 0.065
+3VS VCCIO[26] VCCDFTERM[1]
Share ROM
BH29 AG17 +1.8VS VccSusHDA 3.3 / 1.5 0.01
VCC3_3[3] 190mAVCCDFTERM[2]

DFT / SPI
1 Near AG16
C227
.1U_0402_16V7K +1.5VS AJ16 +3V_ROM VccVRM 1.8 / 1.5 0.167
VCCDFTERM[3]
2 1
AP16 C228
VCCVRM[2] AJ17
VCCDFTERM[4]
.1U_0402_16V7K VccCLKDMI 1.05 0.075
This pin can be left as no connect in +1.05VS_VCCAPLL_FDI BG6 2
On-Die VR enabled mode (default). +V1.05S_VCCP VccAFDIPLL
VccSSC 1.05 0.095
AP17 Near V1
VCCIO[27] V1 VccDIFFCLKN 1.05 0.055
FDI

20mA VCCSPI
1
AU20
+V1.05S_VCCP VCCDMI[2] C230 VccALVDS 3.3 0.001
1U_0402_6.3V6K
B PANTHER-POINT_FCBGA989 2 B
VccTX_LVDS 1.8 0.04
HM76@
Share ROM
+3VALW +3V_ROM +3VS
@
1 R413 2
0_0402_5%

@
Q21
AO3413_SOT23 @
+5VALW R419

D
3 1 1 2

.1U_0402_16V7K
C243
1 @ 0_0402_5%
@

G
2
R418
100K_0402_5%
2

2
@ Q22

1
R40 D
1 2 PCH_PWR_EN_R 2
<32> PCH_PWR_EN

.1U_0402_16V7K
0_0402_5% G
.1U_0402_16V7K
C237

C252
1 2N7002H_SOT23-3 S 1 @
3

@
@
A 2 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 20 of 60
5 4 3 2 1
5 4 3 2 1

Have internal VRM


+3VS +V1.05S_VCCP R268 @
0_0603_5%
2 1 +VCCACLK
+3VALW +3V_PCH
PJ1
Near T38 2 1
+3V_PCH
Near T16 U4J POWER +V1.05S_VCCP JUMP_43X118
1 1

10U_0603_6.3V6M
C231

1U_0402_6.3V6K
C232
1 AD49 N26
@ VCCACLK VCCIO[29]
2 2 1
C234 P26
.1U_0402_16V7K T16 VCCIO[30] C233
D 2 VCCDSW3_3 3mA P28 1U_0402_6.3V6K D
VCCIO[31] 2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
C235 @ T29
.1U_0402_16V7K T38 VCCIO[33] +3V_PCH
+3VS VCC3_3[5]
On-Die PLL Voltage Regulator
HOn-Die PLL voltage regulator enable T23
+VCCAPLL_CPY_PCH BH23 119mA VCCSUS3_3[7]
VCCAPLLDMI2 +3V_PCH

.1U_0402_16V7K
C236
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 T24 1
AL29 VCCSUS3_3[8]
,VCCAPLLSATA +V1.05S_VCCP VCCIO[14] V23
VCCSUS3_3[9]

USB
2 1
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] C238
1
P24 .1U_0402_16V7K
@ C239 VCCSUS3_3[6] 2 +V1.05S_VCCP
1U_0402_6.3V6K AA19
2 VCCASW[1] T26
+V1.05S_VCCP AA21 VCCIO[34]
Near AA19 VCCASW[2]
1010mA
AA24 M26 +PCH_V5REF_SUS
VCCASW[3] 1mA V5REF_SUS
1 1

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous


VCCASW[4] AN23 +VCCA_USBSUS
AA27 DCPSUS[4]
2 2 VCCASW[5] AN24
VCCSUS3_3[1] +3V_PCH
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
C VCCASW[8] 1mA V5REF C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27
VCCASW[9] N20
VCCSUS3_3[2] 1
+V1.05S_VCCP AC29

PCI/GPIO/LPC
2 2 2 VCCASW[10] N22 C247
AC31 VCCSUS3_3[3] 1U_0402_6.3V6K
VCCASW[11] P20 2 +3VS +5VALW +3V_PCH
AD29 VCCSUS3_3[4]
VCCASW[12] P22
VCCSUS3_3[5]

2
AD31 1
VCCASW[13] C249 R275 D1
W21 AA16 .1U_0402_16V7K 10_0402_5% CH751H-40PT_SOD323-2
VCCASW[14] VCC3_3[1]
L6 W23 W16 2 +3VS

1
1 2 +1.05VS_VCCA_A_DPL VCCASW[15] VCC3_3[8] +PCH_V5REF_SUS
10UH_LB2012T100MR_20% W24 T34 1
VCCASW[16] VCC3_3[4]
1 1
1U_0402_6.3V6K
C251

22U_0805_6.3V6M
C187

1U_0402_6.3V6K
C253

1 1 1 @ W26 C240
+ C250 VCCASW[17] C254 0.1U_0603_25V7K
220U_6.3V_M W29 +3VS .1U_0402_16V7K 2
VCCASW[18] 2
2 2 2 2 W31 AJ2
VCCASW[19] VCC3_3[2] +V1.05S_VCCP
1
W33
VCCASW[20] AF13
@ VCCIO[5] C255 +5VS +3VS
2 .1U_0402_16V7K 1
+VCCRTCEXT N16
+1.5VS DCPRTC AH13 C257
1 VCCIO[12]

2
C258 1U_0402_6.3V6K
.1U_0402_16V7K Y49 AH14 2 R279 D2
VCCVRM[4] VCCIO[13] CH751H-40PT_SOD323-2
10_0402_5%
2
B AF14 B
Near AF17

1
+1.05VS_VCCA_A_DPL BD47 VCCIO[6] +PCH_V5REF_RUN
+V1.05S_VCCP VCCADPLLA 80mA

SATA
AK1 +VCCSATAPLL 1
+1.05VS_VCCA_A_DPL BF47 VCCAPLLSATA
1 VCCADPLLB 80mA
+1.5VS On-Die PLL Voltage Regulator
C256 HOn-Die PLL voltage regulator enable C248
1U_0402_6.3V6K AF11 1U_0603_10V6K
AF17 VCCVRM[1] +V1.05S_VCCP 2
2 VCCIO[7] VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
AF33
Near AF33 AF34 VCCDIFFCLKN[1]
55mA AC16 ,VCCAPLLSATA
AG34 VCCDIFFCLKN[2] VCCIO[2]
+V1.05S_VCCP VCCDIFFCLKN[3]
1 AC17 1
VCCIO[3] C261
C259 AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +V1.05S_VCCP
DCPSST
Near AG33 C263
1
+V1.05S_VCCP
1 .1U_0402_16V7K +1.05VM_VCCSUS T17 T21
V19 DCPSUS[1] VCCASW[22]
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +V1.05S_VCCP V21


2 VCCASW[23]
CPU

Near BJ8 BJ8


V_PROC_IO 1mA T19
@ @ VCCASW[21]
1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

.1U_0402_16V7K
C266

A22 P32
10mA VCCSUSHDA
RTC

2 2 VCCRTC
HDA
1U_0402_6.3V6K
C268

.1U_0402_16V7K
C269

1 1 1
PANTHER-POINT_FCBGA989 C271
A .1U_0402_16V7K A

2 2 HM76@ 2

@
Security Classification Compal Secret Data Compal Electronics, Inc.
2011/06/15 2012/07/11 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 21 of 60
5 4 3 2 1
5 4 3 2 1

U4I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
D U4H B15 VSS[163] VSS[263] K7 D
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
AA34 VSS[4] VSS[83] AK8 B7 VSS[170] VSS[270] L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
C AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48 C
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
B AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3 B
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
HM76@ VSS[249]
H12
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A

PANTHER-POINT_FCBGA989

HM76@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9632P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 27, 2013 Sheet 22 of 60
5 4 3 2 1
5 4 3 2 1

LCD POWER CIRCUIT Camera


+3VS

W=60mils
+3VS +LCDVDD_CONN
W=60mils U72 (20 MIL)
1 +LCDVDD_CONN CMOS@ +3VS_CMOS
5 VOUT Q83

4.7U_0603_6.3V6K
VIN LP2301ALT1G_SOT23-3
D D

C516
2 1 (20 MIL)
GND

D
4 3 1
SS
1 1
1 3 CMOS@
EN 2 C518 C519 @

G
2
C4 APL3512ABI-TRG_SOT23-5 .1U_0402_16V7K R02 10U_0603_6.3V6M
1500P_0402_50V7K R435CMOS@ 2 2
2 150K_0402_5%
4.7V
<17> PCH_ENVDD <32> CMOS_ON#

1
C520 CMOS@
R408 .1U_0402_16V7K
100K_0402_5% 2

LCD Conn.

2
+LEDVDD B+
@
R813
1 2
C C
1
0_0805_5%
C541
4.7U_0805_25V6-K
2 @

JLVDS1
1
2 1 31
3 2 G1 32
4 3 G2 33
5 4 G3 34
R509 1 @ 2 0_0402_5% 6 5 G4
BKOFF# 7 6
8 7
<17> PCH_PWM 8
9
10 9
<17> LVDS_ACLK 10
11
<17> LVDS_ACLK# 11
12
BKOFF# 13 12
<32> BKOFF# <17> LVDS_A2 13
14
<17> LVDS_A2# 14
15
<17> LVDS_A1 15
1

16
<17> LVDS_A1# 16
R716 17
<17> LVDS_A0 18 17
B 10K_0402_5% <17> LVDS_A0# 18
B
<17> EDID_DATA 19
20 19
<17> EDID_CLK
2

21 20
+3VS 21
22
+LCDVDD_CONN 22
(60 MIL) 23
24 23
+3VS 24
25
26 25
+3VS_CMOS 26
USB20_P3_R 27
USB20_N3_R 28 27
CMOS
For EMI 29
30
28
29
30

<18> USB20_P3 USB20_P3 1 R688@ 2 0_0402_5% USB20_P3_R ACES_88341-3001 ME@


<18> USB20_N3 USB20_N3 1 R684@ 2 0_0402_5% USB20_N3_R

L58 @
USB20_P3 1 2 USB20_P3_R
1 2

USB20_N3 4 3 USB20_N3_R
4 3
WCM-2012-900T_4P
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 23 of 60
5 4 3 2 1
A B C D E

1 1

FCM1608CF-121T03 0603
1 2 RED
<17> DAC_RED
L30
FCM1608CF-121T03 0603
1 2 GREEN
<17> DAC_GRN
L31
FCM1608CF-121T03 0603
1 2 BLUE
<17> DAC_BLU

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
C522

C523

C524

C525

C526

C527
L32
1 1 1 1 1 1

RP22
8 1 DAC_BLU 2 2 2 2 2 2 +5V_Display
7 2 DAC_GRN
6 3 DAC_RED
5 4

150_0804_8P4R_1% JCRT1
6
PAD T66 NC11 11
For EMI RED

CRT_DDC_DAT_CONN
1
7
12
GREEN 2
8 16
2 G 2
JVGA_HS_R 13 17
BLUE 3 G
9
JVGA_VS_R 14
4
10
CRT_DDC_CLK_CONN 15
5

CONTE_80431-5K1-152
ME@
+5VS

1 1
@
C529 C531
U10
.1U_0402_16V7K .1U_0402_16V7K
2 2 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_Display

2 3 RED
+3VS VCC_VIDEO VIDEO1

1
7 4 GREEN
VCC_DDC VIDEO2 R31 R33
1 4.7K_0402_5% 4.7K_0402_5%
<17> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3

2
.1U_0402_16V7K
3 2 11 9 CRT_DDC_DAT_CONN 3
<17> CRT_DDC_CLK DDC_IN2 DDC_OUT1

13 12 CRT_DDC_CLK_CONN
<17> CRT_VSYNC SYNC_IN1 DDC_OUT2

15 14 JVGA_VS 1 R411 2 JVGA_VS_R


<17> CRT_HSYNC SYNC_IN2 SYNC_OUT1 22_0402_5%

6 16 JVGA_HS 1 R412 2 JVGA_HS_R


GND SYNC_OUT2 22_0402_5%
10P_0402_50V8J

10P_0402_50V8J
TPD7S019-15DBQR_SSOP16
@ 1 @ 1
C411

C412

2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 24 of 60
A B C D E
5 4 3 2 1

For EMI U73


+5V_Display

L35 HDMI@ +5VS 3


W=40mils
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN OUT
<17> HDMI_CLK+_CK 1 2 1
+3VS 1
IN C543
1
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 2
<17> HDMI_CLK-_CK 4 3 GND 2
C544 .1U_0402_16V7K

2
WCM-2012HS-900T
D R485 .1U_0402_16V7K 2 AP2330W-7_SC59-3 D
L36 HDMI@ 1M_0402_5% Q93
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN HDMI@ HDMI@
<17> HDMI_TX0+_CK 1 2

2
G
2N7002H_SOT23-3 ZZZ3 45@

1
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN TMDS_B_HPD# 3 1
For CRT and HDMI
<17> HDMI_TX0-_CK 4 3 <17> TMDS_B_HPD#

D
WCM-2012HS-900T

2
L37 HDMI@ HDMI Logo
<17> HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN R488
1 2 RO0000003HM
20K_0402_5%
HDMI@
<17> HDMI_TX1-_CK HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN JHDMI1

1
4 3 HDMI_DET 19
WCM-2012HS-900T 18 HP_DET
+5V_Display +5V
17
L38 HDMI@ HDMIDAT_R 16 DDC/CEC_GND
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN HDMICLK_R 15 SDA
<17> HDMI_TX2+_CK 1 2 SCL
14
13 Reserved
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN HDMI_CLK-_CONN 12 CEC 20
<17> HDMI_TX2-_CK 4 3 CK- G1
11 21
WCM-2012HS-900T HDMI_CLK+_CONN 10 CK_shield G2 22
C CK+ G3 C
HDMI_TX0-_CONN 9 23
8 D0- G4
HDMI_TX0+_CONN 7 D0_shield
+3VS HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
Pull up R for PCH OR VGA SIDE HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
SUYIN_100042GR019M23DZL
ME@
+3VS Q63A
HDMI@ DVT

2
+5V_Display RP21 2N7002DW-T/R7_SOT363-6
8 1 HDMIDAT_NB RP26
7 2 HDMIDAT_R <17> HDMICLK_NB 1 6 HDMICLK_R HDMI_TX1+_CONN 5 4
6 3 HDMICLK_NB HDMI_TX1-_CONN 6 3
5

5 4 HDMICLK_R HDMI_CLK+_CONN 7 2
HDMI_CLK-_CONN 8 1
2.2K_0804_8P4R_5% 4 3 HDMIDAT_R
<17> HDMIDAT_NB
HDMI@ 680 +-5% 8P4R
Q63B HDMI@
B HDMI@ B
2N7002DW-T/R7_SOT363-6 RP27
HDMI_TX0+_CONN 5 4
HDMI_TX0-_CONN 6 3
HDMI_TX2+_CONN 7 2
HDMI_TX2-_CONN 8 1
ESD
680 +-5% 8P4R
HDMI@
@ D32 @ D28 @ D33
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0+_CONN 9 10 1 1 HDMI_TX0+_CONN

HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0-_CONN 8 9 2 2 HDMI_TX0-_CONN


+3VS
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2+_CONN 7 7 4 4 HDMI_TX2+_CONN

1
D
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2-_CONN 6 6 5 5 HDMI_TX2-_CONN 2
G
3 3 3 3 3 3 S Q95

3
HDMI@
8 8 8 2N7002H_SOT23-3

YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9


A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 25 of 60
5 4 3 2 1
A B C D E

Mini Card for WLAN/WiMAX(Half)

1 1

+3VS 80mil +3VS_WLAN


J6
1 2
1 2 +1.5VS
JUMP_43X79
@ JWLN1
<16> PCIE_WAKE# R508 1 2 0_0402_5% PCIE_WAKE#_WLAN 1 2
3 1 2 4
5 3 4 6
<19> PCH_BT_ON# 5 6
<15> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<15> CLK_PCIE_WLAN1# 11 12
13 14
<15> CLK_PCIE_WLAN1 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 PCH_WL_OFF# <18>
21 22 PLT_RST# <18,27,32>
23 24 +3VS_WLAN
2 <15> PCIE_PRX_DTX_N2 25 23 24 26
2
<15> PCIE_PRX_DTX_P2 25 26
27 28
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 SMB_CLK_S3 <12,13,15>
31 32 1 R502 2 @ 0_0402_5%
<15> PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 <12,13,15>
33 34
<15> PCIE_PTX_C_DRX_P2 35 33 34 36
+3VS_WLAN 35 36 USB20_N10 <18>
37 38
39 37 38 40 USB20_P10 <18>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<32,33> EC_TX 1 2 51 49 50 52
<32,33> EC_RX 51 52
R506
DVT 100_0402_1% 53 54
1 R405 2 INTEL_BT_OFF#_R GND1 GND2
<19> INTEL_BT_OFF#
1K_0402_5%
BELLW_80003-8041

2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/NEW Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 26 of 60
A B C D E
5 4 3 2 1

For LAN & Green CLK +3VALW +3V_LAN


+LX
Close together
J10
LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P

1000P_0402_50V7K
1 2 1 2

10U_0603_6.3V6M
+1.1_AVDDL_L +1.1_AVDDL +LX_R

.1U_0402_16V7K
4.7UH_SIA4012-4R7M_20%
JUMP_43X79

CL1

CL2

.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
1 1

CL4

CL5

CL6
D
Note: Place Close to LAN chip 1 1 1 D
3 1

D
2 2 LL1 DCR< 0.15 ohm

CL3
@
@ Rate current > 1A
RL3 2 2 2
QL1

G
2
LAN_PWR_ON# 2 1 LP2301ALT1G_SOT23-3
<32> LAN_PWR_ON# 10U
2
@
10K_0402_5% CL7 SWR@SWR@SWR@
1
.1U_0402_16V7K Place close to Pin34
Close to
Pin40

Vendor recommand reseve the


PU resistor close LAN chip

RL4 1 2 4.7K_0402_5% UL1 8172@ +3V_LAN


+3V_LAN
@
PLT_RST#
<18,26,32> PLT_RST#

.1U_0402_16V7K

1U_0402_6.3V6K
QCA8172-BL3A-R
SA000065410

CL10

CL8
S IC QCA8172-BL3A-R QFN 40P E-LAN CTRL 1 1

UL1
C
Place Close to Chip 2 2
C

CL9 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 RL12 10K_0402_5%


<15> PCIE_PRX_DTX_N1 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 23
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<15> PCIE_PTX_C_DRX_N1 RX_N 12 MDI0- @
35 TRXN0 11 MDI0- <28>
MDI0+
<15> PCIE_PTX_C_DRX_P1 RX_P TRXP0 MDI0+ <28>
15 MDI1-
TRXN1 MDI1- <28>
32 14 MDI1+
<15> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <28>
<15> CLK_PCIE_LAN REFCLK_P TRXN2 17
PLT_RST# 2 TRXP2 21
PERST# TRXN3 20
PCIE_WAKE#_R 3 TRXP3 Place Close to PIN1
RL7 1 @ 2 0_0402_5% W AKE#
<32> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33

CL12

CL13

CL14

CL15

CL16
27

1000P_0402_50V7K

10U_0603_6.3V6M

10U_0603_6.3V6M
Vendor recommand reseve the

.1U_0402_16V7K

1U_0402_6.3V6K
TESTMODE 1 1 1 1

2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7
don't @ (could be B C cost done)

1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 @ 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
4
<15> CLKREQ_LAN# CLKREQ# 24 @ @
B DVDDL/PPS 37 +LX_R B
+1.1_AVDDL 13 DVDDL_REG/DVDDL
AVDDL +2.7_AVDDH @
+1.1_AVDDL 19
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K
CL17

CL18

CL19

CL20

CL21
.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

1 1 1 1 1

CL22

CL23

CL24

CL25

CL26
41 1 1 1 1 1
GND
AR8162-BL3A-R_QFN40_5X5
2 2 2 Near 2 2 8162@
SA000052J20 2 2 2 2 2
Pin6 S IC AR8162-BL3A-R QFN 40P E-LAN CTRL
@ @

Near
Near Near Near Near @
Near
Pin9
Pin13 Pin19 Pin31 Pin22 Pin37

LAN_XTALI

A YL1 LAN_XTALO A
4 3
NC OSC
1 2
OSC NC
1 25MHZ_10PF_7V25000014 1
CL28 CL29
15P_0402_50V8J 15P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8162/8172
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Lenovo 5 Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 27 of 60
5 4 3 2 1
5 4 3 2 1

ESD

@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
D D

DL1 2 5

1'S PN:SC300001G00
GND VDD
For EMI
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-

RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V

2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<27> MDI0+ 2 TD+ TX+ 15
MDI0- MDO0- GAS@
<27> MDI0- TD- TX-
3 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
1 6 11 MCT
C CT CT C
MDI1+ 7 10 MDO1+
For EMI CL31
0.01U_0402_16V7K
<27> MDI1+
<27> MDI1-
MDI1- 8 RD+
RD-
RX+
RX-
9 MDO1-
2
MHPC_NS681612A For EMI
CL63 1 2 0.1U_0603_50V7K

CL61 1 2 0.1U_0603_50V7K

CL64 1 2 0.1U_0603_50V7K

CL65 1 2 0.1U_0603_50V7K

JLAN1 ESD
MDO0+ 1
PR1+ CHASSIS1_GND
B MDO0- 2 B
PR1-
MDO1+ 3
PR2+
MCT 4
PR3+
MCT 5
PR3-
MDO1- 6
PR2-
MCT 7 9
PR4+ GND 10
MCT 8 GND
PR4-
SANTA_130456-121

ME@ CHASSIS1_GND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_Transformer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9632P
Date: Wednesday, February 27, 2013 Sheet 28 of 60
5 4 3 2 1
5 4 3 2 1

2 Channel

D D

+3VS
SMSC thermal sensor
C329
2 placed near PCH
.1U_0402_16V7K
@
1
U9 Lenovo 1
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <15,32>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <15,32>
C587
2200P_0402_50V7K REMOTE1- 3 6
2 D- ALERT#
C +3VS
1 R335 2 4 5 C
@ THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P

Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

B B

CPU HDD
@ @ @ @
H1 H2 H3 H18 @ @ @ @
HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4
1

1
FAN1 Conn
H_3P8 H_3P8 H_3P8 H_2P8

+5VS C
R581
@
JFAN1
A
2 1 1 R
2 1 @ @ @ @ @ @
<32> EC_TACH 2
0_0603_5%<32> EC_FAN_PWM 3 H6 H7 H8 H10 H11 @ H17
4 3 HOLEA HOLEA HOLEA HOLEA HOLEA H16 HOLEA
5 4 HOLEA
2 G5
6
C591 G6
1

1
10U_0603_6.3V6M ACES_85205-04001

1