Vous êtes sur la page 1sur 4

IJSRD - International Journal for Scientific Research & Development| Vol.

4, Issue 04, 2016 | ISSN (online): 2321-0613

Packet Switched Wormhole Router Design and Low Latency Adapter


Design for NOC Architecture and Its FPGA Implementation
Madusudhan Patil M1 Suma V Shetty2
1
M.Tech. Student 2Assistant Professor
1,2
Department of Electronic & Communication Engineering
1,2
Sapthagiri College of Engineering Bengaluru, India
Abstract As growth in an integrated technology the
number of processing elements used in single chip increases,
which causes the interconnection of elements in a chip is
complex using conventional bus based system. A network
on chip (NoC) is new paradigm for communication between
components in a system on chip. Other aspect is the speed of
communication between nodes gets reduced, for this reason
various routing algorithms and switching techniques are
introduced, amongst selection is a main criteria. In this
project wormhole switching with XY routing algorithm is
used. The speed of the communication between components
is increased though adapter design. In this project wishbone
architecture is used to communicate between nodes. The
Mesh topology is used to reduce the network congestion
problems in NoC. IP cores and adapter are designed using Fig. 1: NoC component overview
Wishbone Protocol to communicate with NoC nodes. The The massive design space of NoCs means that even
design will be implemented using Artix-7 FPGA board. a simple design of a NoC component is a valuable research
ISim tool is used to simulate and test the system. contribution since it expands on existing understandings and
Key words: System on Chip (SoC), Network On chip (NoC), provides reinforcement to existing theories. More precisely,
Wishbone Protocol, Field programmable gate array (FPGA), the optimal selection of the channel width in packet-
Packet Switched Wormhole Roting (PWR) switched routers remains an open research problem [3].

I. INTRODUCTION II. LITERATURE SURVEY


As Moores Law continues to hold true for the near future, Matthew Murawski et al.[1] design and evaluation of two
the design of embedded systems becomes challenging and major NoC components: a flexible adapter compatible with
complex due to large number of hardware modules and the the Altera Avalon interconnect standard and a
difficulty of interconnecting them. Designers have shifted parameterizable wormhole router is discussed, The Avalon
their focus from micro-level to macro-level system design compatible adapter will be very useful to NoC designers
through the employment of hardware reuse. This shift in using IP cores provided by Altera to implement NoC-based
focus has opened the way for adoption of System-on-Chip systems on Altera FPGAs.
(SoC) paradigm (called FPSoC when implemented in Mohandeep Sharma et al. [2] A survey of the
FPGAs). This involves interconnecting pre-made hardware Wishbone bus and its comparison with three other buses
modules together to form a coherent system. These AMBA from the ARM, CoreConnect from the IBM and
hardware modules are known as Intellectual Property (IP) Avalon by the Altera Corporation reveals that in terms of
cores[1]. compared performance parameters, the Wishbone bus tends
The NoC medium features a high level of to gain an upper edge over the other three types because it
modularity, flexibility, and throughput. The NoC relies on provides for connecting circuit functions together in a way
data packet exchange. The path for a data packet between a that is simple, flexible and portable due to its synchronous
source and a destination through the routers is defined by design.
the routing algorithm. Therefore, the path that a data packet Swati R. Mishra et al. [5] The Wishbone
is allowed to take in the network depends mainly on the interconnect is proposed as a general purpose interface. As
adaptiveness permitted by the routing algorithm, which is such, it defines the standard data exchange between IP core
applied locally in each router being crossed and to each data modules. The Wishbone architects were strongly influenced
packet [2]. by three factors.
A NoC consists of four major components shown First, there was a need for a good, reliable System-
in Fig.1. IP cores, the network adapters, routing nodes and on-Chip integration solution. Second, there was a need for a
links. These are similar to the components in a macro common interface specification to facilitate structured
computer network. There are many different architectures, design methodologies on large project teams. Third, they
mechanisms, parameters and techniques involved in NoCs were impressed by the traditional system integration
[8]. solutions afforded by microcomputer buses such as PCI bus
and VME bus. A SoC which utilizes ALU master cores and
memory slave cores using Wishbone bus interconnection
scheme has been designed for this purpose.

All rights reserved by www.ijsrd.com 352


Packet Switched Wormhole Router Design and Low Latency Adapter Design for NOC Architecture and Its FPGA Implementation
(IJSRD/Vol. 4/Issue 04/2016/089)

Shubhangi D. Chawade et al. [6] XY routing XY routing is that it never turns into deadlock or livelock.
algorithm which employs a simple XY routing algorithm The flow chart for PWR is shown in fig.4.
combined with a scheduler to be used on NoCs. The results
show that the proposed method is a fast and an efficient way
to transferring data via a specific path between two nodes in
the network and the scheduler further helps to avoid
collision.

III. METHODOLOGY

Fig. 2: Block diagram of proposed method


The adapter is specifically designed to work with
the proposed Wormhole Router (PWR). It is responsible for
sending packets from NoC nodes (IP cores) to routers. It Fig. 4: Flow chart of PWR design
also receives packets from the routers and forwards it to The NoC architecture is based on a network of
NoC nodes. The nodes send and receive packets using the switches also called nodes. Each switch is connected to
Wishbone generic architecture. It makes the IP cores another by mean of some physical links like wires. The
compatible with the NoC. connections between switches can be of different topologies.
The most commonly used topology is the Mesh topology, in
A. Router Design
which the nodes are arranged in the form of a mesh like in
The PWR is a packet-switched wormhole router with network of computers. In Mesh topology every switch is
deterministic routing scheme XY routing. The switching connected to every other switch using links. The
mechanism uses verilog FOR loops to implement a full communication is done by routing packets over the network
crossbar switch. 4x4 mesh topology is used to interconnect instead of driving dedicated wires.
all the nodes which are designed using wormhole routing.
B. Adapter Design
There are two types of adapters Master and Slave. As
illustrated in Fig.5, the Master adapter is responsible for
receiving requests from a master component and applying
the response signals. The Slave adapter is responsible for
applying the master requests and receiving the slave
responses. The adapter is designed to be compatible with a
wide range of signal widths.
The Wishbone Master Interface consists of a
Wishbone Slave that can connect to an external Wishbone
Master. When an external Wishbone Master starts a
Wishbone cycle, the Master Interface will select the
appropriate Slave Interface, based on Wishbone Address
Fig. 3: 4x4 mesh topology bits [MSB:MSB-3]. Each Master interface consists of a
Interconnection of NoC components using mesh Wishbone Slave interface and decoding logic. The Master
topology is shown in fig.3.In wormhole routing packet is Interface performs simple interface signal steering based on
switched between two nodes in each transmission. The the upper four Wishbone Address Bits. A 0 on the upper
destination address is included in the packets four Wishbones address bits selects Slave 0, a 15 selects
XY routing algorithm is one kind of distributed Slave 15.
deterministic routing algorithms. XY routing is one of the
type of Dimension order routing (DOR) which is a typically
a minimal turn algorithm and is more suitable for networks
using mesh or torus topology. XY routing algorithm routes
packets first in X-direction (or horizontal direction) to the
correct column and then in Y- direction (or vertical
direction) to the receiver. In XY routing the addresses of the Fig. 5: Adapter overview
routers are their XY-coordinates. One of the advantages of

All rights reserved by www.ijsrd.com 353


Packet Switched Wormhole Router Design and Low Latency Adapter Design for NOC Architecture and Its FPGA Implementation
(IJSRD/Vol. 4/Issue 04/2016/089)

The Wishbone Slave Interface consists of a


Wishbone Master that can connect to an external Wishbone
Slave. When an internal Master Interface starts a Wishbone
cycle, the Slave Interface will select the appropriate Master
Interface, based on internal arbitration. Each Slave interface
consists of a Wishbone Master interface and a prioritizing
Arbiter. The Slave Interface performs interface signal
steering based on the output of the prioritizing arbiter. An
implementation that required less than the provided 16 Slave
interfaces should leave the outputs of the unused interfaces
unconnected, and connect the inputs of the unused interfaces Fig. 7: Node/router simulation result
to ground. The unused interfaces will then be automatically
removed during the synthesis process. Note that Slave
Interface 15 is also used for accessing the register file and
therefore cannot be completely removed.

Fig. 8: Wishbone master simulation output

Fig. 9: Wishbone slave simulation output

Fig. 10: Packet switched wormhole routing simulation result

Fig. 6: Wishbone design flow


In router, Arbiter is used in network on chip when
number of input are requested for same output port, the
arbiter has generate the grant signal on the basis of that
number of input port getting a priority and the input port
Fig. 11: Packet routing in 4x4 mesh topology
transmit a packet to output port. The prioritizing arbiter
selects the Master that will own the Slave, based first on
priority, and secondarily, if all priorities are equal, in a
round robin way. Each master interface has a 21 bit priority
value associated with it. A value of 0 identifies a master
with very low priority; a value of 3 identifies a master with
very high priority. Masters with the same priority are
processed in a round robin way, as long as there are no
Masters with a higher priority.
Fig. 12: Packet routing using adapter design
IV. RESULTS
Initially the wishbone signal disabled and output observed.
The packets are routed according to destination address
given in packet input. The destination addresses will MSB 4
bits of packet input. When Wishbone signal is enabled
packet is routed to adjacent nodes. Fig 4 shows the node
simulation output. The packet input is routed according to
XY direction given inn MSB bits of packets. Wishbone
master responds to slave signals and decodes the packets
and send to the slave response.

Fig. 13: FPGA implementation result viewed on Chipscope

All rights reserved by www.ijsrd.com 354


Packet Switched Wormhole Router Design and Low Latency Adapter Design for NOC Architecture and Its FPGA Implementation
(IJSRD/Vol. 4/Issue 04/2016/089)

V. CONCLUSION [10] K. Goossens, J. Dielissen,and A. Radulescu, A Ethereal


The main goal of this work is to design an efficient adapter network on chip: concepts, architectures, and
which is compatible with Wishbone protocol and proposed implementations, Design & Test of Computers, IEEE,
packet switched Wormhole router. First router is designed Vol 22, Issue 5, 2005, pp 414 421
then using mesh topology single NoC system is designed [11] G. Kumaran and S. Gokila, M.E, Dynamic Router
then wishbone protocol is designed to communicate between Design For Reliable Communication In Noc,
IP cores and NoC. International Journal of Innovative Research in
This framework is really useful in all Complex Computer and Communication Engineering Vol 2,
SOC Designs, in high speed networking systems to improve Issue 1, March 2014.
the latency by using wishbone. This is a Flexible
architecture either with only routing or with interfacing with
wishbone and router. Instead of using standard Protocols for
interface, we can use adapter for communication with
master and slave.

REFERENCES
[1] Matthew Murawski, R.M Jenita Priya and Mohammed
Khalid, Design and evaluation of avalon compatible
adapter and parameterizable NoC router for FPGAs
hammed Khalid, Proceedings of the IEEE 28 th Canadian
conference on Electrical and Computer Engineering
Halifax, Canada, May 3-6, 2015
[2] Mohandeep Sharma and Dilip Kumar, Wishbone bus
architecture a survey and comparison, International
Journal of VLSI design & Communication Systems
(VLSICS), Vol 3, No 2, April 2012
[3] W. C. Tsai, Y. C. Lan, Y. H. Hu, and S. J. Chen,
Networks on Chips: Structure and Design
Methodologies, Journal of Electrical and Computer
Engineering, special issue on Networks on Chips:
Architectures, Design Methodologies, and Case Studies,
2012
[4] T. Bjerregaard, and S. Mahadevan, A survey of research
and practices of Network-on-Chip, ACM Computing
Surveys (CSUR), Vol. 38, Issue 1, 2006
[5] Swati R. Mishra1, Pramod Patil and Sudhir Shelke,
Design and implementation of Wishbone bus interface
architecture for SOC integration using VHDL on
FPGA, International Journal on Recent and Innovation
Trends in Computing and Communication Vol 2, Issue
7, July 2014
[6] Shubhangi D. Chawade, Mahendra A. Gaikwad and
Rajendra M. Patrikar, Modified XY routing algorithm
with scheduler for NoC, International Journal of
Electronics Communication and Computer Engineering
Vol 3, Issue 5, 2012
[7] Ahmed H.M. Soliman, E.M. Saad, M. El-Bably and
Hesham M. A. M. Keshk, Designing a WISHBONE
protocol network adapter for an asynchronous network-
on-chip, IJCSI International Journal of Computer
Science Issues, Vol 8, Issue 4, No 2, July 2011
[8] R. Marculescu, U. Y. Peh, N. E. Jerger, and Y. Hoskote,
Outstanding Research Problems in NoC Design:
System, Microarchitecture, and Circuit Perspectives,
IEEE Trans. on CAD of ICs and Systems, vol 28, no 1,
Jan 2009
[9] F. Moraes, N. Calazans, A. Mello, L. Moller, and L.
Ost, HERMES:an infrastructure for low area overhead
packet-switching networks onchip, Amsterdam, The
Netherlands : Elsevier Science Publishers B. V, Vol 38,
2004

All rights reserved by www.ijsrd.com 355