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READ BEFORE PROCEED!
PRINTS MARKED WITH COPER ARE NC,EMPTY!

PRINTS MARKED WITH GOLD ARE CONNECTED ONLY


TO TEST POINTS NO OTHER CIRCUIT!
IF YOU REBALL U3100 LOOK CAREFUL IF B9 AND B10
THAT LOOK LIKE A JUMPER IS REMOVED TOUCH WILL
NOT WORK IF SO HAPPEN MAKE A JUMPER ON THE IC!
NOSTUFF COMPONENTS JUST LOOK ON BOARD
THEY ARE NOT MOUNTED(MISSING)!

D D

WLAN/BT PCB

BCM43291HKUBG

T4149
127271 3TC
TE1111 P10

1114
7871
LA

BROADCOM
G8

21
4
J3700
4 3 2 1

C5783
C6000
L6001

C5721

C5722

R5790
R2050
R8100
C1032 L5757

C2014
C2002

C2003
C1023 C8101

C3752
C3750

C3751

C3753
U2001
R8216

C2004
R2051 TP170
TP37 TP39 TP41 TP43 TP46 C6001
L6000

C1125
TP86 TP90
TP171 TP172

C8122
TP45 TP47

C8121
TP36

C1130
FL2001

C8100

C1034
1 2

C1024
TP40 TP85

C1129
TP38 TP42 TP44 DZ5760
H G F E D C B A

C2010
C1131 C1132
3 4
C1127

C
R0765
1 1

C1046
C
5 6

C1126
C2011 R2006

C1128
R1207

R1208

R1209

R9000

R0737

R0738

R0739

C8165
R0735

R0770

J6000
C5750

R0736

C2000
2 2 7 8 2 1

R0771
R8218

C8107

C8108
Q8123
50 C2017

C8117
TP21 TP22 TP23 C1136
C2013 9 10 4 3
TP1 TP25
3 3

R2001
R1055
49 TP24

U2000

C1101
TP26 C1042

L8119 L8100
11 12

L8105

L8121 L8101
C1141 C1135 C1140 C1133 C1040 6 5

C1029
C1036 C1037 DZ5711

C1035
48
4 4

C1150

R1201

R1200

R1202

C1151

C1012

C1030
C1020
R1056
13 14

C1027
C8352

C2016
FL2002

Q8104

C1152

C1013
8 7

R0878
R1203
47
C1137 C1138 C1134 C1139 C1038
5 5 DZ5710
C1056 C1026
46 R2010
R2002 15 16 10 9
TP173

J5900
J7500
TP19
45 AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A C1010 17 18
6 6

R2008
C8353 DZ5712 12 11
44 1 1 R2052
19 20 14 13

L8110

L8107
43
TP35 2 2 C1001 7 7 21 22
R5740
TP174
42 TP88 16 15
3 3 C1100 8 8 C8118 DZ8120

R2003
C1111

C1119

C1120

C1104
41 TP87 23 24

C1022
C8351 18 17
C7522

4 4
R7541
LED9000

TP18 TP30
40 TP29
H G F E D C B A 25 26

J5600
20 19

R8130
C0930
TP31 5 5 TP89
39
U5700

C1105
27 28

C1021
C1 B1 A1
TP17 22 21
38
C1121

C1112

C1118

C1116

FL2000
6 6

C8102
C2001 C2015 C2012 Q8350
C2 B2 A2 29 30 TP96 24 23
L8115
37 R5613
7
L5601

7
C7523

FL7500

TP34

R8116
36 26 25 TP175

C1000
TP2 35 R5612 8 8 C3 B3 A3
DZ5752

C1113
C1110

C1115
TP16

C0908

C0903
9 9 C1102 28 27

C1107
34
C8119 C5753

C8103
TP32 30 29
C7524

C7525

C5752
33 R5611 TP33 R9002 10 10
L5600

32 C5760 32 31

C1106
J6100

Q8351
11 11

C1108

C1109

C1117

C1114
C0902
R5610
C1103

C8138

C8139

C8141
31

C8140
33

C0661
34
C8124

C8157
TP15 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 12 12 R5753

DZ5753
30
C8120

R8350
35

R8202
36

C8164
L8112

C8131
29 TP28 13 13
C8158

C8137
TP14 FL0610 C1039 C5755 38 37
14 14

U0652
28 R0620

TP3
C5617
C5621
L5611
C5620
C5600

R5600

C5612
R3621

R3622

39
L5613

R3608
40
L5612
C5614

C5623

C5616

L5610
C5601

TP27
C563

27
C5613 A B C D E F G H J
R0703

C5615 C5618 R0700 C3031 C3030


R0702

15 15 R5721

C0651
R0931

R3031

C0907

C0654
R8351
R0930

R2205 R2211
R0705

R0704

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C5602

R8353
R0621

C3714
C0648
26

C3704
41

R3703
9 9 R3032 DZ5751 42

C3041
A3 B3 C3

R3030
R9001
A A A3 B3 C3

R3713

DZ5750
R3620
25 TP13 16 16 R8354
R0701
D5701 D5703 D5700 D5702
R8352
U3700 R5720

C0607
U3710

Y0602
R0624 TP79 44 43
8 8

L8128
C1414

C0655
A2 B2 C2

C3713
B B A2 B2 C2

C3703
24 17 17 R3120

C0608
C0660
C0920 C5782

R3700
U3007
23 18 C5754

U3009
C1404 18
7 7
A1 B1 C1 A1 B1 C1
TP77 C C

C8159
C1402
R3180
TP176

C3107
C8210
22

R0655

C0640
R1001
19 19 Q2201 TP94 C5751

C0613
C1018
R1401

U3101
21 TP12 D D
R3173 6 6 L5716 L5720 TP168

C3712

C3701
C3711

C3702
TP4 20 20 L5701 L5700

C0644
20 R1400 TP76 DZ5790 TP169

U8100
C3608
C3615

R0623 E E
C3603

5 5
C3851

C3850
C3614

C3613

TP78
OA8 OE8 OF8
21 21 R5750

OB8 OC8 OD8


19 FL5711
MT1

R3171
L5714
C3616

R0801
18 C1007 R0622 R0642 F F
4 4

C0646
22 22 R3033

R2204

R3025
R3712 R3711 R3701 R3702
TP95 R3161 R5751
C3609

R1260 TP177
17 TP11 FL5707
TP5
R0803
23 23 C0652 C1009 C3112

U3010
R0625 G G R2210
R1005
C8161 C2241
3 3
R3851

R3850

16

L5760
R3160

A B C D E F G H J K L M N

L5763

L5761
R0810 FL5708 TP167
24 24

L5762
15 C1004 C1142 H H
2 2
C3607

C2204

C1002

R1006
R2250 TP163

C3103
C2240 R2203

C3050
OA8 OB8 OC8 OD8 OE8 OF8
C3604 C3110 TP166
C3104

1
C1412
14 25 25 C1181
R0800
C8135

C3105
TP178

DZ0600
J J
1 1 R3101

C1054

R1054

R1053

2
13
C3618 11 10 9 8 7 6 5 4 3 2 1 C3611
7 7 26 26

C2202
TP164
A B C D E F G H J

3
C8206
C3606

12 C1145 TP65
C1411

G G K K

C8125
27 27 A B C D E F G H J K

4
11
C0640 C8209
A B C D E F G H J K L M N
R3190

C0641

C2230

C2203
C0642
C8207
F F
D8100 Q2200

5
C4217

R0651
R3181 TP165
C1403

C1144 L L

U3600
10 28 28

C8160
C3617 10 10

C3101
R3107
6 6

C3108

C3106
C3109
TP64

6
C1413
C8217 TP160 TP179
9 E E
C3191
C0630 C8169
29 29
C3111
C1400

C0627
M M TP161
R4213
R4212

7
R3155
C3102
D D C0909

7 7
8 TP10

XW8114
C8223
L4303

8
C4310 C3605
30 30 L2201 9 9

U1410
C8149 C8167
C4213

7 TP68 N N
C C

9
C0643 C8215 TP162

5 5
R0866
C3602 C1005 31 31 R1253 C1705

10 12 14 16 18 20 22 24 26 28 30 32 34 36
R4312
6
B B C4211 R0825
TP66 C8204 P P TP157 TP180

J3010
TP63 C8221

11 13 15 17 19 21 23 25 27 29 31
5 32 32 8 8
6 6
C3852 C3853 C3600 C1017
R1252 C1251 C1704 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A A R0833
C8147
R4202

R8219
R4203 C8142

C8220
R8222
C3601 11 10 9 8 7 6 5 4 3 2 1 33 33 TP158

4 4

C8152

C8238
L4304

C8201

C8143
C8168 C8145

C8212
3

U1400
TP159
C1015 C1016 TP70 C8144
TP69
C8155
L4306

R0864
34 34
2
TP9 C4200 AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A TP67 C8236 7 7
R3602

R3601

R3603

5 5
TP93 TP181

R8231
R8227

R8232

R8235

R8239

R8240

R2200
TP97

R2201

C2200

C2231

C2232

C2206
L4301

C8166
R0832 TP92 TP154
1 A1 A2 A3 A4
C4201 L2202 L2232 L2222 L2212
Y8138

U3100
C1031
C8130 C8153 C8162 TP91
3 3

L8229
C3854
C0925

R0900

R0955

R0950
R0956
R0957

C0955
C1148

R0940

C1006
R1205

R8203
U4200
C1052

C8214
C0924
6 6
B1 B2 B3 B4 C1160

C1043
R0831 C1041

R1000
C1019
TP6
C8156 TP155

C1706

C1707

R1250

R1251
TP156

C8154
L5510

4 4
C1 C2 C3 C4
C5511

C5512

C4216

C4212

R4201

R1052 C8163

C8237
R0802
TP71 TP72
31 32

C1143
C5510 L4302 C1147 C1045

C8136

C8151
C1161 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
R3604

R3605

TP182

C0927
R0720

R5752
C0926
D1 D2 D3 D4
5 5

C8146
2 2

R1204

R1206
R0862

C1149

R1051
R0920

C0951
C0954

FL0910
C0952
C1180
C1044

R1723

R1720
C1011

C1703

C1250
C1702
C1301
TP7 R0863

3 3
R0860 C0950
C1146
C8150 C8148

C1014
C1182 4 3 2 1 C1300
4 4 TP150

1 1

U1300
R0813 R0834

C1008 F

C1410
TP8 TP60 F TP73 TP183
R0811 TP48
TP57
TP62 R1315 D8230 TP145

J2201
E E TP82
C1401

2 2
TP151
3 3

L8225
C5520

TP152
C5500
C8234 C8235
TP146
C5522

A B C D E F G H J K L M N C8226
C5521 R0812
D C1370
D
U5500
R5513

R5512

TP51
U5501
R5511

R5510

R5730
C0956

R0645
L5501 L5500 TP59
L5520 R0865 TP53 TP56 TP61 R1372
C C R1370
TP81
TP184
2 2
1 1
C5501 TP144
C2233

R0662
R1210
B B R1320 R1371 TP74 TP147

C8233
R0867

TP20
OA0 OB0 OC0 OD0 OE0 OF0 TP49
TP50 R5731
A A TP80
L5540

R5795
4 3 2 1

R0646
1 1
R0827

A B C D E F G H J K L M N

R1362
TP148
TP54 TP58 R5796
C2220 TP149
TP185

XW0605
DZ5720
TP83 TP84 TP143
A B C D E F G H J K

R1731
TP75

R1361
R1360
U1701
R5710

33 35 37
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 R0932
R0828
TP52 TP55

C8232
C5730
C5780

L2200
C5542

C0618
U5730

R1212
OA0 OB0 OC0 OD0 OE0 OF0

R0688

R0632
R0689

R0617
R0861

D8228

R1750

R1751
R0910
J5501

C1750
A B C D E F G H J K L
R0933
TP141

C0923
R6100 C6100

R1213
R0647

R1214
TP186
R0836

TP140
11 11
R5501

XW0604 R1211
R6101 TP142
C5541

10 10
R3800

C3801
C3803

9 9
C5530

C3800 C3802
C5540

C3053 C3007
8 8

U3003
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 7 7 TP135

B B
6 6 TP136
TP137

1
5 5 TP138

2
TP139
4 4 TP131

3
TP132

4
3 3 TP133

5
TP134

6
2 2 TP126

7
1 1 TP127

8
TP128
A B C D E F G H J K L

9
TP129

10 12 14 16 18 20 22 24 26 28 30 32 34 36
TP130

J3011
11 13 15 17 19 21
TP122
TP123

R3066
C3009 C3000 TP124
TP125

TP117

C3001
TP118
TP119

C3005 TP99 TP120


TP121
TP113
TP98
TP114
C3008 TP115
TP116

R3009
D3000

23 25 27 29 31 33 35 37
TP108
R3012 TP109
TP110
C3002 C3006 TP111
TP112
TP104
TP105
TP106
TP107

4R7
U3000 L3000
TP100
TP101
TP102
TP103

A A

820-2875-05 MLB TOP PCB


8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

TP187

TP191

TP188
TP190
TP388
TP379

J7500
TP349 TP381
TP192
TP189
TP380

TP282 TP367 TP387


TP303 TP321 TP368
TP341
TP264 TP265 TP389

C
TP390 TP391

C
TP193
TP386

4 3 2 1
TP281 TP283
TP320 TP392 TP393 TP394
TP302 TP382
TP263 TP266 TP304
TP348
TP594
TP337 TP385
TP194 TP595
TP267 TP395 TP397
TP284 TP301 TP319 TP342 TP347 TP371 TP372 TP383
TP280 TP285 TP322
TP362 TP396
TP369 TP593
TP336 TP370
TP261 TP262 TP384
TP195 TP596
TP343 TP346 TP363
TP318 TP338 TP373
TP452 TP7502 TP7500
TP220 TP221 TP454
TP597
TP197
TP259 TP260 TP300
TP196 TP453
TP198 TP219 TP398
TP305 TP616
TP335 TP339 TP508
TP399 TP467 TP571
TP344 TP345
TP618
TP199 TP218
TP451
TP200 TP566 TP567 TP617
TP575
TP201
TP545 TP576
TP340 TP455
TP226 TP227 TP400
TP401 TP466 TP572
TP258 TP268
TP202
TP350
TP568 TP620
TP228 TP361 TP574
TP468
TP465 TP621
TP7501 TP544 TP565
TP206 TP577
TP211 TP402 TP403
TP225 TP598
TP203 TP205 TP286
TP204 TP208 TP257 TP619
TP213 TP256 TP299 TP450 TP456 TP509 TP623
TP569 TP573 TP578
TP532 TP622
TP269 TP374 TP546 TP599
TP222 TP229 TP270
TP224 TP360 TP8101 TP7503
TP507
TP207
TP287
TP212 TP405 TP531
TP214 TP449
TP230 TP404 TP457 TP570 TP624
TP271 TP600
TP223 TP279 TP406
TP254
TP255 TP8133
TP288
TP209 TP210
TP217 TP272 TP306
TP627
TP464 TP490
TP231 TP253 TP289 TP307
TP216 TP625 TP629
TP407 TP543
TP351
TP215 TP298 TP580
TP448 TP631
TP290 TP323 TP579
TP252 TP308 TP359 TP628
TP251 TP408 TP510 TP547
TP250 TP273 TP275
TP352 TP469 TP474 TP630 TP632
TP480 TP491
TP278 TP542
TP291
TP626
TP309 TP334 TP409
TP274 TP433
TP317 TP366 TP463 TP479 TP485 TP489 TP633
TP473
TP277 TP292 TP297 TP410
TP249
TP333 TP511 TP515 TP522 TP530 TP541 TP581 TP601
TP353
TP493
TP462 TP470 TP481 TP602
TP358 TP365 TP475 TP492 TP564
TP316 TP634
TP276 TP375 TP514 TP521 TP525 TP533 TP540
TP247 TP248
TP354 TP582
TP355
TP332 TP427
TP327 TP432 TP592
TP314
TP310 TP426 TP512 TP516 TP523 TP529 TP539 TP548
TP324 TP357
TP437
TP471 TP603 TP604
TP447 TP476 TP482 TP486 TP494 TP497
TP313 TP356
TP315 TP331 TP419 TP461 TP583
TP296 TP549
TP246 TP428 TP434 TP438
TP472 TP478 TP591
TP311
TP326 TP328 TP484 TP488 TP496 TP585
TP376 TP563
TP293 TP424 TP431 TP605
TP245 TP517

COMPEQ
TP416 TP420 TP513 TP524 TP528 TP536 TP538 TP550
TP244 TP312 TP325 TP413 TP606
TP295 TP425
TP429 TP487 TP495 TP498
TP460 TP477 TP483 TP590
TP377 TP378
TP329 TP446 TP520 TP526 TP534 TP537 TP551
TP607
TP294 TP418 TP421 TP443
TP414 TP439
TP241
TP435 TP506 TP562 TP584 TP586 TP613
TP415 TP430 TP459 TP518 TP527 TP553
TP422 TP535 TP608
TP242 TP552
TP243 TP411 TP412
TP417 TP499 TP589
TP330 TP364 TP502 TP612
TP561 TP636 TP638
TP239 TP458 TP609
TP560 TP587
TP445 TP614
TP554
TP240 TP444
TP423 TP436
TP440
TP442 TP519 TP610 TP635
TP588 TP611 TP637 TP639
TP238 TP441
TP555 TP615
TP500 TP557

TP504 TP559
TP503 TP556
TP558
TP237 TP505
TP501

HF/e1
TP236

B
TP235

B
820-XXXX-X
TP232

TP233

TP234

A A

820-2875-05 MLB BOTTOM PCB


8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

K94 CHOPIN MLB


CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
A 0001052699 PRODUCTION RELEASED 2011-01-10

PVT
D REV. A D
LAST_MODIFIED=Mon Jan 10 13:11:06 2011
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE

1 1 TABLE OF CONTENTS MIKE N/A 32 73 POWER: ALIASES YOSH N/A


TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

2
TABLE_TABLEOFCONTENTS_ITEM
2 BLOCK DIAGRAM: SYSTEM MIKE N/A 33
TABLE_TABLEOFCONTENTS_ITEM
75 POWER: BATTERY CONNECTOR YOSH N/A

3
TABLE_TABLEOFCONTENTS_ITEM
5 BOM TABLE MIKE N/A 34
TABLE_TABLEOFCONTENTS_ITEM
81 POWER: PMU YOSH N/A

4
TABLE_TABLEOFCONTENTS_ITEM
6 AP: MAIN JAMES N/A 35
TABLE_TABLEOFCONTENTS_ITEM
82 POWER: PMU YOSH N/A

5 7 AP: I/Os JAMES N/A 36 83 POWER: 3.3V VR YOSH N/A


TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

6
TABLE_TABLEOFCONTENTS_ITEM
8 AP: NAND JAMES N/A 37
TABLE_TABLEOFCONTENTS_ITEM
90 DEBUG AND MISC MIKE N/A

7
TABLE_TABLEOFCONTENTS_ITEM
9 AP: TV,DP,MIPI JAMES N/A 38
TABLE_TABLEOFCONTENTS_ITEM
93 FCT/ICT TEST/BRACKETS MIKE N/A

8 10 AP: PWR JAMES N/A 39 100 CONSTRAINTS: ASSIGNMENTS MIKE N/A

C C
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

9
TABLE_TABLEOFCONTENTS_ITEM
11 AP: PWR JAMES N/A 40
TABLE_TABLEOFCONTENTS_ITEM
101 CONSTRAINTS: ASSIGNMENTS MIKE N/A

10
TABLE_TABLEOFCONTENTS_ITEM
12 AP: MISC & ALIASES JAMES N/A 41
TABLE_TABLEOFCONTENTS_ITEM
102 CONSTRAINTS: MLB RULES MIKE N/A

11 13 AP: VIDEO BUFFER,BB USB MUXES JAMES N/A 42 106 CONSTRAINTS: RF RULES MIKE N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

12
TABLE_TABLEOFCONTENTS_ITEM
14 NAND JONATHANN/A

13
TABLE_TABLEOFCONTENTS_ITEM
17 VIDEO: DISPLAY PORT JAMES N/A

14
TABLE_TABLEOFCONTENTS_ITEM
20 VIDEO: MLC MIKE N/A

15 21 VIDEO: MLC ALIASES MIKE N/A


TABLE_TABLEOFCONTENTS_ITEM

16
TABLE_TABLEOFCONTENTS_ITEM
22 VIDEO: LVDS CONNECTOR ALEX N/A

17
TABLE_TABLEOFCONTENTS_ITEM
30 GRAPE: GROUNDHOG,CONN,BOOST RAMSIN N/A

18 31 GRAPE: Z1, Z2 RAMSIN N/A


TABLE_TABLEOFCONTENTS_ITEM

19 36 AUDIO: L63 CODEC LENG N/A


B TABLE_TABLEOFCONTENTS_ITEM
B
20 37 AUDIO: SPEAKER AMP LENG N/A
TABLE_TABLEOFCONTENTS_ITEM

21
TABLE_TABLEOFCONTENTS_ITEM
38 AUDIO: HEADPHONE OUT LENG N/A

22
TABLE_TABLEOFCONTENTS_ITEM
39 AUDIO: BLANK LENG N/A

23 42 AUDIO: DETECT/MIC BIAS LENG N/A


TABLE_TABLEOFCONTENTS_ITEM

24
TABLE_TABLEOFCONTENTS_ITEM
43 AUDIO: HP/MIC FILTERS LENG N/A

25
TABLE_TABLEOFCONTENTS_ITEM
54 CONNECTOR: CANADA FLEX CONN,SENSOR
MARKPANEL
B. N/A ALIASES

26
TABLE_TABLEOFCONTENTS_ITEM
55 CONNECTOR: CANADA FLEX FILTERS MARK B. N/A

27 56 CONNECTOR: SENSOR PANEL CONNECTORMARK B. N/A


TABLE_TABLEOFCONTENTS_ITEM

28
TABLE_TABLEOFCONTENTS_ITEM
57 IO FLEX: DOCK COMPONENTS JAMES N/A

29 59 IO FELX: B2B Connector JAMES N/A


A A
TABLE_TABLEOFCONTENTS_ITEM

30 60 CONNECTOR: X23 WIFI/BT MIKE N/A DRAWING TITLE


TABLE_TABLEOFCONTENTS_ITEM

CHOPIN MLB
31 61 CONNECTOR: X24 CELLULAR/GPS MIKE N/A DRAWING NUMBER SIZE
TABLE_TABLEOFCONTENTS_ITEM

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=BACH
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 106
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ISP_I2C1 FF CAMERA
Z2
CSA 31
SPI1
H4P MIPI1C
ISP_I2C0
CANADA FLEX

REAR CAMERA
MIPI0C SENSOR PANEL

D D
GROUNDHOG DUAL-CORE ARM
Z1 CORTEX-A9 W/ SMP
850 MHZ SDIO X23
CSA 30 CSA 31 WIFI/BT WIFI/BT ANT
UART3
BT_I2S
LPDDR2 CSA 60

2X32-BIT
400MHZ/800MB/S X24
ICE3.0/GPS
DISPLAY/ USB1.1 USB1.1
TOUCH PANEL MLC MIPI0D
UART1 USART
GPU UART2 UMTS
CELLULAR ANT
LVDS DUAL-CORE IMG UART4 GPS
CSA 20 SGX543-MP
C SPI2 IPC GPS ANT C
BACKLIGHT
AUDIO CSA 61
AE2
ARM A5 CPU
UART5
USB2.0

PMU UART0
BATTERY 30-PIN
ALISON DOCK
DISPLAYPORT
CSA 75
VIDEO DAC AMP
DWI
I2C0
CSA 81
B B
AUDIO CODEC
I2C1 L63
I2S2 VSP LINEOUT CSA 57

PROX SENSOR COMPASS I2S0 ASP


AMP SPEAKER
SENSOR PANEL SENSOR PANEL I2S3 XSP
AMP
I2C2 FMI0 FMI1 FMI2 FMI3 HSIC0
MIC

CSA 36 HP
A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

GYRO ACCELEROMETER ALS NAND FLASH NAND FLASH BLOCK DIAGRAM: SYSTEM
DRAWING NUMBER SIZE

SD CARD READER Apple Inc. 051-8962 D


REVISION

SENSOR PANEL SENSOR PANEL CANADA FLEX


R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

CSA 58 THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CSA 14 CSA 14 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
BOM OPTIONS
Power aliases required by this page:
(NONE)

Signal aliases required by this page:


(NONE)

BOM options provided by this page:


PROGRAMMABLE PARTS

ALL AVAIL BOM OPTIONS

D COMMON
ALTERNATE D
16GB_PROD
32GB_PROD
64GB_PROD
BKLT_PLL
DEVELOPMENT_JTAG
DEVELOPMENT_JTAG_TAP
SCH AND BOARD P/N
JTAG_DAP
JTAG_TAP_NOT
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


SPEAKER TABLE_5_ITEM

INTERNAL_MIC 051-8962 1 SCH,CHOPIN_AUDIO,MLB,K94 SCH1


PORTRAIT_DOCK TABLE_5_ITEM

MLC_DEV 820-3069 1 PCBF,CHOPIN_AUDIO,MLB,K94 PCB1


MLC_PROD

K93
K94

TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS


PD PARTS
TABLE_BOMGROUP_ITEM

BASIC COMMON,ALTERNATE
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


TABLE_5_ITEM

806-1396 1 FENCE,GRAPE,MLB,K93/K94 FENCE1


TABLE_5_ITEM

806-1397 1 CAN,GRAPE,MLB,K93/K94 CAN1 NOSTUFF


ADD DEVELOPMENT AND OTHER BOMS ONCE YOU GET BOM NUMBERS TABLE_5_ITEM

806-1398 1 FENCE,CPU,MLB,K93/K94 FENCE2


TABLE_5_ITEM

806-1399 1 CAN,CPU,MLB,K93/K94 CAN2 NOSTUFF

C C
TABLE_5_ITEM

806-1400 1 FENCE,NAND,MLB,K93/K94 FENCE3


TABLE_5_ITEM

806-1401 1 CAN,NAND,MLB,K93/K94 CAN3 NOSTUFF

TOP BARCODE LABEL/EEE CODES


(ONLY ONE IS USED PER BOM)
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1180 (K93 16G) DH36 CRITICAL EEEE_K93_16G


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1426 (K93 32G) DH37 CRITICAL EEEE_K93_32G


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1428 (K93 64G) DG99 CRITICAL EEEE_K93_64G


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1112 (K94 16G) DFC4 CRITICAL EEEE_K94_16G


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1181 (K94 32G) DFC5 CRITICAL EEEE_K94_32G


TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1182 (K94 64G) DFC6 CRITICAL EEEE_K94_64G


TABLE_5_ITEM

B
825-7651

825-7651
1

1
EEEE FOR 639-1430 (K95 16G)

EEEE FOR 639-1427 (K95 32G)


DH3C

DH3D
CRITICAL
CRITICAL
EEEE_K95_16G

EEEE_K95_32G
TABLE_5_ITEM

B
TABLE_5_ITEM

825-7651 1 EEEE FOR 639-1429 (K95 64G) DG9C CRITICAL EEEE_K95_64G

BOTTOM LABEL TYPE 1


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

825-7639 1 631- B/C LABEL LBL1 CRITICAL


TABLE_5_ITEM

825-7639 1 639- B/C LABEL LBL2 CRITICAL

BOTTOM LABEL TYPE 2


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

825-7640 1 MATRIX LABEL LBL3 CRITICAL


TABLE_5_ITEM

825-7640 1 631- MATRIX LABEL LBL4 CRITICAL

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

BOM TABLE
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: NEED TO ADD BOM TABLE FOR ALT P/N OF HYNIX (?)
PART NUMBER =PP1V1_PLL_H4 R0620 TP401

32
1
0.00 2 PP1V1_PLL4_F
TABLE_5_HEAD

0% VOLTAGE=1.1V PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


1/32W
MF
1 C0651 MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
01005 0.01UF NET_SPACING_TYPE=PWR
10% MAX_NECK_LENGTH=3 MM
6.3V
2 X5R
01005
AU14
U0652 D27 R0621 TP403

AU15 D32 0.00 2


AU16 H4P-512MB E1
1

BGA 0%
AU17 E2 1/32W 1 C0648
D AV1
AV2
SYM 11 OF 12
SC58940X01-A030
E3
E4
MF
01005
10%
0.01UF
PP1V1_PLL3_F

VOLTAGE=1.1V
D
2 6.3V
X5R MIN_LINE_WIDTH=0.2MM
AV3 E6 01005 MIN_NECK_WIDTH=0.1MM
AV4 E8 R0622 TP407 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
1
0.00 2 MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
AV5 E10 TP409

AV6 E12 0%
MAX_NECK_LENGTH=3 MM
R0625
1/32W 1 C0646 PP1V1_PLL2_F PP1V1_PLL_USB_F 1
0.00 2 =PP1V1_USB_H4
AV7 E14 MF 4 32
01005 0.01UF VOLTAGE=1.1V
AV8 E16 10% MIN_LINE_WIDTH=0.2MM 0%
AV9 E17 2 6.3V
X5R MIN_NECK_WIDTH=0.1MM 1 C0652 1/32W
MF
01005 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM 0.01UF 01005
AV10 E18 10%
AV11 E19 R0623 TP405
6.3V
2 X5R
1
0.00 2 01005
AV12 E20 VOLTAGE=1.1V
AV13 E21 0% PP1V1_PLL1_F MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
AV14 E22
1/32W
MF
1 C0644 TP456
NET_SPACING_TYPE=PWR FL0610
01005 0.01UF VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
80-OHM-0.2A-0.4-OHM
AV15 E23 10% MIN_NECK_WIDTH=0.1MM
6.3V PP1V1_MIPID_PLL_F =PP1V1_MIPI_PLL_H4
AV16 E25 2 X5R NET_SPACING_TYPE=PWR 1 2 32
01005 MAX_NECK_LENGTH=3 MM
AV17 E26 0201-1
AV29 E27 R0624 TP406
1 C0661 1 C0654 1 C0655
1
0.00 2 PP1V1_PLL0_F 56PF 0.1UF 1UF
AV33 E28 5% 10% 10%
AV34 E30 0% VOLTAGE=1.1V 2 6.3V
NP0-C0G 2 6.3V
X5R 2 6.3V
CERM
MIN_LINE_WIDTH=0.2MM
AW1 E31
1/32W
MF
1 C0608 1 C0660 MIN_NECK_WIDTH=0.1MM 01005 201 402

AW2 E32
01005 0.01UF 56PF NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
10% 5%
AW4 E34 2 6.3V
X5R 2 6.3V
NP0-C0G
01005 01005 =PP1V1_USB_H4
AW23 F1 4 32

AW33 F2 1 C0627
AW34 F3 0.01UF
10%

C
AY1
AY2
F5
F19 32 4
=PP1V1_USB_H4 2 6.3V
X5R
01005 C
AY3 F20 1 C0643
AY4 F21 0.22UF
20%
AY20 F22 6.3V
2 X5R
AY22 F23 0201
=PP3V3_USB_H4
AY24 F25 4 32

AY30 F26 =PP1V2_HSIC_H4


32
1 C0640 1 C0630
AY31 F29 1UF 0.01UF

AR10
AT14
AY32 F30
1 C0642 1 C0641 10% 10%

D25
D24

F24

C19
C20
C21
C18
C17
C22

C28

H27
H28
6.3V 6.3V
0.01UF 0.01UF 2 CERM 2 X5R
AY33 F31 10% 10% 402 01005
6.3V 6.3V
2 X5R 2 X5R

HSIC_VDD121
HSIC_VDD122

HSIC_DVDD

PLL0_AVDD11
PLL1_AVDD11
PLL2_AVDD11
PLL3_AVDD11
PLL4_AVDD11
PLL_USB_AVDD11
MIPI0D_VDD11_PLL
MIPI1D_VDD11_PLL

USB_DVDD
AY34 F32

USB_VDD330
01005 01005
B1 G1
B2 G3
B7 G4 JTAGSEL
B9 G7 0 - PARALLEL 5MA
VSS VSS 7MA
B10 G8 1 - DAISY-CHAIN (FOR USE WITH 5-WIRE JTAG)
17MA 17MA 2.5MA EACH 28MA
PER RADAR #6755237 TP59
B12 G9
B13 G10 TP_HSIC1_AP_DATA A26 HSIC1_DATA
2.5MA
WDOG P30 RST_PMU_IN OUT 35
B15 G12 TP_HSIC1_AP_STB A27 HSIC1_STB
6.5MA

B17 G13 TP62


TP58 NC_HSIC2_AP_DATA C26 HSIC2_DATA XI0 A18 39 XTAL_24M_I
B18 G14 =PP1V8_H4 DEVELOPMENT_JTAG_TAP
B20 G15
32 13 10 7 5 4
R0645 R0662
TP61 NC_HSIC2_AP_STB D26 HSIC2_STB SYM 1 OF 12
100K 2
1 JTAG_AP_TCK 100K 2 R0655

2
B22 G16 4 28 39 =PP1V8_H4 10 AP_JTAG_SEL
N31
B23 G17 R0646
32 13 10 7 5 4 1
NC_JTAG_AP_RTCK M30
JTAG_SEL
JTAG_TRTCK
U0652 1.00M CRITICAL
B28 G18 100K 2 N29 H4P-512MB 1% MF
1 JTAG_AP_TMS 4 28 39 39 10 OUT JTAG_AP_TRST_L JTAG_TRST* 010051/32W Y0602
B29 G19 M31 BGA

1
JTAG_AP_TDO
B B30 G20
G21
R0647
1
100K 2
JTAG_AP_TDI
39 10

39 10 4
OUT
IN JTAG_AP_TDI M32
N32
JTAG_TDO
JTAG_TDI R0640
22
SM-2
24.000MHZ-16PF-60PPM B
B32 XO0 A19
4 10 39
39 28 4 OUT JTAG_AP_TMS JTAG_TMS 39 XTAL_24M_O 1 2 1 3
B33 G22 JTAG_AP_TCK N30 JTAG_TCK 5%
39 28 4 OUT 1/32W 39 24M_O 2 4
B34 G25 MF
TP60 AP_TESTMODE P29 TESTMODE USB11_DP A22 USB_FS_D_P 01005 1 C0613 1 C0607
C1 G28 10 BI 11 39

USB11_DM A23 USB_FS_D_N 22PF 22PF


C2 G29 M28 FUSE1_FSRC BI 11 39
5% 5%
=PP3V3_USB_H4 16V 16V
C3 G30 32 4 2 CERM 2 CERM
AP_TST_STPCLK P33 TST_STPCLK 01005 01005
C4 H1 10

TP_AP_TST_CLKOUT P34 TST_CLKOUT USB_DP A29 USB_D_P


C5 H2 1 BI 28 39
R0617 USB_DM A28 USB_D_N
C6 H3 10K 10 AP_FAST_SCAN_CLK T32 FAST_SCAN_CLK (FOR IC TESTER)
BI 28 39

C7 H5 1%
1/32W P31
AP_HOLD_RESET HOLD_RESET
C8 H7 MF
2 01005
R0632 10 (0=NORMAL)
USB_ANALOGTEST G26 NC_USB_ANALOGTEST
TP410
R0651
C9 H8 100K 2 P32
RST_AP_L 1 RESET* 100K 2 PPVBUS_USB
USB_VBUS F27
35 31 28 IN NOSTUFF USB_AP_VBUS 1
C10 H10 1% RST_AP_1V8_L
34

H12 1/32W XW0604 5%


C11 MF SHORT-01005 USB_ID F28 NC_USB_ID 2
DZ0600 1/32W
H14 01005 W30 MF TP68
C12 1 2 AP_CFSB CFSB USB_BRICKID G27 GDZT2R5.1B 01005
C13 H16 GDZ-0201
G11 DDR0_CKEIN USB_REXT A21 USB_REXT 1
C14 H18 TP64
C15 H20 R0688 1 1 C0618 TP54
R7 DDR1_CKEIN
1000PF

PLL_USB_AVSS11
C16 H22 42.2K 10%
1
R0642
1%
1/32W
16V
2 X7R 44.2

HSIC_VSS121
HSIC_VSS122

PLL0_AVSS11
PLL1_AVSS11
PLL2_AVSS11
PLL3_AVSS11
PLL4_AVSS11
C23 H24 MF 1% USB_BRICKID OUT

MIPI_VSS_0
MIPI_VSS_1
201 NOTE: 35
01005 2 1/20W

HSIC_DVSS

USB_VSSA0
USB_VSSAC
C27 H25 PAGE 4608
NOSTUFF

USB_DVSS
H4P UM V0.83 MF
C29 H29 XW0605 2 201
C32 H30 SHORT-01005
C33 J1 AP_DDR1_CKEIN_1V2 1 2 AP_DDR1_CKEIN

A
D1 J2
A

C25
C24

E24

D19
D20
D21
D18
D17
D22
AN10
AN11

D28

H26
J26
D3 J3 SYNC_MASTER=JAMES SYNC_DATE=N/A
D5 J4 R0689 1 PAGE TITLE
82.5K
D7
D9
J7
J9
1%
1/32W
MF
AP: MAIN
01005 2 DRAWING NUMBER SIZE
D11 J11 TP420 TP423 TP426 TP431 TP438
Apple Inc. 051-8962 D
D13 J13 REVISION
D15 J15 R
A.0.0
D16 J17 NOTICE OF PROPRIETARY PROPERTY: BRANCH
D23 J19 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

32 27 26 =PP3V0_OPTICAL R0771
=PP1V8_S2R_MISC 1
220K 2
32 13 10 7 4 =PP1V8_H4 32 28 5
AA3
5% 35 29 5 IN HOME_L GPIO0
1 1 1 1 1 1 1/20W ONOFF_L AA4 U0652
R0700 R0701 R0702 R0703 R0704 R0705 MF
201
35 25 5 IN
AA5
GPIO1
H4P-512MB
4.7K 4.7K 4.7K 4.7K 1.8K 1.8K HOME_L NC_AP_GPIO2 GPIO2
5%
1/32W
5%
1/32W
5%
1/32W
5%
1/32W
5%
1/32W
5%
1/32W
35 29 5 TP47
NC_AP_GPIO3 AA6 GPIO3
BGA
MF MF MF MF MF MF R0770 AA7 SC58940X01-A030
2 01005 2 01005 2 01005 2 01005 2 01005 2 01005
NC_AP_GPIO4 GPIO4 SYM 2 OF 12
220K 2 AB3 EHCI_PORT_PWR0 AL7 AP_GPIO40_BRD_REV0 IN 10
39 35 19 10 5 I2C0_SDA_1V8 32 =PP1V8_ALWAYS 1 NC_AP_GPIO5 GPIO5
TP69
AB4 EHCI_PORT_PWR1 AL6 AP_GPIO41_BRD_REV1 IN 10
39 35 19 10 5 I2C0_SCL_1V8 5% NC_AP_GPIO6 GPIO6
TP67 1/20W AB5 EHCI_PORT_PWR2 AM6 AP_GPIO42_BRD_REV2 IN 10
MF 30 OUT PM_BT_WAKE GPIO7
I2C1_SDA_1V8
D
ONOFF_L 201
39 25 5
TP27 AC7
D
35 25 5 TP571 NC_AP_GPIO8 GPIO8
39 25 5 I2C1_SCL_1V8 TP565 AC4
PM_RADIO_ON
R0765 31 5 OUT
AD7
GPIO9
TMR32_PWM0 AC30 NC_AP_GPIO185
39 26 25 5 I2C2_SDA_3V0 220K 2 NC_AP_GPIO10 GPIO10
TP554
32 28 5 =PP1V8_S2R_MISC 1
AC3 TMR32_PWM1 AA27 NC_AP_GPIO186
39 26 25 5 I2C2_SCL_3V0 31 RST_DET_L GPIO11
5% IN
AD6 TMR32_PWM2 AB30 NC_AP_GPIO187
1/20W 31 IN SPI_IPC_SRDY GPIO12
MF
201 TP619
IRQ_PMU_L AD5 GPIO13
35 25 5 SRL_L 35 IN
(SCREEN ROTATION LOCK) NC_AP_GPIO14 AD4 GPIO14
IRQ_CODEC_L AD3 GPIO15 UART0_RXD R31 UART_0_RXD
19 IN IN 10
TP46 AE7 3.0V
NC_BOARD_ID_3 GPIO16 UART0_TXD R30 UART_0_TXD OUT 10 TO DOCK MUX
AD1
25 5 OUT IRQ_GYRO_INT2 GPIO17 AN4 UART_1_CTS_L
AE1 UART1_CTSN IN 10
10 IN BOOT_CONFIG_0 GPIO18 AM5 UART_1_RTS_L
AE4 UART1_RTSN OUT 10
35 5 OUT PM_KEEPACT GPIO19 AM3 UART_1_RXD TO BB USART
AE3 UART1_RXD IN 10
NC_AP_GPIO20 GPIO20 AM1
AE2 UART1_TXD UART_1_TXD OUT 10
18 OUT IRQ_GRAPE_HOST_INT_L GPIO21
NC_AP_GPIO22 AF4 GPIO22 UART2_CTSN AP4 SRL_L 5 25 35
IN
GPS_SYNC AF3 GPIO23 UART2_RTSN AM2 RST_BB_L TP577
31 OUT OUT 31
TP616
GSM_TXBURST_IND AF7 GPIO24 UART2_RXD AM4 UART_2_RXD
31 IN IN 10
TP599
BOOT_CONFIG_1 AF2 GPIO25 UART2_TXD AN5 UART_2_TXD TO BB UMTS
10 IN OUT 10

FORCE_DFU AG7 GPIO26


37 5 IN AP1 UART_3_CTS_L
AG6 UART3_CTSN IN 10
5 OUT DFU_STATUS GPIO27 AR2
AG5 UART3_RTSN UART_3_RTS_L OUT 10
TO BT UART
10 IN BOOT_CONFIG_2 GPIO28
UART3_RXD AR4 UART_3_RXD
BOOT_CONFIG_3 AG4 GPIO29 IN 10
10 IN AP2 UART_3_TXD
AG3 UART3_TXD OUT 10
31 OUT RST_GPS_L GPIO30
PM_GPS_STANDBY_L AG1 GPIO31 UART4_CTSN AU1 UART_4_CTS_L
31 OUT IN 10
TP618
IRQ_PROX_INT_L AH1 GPIO32 1.8V UART4_RTSN AT3 UART_4_RTS_L
25 OUT OUT 10
TP566
25 IRQ_GYRO_INT1 AH2 GPIO33 GROUP 1 UART4_RXD AT4 UART_4_RXD 10
TO GPS UART
IN IN
TP572
IRQ_GPS_INT_L AH7 GPIO34 1.8V/3.0V UART4_TXD AT1 UART_4_TXD
C C
31 IN OUT 10

TP_IRQ_COMPASS_INT_L AH3 GPIO35 GROUP 0


AH4 UART5_RTXD AR3 BATTERY_SWI OUT 33 35
25 IN IRQ_ACCEL_INT1_L GPIO36
TP573
IRQ_ALS_INT_L AJ5 GPIO37 UART6_CTSN AU2 AUD_VOL_DOWN_L
26 IN IN 25

25 IRQ_ACCEL_INT2_L AJ4 GPIO38 UART6_RTSN AN3 IPC_GPIO 31


TP574
IN IN
TP453
AUD_SPKRAMP_MUTE_L AJ3 GPIO39 UART6_RXD AU3 AUD_VOL_UP_L TP620
20 OUT IN 25

UART6_TXD AP3 TP_PROX_GPIO TP575


PORT_DOCK_VIDEO_AMP_EN U30 GPIO_3V0
11 OUT
NC_GPIO_218 V30 GPIO_3V1
VSS

A1
A2
A3
A6
A7
A8
A9
A10
A11
A12
TP42
PM_KEEPACT 5 35

IRQ_GYRO_INT2
R0720 TP567 5 25

33.2 FORCE_DFU 5 37
1%
1/32W
TP40
DFU_STATUS 5
MF
01005 PM_RADIO_ON
2 I2S_AP_0_MCK Y32
5 31
39 19 OUT I2S_AP_0_MCK_R 1 I2S0_MCK U0652
AB33 I2S0_BCLK H4P-512MB
39 19 OUT I2S_AP_0_BCLK
Y31 1 1 1 1 1
39 19 OUT I2S_AP_0_LRCK I2S0_LRCK BGA R0735 R0736 R0737 R0738 R0739
CODEC ASP AC34
39 19 IN I2S_AP_0_DIN I2S0_DIN SC58940X01-A030 I2C0_SCL AD26 I2C0_SCL_1V8 BI 5 10 19 35 39 100K 100K 100K 100K 100K
AA32 5% 5% 5% 5% 5%
39 19 I2S_AP_0_DOUT
OUT I2S0_DOUT SYM 3 OF 12 I2C0_SDA AD29 I2C0_SDA_1V8 OUT 5 10 19 35 39 1/20W 1/32W 1/20W 1/20W 1/20W

B NC_I2S_AP_1_MCK AC33
AD32
I2S1_MCK I2C1_SCL AD31 I2C1_SCL_1V8 BI 5 25 39
MF
2 201
MF
2 01005
MF
2 201
MF
2 201
MF
2 201 B
NC_I2S_AP_1_BCLK I2S1_BCLK I2C1_SDA AE30 I2C1_SDA_1V8 OUT 5 25 39

BB (NOT USED) NC_I2S_AP_1_LRCK Y34 I2S1_LRCK


W34 I2C2_SCL AF30 I2C2_SCL_3V0 BI 5 25 26 39
NC_I2S_AP_1_DIN I2S1_DIN GROUP 7
AC32 I2C2_SDA AF29 I2C2_SDA_3V0 OUT 5 25 26 39
NC_I2S_AP_1_DOUT I2S1_DOUT
V33 SWI_DATA AA30 NC_SWI_AP
NC_I2S_AP_2_MCK I2S2_MCK
V32 DWI_CLK AB34
30 19
39
OUT I2S_AP_2_BCLK I2S2_BCLK DWI_AP_CLK OUT 35 39
U34 DUAL-WIRE INTF DWI_DI AA31
30 19 OUT I2S_AP_2_LRCK I2S2_LRCK DWI_AP_DI IN 35 39
39
U32 FOR PMU
CODEC VSP & BT 30 19 IN I2S_AP_2_DIN I2S2_DIN DWI_DO Y27 DWI_AP_DO OUT 35 39
39
V31
30 19
39
OUT I2S_AP_2_DOUT I2S2_DOUT

NC_I2S_AP_3_MCK T31 I2S3_MCK


I2S_AP_3_BCLK W32 I2S3_BCLK
39 19 OUT
I2S_AP_3_LRCK U31 I2S3_LRCK
39 19 OUT
CODEC XSP T30
39 19 IN I2S_AP_3_DIN I2S3_DIN
W29
39 19 OUT I2S_AP_3_DOUT I2S3_DOUT
NC_AP_GPIO216 W31 SPDIF

BOARD_ID_2_SPI_FLASH_DOUT AE29 SPI0_MISO SDIO0_CLK AB27 SDIO_WL_CLK OUT


10 IN 30 40

10 BOARD_ID_1_SPI_FLASH_DIN AG34 SPI0_MOSI SDIO0_CMD AC26 SDIO_WL_CMD OUT 30 40


IN
BOARD_ID_0_SPI_FLASH_CLK AE31 SPI0_SCLK SDIO0_DATA0 AB31 SDIO_WL_DATA<0>
10 IN BI 30 40
AE32 AD30 TO WIFI
NC_SPI_FLASH_CS_L SPI0_SSIN SDIO0_DATA1 SDIO_WL_DATA<1> BI 30 40

SDIO0_DATA2 AB26 SDIO_WL_DATA<2>


SPI_GRAPE_MISO AH32 SPI1_MISO
BI 30 40
40 17 IN AB32 SDIO_WL_DATA<3>
AF28 SDIO0_DATA3 BI 30 40
40 17 OUT SPI_GRAPE_MOSI SPI1_MOSI
TO GRAPE AG32
SPI_GRAPE_SCLK SPI1_SCLK GROUP 6 TP333

A
40 17 OUT
40 17 OUT SPI_GRAPE_CS_L AF31

AF34
SPI1_SSIN
AH31
SYNC_MASTER=JAMES
PAGE TITLE
SYNC_DATE=N/A A
SPI_IPC_MISO SPI2_MISO SPI3_MISO NC_SPI_AP_3_MISO
IN
AP: I/Os
40 31

40 31 SPI_IPC_MOSI AG33 SPI2_MOSI 1.8V/3.0V SPI3_MOSI AH29 NC_SPI_AP_3_MOSI


OUT
TO BB SPI_IPC_SCLK AE27 SPI2_SCLK GROUP 5 SPI3_SCLK AH30 NC_SPI_AP_3_SCLK DRAWING NUMBER SIZE
40 31 IN
40 31 OUT SPI_IPC_MRDY AE28 SPI2_SSIN SPI3_SSIN AG30 NC_SPI_AP_3_CS_L
Apple Inc. 051-8962 D
REVISION
VSS R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
A13
A14
A15
A16
A17
A20
A30
A33
A34
AA9

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
TP334
IV ALL RIGHTS RESERVED 5 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

10 9 6 =PPIO_NAND_H4

J21 R3 1 =PPIO_NAND_H4
U0652 R0832 1 R0836 1 R0833 1 R0828 1 1
R0834 R0825
1 1
R0827 10 9 6
J23 R4 100K 100K 100K 100K R0831 100K
J25 H4P-512MB R9 5% 5% 5% 100K 100K 100K 5%
BGA 1/32W 5% 1/32W 1/32W 5% 5% 5% 1/32W
MF 1/32W MF MF 1/32W 1/32W 1/32W MF
J27 SYM 12 OF 12 R11 MF MF MF 1 1 1 1
2 01005 2 01005 2 01005 2 01005 2 MF
01005 2 01005 2 01005 2 01005 R0800 R0801 R0802 R0803
J28 SC58940X01-A030 R13 39 12 6 F1CE0_L 100K 5%
100K 100K
5%
100K
5%
J29 R15 F1CE1_L 5%
39 12 6 1/32W 1/32W 1/32W 1/32W
J30 R17 MF MF MF MF
39 12 6 F1CE2_L 2 01005 2 01005 2 01005 2 01005
K1 R19 F1CE3_L
D K3 R21
39 12 6

39 12 6 F0CE0_L D
K5 R23 39 12 6 F0CE1_L
K7 R25 F0CE2_L
K8 R27
39 12 6
F0WE_L
F0CE3_L 39 12 6

K10 R29
39 12 6
39 12 6 F0RE_L
K12 R34 39 12 6 F1WE_L
K14 T1 39 12 6 F1RE_L
K16 T2
K18 T3 10 9 6 =PPIO_NAND_H4 39 12 6 F0ALE
K20 T5 R0860 R0861 R0862 R0864 R0865 R0866 39 12 6 F0CLE
1 1 1 1 1 1 1
K22 T7 100K 1100K 100K R0863 100K 100K 100K R0867 39 12 6 F1ALE
K24 T8 5% 5% 5% 100K 5% 5% 5% 100K 39 12 6 F1CLE
1/32W 1/32W 1/32W 5% 1/32W 1/32W 1/32W 5%
K26 T10 MF MF MF 1/32W MF MF MF 1/32W
01005 01005 01005 MF 01005 01005 01005 MF
K30 T12 2 2 2 2 01005 2 2 2 2 01005
K31 T14 39 12 6 F1CE4_L
K32 T16 39 12 6 F1CE5_L
1 1
L1 T18 39 12 6 F1CE6_L R0810 R0811 1 R0812 1
R0813
F1CE7_L 100K 100K 100K 100K
L2 T20 39 12 6
5% 5% 5% 5%
L3 T22 39 12 6 F0CE4_L 1/32W 1/32W
MF
1/32W
MF
1/32W
MF
MF
L4 T24 39 12 6 F0CE5_L 2 01005 2 01005 2 01005 2 01005

L7 T26 39 12 6 F0CE6_L
L9 T29 39 12 6 F0CE7_L
L11 T33
L13 U1
L15 U3
L17 U4

C
L19
L21
U7
U9 C
L23 U11
L25 U13
L28 U15
L29 U17
L30 U19
L31 U21
L32 U23
L33 U25
M1 U27
M3 VSS VSS U28 U0652
M5 V1 H4P-512MB BGA
M7 V2
F0CE0_L AV20 FMI0_CEN0 FMI2_CEN0 AY26 NC_F2CE0_L
M8 V3 39 12 6 OUT
F0CE1_L AW21 FMI0_CEN1 GROUP 2 GROUP 2 FMI2_CEN1 AU26 NC_F2CE1_L
M10 V5 39 12 6 OUT
F0CE2_L AU19 FMI0_CEN2 FMI2_CEN2 AW26 NC_F2CE2_L
M12 V7 39 12 6 OUT TP70
F0CE3_L AU20 FMI0_CEN3 FMI2_CEN3 AV26 NC_F2CE3_L
M14 V8 39 12 6 OUT
SYM 4 OF 12
M16 V10 39 12 6 OUT F0CE4_L AV31 FMI0_CEN4 FMI2_CEN4 AP34 RST_MLC_L OUT 14

F0CE5_L AT31 FMI0_CEN5 GROUP 3 FMI2_CEN5 AL32 TP_GPIO_SD_CTRL


M18 V12 39 12 6 OUT
AV32 GROUP 5
M20 V14 39 12 6 OUT F0CE6_L FMI0_CEN6 3.3V FMI2_CEN6 AK31 RST_GRAPE_L OUT 17
1
R0878
M22 V16 39 12 6 OUT F0CE7_L AU30 FMI0_CEN7 FMI2_CEN7 AM32 GRAPE_FW_DNLD_EN_L OUT 17 100K
5%
1/32W
M24 V18 39 12 BI F0AD<0> AV18 FMI0_IO0 FMI2_IO0 AY29 NC_F2AD<0> MF
M26 V20 F0AD<1> AU18 FMI0_IO1 FMI2_IO1 AR30 NC_F2AD<1> 2 01005
39 12 BI
M29 V22 39 12 F0AD<2> AT22 FMI0_IO2 FMI2_IO2 AU29 NC_F2AD<2>
BI
M33 V24 39 12 BI F0AD<3> AW19 FMI0_IO3 FMI2_IO3 AV28 NC_F2AD<3>
N1 V26 F0AD<4> AV21 AY28 NC_F2AD<4>
B N2
N3
V28
V34
39 12

39 12
BI
BI F0AD<5> AU22
AY21
FMI0_IO4
FMI0_IO5
FMI2_IO4
FMI2_IO5 AW30 NC_F2AD<5> B
39 12 BI F0AD<6> FMI0_IO6 GROUP 2 GROUP 2 FMI2_IO6 AW28 NC_F2AD<6>
N4 W1 F0AD<7> AR20 FMI0_IO7 FMI2_IO7 AU28 NC_F2AD<7>
39 12 BI
N7 W2
F0ALE AT20 FMI0_ALE FMI2_ALE AW27 NC_F2ALE
N9 W3 39 12 6 OUT
N11 W4 39 12 6 OUT F0CLE AU21 FMI0_CLE FMI2_CLE AU27 NC_F2CLE
F0WE_L AT19 FMI0_WEN FMI2_WEN AV27 NC_F2WE_L
N13 W7 39 12 6 OUT
F0RE_L AV22 FMI0_REN FMI2_REN AY27 NC_F2RE_L
N15 W9 39 12 6 OUT
NC_AP_GPIO76 AT21 FMI0_DQS FMI2_DQS AV30 NC_AP_GPIO_110
N17 W11
N19 W13 39 12 6 OUT F1CE0_L AN22 FMI1_CEN0 FMI3_CEN0 AT30 NC_F3CE0_L
N21 W15 F1CE1_L AY19 FMI1_CEN1 GROUP 2 GROUP 4 FMI3_CEN1 AP31 NC_F3CE1_L
39 12 6 OUT
N23 W17 39 12 6 F1CE2_L AP20 FMI1_CEN2 FMI3_CEN2 AU31 NC_F3CE2_L
OUT
N25 W19 F1CE3_L AT18 FMI1_CEN3 FMI3_CEN3 AU32 NC_F3CE3_L
39 12 6 OUT
N27 W21 F1CE4_L AN30 FMI1_CEN4 FMI3_CEN4 AN34 NC_AP_GPIO_147
39 12 6 OUT
N28 W23 39 12 6 OUT F1CE5_L AU34 FMI1_CEN5 GROUP 3 FMI3_CEN5 AM33 TP_RST_SD_CTRL_L
P1 W25 AU33 GROUP 5
39 12 6 OUT F1CE6_L FMI1_CEN6 3.3V FMI3_CEN6 AM34 PM_MLC_PWR_EN OUT 36
P2 W27 F1CE7_L AP30 FMI1_CEN7 FMI3_CEN7 AN33 TP_CD_SD_CTRL_L
39 12 6 OUT
P3 Y3
F1AD<0> AV25 FMI1_IO0 FMI3_IO0 AP33 NC_F3AD<0>
P5 Y5 39 12 BI
P7 Y7 39 12 BI F1AD<1> AU23 FMI1_IO1 FMI3_IO1 AL31 NC_F3AD<1>
F1AD<2> AW25 FMI1_IO2 FMI3_IO2 AR34 NC_F3AD<2>
P8 Y8 39 12 BI
F1AD<3> AU25 FMI1_IO3 FMI3_IO3 AN32 NC_F3AD<3>
P10 Y10 39 12 BI
F1AD<4> AU24 FMI1_IO4 FMI3_IO4 AM31 NC_F3AD<4>
P12 Y12 39 12 BI
F1AD<5> AV24 FMI1_IO5 GROUP 4 FMI3_IO5 AN31 NC_F3AD<5>
P14 Y14 39 12 BI
GROUP 2
P16 Y16 39 12 BI F1AD<6> AT23 FMI1_IO6 FMI3_IO6 AR32 NC_F3AD<6>
F1AD<7> AV23 FMI1_IO7 FMI3_IO7 AP32 NC_F3AD<7>
A
P18 Y18 39 12 BI
P20
P22
Y20
Y22
39 12 6 OUT F1ALE AP23
AV19
FMI1_ALE FMI3_ALE AT32 NC_F3ALE SYNC_MASTER=JAMES SYNC_DATE=N/A A
F1CLE FMI1_CLE FMI3_CLE AT34 NC_F3CLE PAGE TITLE
OUT
AP: NAND
39 12 6
P24 Y24 39 12 6 OUT F1WE_L AN23 FMI1_WEN FMI3_WEN AT33 NC_F3WE_L
P26 Y29 F1RE_L AN21 FMI1_REN FMI3_REN AR31 NC_F3RE_L DRAWING NUMBER SIZE
39 12 6 OUT
R1 Y30 NC_AP_GPIO93 AY25 FMI1_DQS FMI3_DQS AR33 NC_AP_GPIO_135
Apple Inc. 051-8962 D
VSS REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA29
AB1
AB6
AB8

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MIN_NECK_MIDTH SHOULD BE 0.2MM


VOLTAGE=1.8V
=PP3V0_IO_H4 MIN_LINE_WIDTH=0.4MM
32 9 MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
1 C0954 MAX_NECK_LENGTH=3 MM TP435
R0910
0.01UF 10 PP_AP_DP_AVDD_AUX 1
0 2 =PP1V8_DPORT_H4
32
10%
6.3V 5%
2 X5R 1 C0927 1 C0926 1 C0925 1 C0924 1 C0923
D
1/20W
01005
D
MF
0.22UF 0.22UF 0.22UF 56PF 201 56PF
20% 20% 20% 5% 5%
2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
NP0-C0G 2 6.3V
NP0-C0G
402 402 402 01005 01005

=PP3V0_VIDEO_H4
32 7

PP_DP_PAD_AVDD0 =PP1V8_H4
1 C0951 1 C0952 10
32 13 10 5 4

1UF 0.01UF 1
R0930 1
R0931 1
R0932 1
R0933
10% 10%
PP_DP_PAD_AVDD1
2 6.3V
CERM 2 6.3V
X5R 10 4.7K 4.7K 1.00K 1.00K
402 01005 5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF
2 01005 2 01005 2 01005 2 01005
=PP1V1_DPORT_H4 ISP_AP_0_SCL
32 39 25 7 TP543
ISP_AP_0_SDA
VOLTAGE=1.8V 1 C0909 39 25 7 TP546

DAC_AVDD30A L27

DAC_AVDD30D K29

DP_PAD_AVDD_AUX H31

DP_PAD_AVDD0 E29
DP_PAD_AVDD1 D30

DP_PAD_AVDDP0 D31

DP_PAD_AVDDX G32

DP_PAD_DVDD J31
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM 0.1UF 39 26 7 ISP_AP_1_SCL
NET_SPACING_TYPE=PWR 10% TP606
6.3V ISP_AP_1_SDA
MAX_NECK_LENGTH=3 MM 2 X5R 39 26 7 TP590
201
FL0910
240-OHM-0.2A-0.8-OHM TP428

=PP3V0_VIDEO_H4 1 2 DAC_AP_COMP_FTR
32 7
VOLTAGE=0.4V
0201 MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
21MA 6MA 1.2MA NET_SPACING_TYPE=PWR
1 C0955 63MA 63MA 5MA MAX_NECK_LENGTH=3 MM
0.1UF 2MA
10% <= 5MA
6.3V
2 X5R =PP1V8_MIPI_H4 PP_AP_MIPI0D_0P4V
32
201
1 C0907 1 C0902
C DAC_AP_VREF J33 DAC_VREF SC58940X01-A030
SYM 6 OF 12
DAC_OUT3 L34
DAC_OUT2 M34
DAC_AP_OUT3 OUT 11
40
YIN
0.1UF
10%
2 6.3V
VOLTAGE=0.4V 10%
2 10V
2.2NF C
DAC_AP_IREF J34 DAC_IREF U0652 DAC_OUT1 N34
DAC_AP_OUT2 OUT
DAC_AP_OUT1 OUT
11
40
CVBSIN
CIN
X5R
201
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
X5R
201
K34 H4P-512MB 11
40 MAX_NECK_LENGTH=3 MM
C0956 1 R0950 1 DAC_AP_COMP DAC_COMP
BGA
0.1UF 6.34K =PP1V1_MIPI_H4 PP_AP_MIPI1D_0P4V
10% 1% DP_HPD R32 DP_AP_HPD IN 13 32
6.3V 1/20W
X5R 2 MF
201 2 1 C0930 1 C0908 1 C0903 1 C0920

AP10
AP11
AP13
AP14
AP15
AP16
AP17
AP18
AR12

MIPI0D_VDD18 AN13
MIPI1D_VDD18 AN15

MIPI0D_VREG_0P4V AR11

MIPI1D_VREG_0P4V AR15
201
H33 DP_PAD_AUXP G34 DP_AP_AUX_P BI 13 40
1UF 0.1UF 0.1UF TP450
2.2NF
TP_DP_AP_ANALOG_TEST DP_PAD_DC_TP 10% 10% 10% 10%
DP_PAD_AUXN F34 DP_AP_AUX_N BI 13 40
6.3V
2 CERM
6.3V
2 X5R
6.3V
2 X5R
10V
2 X5R
NOTE: 0.6V ANALOG REF 402 201 201 201
MIPI_VDD11
AP_DP_R_BIAS H34 DP_PAD_TX0P D34 DP_AP_TX_P<0> OUT 10 13 40
DP_PAD_R_BIAS 28MA
DP_PAD_TX0N C34 DP_AP_TX_N<0> OUT 10 13 40

C0950 1 1
R0920 DP_PAD_TX1P A32 DP_AP_TX_P<1> OUT 10 13 40
0.01UF 4.99K
10%
NOSTUFF 6.3V 1% DP_PAD_TX1N A31 DP_AP_TX_N<1> OUT 10 13 40
DP_PAD_AVSS_AUX

X5R 2 1/32W
01005 MF 2MA ???
DP_PAD_AVSSP0

2 01005
DP_PAD_AVSS0
DP_PAD_AVSS1

DP_PAD_AVSSX

1
R0955 1 R0956 1 R0957
DAC_AVSS30D

DP_PAD_DVSS
M27 DAC_AVSS30A
K27 DAC_AVSS30A

200 200 200 AA26 AG31


1% 1% 1% NC_AP_GPIO184 MIPI_VSYNC ISP0_FLASH NC_AP_GPIO153
1/20W 1/20W 1/20W SYM 5 OF 12 AG29
MF MF MF NOTE: PLACE R0955-57 NEAR U0652 AW10 ISP0_PRE_FLASH NC_AP_GPIO152
2 201 2 201 2 201 40 27 IN MIPI0C_AP_DATA_P<0> MIPI0C_DPDATA0 SC58940X01-A030 AE26
AY10 ISP0_SCL ISP_AP_0_SCL OUT 7 25 39
40 27 IN MIPI0C_AP_DATA_N<0> MIPI0C_DNDATA0 REAR CAMERA
GROUP 5 ISP0_SDA AC29 ISP_AP_0_SDA 7 25 39
BI
NC_MIPI0C_AP_DATA_P<1> AW11 MIPI0C_DPDATA1
ISP1_FLASH AJ32 NC_AP_GPIO155
K28

G31

D29
C30

C31

H32

J32

NC_MIPI0C_AP_DATA_N<1> AY11 MIPI0C_DNDATA1


ISP1_PRE_FLASH AG28 NC_AP_GPIO154
NC_MIPI0C_AP_DATA_P<2> AW13 MIPI0C_DPDATA2 ISP1_SCL AC31 ISP_AP_1_SCL OUT 7 26 39
REAR CAMERA AY13 AF27 FRONT CAMERA
NC_MIPI0C_AP_DATA_N<2> MIPI0C_DNDATA2 ISP1_SDA ISP_AP_1_SDA BI 7 26 39
TP436 TP443 TP447 R0900
B NC_MIPI0C_AP_DATA_P<3>
NC_MIPI0C_AP_DATA_N<3>
AW14
AY14
MIPI0C_DPDATA3
MIPI0C_DNDATA3
SENSOR0_CLK AA33
SENSOR0_RST Y26
CLK_CAM_RF_R 22 1 2 CLK_CAM_RF
PM_REAR_CAM_SHUTDOWN
OUT 27 39
B
AW12
U0652 R0940
OUT 25
TP446
MIPI0C_AP_CLK_P MIPI0C_DPCLK SENSOR1_CLK AA34 CLK_CAM_FF_R 22 1 2 CLK_CAM_FF
40 27 OUT
AY12 H4P-512MB OUT 26 39

MIPI0C_AP_CLK_N MIPI0C_DNCLK SENSOR1_RST Y33 PM_FRONT_CAM_SHUTDOWN


40 27 OUT BGA OUT 26

40 14 MIPID_AP_DATA_P<0> AW5 MIPI0D_DPDATA0 MIPI1C_DPDATA0 AW15 MIPI1C_AP_DATA_P<0> IN 26 40


OUT
MIPID_AP_DATA_N<0> AY5 MIPI0D_DNDATA0 MIPI1C_DNDATA0 AY15 MIPI1C_AP_DATA_N<0> IN
40 14 OUT 26 40

MIPID_AP_DATA_P<1> AW6 MIPI0D_DPDATA1 MIPI1C_DPDATA1 AW17 NC_MIPI1C_AP_DATA_P<1>


40 14 OUT
AY6 FRONT CAMERA
40 14 OUT MIPID_AP_DATA_N<1> MIPI0D_DNDATA1 MIPI1C_DNDATA1 AY17 NC_MIPI1C_AP_DATA_N<1>

40 14 MIPID_AP_DATA_P<2> AW8 MIPI0D_DPDATA2 MIPI1C_DPCLK AW16 MIPI1C_AP_CLK_P 26 40


OUT OUT
MIPID_AP_DATA_N<2> AY8 MIPI0D_DNDATA2 MIPI1C_DNCLK AY16 MIPI1C_AP_CLK_N
40 14 OUT OUT 26 40

MIPID_AP_DATA_P<3> AW9 MIPI0D_DPDATA3


40 14 OUT
MIPID_AP_DATA_N<3> AY9 MIPI0D_DNDATA3
40 14 OUT

MIPID_AP_CLK_P AW7 MIPI0D_DPCLK


40 14 OUT
40 14 MIPID_AP_CLK_N AY7 MIPI0D_DNCLK
OUT
MIPI_VSS

AN12
AP12
AR14
AR16
AR17
AR18
A SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE

AP: TV,DP,MIPI
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V2_S2R_H4 =PP1V2_S2R_H4
8 32 32 8

1 1
R1005 R1051
2.21K 2.21K
1% 1%
1/32W 1/32W
MF MF
2 01005 2 01005
TP57
TP448
=PP1V2_VDDIOD_H4 D4 AM16
PPVREF_DDR0_CA PPVREF_DDR1_CA
32
D6
U0652 AM18
8 39 8 39
H4P-512MB
1 NOSTUFF VOLTAGE=0.6V 1 NOSTUFF VOLTAGE=0.6V C1032 1 C1034 1 C1035 1
D8 BGA AM20
R1006 1 C1002 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
R1052 1 C1052 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
10UF 4.3UF 0.22UF D10 SYM 9 OF 12 AM22
2.21K 0.01UF 2.21K 0.01UF 20%

D 1%
1/32W
MF
10%
6.3V
2 X5R
NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM 1%
1/32W
MF
10%
6.3V
2 X5R
NET_SPACING_TYPE=VREF
MAX_NECK_LENGTH=3 MM 6.3V
X5R 2
603
20%
4V
X5R-CERM 2
0610
20%
6.3V
X5R 2
0201
D12
D14
SC58940X01-A030 AM24
AM26 D
2 01005 01005 2 01005 01005 E5 AM28
E7 AM29
E9 AM30
E11 AN1
E13 AN14
E15 AN16
F4 AN17
=PP1V2_VDDQ_H4 =PP1V2_VDDQ_H4
32 8 32 8 F6 AN18
1 1 F7 AN19
R1053 R1055 =PP1V2_S2R_H4
1.00K 1.00K
32 8
F8 AN20
1% 1% F9 AN24
1/32W
MF
1/32W
MF C1000 1 C1001 1
F10 AN25
2 01005 2 01005 0.22UF 0.22UF
TP45 20% 20% F11 AN26
TP65 6.3V 6.3V 2
X5R 2 X5R F12 AN27
PPVREF_DDR0_DQ PPVREF_DDR1_DQ
0201 0201
U0652 C1036 1 C1037 1 C1038 1 C1039 1 C1040 1 F13 AN28
8 39 8 39 0.22UF 0.22UF 0.22UF 0.22UF 56PF
BGA 20% 20% 20% 20% 5% F14 AN29
NOSTUFF VOLTAGE=0.6V NOSTUFF VOLTAGE=0.6V 6.3V
1
R1054 1 C1054 MIN_NECK_WIDTH=0.2MM 1
R1056 1 C1056 MIN_NECK_WIDTH=0.2MM H4P-512MB X5R 2
0201
6.3V
X5R 2
6.3V 2
X5R
6.3V 2
X5R
6.3V
NP0-C0G 2 F15 AP5
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM 0201
1.00K 0.01UF NET_SPACING_TYPE=VREF 1.00K 0.01UF NET_SPACING_TYPE=VREF H11
0201 0201 01005
1% 10% MAX_NECK_LENGTH=3 MM 1% 10% MAX_NECK_LENGTH=3 MM DDR0_VDDQ_CKE <1MA VSS_32 AB10 NOSTUFF
F16 AP6
1/32W 6.3V 1/32W 6.3V R8
MF 2 X5R MF 2 X5R DDR1_VDDQ_CKE <1MA VSS_33 AB12 F17 AP7
01005 01005
2 01005 2 01005 F18 AP8
PPVREF_DDR0_CA AY23 DDR0_VREF_CA VSS_34 AB14
39 8
SYM 7 OF 12 G5 AP9
TP437
PPVREF_DDR1_CA AE34 DDR1_VREF_CA VSS_35 AB16
39 8
SC58940X01-A030 G6 AP19
AA1 VDDIOD VSS
39 8 PPVREF_DDR1_DQ DDR1_VREF_DQ VSS_36 AB18 H4
500MA
AP21
R1001 39 8 PPVREF_DDR0_DQ A25 DDR0_VREF_DQ VSS_37 AB20 H6 (VDDQ = VDDIOD: DONT DOUBLE COUNT)
AP22
240 J5 AR1

C (DDR IMPEDANCE CONTROL)


1
1 2
2
1% 1/20W MF 201
1% 1/20W MF 201
DDR0_ZQ
DDR1_ZQ
AY18
AK34
DDR0_ZQ
DDR1_ZQ
VSS_38 AB22
VSS_39 AB24
J6
K4
AR5
AR6
C
240 TP449
AD33 AB29 K6 AR7
R1000 TP49 AH33 AC1 L5 AR8
AW20 AC5 L6 AR9
AW24 VDDCA VSS AC9 M4 AR13
AW29 80MA AC11 M6 AR19
W33 AC13 N5 AR24
=PP1V2_S2R_H4
32 8 N6 AR25
A24 AC15
C1004 1 C1005 1 C1006 1 C1007 1
AA2 AC17
P4 AR26
0.22UF 0.22UF 0.22UF 0.22UF P6 AR27
20% 20% 20% 20% AF33 AC19
6.3V 6.3V 6.3V 6.3V 2 R5 AR28
X5R 2 X5R 2 X5R 2 X5R AK33 AC21
0201 0201 0201 0201 R6 AR29
AL1 AC23
T4 AT5
AW22 AC25
T6 AT6
AW31 AC27
U5 AT7
C1008 1 C1009 1
C1010 1 C1011 1 C1012 1 C1013 1 B4 VDD2 VSS AD2
U6 AT8
10UF 4.3UF 1UF 1UF 0.01UF 56PF B5 320MA AD8
20% 20% 10% 10% 10% 5% V4 AT9
6.3V 4V 6.3V 6.3V 10V 6.3V B25 AD10
X5R 2 X5R-CERM 2 CERM 2 CERM 2 X5R 2 NP0-C0G 2 V6 AT10
603 0610 402 402 201 01005 F33 AD12
NOSTUFF W5 AT11
T34 AD14
W6 AT12
Y1 AD16
Y4 AT13
32
=PP1V8_S2R_H4 A4 AD18 Y6 AT15
A5 AD20
=PP1V8_VDDIO18_H4 AA28 AT16
C1014 1 C1015 1 C1016 1 C1017 1 C1018 1 AB2 AD22 32 9
AB7 AT17
10UF 1UF 1UF 0.01UF 0.01UF AL2 AD24
20% 10% 10% 10% 10% C1041 1 C1042 1 C1043 1 AB28 AT24
B 6.3V
X5R 2
603
6.3V
CERM 2
402
6.3V
CERM 2
402
6.3V
X5R 2
01005
6.3V
X5R 2
01005
AL33
AW18 VDD1 VSS
AD27
AD34
56PF
5%
6.3V
0.22UF
20%
6.3V
1UF
10%
6.3V
AC6
AC28
AT25
AT26
B
AW32 40MA AE5 NP0-C0G 2 X5R 2 CERM 2
01005 0201 402 AD28 AT27
B26 AE9 NOSTUFF AE6 AT28
E33 AE11
AF6 AT29
U33 AE13
AH6 AU4
AC2 AE15 AN6 AU5
AG2 AE17 AN7 VDDIO18 VSS AU6
C1019 1 C1020 1 C1021 1 C1022 1
AK2 AE19 AN8
44MA
AU7
0.22UF 0.22UF 0.22UF
20%
56PF
5%
C1044 1 C1045 1 C1046 1
20%
6.3V 2
20%
6.3V 2 6.3V 2 6.3V AN2 AE21 0.22UF 0.22UF 1UF H23 AU8
X5R X5R X5R NP0-C0G 2 AT2 AE23
20% 20% 10%
P28 AU9
0201 01005 6.3V 6.3V 6.3V
0201 0201 X5R 2 X5R 2 CERM 2
NOSTUFF AW3 AE25 0201 0201 402 R28 AU10
B3 AE33 T28 AU11
B6 AF1 W28 AU12
B8 AF5 Y28 AU13
B11 AF8
32 8
=PP1V2_VDDQ_H4
B14 AF10
B16 AF12
C1023 1 C1024 1 C1026 1
B19 AF14
10UF 4.3UF 0.01UF
20% 20% 10% B21 AF16
6.3V 4V 6.3V
X5R 2 X5R-CERM 2 X5R 2 B24 AF18
603 0610 01005
B27 VDDQ VSS AF20
B31 500MA AF22
D2 (VDDQ = VDDIOD: DONT DOUBLE COUNT) AF24
D33 AF26

A
G2 AF32
C1027 1
56PF
C1029
0.22UF
1 C1030
0.22UF
1 C1031
0.22UF
1 G33
K2
AG9
AG11
SYNC_MASTER=JAMES
PAGE TITLE
SYNC_DATE=N/A A
AP: PWR
5% 20% 20% 20%
6.3V 6.3V 2 6.3V 2 6.3V 2 K33 AG13
NP0-C0G 2 X5R X5R X5R
01005 0201 0201 0201 M2 AG15 DRAWING NUMBER SIZE
NOSTUFF N33 AG17
Apple Inc. 051-8962 D
TP48 R2 AG19 REVISION
R33 AG21 R
A.0.0
U2 AG23 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Y2 AG25 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

=PPVDD_SOC_H4
32

C1100 1 C1101 1 C1102 1 C1103 1

4.3UF 10UF 4.3UF 4.3UF AA20 =PPVDD_CPU_H4


20% 20% 20% 20% AL20 AA8 AH5
4V 6.3V 2
X5R
4V
X5R-CERM 2
4V
X5R-CERM 2 AA22 U0652 AL22
32
AA10 U0652 AH8
X5R-CERM 2
0610 603 0610 0610
AA24 H4P-512MB AL24 C1125 1 C1126 1 C1128 1 AA12 H4P-512MB AH10
BGA C1127 1
AB9
SYM 10 OF 12
AL26 10UF 4.3UF 4.3UF 4.3UF AA14 BGA AH12
20% 20% 20% 20% SYM 8 OF 12
AB11 AM9 6.3V 4V 4V AA16 AH14
SC58940X01-A030 X5R 2 X5R-CERM 2 4V
X5R-CERM 2 X5R-CERM 2
SC58940X01-A030
D
NOSTUFF NOSTUFF NOSTUFF NOSTUFF AB13
AB15
AM11
AM13
603 0610 0610 0610 AA18
N8
AH16
AH18 D
C1104 1 C1105 1 C1106 1 C1107 1
AB17 AM15 N10 AH20
56PF 56PF 56PF 56PF
5% 5% 5% 5% AB19 AM17 N12 AH22
6.3V 6.3V 6.3V 6.3V
NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 AB21 AM19 N14 AH24
01005 01005 01005 01005
AB23 AM21 N16 AH26
AB25 AM23
C1129 1
C1130 1 C1131 1 C1132 1 N18 AH28
56PF
AC8 AM25 5% 56PF 56PF 56PF P9 AH34
6.3V 5% 5% 5%
AC10 H9 NP0-C0G 2 6.3V 6.3V 6.3V P11 AJ1
01005 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2
AC12 H13 01005 01005 01005 P13 AJ2
C1108 1
C1109 1 C1110 1 C1111 1 AC14 H15 P15 AJ6
0.22UF 0.22UF 0.22UF 0.22UF AC16 H17 P17 AJ9
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V AC18 H19 R10 AJ11
X5R 2 X5R 2 X5R 2 X5R 2
0201 0201 0201 0201 AC20 H21
C1133 C1135 C1136 1 R12 AJ13
AC22 J8
1 C1134 1 1
0.22UF R14 AJ15
AC24 J10
0.22UF 0.22UF 0.22UF 20%
20% 20% 20% 6.3V R16 AJ17
6.3V 2 6.3V 2 6.3V 2 X5R 2
AD9 J12 X5R X5R X5R 0201 R18 AJ19
0201 0201 0201
C1112 1 C1113 1 C1114 1 C1115 1 C1116 1 AD11 J14 T9 AJ21
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF AD13 J16 T11 AJ23
20% 20% 20% 20% 20%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 AD15 J18 T13 AJ25
X5R X5R X5R X5R X5R
0201 0201 0201 0201 0201 AD17 J20 T15 AJ28
VDD_CPU VSS
AD19 J22 T17 AJ29
C1137 1 C1138 1 C1139 1 C1140 1 C1141 1 1900MA
AD21 J24 0.22UF U8 AJ30
AD23 K9
0.22UF 0.22UF 0.22UF 0.22UF 20% U10 AJ31
20% 20% 20% 20% 6.3V 2
6.3V 2 6.3V 2 6.3V 2 6.3V 2 X5R
AD25 K11 X5R X5R X5R X5R 0201 U12 AJ33
0201 0201 0201 0201
AE8 K13 U14 AJ34
AE10 K15 U16 AK1

C C1117 1
0.22UF
20%
C1118
0.22UF
20%
1 C1119
0.22UF
20%
1 C1120
0.22UF
20%
1
AE12
AE14
K17
K19
U18
V9
AK3
AK4
C
6.3V 2 6.3V 2 6.3V 2 6.3V 2
X5R X5R X5R X5R AE16 K21 V11 AK5
0201 0201 0201 0201
AE18 K23 V13 AK6
AE20 K25 V15 AK8
AE22 L8 V17 AK10
AE24 L10 W8 AK12
AF9 L12 W10 AK14
AF11 L14 W12 AK16
C1121 1
AF13 L16 W14 AK18
4.3UF
20% AF15 L18 W16 AK20
4V
X5R-CERM 2 AF17 L20 W18 AK22
0610
AF19 L22 Y9 AK24
AF21 L24 Y11 AK26
AF23 L26 Y13 AK28
AF25 M9 Y15 AK29
AG8 VDD VDD M11 Y17 AK30
AG10 M13 =PP3V0_IO_H4
2100MA G23 AK32
AG12 M15 32 9 7
G24 AL3
AG14 M17 C1142 1 C1143 1 VSS
U29 VDDIO30 AL4
AG16 M19 0.22UF 0.22UF 100MA
20% 20%
V29 AL5
AG18 M21 6.3V 6.3V
AG20 M23 X5R 2 X5R 2 AJ7 AL9
0201 0201
AG22 M25 AK7 VDDIOD0 GPIO[30-39] AL11
1.8V
AG24 N20 9MA VSS
AN9 VDDIOD1 UART4 AL13
AG26 N22 1.8V
=PP1V8_VDDIO18_H4 10MA

B AH9
AH11
N24
N26
32 8
NOSTUFF
AP24
AP25
AL15
AL17 B
AH13 P19 C1150 1 C1151 1 C1152 1
AP26 AL19
AH15 P21
0.22UF 0.22UF 56PF AP27 AL21
20% 20% 5%
6.3V 2 6.3V 2 6.3V
AH17 P23 X5R X5R NP0-C0G 2 AP28 VSS AL23
0201 0201 01005 VDDIOD2 FMI[0-2]
AH19 P25 AR21 3.3V AL25
24MA
AH21 P27 AR22 AL28
AH23 R20 AR23 AL29
AH25 R22 =PPIO_NAND_H4
10 6 AP29 FMI[0-1]_CEN[4-7] AL30
AJ8 R24 VDDIOD3 3.3V
AJ10 R26 C1144 1 C1145 1 C1146 1 C1147 1 C1148 1 C1149 1
AL27
24MA
AL34
AJ12 T19
0.22UF 0.22UF 56PF 1UF 1UF 10UF AM27 FMI[3] AM7
20% 20% 5% 10% 10% 20% VDDIOD4 3.3V
6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 2 24MA
AJ14 T21 X5R X5R NP0-C0G 2 CERM CERM 2 X5R
0201 0201 01005 402 402 603 AJ27 FMI[2-3]_CEN[4-7] VSS AM8
AJ16 T23 SPI3,ISP FLASH
NOSTUFF AK27 VDDIOD5 NOT USED AM10
AJ18 T25 24MA
AJ20 T27 AH27 VDDIOD6 SPI1 AM12
1MA
AJ22 U20 =PP3V0_IO_H4 AG27 3.0V AM14
32 9 7 VDDIOD7 1MA I2C2
AJ24 U22
AJ26 U24 C1180 1 C1181 1 C1182 1
C1160 1 C1161 1

AK9 U26 1UF 1UF 1UF 0.22UF 0.22UF


10% 10% 10% 20% 20%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
AK11 V19 CERM CERM CERM X5R 2
402 402 402 X5R
AK13 V21 0201 0201

AK15 V23
AK17 V25
AK19 V27
AK21 W20

A AK23
AK25
W22
W24 SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE
AL8
AL10
W26
Y19 AP: PWR
AL12 Y21 DRAWING NUMBER SIZE

AL14 Y23 Apple Inc. 051-8962 D


AL16 Y25 REVISION

AL18
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BOOT CONFIG ID
=PP1V8_H4
32 13 10 7 5 4

FMI_TEST FMI_NOTEST
JTAG
1
R1200 1
R1201 1
R1202 1
R1203 DEVELOPMENT_JTAG_TAP
5%
10K
5%
10K
5%
10K
5%
10K R1212
1/20W 1/20W 1/20W 1/32W JTAG_DAP 0.00 2
TP41 MF MF MF MF 39 4 IN JTAG_AP_TDO 1 VIDEO_EMI_C_Y OUT 11 28 40
2 201 2 201 2 201 2 01005
BOOT_CONFIG[3] (GPIO29) 5 BOOT_CONFIG_3 R1210 0%
1/32W
100 TP75 MF
1 2 AP_JTAG_SEL OUT 01005
BOOT_CONFIG[2] (GPIO28) 5 BOOT_CONFIG_2 4

DEVELOPMENT_JTAG_TAP

D BOOT_CONFIG[1] (GPIO25) 5 BOOT_CONFIG_1 R1213


0.00 2
D
BOOT_CONFIG[0] (GPIO18) 5 BOOT_CONFIG_0 JTAG_DAP 39 4 OUT JTAG_AP_TDI 1 VIDEO_EMI_Y_PR IN 11 28 40

R1211 0%
1/32W
TP39 TP43 TP44 100 MF
1 2 JTAG_AP_TRST_L OUT 4 10 39 01005
BOOT_CONFIG[3-0] S/W READ FLOW DEVELOPMENT_JTAG_TAP
TP71
R1214
1. SET GPIO AS INPUT 0.00 2
1101 FMI0/1 4/4 CS 39 10 4 OUT JTAG_AP_TRST_L 1 VIDEO_EMI_CVBS_PB IN 11 28 40
2. DISABLE PU AND ENABLE PD
1110 FMI0/1 4/4 CS WITH TEST 0%
3. READ 1/32W
MF
01005

2-WIRE DAP SCAN DUMP PRODUCTION


BOARD ID
32 13 10 7 5 4 =PP1V8_H4 DEVELOPMENT_JTAG DEVELOPMENT_JTAG JTAG_DAP
K93-K94 K94-K95 K9X_DEV JTAG_DAP DEVELOPMENT_JTAG_TAP
1
R1204 1 R1205 1 R1206
10K 10K 10K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF
BOARD_ID[3] BOARD_ID_3 2 01005 2 01005 2 01005
BOARD_ID[2] 5 BOARD_ID_2_SPI_FLASH_DOUT TP51

BOARD_ID[1] 5 BOARD_ID_1_SPI_FLASH_DIN TP50

BOARD_ID[0] 5 BOARD_ID_0_SPI_FLASH_CLK TP52

PLACEMENT NOTE: NEAR U0652 C


C BOARD_ID[3-0]

0100 K93 AP
S/W READ FLOW
7
PP_AP_DP_AVDD_AUX PP_DP_PAD_AVDD0 7
MAKE_BASE=TRUE
1. SET GPIO AS INPUT PP_DP_PAD_AVDD1
0101 K93 DEV DP_AP_TX_P<0> OUT 7 13 40 7
2. DISABLE PU AND ENABLE PD
0110 K94 AP DP_AP_TX_N<0> OUT 7 13 40
3. READ
0111 K94 DEV
DP_AP_TX_P<1> OUT 7 13 40
0010 K95 AP
DP_AP_TX_N<1> OUT 7 13 40
0011 K95 DEV =PPIO_NAND_H4 =PP3V3_NAND_H4
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 9 6 32
NOSTUFF NOSTUFF NOSTUFF NOSTUFF

BOARD REVISION
1
R1250 1
R1251 1
R1252 1
R1253
TP36 TP37 150 150 150 150 R1260 TP433
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 100
5 AP_GPIO42_BRD_REV2 MF MF MF MF 1 2 AP_TESTMODE 4
5 AP_GPIO41_BRD_REV1 2 201 2 201 2 201 2 201 5%
1/32W
5 AP_GPIO40_BRD_REV0 MF
DP_TERM_C1250 DP_TERM_C1251 01005 TP432
NOSTUFF SIGNAL_MODEL=EMPTY NOSTUFF SHORT-01005
SIGNAL_MODEL=EMPTY
1
R1207 R1208 R1209
1 1 NOSTUFF NOSTUFF XW0601 1 2 AP_TST_STPCLK 4

10K 10K 10K 1 C1250 1 C1251


5%
1/20W
5%
1/20W
5%
1/20W
100PF 100PF NOSTUFF SHORT-01005
5%
MF MF MF 25V
5%
25V XW0602 1 2 AP_FAST_SCAN_CLK 4
2 201 2 201 2 201 2 CERM
201
2 CERM NOSTUFF SHORT-01005
201 XW0603 1 2 AP_HOLD_RESET 4

BRD_REV[2-0] S/W READ FLOW


UART_0_RXD UART_AP_0_RXD IN
B 000
001
PROTO 1
PROTO 2
1.
2.
SET GPIO AS INPUT
ENABLE PU AND DISABLE PD
5

5 UART_0_TXD
MAKE_BASE=TRUE

MAKE_BASE=TRUE
UART_AP_0_TXD OUT
11

11 TO DOCK MUX B
3. READ
010 EVT 5 UART_1_CTS_L UART_AP_1_CTS_L IN 31
MAKE_BASE=TRUE
011 EVT2 5 UART_1_RTS_L UART_AP_1_RTS_L OUT 31

100 DVT 5 UART_1_RXD


MAKE_BASE=TRUE
UART_AP_1_RXD IN 31
TO BB USART
MAKE_BASE=TRUE
5 UART_1_TXD UART_AP_1_TXD OUT 31
MAKE_BASE=TRUE

UART_2_RXD UART_AP_2_RXD IN
FOR REFERENCE 5

5 UART_2_TXD
MAKE_BASE=TRUE
UART_AP_2_TXD OUT
31

31
TO BB UMTS
MAKE_BASE=TRUE
BOOT_CONFIG[3:0]
5 UART_3_CTS_L UART_AP_3_CTS_L IN 30
0000 SPI0 MAKE_BASE=TRUE
0001 SPI3 5 UART_3_RTS_L UART_AP_3_RTS_L OUT 30
TO BT UART
0010 SPI0 W/TEST 5 UART_3_RXD
MAKE_BASE=TRUE
UART_AP_3_RXD IN 30
0011 SPI3 W/TEST MAKE_BASE=TRUE
5 UART_3_TXD UART_AP_3_TXD OUT 30
0100 FMI0 2CS MAKE_BASE=TRUE
0101 FMI0 4CS
5 UART_4_CTS_L UART_AP_4_CTS_L IN 31
0110 FMI0 4CS W/TEST MAKE_BASE=TRUE
0111 RESERVED 5 UART_4_RTS_L UART_AP_4_RTS_L OUT 31
1000 FMI1 2 CS 5 UART_4_RXD
MAKE_BASE=TRUE
UART_AP_4_RXD IN 31
TO GPS UART
1001 FMI1 4 CS MAKE_BASE=TRUE

1010 FMI1 4CS W/TEST 5 UART_4_TXD UART_AP_4_TXD OUT 31


MAKE_BASE=TRUE

1011 RESERVED
1100 FMI0/1 2/2 CS
CURRENT SETTING -> 1101 FMI0/1 4/4 CS
23 CHS_SCL I2C0_SCL_1V8 IN 5 19 35 39
1110 FMI0/1 4/4 CS W/TEST MAKE_BASE=TRUE
23 CHS_SDA I2C0_SDA_1V8 OUT 5 19 35 39
1111 RESERVED MAKE_BASE=TRUE

A SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE

AP: MISC & ALIASES


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 10 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
NOTE:
LDO3 PROVIDES 50MA TO BOTH H4P AND U1300
IF THATS NOT ENOUGH, STUFF R1371 AND NOSTUFF R1370

R1371
=PP3V0_VIDEO_BUF 1
0.00 2 =PP3V2_S2R_USBMUX
32 VOLTAGE=3.0V 32
MIN_LINE_WIDTH=0.2MM
0% MIN_NECK_WIDTH=0.1MM
1/32W NET_SPACING_TYPE=PWR
MF MAX_NECK_LENGTH=3 MM
TP73 01005
NOSTUFF TP412
C1301 1 C1300 1

R1370 ~15MA 56PF 0.1UF


5% 10%
=PP3V0_VIDEO_BUFFER 0.00 2 PP3V0_U0900_FILTR 6.3V 6.3V
32 1 NP0-C0G 2 X5R 2
01005 201
0%
1/32W
MF
01005 1 C1370
0.1UF
10%
2 6.3V
X5R
201

TP414

VA_0 C1
VA_1 C4

VDL D2

VDH E2
PORT_DOCK_VIDEO_AMP_EN IN 5 NOTE: PLACE R0960-62 NEAR U0900
JTAG_DAP
R1372 1 R1360
75
C U1300
THS7380IZSYR
100K
5%
1/32W
1
1%
2 VIDEO_EMI_Y_PR OUT 10 28 40
C
MF 1/20W
UCSP 01005 2 MF
201
VID_EN C3
JTAG_DAP
YIN 40 7 IN DAC_AP_OUT3 A3 CH.1_IN CH.1_OUT A2 40 BUF_Y_PR R1361
A4 75
CVBSIN 40 7 IN DAC_AP_OUT2 CH.2_IN CH.2_OUT A1 40 BUF_CVBS_PB 1 2 VIDEO_EMI_CVBS_PB OUT 10 28 40

DAC_AP_OUT1 B4 CH.3_IN CH.3_OUT B1 40 BUF_C_Y 1%


CIN 40 7 IN 1/20W
MF
TP415 201
UART_AP_0_TXD D4 TX_VLOW RX_VHIGH/USB_2D+ E1 USB_FS_P_ACC_RX
10 IN OUT 28 39
JTAG_DAP
UART_AP_0_RXD E4 RX_VLOW TX_VHIGH/USB_2D- D1 USB_FS_N_ACC_TX
10 OUT IN 28 39
R1362
TP416
F3 75
39 31 BI USB_BB_D_P USB_D+ USB_1D+ F2 USB_FS_D_P BI 4 39 1 2 VIDEO_EMI_C_Y OUT 10 28 40

USB_BB_D_N F4 USB_D- USB_1D- F1 USB_FS_D_N 1%


39 31 BI BI 4 39
1/20W
MF TP74
SEL C2 DOCK_BB_EN 201
IN 35 1
R1315
1.00M
5%
TP411 1/32W
AGND DGND MF
2 01005
1
R1320

B2
B3

D3
E3
100K
5%
1/32W
MF
2 01005
NOTE:
DOCK_BB_EN = 1: BB USB <-> DOCK SERIAL
DOCK_BB_EN = 0: BB USB <-> H4P FS USB
H4P UART0 <-> DOCK SERIAL

B B

A SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE

AP: VIDEO BUFFER,BB USB MUXES


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 11 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16GB FLASH CONFIGURATIONS TABLE_5_HEAD
64GB FLASH CONFIGURATIONS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM

335S0701 1 TOSHIBA 32NM 16GB RAW U1400 16GB_PROD 335S0702 2 TOSHIBA 32NM 32GB RAW U1400,U1410 64GB_PROD

TABLE_ALT_HEAD TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER PART NUMBER
TABLE_ALT_ITEM TABLE_ALT_ITEM

335S0682 335S0701 16GB_PROD U1400 SAMSUNG 35NM 16GB RAW 335S0665 335S0702 64GB_PROD U1400,U1410 SAMSUNG 35NM 32GB RAW
TABLE_ALT_ITEM TABLE_ALT_ITEM

335S0790 335S0701 16GB_PROD U1400 SAMSUNG 27NM 16GB RAW 335S0791 335S0702 64GB_PROD U1400,U1410 SAMSUNG 27NM 32GB RAW

D
TABLE_ALT_ITEM TABLE_ALT_ITEM

D 335S0781 335S0701 16GB_PROD U1400 HYNIX 26NM 16GB PPN 335S0722

335S0782
335S0702

335S0702
64GB_PROD

64GB_PROD
U1400,U1410 SANDISK 32NM 32GB RAW

HYNIX 26NM 32GB PPN


TABLE_ALT_ITEM

32GB FLASH CONFIGURATIONS


U1400,U1410

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION


TABLE_5_HEAD

TABLE_5_ITEM
128GB FLASH CONFIGURATIONS
335S0701 2 TOSHIBA 32NM 16GB RAW U1400,U1410 32GB_PROD

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_ALT_ITEM

335S0682 335S0701 32GB_PROD U1400,U1410 SAMSUNG 35NM 16GB RAW


TABLE_ALT_ITEM

335S0790 335S0701 32GB_PROD U1400,U1410 SAMSUNG 27NM 16GB RAW


TABLE_ALT_ITEM

335S0781 335S0701 32GB_PROD U1400,U1410 HYNIX 26NM 16GB PPN

=PP3V3_NAND
12 32

=PP3V3_NAND 12 32

1 C1403 1 C1400 1 C1401 1 C1402


82PF 0.1UF 0.1UF 2.2UF
5% 10%
6.3V
10%
6.3V
20%
6.3V
1 C1410 1 C1411 1 C1412
25V
2 CERM 2 X5R 2 X5R 2 CERM 1 C1413 0.1UF 0.1UF 2.2UF
0201 201 201 402-LF 82PF 10%
6.3V
10%
6.3V
20%
6.3V
5% 2 X5R 2 X5R 2 CERM
25V
2 CERM
C C
201 201 402-LF
0201

OMIT

B6
M6
N1
N7
OMIT

B6
M6
N1
N7
VCC

VCCQ

VCC

VCCQ
TP528
39 12 6 BI F0AD<0> G3 IO0_0
TP527
39 12 6 BI F1AD<0> G1 IO0_1 TP552 TP482
ALE0 C1 F0ALE IN 6 12 39 39 12 6 BI F0AD<0> G3 IO0_0
TP526
39 12 6 BI F0AD<1> H2 IO1_0
ALE1 D2 F1ALE IN 6 12 39
TP537 TP483
39 12 6 BI F1AD<0> G1 IO0_1
F1AD<1> J1 C1 F0ALE TP495

TP524
39 12 6

39 12 6
BI
BI F0AD<2> J3
IO1_1
IO2_0
U1400 CE0* A5 F0CE0_L IN 6 39
TP548
TP478
39 12 6 BI F0AD<1> H2 IO1_0
ALE0
ALE1 D2 F1ALE
IN
IN
6 12 39

6 12 39
TP488
LGA TP477
F1AD<1> J1
TP518
39 12 6 BI F1AD<2> L1 IO2_1 CE1* C5 F1CE0_L IN 6 39
TP539
TP476
39 12 6 BI
F0AD<2> J3
IO1_1
IO2_0
U1410 CE0* A5 F0CE2_L TP493
NAND-XXNM-64GX8
VLGA5-N90

39 12 6 BI IN 6 39
TP520
39 12 6 BI F0AD<3> K2 IO3_0 CE2* A1 F0CE1_L IN 6 39
TP553
TP460
F1AD<2> L1
LGA C5 F1CE2_L TP492
39 12 6 BI IO2_1 CE1* IN 6 39
TP513
F1AD<3> N3 IO3_1 CE3* OA0 F1CE1_L

NAND-XXNM-64GX8
VLGA5-N90
39 12 6 BI IN 6 39
TP529
TP472
39 12 6 BI F0AD<3> K2 IO3_0 CE2* A1 F0CE3_L IN 6 39
TP498
TP516
39 12 6 BI F0AD<4> L5 IO4_0 CE4* G5 F0CE4_L IN 6 39 TP461
39 12 6 BI F1AD<3> N3 IO3_1 CE3* OA0 F1CE3_L IN 6 39
TP502
TP512
39 12 6 BI F1AD<4> N5 IO4_1 CE5* F2 F1CE4_L IN 6 39
TP534
TP470
39 12 6 BI F0AD<4> L5 IO4_0 CE4* G5 F0CE6_L IN 6 39
TP481
TP521
39 12 6 BI F0AD<5> K6 IO5_0 CE6* OB0 F0CE5_L IN 6 39
TP555
TP462
39 12 6 BI F1AD<4> N5 IO4_1 CE5* F2 F1CE6_L IN 6 39
TP484
TP515
39 12 6 BI F1AD<5> L7 IO5_1 CE7* OE0 F1CE5_L IN 6 39
TP519
TP473
39 12 6 BI F0AD<5> K6 IO5_0 CE6* OB0 F0CE7_L IN 6 39
TP499
TP523
39 12 6 BI F0AD<6> J5 IO6_0 TP550 TP469
CLE0 A3 F0CLE IN 6 12 39 39 12 6 BI F1AD<5> L7 IO5_1 CE7* OE0 F1CE7_L IN 6 39
TP459
TP522
39 12 6 BI F1AD<6> J7 IO6_1
CLE1 C3 F1CLE IN 6 12 39
TP538 TP475
39 12 6 BI F0AD<6> J5 IO6_0
TP525
39 12 6 BI F0AD<7> H6 IO7_0 CLE0 A3 F0CLE IN 6 12 39
TP497
TP474
39 12 6 BI F1AD<6> J7 IO6_1
TP530
39 12 6 BI F1AD<7> G7 IO7_1 RE0* C7 F0RE_L IN 6 12 39
TP541
CLE1 C3 F1CLE IN 6 12 39
TP494
TP479
39 12 6 BI F0AD<7> H6 IO7_0
RE1* D6 F1RE_L IN 6 12 39
TP540
TP480
39 12 6 BI F1AD<7> G7 IO7_1 RE0* C7 F0RE_L IN 6 12 39
TP491

R1400 A7 R/B0* E5 TP547


RE1* D6 F1RE_L TP489
100K INC
IN 6 12 39

1 2 NAND0_RB OA8 E7 NAND0_RB


B
R/B1* R1401
B
12 12
A7 R/B0* E5
1% NAND0_VDDL OB8 INC_VDDI
E3 TP536 100K 2 OA8 INC E7
1/20W WE0* F0WE_L IN 6 12 39 1 12 NAND1_RB R/B1* NAND1_RB 12
MF
201 OC0 WE1* E1 F1WE_L IN 6 12 39
TP535
1% NAND1_VDDL OB8 INC_VDDI
WE0* E3
TP542 TP486
1/20W F0WE_L IN 6 12 39
OC8 MF
201 OC0 WE1* E1 F1WE_L TP487
1 C1404 OD0 TP490
OC8
IN 6 12 39

1UF OD8 R
10% 1 C1414 OD0
6.3V OF0
2 X5R 1UF OD8 R
402 OF8 10%
6.3V OF0
2 X5R
VSSQ

402 OF8
VSS

TP584 TP601

VSSQ
VSS
TP506
B2
F6
L3

M2
OE8

B2
F6
L3

M2
OE8
TP510 TP558

TP507 TP496
TP517 TP533 TP551

TP508 TP471 TP485

A SYNC_MASTER=JONATHAN SYNC_DATE=N/A A
PAGE TITLE

NAND
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
14 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
DISPLAYPORT AC COUPLING
40 10 7 IN DP_AP_TX_P<0> C1702 1 2 DP_EMI_TX_P<0> OUT 28 40
=PP3V0_IO_MISC
10% 6.3V X5R 201 32 13
0.1UF
40 10 7 IN DP_AP_TX_N<0> C1703 1 2 DP_EMI_TX_N<0> OUT 28 40
10% 6.3V X5R 201
0.1UF
40 10 7 IN DP_AP_TX_P<1> C1704 1 2 DP_EMI_TX_P<1> OUT 28 40
1
R1720
10% 6.3V X5R 201
0.1UF 100K
1%
40 10 7 IN DP_AP_TX_N<1> C1705 1 2 DP_EMI_TX_N<1> OUT 28 40 1/32W
10% 6.3V X5R 201 MF
0.1UF
2 01005

40 28 13 DP_EMI_AUX_N

40 28 13 DP_EMI_AUX_P

1
R1723
100K
1%
40 7 BI DP_AP_AUX_P C1706 1 2 DP_EMI_AUX_P BI 13 28 40 1/32W
10% 6.3V X5R 201 MF
0.1UF
2 01005
40 7 BI DP_AP_AUX_N C1707 1 2 DP_EMI_AUX_N BI 13 28 40
10% 6.3V X5R 201
0.1UF

C C

DISPLAYPORT HOT PLUG DETECT

32 13 =PP3V0_IO_MISC

1
R1731
32 10 7 5 4 =PP1V8_H4 220K
B 1 C1750
0.1UF CRITICAL
5%
1/32W
MF
2 01005
B

6
10%
R1750 6.3V
2 X5R
VCC
0.00 201 U1701
0%
1/32W 74LVC1G07
MF SOT886
01005
35 28 IN FW_ZENER_PWR 1 2 DP_BUF_HPD 2 A Y 4 DP_AP_HPD OUT 7

NOSTUFF 1 NC NC 5
TP361
1
R1751 TP55
GND
10K TP56

3
5%
1/32W
MF
2 01005

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_ALT_ITEM

311S0536 311S0341 U1701 RADAR:8481319

A SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE

VIDEO: DISPLAY PORT


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 13 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MLC EEPROM:RAW APN 335S0661


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

=PP3V3_MLC
341S2799 1 MLC EEPROM 100MHZ LVDS,2MHZ SWI U2001 CRITICAL 100MHZ_PANEL
32 16 14

1 C2017
0.1UF 8 OMIT
20%
2 10V
CERM VCC
1 402
R2006 U2001 R2050 1 R2051 1
10K M24C64
EEPROM
4.7K 4.7K
1% 5% 5%
1/20W 3 E2 MLP 1/20W 1/20W
WHEN WC_L IS LOW, CAN WRITE TO EEPROM MF MF MF
2 E1
D WHEN WC_L IS HIGH, CANNOT WRITE TO EEPROM
201 2
1
7
E0
201 2 201 2
D
MLC_2WC_L WC*
6 SCL SDA 5 MLC_MUX_SDA_3V3 15
BI
VSS THM_P MLC_MUX_SCL_3V3 IN 15

4 9
TP380 TP381

FL2000 TP398
80-OHM-0.2A-0.4-OHM
32 16 14 =PP3V3_MLC 1 2 PP3V3_MLC_LVDS
0201-1 VOLTAGE=3.3V TABLE_ALT_HEAD

MIN_LINE_WIDTH=0.4 MM PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
C2016 FL2001 PART NUMBER
C
MIN_NECK_WIDTH=0.2 MM

C
1 MAX_NECK_LENGTH=3 MM
82PF 80-OHM-0.2A-0.4-OHM
TP386
NET_SPACING_TYPE=PWR TABLE_ALT_ITEM

5% 138S0652 138S0618 RADAR:8377307


25V C2000,C2001,C2002,C2003,C2010,C2011,C2012,C3609,C3611,C3616

2 CERM 1 2 PP3V3_MLC_18LDO_12LDO
0201 VOLTAGE=3.3V
0201-1 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
FL2002 TP385
NET_SPACING_TYPE=PWR

80-OHM-0.2A-0.4-OHM
1 2 PP3V3_MLC_DIG_12LDO
VOLTAGE=3.3V
0201-1 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
NOSTUFF
PP2000
P4MM
SM
C2010 1 1 C2013 C2011 1 1 C2014 C2012 1 1 C2015
PP
1 MIPID_AP_CLK_P 7 14 40
4.7UF 0.1UF 4.7UF 0.1UF 4.7UF 0.1UF
20% 20% 20% 20% 20% 20%
6.3V 10V 6.3V 10V 6.3V 10V
X5R-CERM 2 2 CERM X5R-CERM 2 2 CERM X5R-CERM 2 2 CERM

VDD33A_OSC H4

VDD33A_18LDO A2

VDD33A_12LDO_0 F3
VDD33A_12LDO_1 H8
VDD33A_12LDO_2 B4

VDD33P_LVDS D5

VDD33A_LVDS C6

VDD33D_LVDS E5
402 402 402 402 402 402

VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM TP384
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR C3
NOSTUFF CAP_18LDO MLC_CAP_1V8LDO
VOLTAGE=1.2V
PP2009 MLC_VREG_0V4 B3 M_VREG_0P4V CAP_12LDO_0 E3 MLC_CAP_1V2LDO_0 MIN_LINE_WIDTH=0.4 MM
P4MM H7 VOLTAGE=1.2V MIN_NECK_WIDTH=0.2 MM
SM CAP_12LDO_1 MLC_CAP_1V2LDO_1_3 MIN_LINE_WIDTH=0.4 MM MAX_NECK_LENGTH=3 MM
1 MIPID_AP_DATA_N<3> 7 14 40 VOLTAGE=1.2V MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR
PP
CAP_12LDO_3 A7 MIN_LINE_WIDTH=0.4 MM MAX_NECK_LENGTH=3 MM
1 C2004 U2000 CAP_12LDO_5 A4 MLC_CAP_1V2_LDO_5
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
2.2NF VOLTAGE=1.2V NET_SPACING_TYPE=PWR
10%
NC_MIPI_MLC_MASTER_CLK_P C1 M_DPCLK FBGA1 A6 MLC_SCL_3V3
MIN_LINE_WIDTH=0.4 MM

B B
10V MLC_SCL OUT 15 MIN_NECK_WIDTH=0.2 MM
2 X5R
NC_MIPI_MLC_MASTER_CLK_N C2 M_DNCLK S6T2MLC A5 MLC_SDA_3V3
MAX_NECK_LENGTH=3 MM
201 MLC_SDA BI 15 NET_SPACING_TYPE=PWR
NOSTUFF NC_MIPI_MLC_MASTER_DATA_P B1 M_DPDATA0 A8 LVDS_DDC_CLK
EDID_SCL
PP2011 NC_MIPI_MLC_MASTER_DATA_N B2 M_DNDATA0 B6 LVDS_DDC_DATA
OUT 16
C2000 1 C2001 1 C2002 1 C2003 1
P4MM EDID_SDA OUT 16
SM
1
4.7UF 4.7UF 4.7UF 4.7UF
MIPID_AP_DATA_P<0> 7 14 40 20% 20% 20% 20%
PP MIPID_AP_CLK_P F1 S_DPCLK 6.3V 6.3V 6.3V 6.3V
40 14 7 IN C8 LVDS_CLK_P
TP393 F2 S_DNCLK TCLKP OUT 16 40 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2
40 7 IN MIPID_AP_CLK_N 402 402 402 402
TCLKN C7 LVDS_CLK_N OUT 16 40

MIPID_AP_DATA_P<0> D1 S_DPDATA0
40 14 7 IN G8 LVDS_DATA_P<0>
D2 S_DNDATA0 TAP OUT 16 40
40 7 IN MIPID_AP_DATA_N<0>
TAN G7 LVDS_DATA_N<0> 16 40
TP392 OUT
=PP3V3_MLC MIPID_AP_DATA_P<1> E1 S_DPDATA1
32 16 14 40 7 IN F8 LVDS_DATA_P<1>
E2 S_DNDATA1 TBP OUT 16 40
40 7 IN MIPID_AP_DATA_N<1>
NOSTUFF TBN F7 LVDS_DATA_N<1> OUT 16 40
G1 S_DPDATA2
R2052 1 R2008 1 40 7 IN MIPID_AP_DATA_P<2>
TCP E8 LVDS_DATA_P<2> OUT 16 40
100K 100K 40 7 IN MIPID_AP_DATA_N<2> G2 S_DNDATA2
E7
1% 1% TCN LVDS_DATA_N<2> OUT 16 40
1/20W 1/20W H1 S_DPDATA3
MF MF 40 7 IN MIPID_AP_DATA_P<3>
201 2 201 2 TDP D8 NC_LVDS_DATA_P<3>
TP391 MIPID_AP_DATA_N<3> H2 S_DNDATA3
40 14 7 IN D7 NC_LVDS_DATA_N<3> TP382
TDN
MLC_BIST B7 BIST
ROUT_LVDS C5 ROUT_LVDS
MLC_TEST B8 TEST
F5 1
6 IN RST_MLC_L B5 RESET* VSYNC TP_MLC_VSYNC TP395 TP396 R2001
PWM D4 TP_PM_LCD_BKLT_PWM 8.45K
H6 SWI G6 1%
SWI_MLC PPC PM_MLC_PPC_OUT OUT 16 1/20W
MF
MLC_MONITOR0_PD H5 MONITOR0 2 201
MONITOR4 F4 NC_MLC_MONITOR4
NC_MLC_MONITOR1 G3 MONITOR1
E4
R2002 1 1
R2003 NC_MLC_MONITOR2 G4 MONITOR2 MONITOR5 NC_MLC_MONITOR5
100K 100K R2010 1 MONITOR6 D3 NC_MLC_MONITOR6
A
G5 MONITOR3
A
1% 1% NC_MLC_MONITOR3
1/20W 1/20W 100K
SYNC_MASTER=MIKE SYNC_DATE=N/A
H3 VSS33A_12LDO_0
C4 VSS33A_12LDO_1

MF MF 1%
201 2 2 201 1/20W PAGE TITLE
A1 VSS33A_18LDO

MF
VIDEO: MLC
E6 VSS33P_LVDS

D6 VSS33A_LVDS

F6 VSS33D_LVDS

201 2
A3 VSS12D_PLL

DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C
14 MLC_SDA_3V3 MLC_MUX_SDA_3V3 14

14 MLC_SCL_3V3 MLC_MUX_SCL_3V3 14

B B

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

VIDEO: MLC ALIASES


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

LVDS(LCD)CONNECTOR
D
CRITICAL
Q2200 VOLTAGE=3.3V
L2201
D
SIA413DJ TP309
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM FERR-120-OHM-1.5A
TP97 C2206
SC70-6L 1000PF
PP3V3_S0_LCD_FERR 1 2 1 2
CABLINE-CA CONNECTOR: 518S0787

7
32 =PP3V3_LCD 0402

D
4

1
10%
16V

1 C2240 1 C2241
1
NOSTUFF
R2210 1 1 C2203 1 C2202
1 C2230 X7R
201 NOTE: CONNECTOR ON PANEL IS FLIPPED
10K R2203 0.1UF 10UF 82PF
82PF 82PF

G
1% 39K 10% 20% 5% CRITICAL
=PP3V3_MLC
5%
25V
2 CERM
5%
25V
2 CERM
1/20W
MF
1%
1/20W 2 6.3V
X5R 2 6.3V
X5R
2 25V
CERM J2201

3
32 16 14 0201
0201 0201 2 201 MF 201 603 CABLINE-CA
NOSTUFF R2204 2 201
R2250 C2204 F-RT-SM
32
R2211 1 0.015UF
21.5K2 0
10K LCDVDD_PWREN_L 1 1 2 LCDVDD_PWREN_L_R 1 2
1%
1/20W 1%
R2250_1
5%
TP297
C2231 41
MF 1/20W
MF
1/20W
MF
10%
6.3V 82PF 1 C2232 40
201 2
D 3 201 201 TP95 X5R 1 2 82PF
0201 5% 39
25V
Q2201 5%
25V
2 CERM
0201
38
14 IN PM_MLC_PPC_OUT 1
G
2N7002TXG CERM 37
SOT-523-3 0201
1
R2205 S 2
C2200
36
TP94 100K 1000PF 35
1%
1/20W
MF 32 16 14 =PP3V3_MLC 1 2 34

2 201 33
10%
16V
X7R
201 VOLTAGE=3.3V 30
1
1
R2201 R2200 MIN_LINE_WIDTH=0.30 MM 29
10K MIN_NECK_WIDTH=0.20 MM PP3V3_LCDVDD_SW_F
10K 5% 28
5% 1/20W
TP293 1/20W MF (LVDS DDC POWER) 27
MF 2 201
C 14 IN
LVDS_DDC_CLK
2 201 35 OUT BOARD_TEMP4 26
25 C
24
40 LVDS_DATA_CONN_N<0> 23

14 IN LVDS_DDC_DATA 40 LVDS_DATA_CONN_P<0> 22

SIA413DJ LVDS_DATA_CONN_N<1>
21
20
TP296 TP295 L2212 40

40 LVDS_DATA_CONN_P<1> 19
MOSFET SIA413DJ 90-OHM-50MA
TCM0605 18
40 14 LVDS_DATA_N<0> 2 3
IN
CHANNEL P-TYPE 40 LVDS_DATA_CONN_N<2> 17
40 LVDS_DATA_CONN_P<2> 16
RDS(ON) 100MOHM @-1.5V 40 14 IN LVDS_DATA_P<0> 1 4 15
SYM_VER-2

IMAX 3 A 40 LVDS_CLK_CONN_N 14
TP311 40 LVDS_CLK_CONN_P 13
VGS MAX +/- 8V 12
TP310 L2222 L2200 NC_LCD_PGAMMA 11
90-OHM-50MA
LVDS_DATA_N<1> 2 TCM0605 3 FERR-240-OHM-25%-300MA 10
40 14 IN
32 =PPLED_REG 1 2 PPLED_BACK_REG 9
0402 8
LVDS_DATA_P<1> 1 4 NC 7
40 14 IN 35 IN LED_IO_6
SYM_VER-2
TP93 6
35 IN LED_IO_5
TP313 TP326 5
35 IN LED_IO_4
TP328 4
LED_IO_3
TABLE_ALT_HEAD
TP315 L2232 TP91
35 IN
LED_IO_2 3
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 90-OHM-50MA 35 IN
PART NUMBER 2 TCM0605 3 TP92 2
TABLE_ALT_ITEM
40 14 IN LVDS_DATA_N<2> 35 IN LED_IO_1
376S0961 376S0796 Q2200 RADAR:8403895
TP329
35 BOARD_TEMP4_N 1

B
VOLTAGE=20.4V
B
TABLE_ALT_ITEM

376S0903 376S0796 Q2200 RADAR:8403865 LVDS_DATA_P<2> 1 4 MIN_LINE_WIDTH=0.6 MM


40 14 IN 31
SYM_VER-2 MIN_NECK_WIDTH=0.2 MM
L2202,L2212,L2222,L2232,L5500,L5501,L5600,L5601,L5702,L5716
TABLE_ALT_ITEM

NET_SPACING_TYPE=PWR
155S0583 155S0460 RADAR:8376383 MAX_NECK_LENGTH=3 MM
TP314
TP330

TP316
L2202 1 C2233 1 C2220
90-OHM-50MA
LVDS_CLK_N 2 TCM0605 3 100PF 820PF
40 14 IN 5% 10%
2 50V
CERM 2 50V
CERM
402 402
TP312
40 14 LVDS_CLK_P 1 4
IN
SYM_VER-2

TP323 TP325
TP317

NOSTUFF RESISTORS ARE THERE TO


INVESTIGATE POSSIBILITY OF REMOVING
THE CHOKE

A SYNC_MASTER=ALEX SYNC_DATE=N/A A
PAGE TITLE

VIDEO: LVDS CONNECTOR


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
22 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V0_GRAPE 17 18 32
17 PP18V_GRAPE
=PP3V0_GRAPE_MARIO1 32

C3005 1 C3007 1 C3053 1


1 C3006
1
R3025
0.1UF 0.1UF 0.1UF 10K
10% 10% 10% 0.1UF 5%
25V 2 25V 2 25V 2 10% 1/20W
X5R X5R X5R 6.3V
TABLE_5_HEAD

402 402 402 2 X5R MF

F3
E9
B6

A6
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 201 2 201
TABLE_5_ITEM

TP280
343S0525 1 IC,ASIC,GROUNDHOG B0,120B BGA U3003 CRITICAL VCC_DIG
VDDH
SPI_GRAPE_SCLK MAKE_BASE=TRUE GRAPE_SCLK
U3003 40 17 5 IN
SPI_GRAPE_CS_L MAKE_BASE=TRUE GRAPE_CS_L
OUT 18

MUX_IN<0> B1 GROUNDHOG A1 MT_PANEL_OUT<0> 17


40 17 5 IN OUT 18

D
18 MUX0 BGA VSTM0

D 18

18
MUX_IN<1>
MUX_IN<2>
C1
E1
MUX1
MUX2
CRITICAL
I DONT WANT TO OMIT!
VSTM1
VSTM2
B2
C2
MT_PANEL_OUT<1> 17
MT_PANEL_OUT<2> 17
F2 D1 SPI_GRAPE_MOSI MAKE_BASE=TRUE GRAPE_MOSI
18 MUX_IN<3> MUX3 Texas Instruments VSTM3 MT_PANEL_OUT<3> 17 40 17 5 IN OUT 18
RST_GRAPE_Z1_L
18 MUX_IN<4> H1 MUX4 CD3240B0 VSTM4 D2 MT_PANEL_OUT<4> 17 6 IN
RST_GRAPE_L
OUT 18

18 MUX_IN<5> J1 MUX5 VSTM5 E2 MT_PANEL_OUT<5> 17 MAKE_BASE=TRUE

18 MUX_IN<6> J2 MUX6 VSTM6 F1 MT_PANEL_OUT<6> 17


J3 G1
TP245 TO Z2
18 MUX_IN<7> MUX7 VSTM7 MT_PANEL_OUT<7> 17
MUX_IN<8> K4 MUX8 VSTM8 G2 MT_PANEL_OUT<8> 17 RST_GRAPE_Z2_L
18 OUT 18

18 MUX_IN<9> H5 MUX9 VSTM9 I1 MT_PANEL_OUT<9> 17


18 MUX_IN<10> I5 MUX10 VSTM10 H2 MT_PANEL_OUT<10> 17
18 MUX_IN<11> J8 MUX11 VSTM11 I2 MT_PANEL_OUT<11> 17

(TOUCH SCREEN) 18

18
MUX_IN<12>
MUX_IN<13>
MUX_IN<14> J10
J9
K8
MUX12
MUX13
VSTM12
VSTM13
K1
K2
I3
MT_PANEL_OUT<12> 17
MT_PANEL_OUT<13> 17
MT_PANEL_OUT<14> 17

CONNECTORS TO GRAPE FLEX


18 MUX14 VSTM14
18 MUX_IN<15> I10 MUX15 VSTM15 K3 MT_PANEL_OUT<15> 17
18 MUX_IN<16> H10 MUX16 VSTM16 J4 MT_PANEL_OUT<16> 17 TP284

MUX_IN<17> F11 MUX17 VSTM17 I4 MT_PANEL_OUT<17> 17


P/N 518S0817 18

18 MUX_IN<18> C11 MUX18 VSTM18 K6 MT_PANEL_OUT<18> 17 40 17 5 OUT SPI_GRAPE_MISO GRAPE_MISO


IN 18

MAKE_BASE=TRUE
MATES WITH LEFTMOST GRAPE FLEX TAIL 18 MUX_IN<19> E10 MUX19 VSTM19 H6 MT_PANEL_OUT<19> 17
NC A11 MUX20 VSTM20 K5 MT_PANEL_OUT<20> 17
J3010 NC B4 MUX21 VSTM21 J5 MT_PANEL_OUT<21> 17
502250-8237 NC A5 MUX22 VSTM22 I7 MT_PANEL_OUT<22> 17
F-RT-SM NC A2 MUX23 VSTM23 K9 MT_PANEL_OUT<23> 17
41
VSTM24 I8 MT_PANEL_OUT<24> 17
39 18 Z1_BON_L<0> C7 BON_L0
VSTM25 K10 MT_PANEL_OUT<25> 17 =PP3V0_GRAPE 17 18 32
18 Z1_BON_L<1> A7 BON_L1
VSTM26 I6 MT_PANEL_OUT<26> 17
17 MT_PANEL_OUT<36> 37 Z1_BON_L<2> B7 BON_L2 1
R3030
1
R3031
1 C3030 1 C3031 1 R3032 1
R3033
C C
18
TP142
36 MT_PANEL_OUT<37> 17 VSTM27 J7 MT_PANEL_OUT<27> 17
17 MT_PANEL_OUT<38> 35 TP141
18 Z1_BON_L<3> B8 BON_L3 10K 10K 0.1UF 0.1UF 3.3K 10K
TP140
34 MT_PANEL_OUT<39> 17 VSTM28 K11 MT_PANEL_OUT<28> 17 5% 5% 10% 10% 5% 5%
33 TP143
18 Z1_BON_L<4> A8 BON_L4 1/20W 1/20W 2 6.3V 2 6.3V 1/20W 1/20W
TP160
32 VSTM29 I9 MT_PANEL_OUT<29> 17 MF MF X5R CRITICAL X5R MF MF

2
MT_PANEL_IN<29> 31 TP186
Z1_BON_L<5> C8 201 201
TP150
18
MT_PANEL_IN<28> 18 BON_L5 J11 MT_PANEL_OUT<30> 17 2 201 2 201 2 201 2 201
30 18 VSTM30 VCCA VCCB
18 MT_PANEL_IN<27> 29 TP185
TP151
28 MT_PANEL_IN<26> C6 I11 MT_PANEL_OUT<31> 17
18 MT_PANEL_IN<25> 27
18
TP146 NC VSTM31 U3007
TP152
26 MT_PANEL_IN<24> 18 NC D3 VSTM32 H11 MT_PANEL_OUT<32> 17 DIR_U3007 PQFP1
18 MT_PANEL_IN<23> 25 TP184
TP149
24 MT_PANEL_IN<22> D4 VSTM33 G11 MT_PANEL_OUT<33> 17 SPI_GRAPE_SCLK 6 1A1 1B1 15 Z1_SCLK OUT

SN74AVCH4T245RSV
MT_PANEL_IN<21>
18
TP148 NC 40 17 5 IN 18
18 23 SPI_GRAPE_CS_L
TP158
22 MT_PANEL_IN<20> 18
NC D5 VSTM34 G10 MT_PANEL_OUT<34> 17 8 2A1 2B1 13 Z2_H_CS_L OUT
18 MT_PANEL_IN<19> 21 TP183 40 17 5 IN 17 18
TP145
20 MT_PANEL_IN<18> 18 NC D6 VSTM35 F10 MT_PANEL_OUT<35> 17 TO Z1/Z2
18 MT_PANEL_IN<17> 19 TP144 4 1DIR
TP156
18 MT_PANEL_IN<16> 18 NC D8 VSTM36 C10 MT_PANEL_OUT<36> 17 TP269
18 MT_PANEL_IN<15> 17 TP182 TP272 1 1OE* TP252
TP154
16 MT_PANEL_IN<14> 18
NC D9 VSTM37 D10 MT_PANEL_OUT<37> 17
18 MT_PANEL_IN<13> 15 TP155
TP159
14 MT_PANEL_IN<12> 18 NC E4 VSTM38 E11 MT_PANEL_OUT<38> 17 40 17 5
SPI_GRAPE_MOSI 7 1A2 1B2 14 Z1_MISO OUT 18
18 MT_PANEL_IN<11> 13 TP181 IN
TP157
12 MT_PANEL_IN<10> 18 NC E8 VSTM39 D11 MT_PANEL_OUT<39> 17 9 2A2 2B2 12 Z1_CS_OE OUT 17 18
18 MT_PANEL_IN<9> 11 TP147
TP162
10 MT_PANEL_IN<8> 18 NC F4 VSTM40 B11 NC
18 MT_PANEL_IN<7> 9 TP180 TP63 5 2DIR
TP161
8 MT_PANEL_IN<6> 18 NC F5 VSTM41 B10 NC
TP270 TP254
MT_PANEL_IN<5> 7 TP179
GRAPE_FW_DNLD_EN_L 16 2OE*
F8 NC
18 6
TP165
6 MT_PANEL_IN<4> C4 IN
MT_PANEL_IN<3>
18
TP178 NC VSTM42 NC APN:311S0485
18 5
TP164
4 MT_PANEL_IN<2> 18 NC F9 VSTM43 A4 NC (A -> B)
18 MT_PANEL_IN<1> 3 TP177
TP166
2 MT_PANEL_IN<0> 18
TP163 NC G3 VSTM44 B5 NC TP255
1 GND
NC G4 VSTM46 A3 NC

10

11
NC G9 VSTM45 C5 NC
38
NC H3 VSTM47 B3 NC TP253 TP273
40
NC H4
H7 A_AD_R0 A10 Z1_B_ADR<0> 18
NC
A_AD_R1 B9 Z1_B_ADR<1> 18
NC H8
A_AD_R2 A9 Z1_B_ADR<2> 18
NC H9
NC J6 =PP3V0_GRAPE 17 18 32

K7
B MATES WITH RIGHTMOST GRAPE FLEX TAIL
NC
GND CRITICAL
1 C3050
B

6
0.1UF
VCC 10%
6.3V
G8
G7
G6
G5
F7
F6
E7
E6
E5
E3
D7
C9
J3011 U3010
SN74LVC1G126DRYR-M
2 X5R
201

502250-8237 LLP =PP3V0_GRAPE


F-RT-SM Z1_CS_OE 1 OE 17 18 32
18 17 IN
41 1 C3041
39 Z2_H_CS_L 2 A Y 4 0.1UF
18 17 IN Z1_CS_L OUT 18
10%
6.3V

17 MT_PANEL_OUT<1>
37
35
36 MT_PANEL_OUT<0> 17
TP103
BOOST CONVERTOR MIN_NECK_MIDTH SHOULD BE 0.4MM GND NC TP275
CRITICAL
U3009
2 X5R
201

SN74LVC1G125DRYR-M

5
TP102
34 MT_PANEL_OUT<2> 17 NET_SPACING_TYPE=PWR 6
TP100
17 MT_PANEL_OUT<3> 33
32 MT_PANEL_OUT<4>
TP101
MIN_LINE_WIDTH=0.2MM L3000 MIN_LINE_WIDTH=0.2MM
D3000
MIN_LINE_WIDTH=0.6MM
TP99 LOAD CURRENT ~ 153UA
SPI_GRAPE_MISO
LLP
2 Z1_MOSI
17 MT_PANEL_OUT<5> 31
17
TP107 4.7UH-700MA-280MOHM SOD-323
MIN_NECK_WIDTH=0.25MM
VOLTAGE=18V R3066 40 17 5 OUT 4 IN 18
TP106
30 MT_PANEL_OUT<6> 17 0.1
17 MT_PANEL_OUT<7> 29 TP105
VR_BOOST_L 1 2 VR_BOOST_SW 1 2 PP18V_R_GRAPE 1 2 PP18V_GRAPE NC 5
TP104
28 MT_PANEL_OUT<8> TP98 17 OE*
17 3 TP271
17 MT_PANEL_OUT<9> 27 TP111 VLF 1%
MIN_LINE_WIDTH=0.6MM
TP110
26 MT_PANEL_OUT<10> MIN_NECK_WIDTH=0.2MM
17 MT_PANEL_OUT<11> 25
17
TP109 C3009 B0520WSXG 1/20W
MF
VOLTAGE=18V 1
TP108
17 MT_PANEL_OUT<13> 23
24 MT_PANEL_OUT<12> 17
TP116 =PP3V0_GRAPE 1 2 C3008 1 R3009 1 1 C3000 201 TP236
NET_SPACING_TYPE=PWR

TP115
22 MT_PANEL_OUT<14> 17
32 18 17
1M 1UF
17 MT_PANEL_OUT<15> 21 TP114 33PF 1% 10% 18 17 IN Z1_CS_OE
TP113
20 MT_PANEL_OUT<16> 17 0.1UF 5% 1/16W 2 25V
17 MT_PANEL_OUT<17> 19 TP120 25V
2 MF-LF
X5R
TP119
18 MT_PANEL_OUT<18> 17 10% NP0-C0G
402
603-1
17 MT_PANEL_OUT<19> 17 TP118 16V 201 2
TP117
16 MT_PANEL_OUT<20> 17
CRITICAL 2 X5R
17 MT_PANEL_OUT<21> 15 TP125 402
TP124
14 MT_PANEL_OUT<22> 17
17 MT_PANEL_OUT<23> 13 TP123 VIN
TP122
12 MT_PANEL_OUT<24> 17
17 MT_PANEL_OUT<25> 11 TP129
TP128
17 MT_PANEL_OUT<27> 9
10 MT_PANEL_OUT<26> 17
TP127 1 L U3000 FB 4 VR_BOOST_FBK
TP126
8 MT_PANEL_OUT<28> 17 TPS61045
17 MT_PANEL_OUT<29> 7 TP134
QFN-1
TP133
6 MT_PANEL_OUT<30> NC 3 5 1
17 MT_PANEL_OUT<31> 5
17
TP132 DO CTRL PM_BOOST_EN 18 R3012
TP131
4 MT_PANEL_OUT<32> 17 1 C3002 71.5K
A MT_PANEL_OUT<33> TP138
3
A
17
1%
TP137
17 MT_PANEL_OUT<35> 1
2 MT_PANEL_OUT<34> 17
TP136
1 C3001 SW 8 470PF
10%
1/20W
MF SYNC_MASTER=RAMSIN SYNC_DATE=N/A
PGND

TP135 2.2UF
TABLE_ALT_HEAD

16V
THRML 2 201 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
GND

10% 2 X5R-X7R PAGE TITLE


PART NUMBER
2 6.3V PAD
GRAPE: GROUNDHOG,CONN,BOOST
TP234
X5R 201
TP112
38 603
TABLE_ALT_ITEM

9 7 6 311S0523 311S0485 U3007


TP121
40 TP139 DRAWING NUMBER SIZE
AGND_U3000
051-8962 D
TABLE_ALT_ITEM

TP130 2
MIN_LINE_WIDTH=0.2MM 311S0524 311S0533 U3009
Apple Inc. REVISION
TP233
TABLE_ALT_ITEM

XW3000
311S0525 311S0532 U3010 R
A.0.0
SM NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
TP232 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 17 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ARM9 MCU (Z2 BASED) TP292


ZEPHYR 1+ ASIC
TP274
32 =PP3V0_GRAPE_Z1
Z2_VDDCORE =PP3V0_GRAPE_Z2
18 32
VOLTAGE=1.8V
1 C3102 18 Z1_1V8_OUT
MIN_LINE_WIDTH=0.5MM
1 C3111 1 C3109 1 C3105 1 C3107 0.1UF
MIN_NECK_WIDTH=0.1MM
10UF 0.1UF 0.1UF 4.7UF 10%
NET_SPACING_TYPE=PWR 20% 10% 10% 20% 2 6.3V
X5R 1 C3101
6.3V 6.3V 6.3V 6.3V VOLTAGE=3.0V 201
TP250
2 X5R 2 X5R 2 X5R 2 X5R
R3101 MIN_LINE_WIDTH=0.2MM 2.2UF
VDDANA AND VDDCORE 603 201 201 402 20%
ARE EACH GENERATED WITHIN 4.7 NET_SPACING_TYPE=PWR
2 4V
Z2 AND BYPASSED OUTSIDE 1 2 MT_3V3_INT X5R
TP308 402
5%
VOLTAGE=1.8V
1 C3104 1 C3103
D
1/20W
Z2_VDDANA
TP277 NET_SPACING_TYPE=PWR
R3190
D
MF
MIN_LINE_WIDTH=0.6MM 201 2.2UF 0.1UF
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM Z2_3V3_1V8_IN 1
1.00 2 Z1_1V8_OUT
20% 10%
MIN_NECK_WIDTH=0.1MM
18
2 4V
X5R 2 6.3V
X5R =PP3V0_GRAPE
MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWR
1 C3112 1 C3110 1%
1/20W MIN_NECK_WIDTH=0.25MM
402 201 TP251 17 18 32

2.2UF 0.1UF 1 C3108 1 C3106 1 C3191 MF


201
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
10%
20% 6.3V 0.1UF 0.1UF 22UF MIN_NECK_MIDTH SHOULD BE 0.4MM 1
4V
2 X5R
2 X5R
201
10%
6.3V
10%
6.3V
20% R3155
402 2 X5R 6.3V 100K

C10
2 X5R 2 X5R-CERM

C1

D5
E5
F5

VDDDIG C7
C4

V18 C6
201 201 603 5%
1/20W
VDDANA MF

VDDIO
2 201 TP278

D2

E1

G8
H2
J5

E2
E3
TP276
R3120 17 MT_PANEL_IN<0> D1 IN0 SCLK A9 Z1_SCLK IN 17 18
0 D2 IN1
5% 17 MT_PANEL_IN<1> CRITICAL CS* A8 Z1_CS_L IN 17
VDDANA VDDCORE VDDIO VDDLDO 1/20W
MF
201
17 MT_PANEL_IN<2> D3 IN2 U3100 MISO A7 Z1_MISO IN 17 18

NC
A9 IN0_0 B_ADR0 F9 1 2 Z1_CS_OE IN 17 17 MT_PANEL_IN<3> D4 IN3 BROADCOM MOSI A6 Z1_MOSI OUT 17 18

NC
B9 IN0_1 B_ADR1 F8 Z1_PCLK 18 17 MT_PANEL_IN<4> E1 IN4 BCM5973
G9 E2 IN5 BGA-HF GO B5 Z1_GO 18
CRITICAL B_ADR2 =PP3V0_GRAPE_Z2 17 MT_PANEL_IN<5> TP248
A7 IN1_0 DONE B6 Z1_DONE
NC NOSTUFF
18 32
17 MT_PANEL_IN<6> E3 IN6 18
A8 J8
NC IN1_1 U3101 BON_L0 Z1_CS_OE_R 1 E4 IN7 PCLK A10
TP279

BROADCOM BON_L1 H9 NC_BON_L1 R3161 17 MT_PANEL_IN<7> Z1_PCLK 18


B8 IN2_0 100K NOTE: PLATEFORM DETECTION PIN "H5" 17 MT_PANEL_IN<8> F1 IN8
NC J9
C8 IN2_1
BCM5974CKFBGH BON_L2 NC_BON_L2 5%
1/20W
PULL DOWN = K48
FLOATING = K93/K94 17 MT_PANEL_IN<9> F2 IN9 TP249

NC FBGA BON_L3 H7 NC_BON_L3 MF PULL UP = RESERVED FOR FUTURE STMOUT B9


MT_PANEL_IN<10> F3 IN10
B7 IN3_0 BON_L4 J7 NC_BON_L4 TP285
2 201 17
STMIN B10 Z1_STMIN
NC 17 MT_PANEL_IN<11> F4 IN11
C7 IN3_1 BON_L5 H5 Z2_BON_L4
NC 17 MT_PANEL_IN<12> G1 IN12
A6 J2 G2 IN13 Wites OM Tesla NOTE:WARNING!!!
IN4_0 GPIO0 IRQ_GRAPE_HOST_INT_L OUT 5 17 MT_PANEL_IN<13>
NC B6 VERY IMPORTANT IF THIS JUMPER IS
IN4_1 GPIO1 J3 PM_BOOST_EN 17 17 MT_PANEL_IN<14> G3 IN14 REMOVED ON BOARD TOUCH WILL NOT WORK
NC OUT
H4 Z1_GO MT_PANEL_IN<15> G4 IN15 IF SO JUMPER B9 AND B10 ON THE IC!
C6 GPIO2 18 17
IN5_0 J6 1 G5 IN16
NC C5 GPIO3 Z1_DONE 18 R3160 17 MT_PANEL_IN<16> B_ADR0 B2 Z1_B_ADR<0> 17
IN5_1
C
TP238

C NC GPIO4 G3 GRAPE_CS_L 17 100K 17 MT_PANEL_IN<17> H1 IN17 B_ADR1 B3 Z1_B_ADR<1> 17


IN 5% TP241
B5 IN6_0 GPIO5 F3 GRAPE_MOSI 1/20W MT_PANEL_IN<18> H2 IN18 B_ADR2 B4 Z1_B_ADR<2>
NC IN 17
MF
17 17
TP237
A5 IN6_1 GPIO6 F4 GRAPE_MISO MT_PANEL_IN<19> H3 IN19
NC OUT 17
2 201 17

GPIO7 H6 GRAPE_SCLK MT_PANEL_IN<20> H4 IN20


A4 IN 17 17
IN7_0 H5 IN21 BON_L0 A1 Z1_BON_L<0> 17
NC B4 17 MT_PANEL_IN<21> TP240
CFG1 CFG0 MODE IN7_1 JTAG_TCK G6 TP_U3101_TCK BON_L1 A2 Z1_BON_L<1> 17
NC TP283
17 MT_PANEL_IN<22> J1 IN22 TP242
JTAG_TDI E8 TP_U3101_TDI BON_L2 A3 Z1_BON_L<2> 17
0 0 DEPENDENT 1 A3 IN8_0 TP287
MT_PANEL_IN<23> K1 IN23 TP235
NC JTAG_TDO E9 TP_U3101_TDO 17
BON_L3 A4 Z1_BON_L<3> 17
B3 IN8_1
TP286
MT_PANEL_IN<24> J2 IN24 TP244
NC JTAG_TMS F7 TP_U3101_TMS 17
BON_L4 A5 Z1_BON_L<4>
0 1 DEPENDENT 2 TP281 =PP3V0_GRAPE MT_PANEL_IN<25> K2 IN25 17
17 18 32 17 TP246
C2 IN9_0 BON_L5 B1 Z1_BON_L<5>
NC H_CS* H1 Z2_H_CS_L MT_PANEL_IN<26> J3 IN26 17
1 0 AUTONOMOUS A2 IN 17
1 17 TP239
NC IN9_1
H_SCLK J1 Z1_SCLK R3107 MT_PANEL_IN<27> K3 IN27
1 1 SLAVE B2 H3 Z1_MISO
IN 17 18
100K 17
J4 IN28 TM B8 U3100_TM TP247
IN10_0 H_SDI IN 17 18 5% 17 MT_PANEL_IN<28>
NC C1 J4 Z1_MOSI 1/20W
K4 IN29
IN10_1 H_SDO OUT 17 18 MF 17 MT_PANEL_IN<29>
NC 2 201 INTERNAL PU RESET* C5 RST_GRAPE_Z1_L
K48 USES DEPENDENT 2 MODE B1 F1 Z2_A_CS_L 17 MUX_IN<0> J5 IN30 17

NC IN11_0 A_CS*
MUX_IN<1> K5 IN31
TP_Z2_A_SCLK
R3180
17
A1 IN11_1 A_SCLK G1
K6 IN32
R3181
TP291
NC TP_Z2_A_SDI 17 MUX_IN<2>
A_SDI F2 100
E6 ARMTAPMD* TP290 1 2 MUX_IN<3> J6 IN33 100
NC A_SDO G4 TP_Z2_A_SDO 17
1 2
TP289
5% 17 MUX_IN<4> J7 IN34 TP257
BOOT_CFG0_R F6 BOOT_CFG0 1/32W 5%
TP298
TM0 E7 TP_U3101_TM0 MF 17 MUX_IN<5> K7 IN35 1/32W
BOOT_CFG1_R D3 BOOT_CFG1 TP288
01005 MF
TM1 D4 U3101_TM1 17 MUX_IN<6> J8 IN36 01005
TP282
G5 FLOO MUX_IN<7> K8 IN37
NC CLKIN E5 HOST_REFCLK CLK_32K_PMU 35 39
17
1 F5 IN MUX_IN<8> J9 IN38
R3173 NC
LFOO
CLKOUT E4 MAKE_BASE=TRUE 17

0 NC 17 MUX_IN<9> K9 IN39
5% G7 EXTFLLIN TP299
1/20W NC INTERNAL PU RESET* D5 RST_GRAPE_Z2_L MUX_IN<10> J10 IN40
IN 17 17
MF
MUX_IN<11> K10 IN41
2 201 R3171
17
GND MUX_IN<12> H6 IN42
0
17

MUX_IN<13> H7 IN43
B B
C3
C4
D6
D7
D8
C9
D9
G2
D1
H8

17
1 2
17 MUX_IN<14> H8 IN44
17 MUX_IN<15> H9 IN45
TP307
32 18 17 17 MUX_IN<16> H10 IN46
=PP3V0_GRAPE
TP243 TP306
17 MUX_IN<17> G6 IN47
17 MUX_IN<18> G7 IN48
17 MUX_IN<19> G8 IN49
NC G9 IN50
NC G10 IN51
NC F7 IN52
NC F8 IN53
NC F9 IN54
NC F10 IN55
NC E7 IN56
NC E8 IN57
NC E9 IN58
NC E10 IN59
NC D7 IN60
NC D8 IN61
NC D9 IN62
NC D10 IN63

GNDANA GNDDIG GNDIO

C2
C9
D6
E6
F6

B7
C8

C3
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_ALT_ITEM

138S0652 138S0648 C3107 RADAR:8392120

A
TABLE_ALT_ITEM

138S0618 138S0648 C3107 BOM CONSOLIDATION


SYNC_MASTER=RAMSIN
PAGE TITLE
SYNC_DATE=N/A A
GRAPE: Z1, Z2
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

L63 AUDIO CODEC


APN:338S0940

D 32 20
=PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 32 D
32 =PP1V8_AUDIO

1 C3605 1 C3606 1 C3607 1 C3608


27PF 10UF 0.1UF 4.7UF
5% 20% 20% 20%
16V 4V 4V 4V
2 NP0-C0G 2 X5R 2 X5R
01005 402 2 TANT
01005 402-3
C3600 1 C3601 C3602 C3604
1000PF 0.1UF
1
0.1UF
1 C3603 1 1
10% 20% 20% 10UF 0.1UF TP579
6.3V 2 4V 4V 20% 10%
X5R X5R 2 X5R 2 6.3V 6.3V
01005 01005 01005 X5R 2 2 X5R GND_AUDIO_CODEC
603 201 19 21
XW3600

VL C11
VD B11

VCP D11
VP F5

VA G2
SM
1 2
TP580

XW3601
SM
1 2
U3600
CS42L63B XW3602
WLCSP SM MIN_LINE_WIDTH=1.0MM
1 2 MIN_NECK_WIDTH=0.2MM GND_AUDIO_HP_AMP 21 23
I2C ADDRESS: 1001010X??
I2C0_SCL_1V8 C6 SCL HP_DETECT E9 HP_DET
39 35 10 5 IN IN 24

I2C0_SDA_1V8 C7 SDA HPOUTB G9 HP_R OUT


39 35 10 5 BI 21

IRQ_CODEC_L E4 INT* HPOUTA G10 HP_L OUT


5 OUT 21
TP467
RST_L63_L E5 RESET* HPOUT_REF F9 HP_REF
35 IN IN 21 23
TP549
AUD_MIK_HS1_INT_L E3 WAKE* LINEOUT1B G8 CODEC_LINE_OUT_R
35 OUT OUT 21

C TP581

TP556
39 5 IN I2S_AP_0_MCK_R B9 MCLK LINEOUT1A F8
LINEOUT1_REF E8
CODEC_LINE_OUT_L
CODEC_LINE_OUT_REF
OUT
IN
21

21
TP629

TP630 C
I2S_AP_0_LRCK C8 ASP_LRCLK TP628
39 5 IN
B7 ASP_SCLK LINEOUT2A D7 LEFT_CH_OUT_P OUT 20 40
TP560
39 5 IN
I2S_AP_0_BCLK
LINEOUT2A_REF E7
TP593
TP557
39 5 IN I2S_AP_0_DOUT R3601 B8 ASP_SDIN LEFT_CH_OUT_REF IN 20 40

22 A9 ASP_SDOUT
TP596
I2S_AP_0_DIN L63_ASP_SDOUT LINEOUT2B F7
TP562
39 5 OUT 1 2 39 RIGHT_CH_OUT_P OUT 20 40

LINEOUT2B_REF G7
TP594
TP445 5% RIGHT_CH_OUT_REF IN 20 40
I2S_AP_2_LRCK 1/32W C9 VSP_LRCLK
39 30 5 IN MF TP595
39 30 5 I2S_AP_2_BCLK 01005 C10 VSP_SLCLK EAROUT+ G3 NC_EAROUT_AP
IN
TP444
39 30 5 IN I2S_AP_2_DOUT R3602 A11 VSP_SDIN EAROUT- F3 NC_EAROUT_AN
22 L63_VSP_SDOUT A10 VSP_SDOUT
39 30 5 OUT I2S_AP_2_DIN 1 2 39
SPEAKEROUTA+ F6 NC_SPEAKEROUT_AP
TP442 5%
I2S_AP_3_LRCK 1/32W B6 XSP_LRCLK SPEAKEROUTA- G6 NC_SPEAKEROUT_AN
39 5 IN MF
TP440
39 5 I2S_AP_3_BCLK 01005 A6 XSP_SCLK
IN
R3603 A8 XSP_SDIN/DAC2B_MUTE SPEAKEROUTB+ F4 NC_SPEAKEROUT_BP
39 5 IN I2S_AP_3_DOUT
22 A7 XSP_SDOUT SPEAKEROUTB- G4 NC_SPEAKEROUT_BN
TP441
39 5 OUT I2S_AP_3_DIN
1 2 39 L63_XSP_SDOUT
NOSTUFF R3608 22 5%
DMIC_SCLK_CODEC B5 DMIC_SCLK FLYP E11 VHP_FLYP C3617
25 OUT DMIC_SCLK_SENSOR 1 2
5% MF
1/32W
MF
2.2UF
DMIC_SD_CODEC A5 DMIC_SD 1 2
TP21
1/32W 01005
R3620 22
01005
C3618
DMIC_SCLK_CANADA 1 2 NC_LINE_IN1_CODEC C5 LINEINA
FLYC F11 20% 2.2UF
25 OUT 10V
5% MF
C4 LINEINA_REF VHP_FLYC 1 2
1/32W 01005 NC_LINE_IN1_REF_CODEC X5R-CERM
402
TP22 20%
NC_LINE_IN2_CODEC D6 LINEINB 10V
NOSTUFF R3621 22 D5 LINEINB_REF FLYN G11 VHP_FLYN X5R-CERM
25 IN DMIC_SD_SENSOR 1 2
TP582
NC_LINE_IN2_REF_CODEC 402
5% MF
1/32W 01005 D4 MIC1_BIAS SPEAKER_VQ E6 SPKR_VQ NOT USING SPEAKER AMPLIFIER, THIS CAN BE A NO STUFF
NC_MIC1_BIAS_CODEC
R3622 22
25 IN DMIC_SD_CANADA 1 2
A3 MIC1 FILT+ G1 FILT_P
5% MF NC_MIC1P_CODEC
1/32W 01005
B3 MIC1_REF
B
NC_MIC1N_CODEC
B TP583
NC_MIC1_FILT_CODEC E2 MIC1_BIAS_FILT

EXT_MIC_BIAS R3604 C2 MIC2_BIAS


23 OUT
1.00K
HSMIC_C_P 1 2 MIC2_DET D3 MIC2_DETECT
23 IN
1%
EXT_MIC_P 1/32W B1 MIC2
40 23 IN MF
01005
40 23 IN EXT_MIC_REF R3605 B2 MIC2_REF

HSMIC_C_N
1.00K2
1 MIC2_DET_REF C3 MIC2_DETECT_REF
23 IN
1%
1/32W MIC2_BIAS_FILT C1 MIC2_BIAS_FILT +VCP_FILT D10 VHPPFILT
MF
-VCP_FILT F10 VHPNFILT
TP563
01005
D2 MIC3A_BIAS

A1 MIC3A

A2 MIC3A_REF 2.2UF
RECOMMENDED
D1 MIC3A_BIAS_FILT C3614 1 CRITICAL
10UF
1 C3616
F1 MIC3B_BIAS 20% 4.7UF
6.3V 20%
X5R 2
A4 MIC3B 603 CRITICAL 2 6.3V
X5R-CERM
1 402
B4 MIC3B_REF
C3615
1UF
1 C3613 10%
E1 MIC3B_BIAS_FILT 10UF 2 6.3V
C3611 1
20% TANT
402-1
4.7UF 6.3V
2 X5R
E10 GNDCP

20%
GND
B10 GNDD

F2 GNDA

G5 GNDP

6.3V 603
X5R-CERM 2
402

A C3609 A
D8

D9

1
SYNC_MASTER=LENG SYNC_DATE=N/A
4.7UF PAGE TITLE

AUDIO: L63 CODEC


20%
6.3V
X5R-CERM 2
402
TP597 DRAWING NUMBER SIZE
TP564
TP623 TP631 Apple Inc. 051-8962 D
REVISION
GND_AUDIO_CODEC
21 19
MIN_LINE_WIDTH=0.6MM
R
A.0.0
MIN_NECK_WIDTH=0.2MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAX_NECK_LENGTH=75 MM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

GAIN VDD GND


D 12DB 47K NC
D
9DB NC 47K
SPEAKER AMPLIFIER 1 6DB
3DB
SHORT
NC
NC
NC
APN:353S2958 0DB NC SHORT
TURN ON TIME: 7.5MS
80HZ +/- XXX% TURN ON DELAY: 20MS
XW3701 TP224
SM
MIN_LINE_WIDTH=0.30MM
32 20 19 =PPVCC_MAIN_AUDIO 1 2 MIN_NECK_WIDTH=0.20MM AUD_SPKR_AMP1_PBUS

LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2


CRITICAL C3703 1 R3703 1 1 C3704
0.00 10UF

C2
0.1UF 20%
C3702 10%
6.3V VDD
0%
1/32W 10V
2 X5R
0.047UF X5R 2 MF
LEFT_CH_OUT_REF 1 2 SSM2375_L_IN_N
201 U3700 01005 2
603
40 19 OUT 40 SSM2375
WLCSP
B1 IN+ MIN_LINE_WIDTH=0.50MM
10%
6.3V OUT+ C3 SPKRAMP_L_OUT_P MIN_NECK_WIDTH=0.20MM OUT 20
X5R A1 IN- OUT- B3 SPKRAMP_L_OUT_N
R3701 201 C3701 MIN_LINE_WIDTH=0.50MM OUT 20

0.047UF A2 SD* MIN_NECK_WIDTH=0.20MM


100 GAIN A3 SSM2375_L_GAIN
40 19 IN LEFT_CH_OUT_P 2 1 40 LEFT_CH_P 2 1 40 SSM2375_L_IN_P
1%
10% EDGE B2
1/32W
MF 6.3V GND
01005 X5R
201

C1
C
TP225

C 20 5 IN AUD_SPKRAMP_MUTE_L
CRITICAL
GAIN:6DB
SPEAKER CONNECTOR
R3702 1 R3700 1 APN 518S0521
J3700
100K
0.00 5% 78171-0004
0% 1/32W M-RT-SM
1/32W MF
MF 01005 2 XW3700 5
01005 2 SM TP191 TP190 TP187 TP188
1 2 GND_SPKR_AMP1
TP223
MIN_LINE_WIDTH=0.30MM 20 SPKRAMP_L_OUT_P 1
MIN_NECK_WIDTH=0.20MM
20 SPKRAMP_L_OUT_N 2

TP222 20 SPKRAMP_R_OUT_P 3

20 SPKRAMP_R_OUT_N 4

NOSTUFF NOSTUFF
CRITICAL CRITICAL 6
1 C3750 1 C3752
100PF 100PF
5% 5%
16V 16V
2 NP0-C0G 2 NP0-C0G
01005 01005
NOSTUFF NOSTUFF
CRITICAL CRITICAL
L63 LINEOUT2A IS CONNECTED TO U3700
L63 LINEOUT2B IS CONNECTED TO U3710 SPEAKER AMPLIFIER 2 C3751
100PF
5%
16V
1 C3753
100PF
5%
16V
1

NP0-C0G 2 NP0-C0G 2
01005 01005

XW3711 TP229
TP189
SM
MIN_LINE_WIDTH=0.30MM
32 20 19 =PPVCC_MAIN_AUDIO 1 2 AUD_SPKR_AMP2_PBUS MIN_NECK_WIDTH=0.20MM
TP192

R37131
B C3713 1 0.00
0%
1 C3714
10UF
B

C2
0.1UF 1/32W 20%
10% MF 10V
CRITICAL 6.3V VDD 01005 2 2 X5R
2
C3711
X5R
201 U3710 603

R3711 0.047UF SSM2375


WLCSP
RIGHT_CH_OUT_P 100 RIGHT_CH_P SSM2375_R_IN_P B1 IN+ SPKRAMP_R_OUT_P MIN_LINE_WIDTH=0.50MM
40 19 IN
2 1 40 2 1 40 OUT+ C3 MIN_NECK_WIDTH=0.20MM OUT 20

1% A1 IN- OUT- B3 SPKRAMP_R_OUT_N


10% OUT 20
1/32W
6.3V CRITICAL MIN_LINE_WIDTH=0.50MM
MF
01005 X5R C3712 A2 SD* GAIN A3 SSM2375_R_GAIN MIN_NECK_WIDTH=0.20MM
201 0.047UF
40 19 OUT RIGHT_CH_OUT_REF 2 1 40 SSM2375_R_IN_N EDGE B2
GND
10% TP256

C1
TP267 6.3V
X5R

20 5 AUD_SPKRAMP_MUTE_L
201
GAIN:6DB

R37121
0.00
0% XW3710
1/32W SM
MF MIN_LINE_WIDTH=0.30MM
01005 2 TP231
1 2 MIN_NECK_WIDTH=0.20MM GND_SPKR_AMP2

TP230

A SYNC_MASTER=LENG SYNC_DATE=N/A A
PAGE TITLE

AUDIO: SPEAKER AMP


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 20 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

HEADPHONE OUTPUT ZOBEL NETWORK


XW3851
D 19 IN HP_L 1
SM
2 AUD_HP1_MLBCON_L OUT 24
D
XW3850
SM
19 IN HP_R 1 2 AUD_HP1_MLBCON_R OUT 24

R3850 1 1
R3851
100 100
1% 1%
1/32W 1/32W
MF
01005 2
MF
2 01005
1 C3853 1 C3852
27PF 27PF
5% 5%
2 16V 16V
2 NP0-C0G

HP_ZL
NP0-C0G

HP_ZR
01005 01005

C3850 1 1 C3851
33000PF 33000PF
10% 10%
6.3V 2 2 6.3V
X5R X5R
201 201

23 19 GND_AUDIO_HP_AMP

23 19 OUT HP_REF IN

C 1 C3854
C
27PF
5%
16V
2 NP0-C0G
01005

DOCK LINE OUTPUT


XW3800 R3800
SM MIN_LINE_WIDTH=0.1MM MIN_LINE_WIDTH=0.1MM
CODEC_LINE_OUT_REF AUD_LO_REF_FILT
1.00 2 MIN_NECK_WIDTH=0.07MM AV_EMI_DIFF_SENSE
19 OUT
1 2 MIN_NECK_WIDTH=0.07MM 1
IN 28
MIN_LINE_WIDTH=0.1MM 1%
MIN_NECK_WIDTH=0.07MM XW3801 1/20W
MF

B 19 IN CODEC_LINE_OUT_L 1
SM
2
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM
201
AUDIO_EMI_LO_L OUT 28 B
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM XW3802
SM
MIN_LINE_WIDTH=0.1MM
19 IN CODEC_LINE_OUT_R 1 2 MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_R OUT 28

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM
1 C3801
15PF
CODEC 5%
16V
2 NP0-C0G-CERM
C3803
15PF
1
DOCK
01005 5%
NOSTUFF 16V
NP0-C0G-CERM 2
C3802 1 C3800 1 01005

15PF 0.01UF
10%
5% 10V 2
16V X7R
NP0-C0G-CERM 2 201
01005
XW3803
SM
MIN_LINE_WIDTH=0.6MM GND_AUDIO_PT_DK
19 GND_AUDIO_CODEC 1 2 MIN_NECK_WIDTH=0.2MM IN 28
MAX_NECK_LENGTH=75 MM

A SYNC_MASTER=LENG SYNC_DATE=N/A A
PAGE TITLE

AUDIO: HEADPHONE OUT


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER=LENG SYNC_DATE=N/A A
PAGE TITLE

AUDIO: BLANK
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
39 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 22 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

EXTERNAL (HEADSET) MIC INPUT CIRCUITRY

TP569

32 =PP3V0_S2R_HALL_CHSW
1 C4200
0.1UF
10%
2 6.3V CHS_CLAMPI

A1
X5R
201

VDD
U4200 R4203 R4202 R4201
2.2K 2 2.2K 2 1K
TS3A8235YFP 1 1 1 2 EXT_MIC_BIAS IN 19

C WCSP
RAMPI D4
1%
1/20W
MF
201
1%
1/20W
MF
201
5%
1/20W
MF
201 HSMIC_C_P OUT 19 2319 23
C
RAMPO D3 C4211 R4212
CLAMPI C4 0.1UF 470
1 2 HSMIC_R_P 1 2 EXT_MIC_P OUT 19 40
24 IN AUD_HS_MIC1_HI 1%
CLAMPO B4 CHS_CLAMPO 10% 1/20W
6.3V MF
X5R
201
201 1 C4217
B1 MIC1 MIC D2 HSMIC_C_P 1 C4201 1000PF

FROM HEADSET
C4216
33PF
1 C4212
15PF
1 C1 MIC2 REF D1 HSMIC_C_N 10UF
20%
6.3V
10%
2 16V
X7R
201
TO CODEC
5% 5% 2 CERM-X5R
16V
NP0-C0G 2
16V
NP0-C0G-CERM 2 SCL A3 0402-1 C4213
01005 01005 A4 0.1UF R4213
SDA
1 2 HSMIC_R_N 1
470 2 EXT_MIC_REF
ADDR A2 OUT 19 40
24 IN AUD_HS_MIC1_LO 1%
10% 1/20W

GND2
GND1
6.3V MF
GND X5R 201
201
HSMIC_C_N OUT 19 2319 23

C3
B3

B2
C2
24 AUD_HS_RET1 CHS_SCL 10

CHS_SDA
24
AUD_HS_RET2 10

GND_AUDIO_HP_AMP
21 19

XW4200 EXT MIC LPF FC = 677KHZ


SM
21 19 OUT
HP_REF 1 2

B B

A SYNC_MASTER=LENG SYNC_DATE=N/A A
PAGE TITLE

AUDIO: DETECT/MIC BIAS


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 23 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29


PLACE ALL COMPONENTS NEAR J5501

L4301
30-OHM-1.7A MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=1.0MM
25 IN CONN_AUD_HS_MIC1_HI 1 2 AUD_HS_MIC1_HI OUT 23

MIN_LINE_WIDTH=1.0MM 0402
MIN_NECK_WIDTH=0.1MM TP589 L4302
30-OHM-1.7A MIN_LINE_WIDTH=1.0MM
MIN_NECK_WIDTH=0.1MM
25 IN CONN_AUD_HS_MIC1_LO 1 2 AUD_HS_MIC1_LO OUT 23

MIN_LINE_WIDTH=1.0MM 0402
MIN_NECK_WIDTH=0.1MM
TP603

MAKE_BASE=TRUE
MIN_LINE_WIDTH=1.0MM
CONN_AUD_HS_RET1 MIN_NECK_WIDTH=0.1MM AUD_HS_RET1
C C
25 IN OUT 23

MAKE_BASE=TRUE
MIN_LINE_WIDTH=1.0MM
25 IN CONN_AUD_HS_RET2 MIN_NECK_WIDTH=0.1MM AUD_HS_RET2 OUT 23

TP602 L4303
240-OHM-0.2A-0.8-OHM
25 IN CONN_AUD_HP1_DET_H 1
0201
2 AUD_HP1_DET_H OUT 24

TP604
L4304
30-OHM-1.7A
25 OUT CONN_AUD_HP1_MLBCON_R 1 2 AUD_HP1_MLBCON_R IN 21
0402
TP609
L4306
30-OHM-1.7A
25 OUT CONN_AUD_HP1_MLBCON_L 1 2 AUD_HP1_MLBCON_L IN 21
0402

HEADSET JACK INSERTION DETECT


R4312
B 24 IN AUD_HP1_DET_H 1
3.3K 2
HP_DET OUT 19 B
5%
1/32W
NOSTUFF
MF 1 C4310
01005 4700PF
10%
10V
2 X7R
201

A SYNC_MASTER=LENG SYNC_DATE=N/A A
PAGE TITLE

AUDIO: HP/MIC FILTERS


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 24 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

CANADA FLEXES CONN. SENSOR BOARD CONN ALIASES


APN: 518S0817

CLK_CAM_RF_FILT CONN_CLK_CAM_RF_FILT
J5501 39 27

40 27 MIPI0C_CAM_DATA_N<0>
MAKE_BASE=TRUE
CONN_MIPI0C_CAM_DATA_N<0>
27

27
CRITICAL MIPI0C_CAM_DATA_P<0>
MAKE_BASE=TRUE
CONN_MIPI0C_CAM_DATA_P<0>
41 40 27 27
MAKE_BASE=TRUE
TP559
39
40 27 MIPI0C_CAM_CLK_N CONN_MIPI0C_CAM_CLK_N 27

31 26 PPVSIM 37 TP588 40 27 MIPI0C_CAM_CLK_P


MAKE_BASE=TRUE
CONN_MIPI0C_CAM_CLK_P 27
36
SIM_CLK_FILT 35 PM_REAR_CAM_SHUTDOWN
MAKE_BASE=TRUE
CONN_PM_REAR_CAM_SHUTDOWN
26 IN
34 SIM_RST 7 27

SIM_DET 33 IN 31
PP1V8_SENSOR_FILT
MAKE_BASE=TRUE
CONN_PP1V8_SENSOR_FILT
31 OUT
32 SIM_IO 27 27

24 CONN_AUD_HS_MIC1_HI 31 BI 31
PP2V85_CAM_REAR
MAKE_BASE=TRUE
CONN_PP2V85_CAM_REAR
OUT 30 CONN_AUD_HS_RET1 27 27

CONN_AUD_HS_MIC1_LO 29 OUT 24
DMIC_SD_SENSOR
MAKE_BASE=TRUE
CONN_DMIC_SD_SENSOR
C CONN_AUD_HS_RET2
C
24 OUT 19 27
28
CONN_AUD_HP1_MLBCON_R 27 OUT 24
DMIC_SCLK_SENSOR
MAKE_BASE=TRUE
CONN_DMIC_SCLK_SENSOR
24 IN 26 CONN_AUD_HP1_MLBCON_L 19 27

24 OUT CONN_AUD_HP1_DET_H 25 IN 24
ISP_AP_0_SCL
MAKE_BASE=TRUE
CONN_ISP_AP_0_SCL
24 DMIC_SCLK_CANADA 39 7 27

IRQ_ALS_INT_CONN_L 23 IN 19
ISP_AP_0_SDA
MAKE_BASE=TRUE
CONN_ISP_AP_0_SDA
26 OUT
22 I2C2_SCL_3V0_ALS IN
39 7 27

39 26 I2C2_SDA_3V0_ALS 21
26 39
I2C2_SCL_3V0
MAKE_BASE=TRUE
CONN_I2C2_SCL_3V0
BI 20 DMIC_SD_CANADA 39 26 5 27
TP612
39 26 BI ISP_CAM_1_SDA 19 OUT 19
I2C2_SDA_3V0
MAKE_BASE=TRUE
CONN_I2C2_SDA_3V0
18 ISP_CAM_1_SCL 39 26 5 27
TP608
IN PM_FRONT_CAM_SHUTDOWN_FILT 17 IN 26 39
IRQ_ACCEL_INT1_L
MAKE_BASE=TRUE
CONN_IRQ_ACCEL_INT1_L
26
16 PP3V0_ALS 26
5
MAKE_BASE=TRUE
27

15 IRQ_ACCEL_INT2_L CONN_IRQ_ACCEL_INT2_L
14 CLK_CAM_FF_CONN IN 26 39
5
MAKE_BASE=TRUE
27

13 IRQ_GYRO_INT1 CONN_IRQ_GYRO_INT1
12 PP1V8_CAM_FF 26
5
MAKE_BASE=TRUE
27

11 IRQ_GYRO_INT2 CONN_IRQ_GYRO_INT2
10 PP2V85_CAM_FF 26
TP613 5
MAKE_BASE=TRUE
27

9 I2C1_SCL_1V8 CONN_I2C1_SCL_1V8
8 MIPI1C_CAM_CLK_P IN 26 40
TP635 39 5
MAKE_BASE=TRUE
27

7 I2C1_SDA_1V8 CONN_I2C1_SDA_1V8
6 MIPI1C_CAM_CLK_N IN 26 40
TP636 39 5
MAKE_BASE=TRUE
27

5 IRQ_HALL CONN_IRQ_HALL
4 MIPI1C_CAM_DATA_P<0> BI 26 40
TP637 35
MAKE_BASE=TRUE
27

3 IRQ_PROX_INT_L CONN_IRQ_PROX_INT_L
2 MIPI1C_CAM_DATA_N<0> BI 26 40
TP638 5
MAKE_BASE=TRUE
27

1 TP639 27 PP3V0_S2R_HALL_FILT CONN_PP3V0_S2R_HALL 27


MAKE_BASE=TRUE
35 5 ONOFF_L CONN_ONOFF_FTR_L 27
MAKE_BASE=TRUE
38 35 5 SRL_L CONN_SRL_FTR_L 27
MAKE_BASE=TRUE
40 5 AUD_VOL_UP_L CONN_AUD_VOL_UP_FTR_L 27
MAKE_BASE=TRUE
5 AUD_VOL_DOWN_L CONN_AUD_VOL_DOWN_FTR_L 27
MAKE_BASE=TRUE
F-RT-SM
502250-8237 27 PP3V0_OPTICAL_SENS CONN_PP3V0_OPTICAL_SENS 27
MAKE_BASE=TRUE

B B

A SYNC_MASTER=MARK B. SYNC_DATE=N/A A
PAGE TITLE

CONNECTOR: CANADA FLEX CONN,SENSOR PANEL ALIASES


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 25 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6MM L5540
TP615 MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
240-OHM-0.2A-0.8-OHM
MAX_NECK_LENGTH=3 MM
PP3V0_ALS 1 2 =PP3V0_OPTICAL
D
25
0201
5 27 32

PPVSIM
1 C5542 1 C5540 1 C5541 FILTER PLACEHOLDER
31 25
1000PF 1UF 82PF
10% 10% 5%
2 16V 2 10V 2 25V
1 C5530 X7R
201
X5R
402
CERM
0201
0.1UF
10%
6.3V
2 X5R
201
CANADA FLEX CONN ON PG 54
VOLTAGE=1.8V
VOLTAGE=2.85V
MIN_LINE_WIDTH=0.3MM L5510
L5520 MIN_LINE_WIDTH=0.6 mm PP1V8_CAM_FF 25 MIN_NECK_WIDTH=0.2MM 240-OHM-0.2A-0.8-OHM
240-OHM-0.2A-0.8-OHM MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
MAX_NECK_LENGTH=3 MM PP2V85_CAM_FF 1 2 =PP2V85_CAM
32 26 =PP1V8_CAM 1 2 25
0201
27 32

0201

1 C5521 1 C5520 1 C5522


FILTER PLACEHOLDER 82PF 1UF 1000PF
5% 10% 10%
2 25V
CERM 2 10V
X5R 2 16V
X7R
1 C5512 1 C5510 1 C5511 FILTER PLACEHOLDER
0201 402 201 1000PF 1UF 82PF
10% 10% 5%
16V
2 X7R 2 10V 2 25V
X5R CERM
201 402 0201

C C

CANADA FLEX SIGNAL FILTERS

R5510
1
0 2
NOSTUFF

B 5%
1/20W
B
31 IN SIM_CLK SIM_CLK_FILT OUT 25 MF
201
L5500
90-OHM-50MA
TCM0605
SYM_VER-1

1 4 MIPI1C_CAM_CLK_P OUT 25 40

U5500 2 3 MIPI1C_CAM_CLK_N OUT 25 40


TP509 800MHZ-100MA-27PF
0603 TP25 TP26 R5511
0
5 IRQ_ALS_INT_L 1 IN1 OUT1 5 IRQ_ALS_INT_CONN_L 25 1 2
OUT IN
40 7 IN MIPI1C_AP_CLK_P 5% MF
2 IN2 OUT2 6 1/20W 201 NOSTUFF
TP586 MIPI1C_AP_CLK_N
I2C2_SDA_3V0 3 IN3 OUT3 7 I2C2_SDA_3V0_ALS 40 7 IN
R5512
39 25 5 BI BI 25 39
MIPI1C_AP_DATA_P<0>
39 7 CLK_CAM_FF 4 IN4 OUT4 8 CLK_CAM_FF_CONN 25 39
40 7 BI
0 NOSTUFF
IN
NOSTUFF OUT
40 7 BI MIPI1C_AP_DATA_N<0> 1 2
5% MF
1 C5501 GND 1/20W 201
1000PF TP587
TP23 TP24
L5501
9
10

10%
16V
2 X7R 90-OHM-50MA
201 TP605
TCM0605
SYM_VER-1

1 4 MIPI1C_CAM_DATA_P<0> BI 25 40

32 26 =PP1V8_CAM
2 3 MIPI1C_CAM_DATA_N<0> BI 25 40
1
R5501 R5513
100K
5%
1/20W TP20
U5501 TP611
1
0 2
MF 800MHZ-100MA-27PF
0603 5% NOSTUFF
2 201
A 39 25 5

39 7
IN I2C2_SCL_3V0
ISP_AP_1_SDA
1
2
IN1
IN2
OUT1 5
OUT2 6
I2C2_SCL_3V0_ALS
ISP_CAM_1_SDA
OUT
25 39
25 39
1/20W
MF
201 SYNC_MASTER=MARK B. SYNC_DATE=N/A A
BI BI PAGE TITLE
PM_FRONT_CAM_SHUTDOWN PM_FRONT_CAM_SHUTDOWN_FILT
39 7
7 IN
IN ISP_AP_1_SCL
3
4
IN3
IN4
OUT3 7
OUT4 8 ISP_CAM_1_SCL OUT 25 39
OUT 25
CONNECTOR: CANADA FLEX FILTERS
DRAWING NUMBER SIZE
TP8 NOSTUFF GND
Apple Inc. 051-8962 D
1 C5500 TP614
REVISION
9
10

100PF
5%
R
A.0.0
2 25V NOTICE OF PROPRIETARY PROPERTY:
TP607
CERM BRANCH
201 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 26 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TP53
R5600 TP544

0
D 39 7 IN CLK_CAM_RF 1
5%
2 CLK_CAM_RF_FILT
NOSTUFF D
1/20W
MF
201
1 C5600
1000PF
10%
16V
2 X7R
R5610 201
0 NOSTUFF
1 2
5% MF
1/20W 201

L5600
90-OHM-50MA
TP30 TCM0605
SYM_VER-1

1 4

2 3
R5611
1
0 2
TP31
5% NOSTUFF
1/20W
MF
201
40 7 IN MIPI0C_AP_DATA_N<0>
40 7

40 7
BI
IN
MIPI0C_AP_DATA_P<0>
MIPI0C_AP_CLK_N
MIPI0C_AP_CLK_P
R5612
1
0
2
NOSTUFF
SENSOR PANEL CONNECTOR
CABLINE-CA CONNECTOR: 518S0787
40 7 BI
5% MF
1/20W 201

L5601
90-OHM-50MA CRITICAL
TCM0605
SYM_VER-1
J5600
C 1 4 CABLINE-CA
F-RT-SM
C
2 3 31
R5613
0 25 39
25 CONN_PP2V85_CAM_REAR 1
1 2 MIPI0C_CAM_DATA_N<0> 25 40
2
25 CONN_PP1V8_SENSOR_FILT
5% NOSTUFF MIPI0C_CAM_DATA_P<0> 25 40
1/20W 3
MF 4
201 25 CONN_CLK_CAM_RF_FILT
MIPI0C_CAM_CLK_N 25 40
5
25 CONN_ISP_AP_0_SCL
MIPI0C_CAM_CLK_P 25 40
6
25 CONN_ISP_AP_0_SDA
25 CONN_PM_REAR_CAM_SHUTDOWN 7

25 CONN_MIPI0C_CAM_DATA_N<0> 8
L5610 TP568
25 CONN_MIPI0C_CAM_DATA_P<0> 9
240-OHM-0.2A-0.8-OHM CONN_MIPI0C_CAM_CLK_N 10
25

32 =PP3V0_S2R_HALL 1 2 PP3V0_S2R_HALL_FILT 25 25 CONN_MIPI0C_CAM_CLK_P 11


0201 VOLTAGE=3.0V 25 CONN_IRQ_HALL 12
MIN_LINE_WIDTH=0.6 mm
C5601 C5602 C563
CONNECTED BY
1 1 1 MIN_NECK_WIDTH=0.2 mm 25 CONN_I2C1_SDA_1V8 13
82PF 1UF 1000PF NET_SPACING_TYPE=PWR 14
MAX_NECK_LENGTH=3 MM 25 CONN_I2C1_SCL_1V8
5% 10% 10%
2 25V 2 10V 2 16V CONN_IRQ_PROX_INT_L 15

PG 54 ALIASES
CERM X5R X7R 25
0201 402 201 25 CONN_PP3V0_S2R_HALL 16

25 CONN_IRQ_GYRO_INT2 17

25 CONN_IRQ_GYRO_INT1 18
CONN_IRQ_ACCEL_INT1_L 19
L5611 TP532
25

CONN_IRQ_ACCEL_INT2_L 20
240-OHM-0.2A-0.8-OHM 25

25 CONN_I2C2_SCL_3V0 21
32 =PP1V8_SENSOR 1 2 PP1V8_SENSOR_FILT 25
CONN_I2C2_SDA_3V0 22
B 0201
1 C5612 1 C5613 1 C5620
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
25

25 CONN_AUD_VOL_DOWN_FTR_L 23
24
B
82PF 1UF 1000PF NET_SPACING_TYPE=PWR 25 CONN_AUD_VOL_UP_FTR_L
MAX_NECK_LENGTH=3 MM
5% 10% 10% CONN_SRL_FTR_L 25
25V
2 CERM
10V
2 X5R
16V
2 X7R
25

CONN_ONOFF_FTR_L 26
0201 402 201 25
TP531
25 CONN_DMIC_SD_SENSOR 27

25 CONN_DMIC_SCLK_SENSOR 28
TP545 TP576 29
CONN_PP3V0_OPTICAL_SENS 30
L5613 TP28
25

240-OHM-0.2A-0.8-OHM
33
32 26 =PP2V85_CAM 1 2 PP2V85_CAM_REAR 25
34
0201 VOLTAGE=3.3V
1 C5617 1 C5618 1 C5621 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
35
82PF 1UF 1000PF NET_SPACING_TYPE=PWR 36
5% 10% 10% MAX_NECK_LENGTH=3 MM
25V
2 CERM 2 X5R
10V 16V
2 X7R 37
0201 402 201 38
39
40
41

L5612 TP598
32
240-OHM-0.2A-0.8-OHM

32 26 5 =PP3V0_OPTICAL 1 2 PP3V0_OPTICAL_SENS 25
0201 VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1 C5614 1 C5615 1 C5616 1 C5623 NET_SPACING_TYPE=PWR
82PF 1UF 0.1UF 1000PF MAX_NECK_LENGTH=3 MM

A
5% 10% 10% 10%
25V
2 CERM
0201
10V
2 X5R
402
2 X5R
6.3V
201
2 X7R
16V
201 SYNC_MASTER=MARK B.
PAGE TITLE
SYNC_DATE=N/A A
CONNECTOR: SENSOR PANEL CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
56 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 27 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VOLTAGE=5V
L5757
USB MIN_LINE_WIDTH=4.1MM FERR-70-OHM-4A
MIN_LINE_WIDTH=4.1MM
MIN_NECK_WIDTH=0.2MM
TP193
JTAG DEVELOPMENT_JTAG

PPVBUS_USB_EMI
MIN_NECK_WIDTH=0.2MM
1 2
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PPVBUS_USB_PT_DK_CONN
ANALOG VIDEO FL5711 R5730 (JTAG_TCK)
32 29
80-OHM-0.2A-0.4-OHM TP217 0
0603 JTAG_AP_TCK 1 2 PT_DK_CON_P14
2
39 4 IN 29
1 C5721 1 C5722 1
R5790 DZ5760 1 C5750 1 C5783 40 11 10 IN VIDEO_EMI_CVBS_PB 1 2 VIDEO_PT_DK_CON_CVBS_PB 28 29 40 39 4 IN JTAG_AP_TMS 1 2 PT_DK_CON_P17 29
27PF 12PF 100K 27V-100PF 27PF 0.01UF 0201 0 (JTAG_TMS)
5% 5% 5% 10%
2 25V
NP0-C0G 2 25V
NP0-C0G
5%
1/20W
0402
2 25V
NP0-C0G 2 25V
X7R TP268
FL5707 R5731
DEVELOPMENT_JTAG
201 201 MF 201 402 80-OHM-0.2A-0.4-OHM DEVELOPMENT_JTAG
2 201 1
40 11 10 IN VIDEO_EMI_C_Y 1 2 VIDEO_PT_DK_CON_C_Y 28 29 40
1
R5795 DEVELOPMENT_JTAG
0201
523K
FL5708
1%
1/32W U5730

D TP212
L5716
90-OHM-50MA
TCM0605
NOTE: MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V
80-OHM-0.2A-0.4-OHM
1 2 32 5
=PP1V8_S2R_MISC
MF
2 01005
B1 REF
MAX9061
UCSP D
SYM_VER-1 40 11 10 IN VIDEO_EMI_Y_PR VIDEO_PT_DK_CON_Y_PR 28 29 40

USB_D_P 1 4 USB_PT_DK_CON_D_P 0201 U5730_IN A2 IN OUT A1 RST_AP_L


39 4 BI 29 39 OUT 4 31 35

TP258 TP200 DEVELOPMENT_JTAG


GND
USB_D_N 2 3 USB_PT_DK_CON_D_N
TP198
VIDEO_PT_DK_CON_Y_PR 28 29 40
1 C5730
0.1UF DEVELOPMENT_JTAG

B2
39 4 BI 29 39

NC_D5703_6 VIDEO_PT_DK_CON_C_Y 28 29 40 10% 1


VIDEO_PT_DK_CON_CVBS_PB 28 29 40
2 6.3V
X5R
R5796
TP214
201 1.00M
6 AV_PT_DK_CON_RET 29 1%
TP201 1/32W
VBUS CRITICAL MF
IO 4 TP213 OMIT U5700 2 01005
NUP412VP5XXG
TP211
5 IO NC 3 XW5700 SOT953 NOTE:
2 NC SM
JTAG_AP_TMS = 3.3V: U5730S IN = 2.13V
28 AUDIO_PT_DK_RET 1 2 1 5
D5703 JTAG_AP_TMS = 1.8V: U5730S IN = 1.16V
2
RCLAMP0502N TP219
TP199
SLP1210N6 GND
1 3 4

LINEOUT
TP220

TP500 L5760
FERR-120-OHM-1.5A
AUDIO_EMI_LO_L 1 2 AUDIO_PT_DK_CON_LO_L
ACCESSORY DISPLAYPORT 21 IN
0402
29

L5700
12-OHM-100MA-8.5GHZ
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM
VOLTAGE=3.3V TP168 TP425 TP173
MIN_LINE_WIDTH=0.3MM TCM0806-4SM 2
L5714 MIN_NECK_WIDTH=0.1MM SYM_VER-1

FERR-120-OHM-1.5A MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR DP_EMI_TX_P<0> 1 4 DP_PT_DK_CON_TX_P<0> DZ5710
1 2
40 13 IN 29 40
UCLAMP0511Z
32 =PP3V3_PORT_ACC ACC_PT_DK_CON_PP3V3 29 0201

C 0402

0.095 OHM DCR


2
DZ5790 1 C5751 1 C5782 40 13 IN DP_EMI_TX_N<0> 2 3 DP_PT_DK_CON_TX_N<0>
NC_D5700_6
29 40
1
C
8V-100PF 27PF 0.01UF
0201 5% 10%
2 25V
NP0-C0G 2 10V
X5R
TP424
6 TP174
201 201 TP221
1 VBUS
IO 4
TP501 L5761
FERR-120-OHM-1.5A
5 IO NC 3
21 AUDIO_EMI_LO_R 1 2 AUDIO_PT_DK_CON_LO_R 29
2 NC IN
32 =PPVCC_MAIN_DOCK 0402 MIN_LINE_WIDTH=0.1MM
D5700 MIN_NECK_WIDTH=0.07MM
2
1
R5750 RCLAMP0502N DZ5711
220K SLP1210N6 GND
UCLAMP0511Z
5% 1 0201
1/20W
MF 1
2 201 TP175

R5751 L5701
12-OHM-100MA-8.5GHZ
TP215
1
10K 2
TCM0806-4SM
35 OUT PORT_DOCK_ACC_DET_L ACC_PT_DK_CON_DET_L 29
SYM_VER-1

5% DP_EMI_TX_P<1> 1 4 DP_PT_DK_CON_TX_P<1>
1/20W 2
40 13 IN 29 40
L5762
MF 1 C5752 TP504
22-OHM-25%-900MA TP218
201 DZ5753 27PF
6.8V-100PF 5% 40 13 IN DP_EMI_TX_N<1> 2 3 DP_PT_DK_CON_TX_N<1> 29 40 21 IN AV_EMI_DIFF_SENSE 1 2 AV_PT_DK_CON_DIFF_SENSE 29
0201 2 25V
NP0-C0G MIN_LINE_WIDTH=0.1MM
NC_D5701_6 0201 MIN_NECK_WIDTH=0.07MM
201
1
2
TP216
6 DZ5712
VBUS 6.8V-100PF
IO 4 0201 1
R5752
TP196
R5740
PLACE BY PMU
PMU_ADC_REF 1
100K 2 TP197
5 IO
2 NC
NC 3 1
100
35 5%
1/20W

B B
1%
1/20W D5701 MF
2 201
MF RCLAMP0502N
TP228
R5753 201 TP202
SLP1210N6 GND L5763
10K 1
TP503
30-OHM-1.7A
35 OUT PORT_DOCK_ACCID
1 2 ACC_PT_DK_CON_ID 29

5% C 21 GND_AUDIO_PT_DK 1 2 AUDIO_PT_DK_RET 28
IN
1/20W
MF
1 C5760 0201
14.2V-6PF 1 C5753 0402 MIN_LINE_WIDTH=0.6MM
201 0.01UF 27PF L5702 MIN_NECK_WIDTH=0.2MM
10%
16V DZ5752 5% TP210 90-OHM-50MA
TCM0605
2 X5R-CERM
A 2 25V
NP0-C0G
SYM_VER-1
0201
201 DP_EMI_AUX_P 1 4 DP_PT_DK_CON_AUX_P
40 13 IN 29 40

40 13 DP_EMI_AUX_N 2 3 DP_PT_DK_CON_AUX_N 29 40
IN
NC_D5702_6
FIREWIRE DETECT/ DISPLAYPORT HPD
TP209

R5720 TP207 6 R5710 TP226

0 VBUS FW_ZENER_PWR 47K


USB_FS_N_ACC_TX 1 2 ACC_PT_DK_CON_TX IO 4 35 13 OUT
1 2 FW_PT_DK_CON_PWR 29
39 11 IN 29 39 TP204
5 IO 5%
5% NOSTUFF NC 3
1/20W TP205 1/20W
MF
1 C5780
MF
201
TP203 1 C5754 2 NC 201 0.01UF
27PF 2
DZ5720 10%
5%
25V
D5702 GDZT2R5.1B
50V
2 X7R
2 NP0-C0G RCLAMP0502N GDZ-0201 402
A1 B1 201 SLP1210N6 GND 1
1
DZ5751
USBULC6-2F3
BGA
A2 B2

A TABLE_ALT_HEAD
SYNC_MASTER=JAMES SYNC_DATE=N/A A
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PAGE TITLE
R5721
0
TP206
PART NUMBER
TABLE_ALT_ITEM
IO FLEX: DOCK COMPONENTS
39 11 OUT USB_FS_P_ACC_RX 1 2 ACC_PT_DK_CON_RX 29 39 377S0090 377S0081 DZ5751 ? DRAWING NUMBER SIZE
5%
1/20W
NOSTUFF
377S0111 377S0099 RADAR:8379541
TABLE_ALT_ITEM

Apple Inc. 051-8962 D


MF
201
1 C5755 DZ5710,DZ5711
REVISION
27PF R
A.0.0
TABLE_ALT_ITEM

TP208
5% 377S0107 377S0066 D5700,D5701,D5702,D5703 RADAR:8289785
2 25V
NP0-C0G
TABLE_ALT_ITEM

NOTICE OF PROPRIETARY PROPERTY: BRANCH


201 155S0625 155S0559 L5700,L5701 RADAR:8423156
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
57 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 28 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

DOCK CONNECTOR
PN 516S0817 (PLUG - MALE)
CRITICAL
J5900
TP194 AXK844135WG
M-ST-SM

C 28 PPVBUS_USB_PT_DK_CONN 2
4
1
3 USB_PT_DK_CON_D_P
C
BI 28 39
6 5 USB_PT_DK_CON_D_N
TP170 TP171 BI 28 39
8 7
TP195
10 9
12 11 DP_PT_DK_CON_TX_P<0> IN 28 40
14 13 DP_PT_DK_CON_TX_N<0> 28 40
IN
16 15
18 17
20 19 DP_PT_DK_CON_TX_P<1> 28 40
IN
VIDEO_PT_DK_CON_CVBS_PB 22 21 DP_PT_DK_CON_TX_N<1>
40 28 IN IN 28 40

VIDEO_PT_DK_CON_C_Y 24 23
40 28 IN
VIDEO_PT_DK_CON_Y_PR 26 25 AV_PT_DK_CON_DIFF_SENSE
40 28 IN OUT 28

ACC_PT_DK_CON_ID 28 27 AUDIO_PT_DK_CON_LO_L
28 OUT IN 28

(DP_HPD) 28 OUT FW_PT_DK_CON_PWR 30 29 AUDIO_PT_DK_CON_LO_R 28


IN
ACC_PT_DK_CON_PP3V3 32 31 AV_PT_DK_CON_RET
28 OUT 28
34 33 ACC_PT_DK_CON_DET_L OUT 28

(JTAG_TCK) 28 PT_DK_CON_P14 36 35 DP_PT_DK_CON_AUX_P 28 40


IN BI
(JTAG_TMS) PT_DK_CON_P17 38 37 DP_PT_DK_CON_AUX_N
28 IN BI 28 40

ACC_PT_DK_CON_RX 40 39
39 28 OUT
39 28 ACC_PT_DK_CON_TX 42 41 HOME_L 5 29 35
IN OUT
44 43
TP417

B B

35 29 5 OUT HOME_L

DZ5750
6.8V-100PF
0201
1

A SYNC_MASTER=JAMES SYNC_DATE=N/A A
PAGE TITLE

IO FELX: B2B Connector


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
59 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 29 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

X23 WIFI/BT CONNECTOR

D D

TP303
L6000
22-OHM-25%-0.5A-0.20DCR
PPVCC_MAIN_WL_CONN 1 2 =PPVCC_MAIN_WL 32
VOLTAGE=4.7V 0603
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM C6000 1
NET_SPACING_TYPE=PWR 68PF
MAX_NECK_LENGTH=3 MM 5%
25V
CERM 2
201

516S0884 L6001
C TP321
J6000
AXT530224
TP302

PP1V8_S2R_WL_CONN
22-OHM-25%-0.4A-0.35DCR C
F-ST-SM
1 2 =PP1V8_S2R_WL 32
VOLTAGE=1.8V 0402
35 IN RST_WLAN_L 1 2 MIN_LINE_WIDTH=0.6MM C6001 1
MIN_NECK_WIDTH=0.2MM
35 OUT PM_WLAN_HOST_WAKE 3 4 NET_SPACING_TYPE=PWR 68PF
MAX_NECK_LENGTH=3 MM 5%
35 IN RST_BT_L 5 6 25V
2
CERM
35 OUT PM_BT_HOST_WAKE 7 8 201
5 IN PM_BT_WAKE 9 10
TP319
TP373 TP322 11 12 TP301

UART_AP_3_RXD TP320
13 14 SDIO_WL_CLK
10 OUT IN 5 40
UART_AP_3_TXD 15 16
10 IN TP318
10
UART_AP_3_CTS_L 17 18 SDIO_WL_CMD 5 40
OUT BI
UART_AP_3_RTS_L 19 20 SDIO_WL_DATA<3>
10 IN BI 5 40

TP422
? TP421 TP337 TP336
21 22 SDIO_WL_DATA<2> BI 5 40

39 19 5 IN I2S_AP_2_BCLK 23 24 SDIO_WL_DATA<1> BI 5 40

39 19 5 IN I2S_AP_2_DOUT 25 26 SDIO_WL_DATA<0> BI 5 40

39 19 5 OUT I2S_AP_2_DIN 27 28
TP305
39 19 5 IN I2S_AP_2_LRCK 29 30 CLK_32K_WLAN IN 35 39

TP300

TP335 TP304 TP96

TP338 TP339 TP340 TP341

B B

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

CONNECTOR: X23 WIFI/BT


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
60 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 30 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

X24 CELLULAR/GPS CONNECTOR

D D

998-3141
J6100
CELL-MODULE-X24
HB-SM
OMIT
TP9 SNSV_BATT_POS_ACF 1
32 =BATT_POS_F_3G 2
1
R6100 3
255K 4
1%
1/32W 5
TP359 MF
6
2 01005
7
35 OUT ADC_IN7
35 28 4 OUT RST_AP_L 8
TP10 PM_RADIO_ON 9
NOSTUFF 1 R6101 TP633
5 IN
RST_BB_PMU_L 10
C6100 1
1%
255K TP626
35 IN
GSM_TXBURST_IND 11
0.01UF 1/32W
5 OUT
10%
6.3V 2 MF 5 IN RST_BB_L 12
X5R 2 01005 TP15 RST_DET_L 13
01005 5 OUT
TP632
14
40 5 IN SPI_IPC_MRDY 15
TP458
5 OUT SPI_IPC_SRDY 16

C TP5
40 5

40 5
IN
IN
SPI_IPC_SCLK
SPI_IPC_MOSI
17
18
C
TP627
40 5 OUT SPI_IPC_MISO 19
TP625
5 OUT IPC_GPIO 20
TP12
35 OUT PM_BB_HOST_WAKE 21
TP4 22
TP11
35 IN BB_VBUS_DET 23
39 11 BI USB_BB_D_P 24
TP624
39 11 BI USB_BB_D_N 25
TP622 26
TP14
10 IN UART_AP_1_RXD 27
TP468
10 OUT UART_AP_1_TXD 28
TP621
10 OUT UART_AP_1_CTS_L 29
TP3 10 IN UART_AP_1_RTS_L 30
TP466
10 OUT UART_AP_2_RXD 31
TP617
10 IN UART_AP_2_TXD 32
TP16 33
TP353

32 =PP1V8_S2R_GPS 34
TP2 RST_GPS_L 35
5 IN
5 IN PM_GPS_STANDBY_L 36
TP465
10 OUT UART_AP_4_RXD 37
TP19 10 IN UART_AP_4_TXD 38
TP455
10 OUT UART_AP_4_CTS_L 39
TP18
10 IN UART_AP_4_RTS_L 40
5 IN GPS_SYNC 41
TP17
5 OUT IRQ_GPS_INT_L 42
TP351
CLK_32K_GPS
B B
39 35 IN 43
NET_SPACING_TYPE=PWR VOLTAGE=1.2V
44
MIN_NECK_MIDTH SHOULD BE 0.2MM MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 MM

26 25 PPVSIM MIN_NECK_WIDTH=0.1 MM
45
25 IN SIM_DET 46
25 OUT SIM_RST 47
26 OUT SIM_CLK 48
25 BI SIM_IO 49

TP350
50

TP1 TP6 TP7


TP13

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

CONNECTOR: X24 CELLULAR/GPS


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
61 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 31 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

POWER CONN / ALIAS


LDO RAILS BUCK RAILS CHARGER MAIN
PROGRAMMABLE ON/OFF

TP570
34 PP1V2_SOC =PPVDD_SOC_H4 9
MAKE_BASE=TRUE
PPVCC_MAIN =PPVCC_MAIN_AUDIO
D 34 PP3V0_S2R_HALL
MAKE_BASE=TRUE
VOLTAGE=3.0V
=PP3V0_S2R_HALL
=PP3V0_S2R_HALL_CHSW
27
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR MIN_NECK_MIDTH SHOULD BE 0.2MM
35 34
MAKE_BASE=TRUE
VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6MM
=PPVCC_MAIN_WL
19 20

30 D
MIN_LINE_WIDTH=0.4 MM
23
MAX_NECK_LENGTH=0.8 MM MIN_NECK_WIDTH=0.2MM =PPVCC_MAIN_DOCK 28
MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM =PPVCC_MAIN_LED 35
MAX_NECK_LENGTH=3 MM

34 PP1V7_VA_VCP =PP1V7_VA_VCP 19
MAKE_BASE=TRUE
VOLTAGE=1.7V 34 PP1V2_CPU =PPVDD_CPU_H4 9
MIN_LINE_WIDTH=0.4MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V
NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.1 MM MIN_NECK_MIDTH SHOULD BE 0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.8 MM
34 PP3V0_VIDEO =PP3V0_VIDEO_BUFFER 11
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_VIDEO_H4 7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 34 PP1V2_S2R =PP1V2_S2R_H4 8
NET_SPACING_TYPE=PWR MAKE_BASE=TRUE
VOLTAGE=1.2V

34
MAX_NECK_LENGTH=3 MM

PP3V0_OPTICAL
TP578

=PP3V0_OPTICAL 5 26 27
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR
MIN_NECK_MIDTH SHOULD BE 0.2MM BATTERY
MAKE_BASE=TRUE MAX_NECK_LENGTH=0.8 MM TP634
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm TP600 37 34 PPBATT_VCC =BATT_POS_F_3G 31
NET_SPACING_TYPE=PWR MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM 34 PP1V8_S2R =PP1V8_S2R_H4 8 VOLTAGE=4.2V =BATT_POS_CONN 33
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.8V =PP1V8_S2R_WL MIN_NECK_WIDTH=0.15 MM
PP3V2_SD MIN_LINE_WIDTH=0.6MM
30
NET_SPACING_TYPE=PWR
34 BI
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM =PP1V8_S2R_GPS 31 MAX_NECK_LENGTH=1.7 MM
VOLTAGE=3.2V NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM =PP1V8_S2R_MISC 5 28
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

34 PP3V3_ACC =PP3V3_PORT_ACC 28
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

C 34 PP3V0_VIDEO_BUF
MAKE_BASE=TRUE
VOLTAGE=3.0V
=PP3V0_VIDEO_BUF 11
34 PP1V8
MAKE_BASE=TRUE
=PP1V8_CAM 26
C
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.8V =PP1V8_SENSOR 27
MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM =PP1V8_AUDIO 19
MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.8 MM =PP1V8_H4 4 5 7 10 13 USB POWER INPUT
34 PP3V2_S2R_USBMUX =PP3V2_S2R_USBMUX 11
MIN_NECK_MIDTH SHOULD BE 0.2MM =PP1V8_VDDIO18_H4 8 9
MAKE_BASE=TRUE
VOLTAGE=3.2V =PP1V8_MIPI_H4 7
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm =PP1V8_DPORT_H4 7
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM 28 PPVBUS_USB_EMI PPVBUS_USB_DCIN 34
MAKE_BASE=TRUE
34 PP3V0_IO =PP3V0_IO_H4 7 9
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_IO_MISC 13
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM 34 PP3V3_OUT =PP3V3_NAND 12
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_USB_H4
34 PP2V85_CAM =PP2V85_CAM 26 27 MIN_LINE_WIDTH=0.6MM
4

MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1MM =PP3V3_MLC_HI 36


VOLTAGE=2.85V NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM MAX_NECK_LENGTH=0.8 MM =PP3V3_LCD 16
MIN_NECK_WIDTH=0.2MM MIN_NECK_MIDTH SHOULD BE 0.2MM
NET_SPACING_TYPE=PWR =PP3V3_NAND_H4 10
MAX_NECK_LENGTH=3 MM

34 PP3V0_GRAPE =PP3V0_GRAPE 17 18
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_GRAPE_Z1 18
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm =PP3V0_GRAPE_Z2 18
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM =PP3V0_GRAPE_MARIO1 17 35 PPLED_OUT =PPLED_REG 16
MAKE_BASE=TRUE
VOLTAGE=20.4V
34 PP1V1 =PP1V1_PLL_H4 4 MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM
VOLTAGE=1.1V =PP1V1_MIPI_H4 7
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM =PP1V1_DPORT_H4 7
NET_SPACING_TYPE=PWR
=PP1V1_USB_H4
B
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_MIDTH SHOULD BE 0.2MM =PP1V1_MIPI_PLL_H4
4

4 B
34 PP1V8_ALWAYS =PP1V8_ALWAYS 5
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR 36 PP3V3_MLC_OUT =PP3V3_MLC 14 16
MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
TP419 TP427

34 PP1V2 =PP1V2_VDDQ_H4 8
MAKE_BASE=TRUE
VOLTAGE=1.2V =PP1V2_VDDIOD_H4 8
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM =PP1V2_HSIC_H4 4
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.8 MM
MIN_NECK_MIDTH SHOULD BE 0.2MM
GND
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.10MM
NET_SPACING_TYPE=GND
MAX_NECK_LENGTH=5 MM

A SYNC_MASTER=YOSH SYNC_DATE=N/A A
PAGE TITLE

POWER: ALIASES
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
73 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

TP388
XW7520
MIN_NECK_MIDTH SHOULD BE 0.2MM SM
34 BATT_SNS 1 2
NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.15 MM

32 =BATT_POS_CONN

TP7500
1 CRITICAL
A
TP-P55 J7500
NOSTUFF
C TP34
FL7500
240-OHM-0.2A-0.8-OHM
BATT-K93
F-ST-SM
7 C
35 5 BI BATTERY_SWI 1
0201-1
2 BATT_SWI_CONN
BATT_NTC_CONN
5
NOTE:
VERIFY PINOUT OF
NET_SPACING_TYPE=ANLG
1
POS
R7541 2

BATTERY CONNECTOR
0 HDQ
35 BI BATTERY_NTC 1 2 C7522 1 C7523 1 C7524 1 C7525 1 3
THERM
NET_SPACING_TYPE=ANLG
5% MF 33PF 33PF 1000PF 82PF 4
1/20W 201 5% 5% 10% 5% GND

VERIFY MOUNTING CONN TO GND


25V 25V 16V 25V
TP35
NOTE: GET RID OF THE NP0-C0G 2 NP0-C0G 2 X7R 2 CERM 2
201 201 201 0201 6
RES AFTER BRINGUP 8
TP32 APN:516-0240
TP7501
A 1
TP-P55
NOSTUFF
TP7502
A 1
TP-P55
NOSTUFF
TP7503
A 1
TP-P55
NOSTUFF

B B

A SYNC_MASTER=YOSH SYNC_DATE=N/A A
PAGE TITLE

POWER: BATTERY CONNECTOR


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
75 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 33 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
L8100 TP367 TP369 TP370
2.2UH-20%-1.85A-80MOHM
BUCK0_LXL 1 2 PP1V2_CPU 32
MIN_LINE_WIDTH=0.6 MM
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION MIN_NECK_WIDTH=0.25 MM PST25201B-SM
NET_SPACING_TYPE=SWITCHNODE CRITICAL CRITICAL CRITICAL ADDITIONAL DISTRIBUTED
DIDT=TRUE
L8101 C8102 C8103
TABLE_5_ITEM

1 1
343S0542 1 IC,PMU,ALISON,D1946A2,OTPXX,UFBGA292 U8100 CRITICAL
2.2UH-20%-1.85A-80MOHM 22UF 22UF
25UF (NO DE-RATING)
20% 20%
BUCK0_LXM 1 2 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
PST25201B-SM 603 603
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE XW8103
BUCK0_FB 1 2
NET_SPACING_TYPE=ANLG
TABLE_ALT_HEAD

SM

D
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS: MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
NOSTUFF
CRITICAL D
L8105
TABLE_ALT_ITEM

197S0392 197S0299 Y8138 ALT FOUNDRY TP371 TP372


2.2UH-20%-1.85A-80MOHM
BUCK2_LXL 1 2 PP1V2_SOC 32
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM PST25201B-SM
NET_SPACING_TYPE=SWITCHNODE CRITICAL CRITICAL CRITICAL ADDITIONAL DISTRIBUTED
CRITICAL SHIT This bull shits from APPLE have OMIT
DIDT=TRUE
L8107 1 C8107 1 C8108 30UF (NO DE-RATING)
manufacturer of the PMIC and not only! 2.2UH-20%-1.85A-80MOHM 22UF 22UF
L8112 20% 20%
2.2UH-3.5A-54M-OHM BUCK2_LXM 1 2 2 6.3V 2 6.3V
U8100 MIN_LINE_WIDTH=0.6 MM
PST25201B-SM
X5R-CERM
603
X5R-CERM
603
35 34 32 PPVCC_MAIN 1 2 SW_CHGA ALISON-A0-OTPXX MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE CRITICAL
DCR=54MOHM MAX
PIME061E-SM
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM D1946A0-110-00 DIDT=TRUE
L8110
D8100
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
UFBGA 2.2UH-20%-1.85A-80MOHM
1 2 3 SOD-123W G24 (SYM 2 OF 3) CRITICAL
BUCK0_LXL A11 BUCK2_LXR 1 2
S PMEG4030ER
CRITICAL 1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
G25 CHG_A_LX BUCK0_LXM A9
MIN_LINE_WIDTH=0.6 MM
PST25201B-SM
L8115 TP418
CRITICAL
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
2.2UH-20%-1.85A-80MOHM
4 G NC_CHGB H24 BUCK0_FB D9 XW8113
Q8104 H25 CHG_B_LX
DIDT=TRUE

BUCK2_FB 1 2
1 2 PP1V8_S2R 32 34

USB REVERSE VOLTAGE PROTECTION FDMC6683


BATT_SNS L25
A7 NET_SPACING_TYPE=ANLG
SM
PST25201B-SM ADDITIONAL DISTRIBUTED
MLP3.3X3.3 33 VBAT BUCK2_LXL B8 MIN_LINE_WIDTH=0.25 MM
NOSTUFF 14UF (NO DE-RATING)
P25 IBAT_S
MIN_NECK_WIDTH=0.20 MM
XW8117 1 C8117 1 C8118

BUCK
MOSFET FDMC6676BZ D N17 BUCK2_LXM A6 BUCK3_LX 22UF 22UF
MIN_LINE_WIDTH=0.6 MM 1 2
5 RDSON=0.0136@VGS=-2.5V P17 BUCK2_LXR A4 MIN_NECK_WIDTH=0.25 MM
SM
20%
6.3V
20%
6.3V
CHANNEL P-TYPE ID=12.0A
IBAT BUCK2_FB D7
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE NOSTUFF
2 X5R-CERM 2 X5R-CERM
N18 603 603

USB/BAT
RDS(ON) 27 MOHM @-4.5V BUCK3_FB CRITICAL CRITICAL CRITICAL
PPBATT_VCC P18 BUCK3_LX A16
37 34 32

ACT_DIO P24 BUCK3_FB D16


NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM L8119
IMAX 6.9 A MIN_LINE_WIDTH=0.2 MM
ACT_DIO MIN_NECK_WIDTH=0.20 MM 2.2UH-20%-1.85A-80MOHM TP439

TP88 TP362 MIN_NECK_WIDTH=0.1 MM F24


VGS MAX +/- 25V NET_SPACING_TYPE=ANLG TP343 TP344 TP345 TP346
F25 VCENTER_A BUCK4_LXL A14 BUCK4_LXL 1 2 PP1V2_S2R 32 34

BUCK4_LXM B11
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM PST25201B-SM ADDITIONAL DISTRIBUTED
PPVBUS_PROT A22
BUCK4_FB D14
NET_SPACING_TYPE=SWITCHNODE CRITICAL 20UF (NO DE-RATING)
L8121
C
MIN_LINE_WIDTH=0.60MM

C C8121 C8122
DIDT=TRUE
MIN_NECK_WIDTH=0.25MM A23 VBUS_A 1 1

NOSTUFF
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM TP352 NC_VBUS_A_OV_N B24 VBUS_A_OV_N F1 2.2UH-20%-1.85A-80MOHM 22UF 10UF
XW8114
2

DZ8120 VOLTAGE=6V BUCK5_LX 20% 20%


3
2
1

1 CRITICAL J24 F2 BUCK4_LXM 1 2 2 6.3V 6.3V


R8116 BZT52C10LP
SHORT-0201 X5R-CERM 2 X5R
470K Q8123 S LLP CRITICAL 4 PPVBUS_USB 2 1 PMU_VCENTER J25 VCENTER_B H1 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM PST25201B-SM 603
CRITICAL
603
CRITICAL
1% MIN_LINE_WIDTH=0.60MM
1/20W FDMC6676BZ CRITICAL C8124 1 NOSTUFF MIN_NECK_WIDTH=0.25MM P22 BUCK5_BYP J1 (BYPASS RON=0.14 OHM MAX)
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE XW8126
1

MF MLP3.3X3.3 G 4 2.2UF NET_SPACING_TYPE=PWR


P23 VBUS_B J2
NOTE: 10V ZENER BUCK4_FB 1 2
2 201 10% MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
25V
X5R-CERM 2 LAYOUT NOTE: PLACE 1 C8125
N22 VBUS_B_OV_N BUCK5_FB G4
NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
NOSTUFF
SM
805
RIGHT AT THE PIN 10UF NC_VBUS_B_OV_N
MIN_NECK_WIDTH=0.20 MM

CRITICAL
D 10% A10 VLDO1 L1 (150MA; 2.5-3.55V) PP3V0_GRAPE
25V
2 X5R B10 VDD_BUCK0 P3 (100MA; 1.65-1.805V; BUCK3) PP1V7_VA_VCP
32 34
L8128 TP463 TP511 TP514
5

VBUS_PROT_G 805 VLDO2 32 34 2.2UH-20%-3.3A-0.064OHM


PPVBUS_USB_DCIN TP89
CRITICAL A3 VLDO3 P9 (50MA; 2.5-3.3V) PP3V0_VIDEO
32 MIN_LINE_WIDTH=0.20MM 32 34
BUCK5_LX 1 2 PP3V3_OUT
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM (100MA; 1.8-3.3V) 32
LAYOUT NOTE: PLACE B3 VLDO4 N5 PP3V0_OPTICAL
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V R8130 1
NET_SPACING_TYPE=ANLG
RIGHT AT THE PIN B7 VDD_BUCK2 P10 (300MA; 2.5-3.6V) PP3V2_SD
32 34 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM PIME051E-SM ADDITIONAL DISTRIBUTED
VLDO5 DCR=64MOHM MAX 47UF (NO DE-RATING)

LDO
32 34 NET_SPACING_TYPE=SWITCHNODE
220K
TP86
1% B6 VLDO6 K1 (150MA; 2.5-3.6V) PP3V3_ACC 32 34
DIDT=TRUE
1 C8119 1 C8120

VCC-MAIN
1/20W A17 VDD_BUCK3 P4 (50MA; 1.5-3.3V) 22UF 22UF
MF VLDO7 PP3V0_VIDEO_BUF 32 34
XW8132 20% 20%
201 2 A13 P8 (10MA; 2.0-3.55V) PP3V2_S2R_USBMUX 6.3V 6.3V
VLDO8 32 34 BUCK5_FB 1 2 2 X5R-CERM 2 X5R-CERM
NET_SPACING_TYPE=ANLG
B13 VDD_BUCK4 VLDO9 P11 (300MA; 1.2-3.0V) PP3V0_IO 32 34 MIN_LINE_WIDTH=0.25 MM
SM 603 603
E1 P5 (200MA; 2.5-3.55V) PP3V0_S2R_HALL
MIN_NECK_WIDTH=0.20 MM NOSTUFF CRITICAL CRITICAL
VLDO10 32 34
E2 VDD_BUCK5 VLDO11 M1 (200MA; 1.7-3.0V) PP2V85_CAM 32 34
TP610
G1 VLDO12 P6 (150MA; 0.6-1.3V) PP1V1 32 34
G2 ON_BUF M2 PP1V8_ALWAYS 32 34
VDD_BUCK5_BYP
H2
G22 VCC_MAIN_S VBUCK4 B17 PP1V2_S2R 32 34
N19 CPU1V2_SW A18 (RON=0.1 OHM MAX) PP1V2

SWITCH POWER
32
P19 DSP_SW B20 (RON=1 OHM MAX)
DSP_SW
TP8133
1
N20 VCC_MAIN TP
VBUCK3 A19 PP1V8_S2R TP-P55
NOTE: FOR NO BATTERY SITUATION
32 34
P20 NOSTUFF
B TP349 TP87
K2
CPU1V8_SW A20 (RON=0.2 OHM MAX)
WDIG_SW B19 (RON=0.5 OHM MAX)
PP1V8 32

TP8101 B
VDD_LDO1_6 PP1V8_GRAPE 1 TP
37 34 32 PPBATT_VCC 34 32
PP1V8_S2R L4 VDD_LDO2 VBUCK0_SW0_G B21 NC_PMU_VBUCK0_SW0_G TP-P55
NOSTUFF N9
1 C8138 1 C8140 1 C8139 1 C8141 TP561 TP592
NOSTUFF
CRITICAL CRITICAL VBUCK0_SW0_S A21 NC_PMU_VBUCK0_SW0_S

LDO INPUT
VDD_LDO3_5_8 1UF 1UF 1UF 1UF
C8100 1 C8101 1
1 C8135 N4 VDD_LDO4_7 20% 10% 10% 10% ADDITIONAL DISTRIBUTED:
1UF VPUMP B18 PMU_VPUMP 2 6.3V 2 6.3V 2 6.3V 2 6.3V PP1V2: 30UF (NO DE-RATING)
22UF 22UF 10% N10 VDD_LDO9 MIN_LINE_WIDTH=0.30MM
X5R CERM CERM CERM
20% 20% 6.3V 0201 402 402 402
6.3V
X5R-CERM 2
6.3V
X5R-CERM 2
2 CERM
402
TP430 N6 VDD_LDO10
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
PP1V8: 6UF (NO DE-RATING)
MAX_NECK_LENGTH=3 MM
603 603 BATT_POS_RC TP90 35 34 32 PPVCC_MAIN L2 VDD_LDO11 C8137 1 VOLTAGE=4.6V
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM 34 32
PP1V2_S2R N7 VDD_LDO12 0.01UF
R8100 1 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
10%
6.3V 2
0.5 VOLTAGE=4.6V 1 C8136 X5R

XTAL
P1 XTAL1 01005
1% 1UF
1/16W 10% NET_SPACING_TYPE=CRYSTAL
P2 XTAL2
MF
402 2 6.3V
2 CERM
402 CRITICAL LDO BYPASS
Y8138 34 32 PP3V0_GRAPE
32.768K-20PPM-12.5PF NET_SPACING_TYPE=CRYSTAL 34 32 PP1V7_VA_VCP
PMU_XTAL 1 2 PMU_EXTAL TP402
34 32 PP3V0_VIDEO TP429
C8142 1 2012 1 C8143 34 32 PP3V0_OPTICAL TP505
18PF 18PF 34 32 PP3V2_SD TP82
5% 5%
25V 25V PP3V3_ACC
NP0-C0G 2 2 NP0-C0G 34 32 TP167
201 201 PP3V0_VIDEO_BUF
34 32
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
C8150 1 C8149 1 C8148 1 C8146 1 C8145 1 C8144 1 C8147 1
2.2UF 2.2UF 4.7UF 2.2UF 2.2UF 10UF 2.2UF
10% 10% 20% 10% 10% 20% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VCC_MAIN BYPASS X5R 2
402
X5R 2
402
X5R-CERM1 2
402
X5R 2
402
X5R 2
402
CERM-X5R 2
0402
X5R 2
402

TOTAL CAPS = ~400UF


A PLACEMENT_NOTE=PLACE NEAR L8225.1
TP263 TP264 TP265 TP266
(PLACE ONE 1UF CAP AT EACH VDD INPUT) (DISTRIBUTED AND NO DE-RATING) 34 32

34 32
PP3V2_S2R_USBMUX
PP3V0_IO
TP81
SYNC_MASTER=YOSH SYNC_DATE=N/A A
PPVCC_MAIN TP434 PAGE TITLE

POWER: PMU
32 34 35
34 32 PP3V0_S2R_HALL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PP2V85_CAM
C8166
1
C8165 1 1 C8154 1 C8155 1 C8156 1 C8157 1 C8158 1 C8159 1 C8160 1 C8161 1 C8162 1 C8130 1 C8131 1 C8163 1 C8164 34 32

PP1V1
TP585
DRAWING NUMBER SIZE
150UF-0.035OHM
20%
150UF-0.035OHM
20% 20%
10UF 10UF
20% 20%
4.7UF
20% 20%
4.7UF
20%
4.7UF
20% 20%
4.7UF
20% 20%
4.7UF
20%
4.7UF 4.7UF 4.7UF 1.0UF
5%
82PF
5%
18PF 34 32

34 32 PP1V8_ALWAYS
TP451 TP591

Apple Inc. 051-8962 D


6.3V 2 6.3V 2 2 6.3V
X5R 2 6.3V
X5R 2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R 2 25V
CERM 2 25V
NP0-C0G TP404 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL REVISION
POLY-TANT POLY-TANT
CASE-B15G-SM CASE-B15G-SM 603 603 402 402 402 402 402 402 402 402 0201-MUR 0201 201
C8169 1 C8168 1 C8167 1 C8153 1 C8152 1 C8151 1 R
A.0.0
0.22UF 2.2UF 2.2UF 2.2UF 4.7UF 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: CONCERNED ABOUT ESR > 20MOHM 20%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
20%
6.3V
10%
6.3V
X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM1 2 CERM 2 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
TP85 TP259 TP260 TP261 TP262 TP363 TP368 TP383 TP387 TP397 TP399 TP400 TP452 TP457 TP464 0201 402 402 402 402 402
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
81 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TP364
1
R8203
D OMIT
1

10%
C8204
0.1UF 1%
200K
1/20W
D
MF
C8206 PPVCC_MAIN 32 34 35 U8100 6.3V
2 X5R 2 201
1
0.01UF
1
C8207 ALISON-A0-OTPXX 201
10% 0.01UF 1
R8202
6.3V
2 X5R 2
10%
220K
D1946A0-110-00 OMIT
6.3V UFBGA
01005 X5R 1%
01005 1/20W (SYM 1 OF 3) PLACEMENT NOTE: PLACE NEAR PIN K4
MF U8100
2 201 ALISON-A0-OTPXX
C8212 C8209 C8210

DIGITAL INPUT
1 1 1
FW_ZENER_PWR (INTERNAL PULL-DOWN) F22 N2 PMU_IREF 0.1UF 1UF 0.22UF D1946A0-110-00

REFERENCES
28 13 IN FW_DET IREF NET_SPACING_TYPE=ANLG 10% 10% 20%
HOME_L L15 BUTTON1 VREF N1 PMU_VREF 6.3V 6.3V 6.3V PLACEMENT NOTE: PLACE NEAR PIN H22 UFBGA
29 5 IN NET_SPACING_TYPE=ANLG
2 X5R 2 CERM 2 X5R B2 (SYM 3 OF 3)
ONOFF_L L16 BUTTON2 VDD_REF H22 PMU_VDD_REF 201 402 0201 A8
25 5 IN NET_SPACING_TYPE=ANLG
25 5 SRL_L L17 BUTTON3 VDD_REF_A K4 B4 VSS_BUCK02 B9
IN
28 IN PORT_DOCK_ACC_DET_L A2 ACC_DET_A VDD_RTC P7 PMU_VDD_RTC
NET_SPACING_TYPE=ANLG
TP348 PMU_ACC_DET_B A1 ACC_DET_B ADC_REF N8 PMU_ADC_REF 28
C2 A5
NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.1MM
D4 VSS_BUCK2 B5
28 IN PORT_DOCK_ACCID K24 ACC_ID
D11
MIN_NECK_WIDTH=0.1MM
1 C8214 D5 A12

ANALOG
GPIO1 CLK_32K_PMU (1.8 PUSH-PULL) 1000PF

INPUT
USB_BRICKID K22 BRICK_ID OUT 18 39
4 IN
GPIO2 D12 CLK_32K_WLAN (1.8_S2R PUSH-PULL) 10% D6 VSS_BUCK04 B12
ADC_IN7 K25 ADC_IN7 OUT 30 39 6.3V
31 IN D13 X5R A15
TP172
TP358 TP347 GPIO3 RST_BT_L OUT 30 (1.8_S2R;NO PD REQD PER BB TEAM) 2 01005
GPIO4 D18 RST_WLAN_L (1.8_S2R;NO PD REQD PER BB TEAM) VSS_BUCK34 B15

GPIO
(DOCK CONN) BOARD_TEMP1 M25 OUT 30
NET_SPACING_TYPE=ANLG TDEV1 D19 E4 D1
GPIO5 RST_BB_PMU_L (PU TO BATTERY IN BB)

TEMPERATURE
OUT 31
(BETWEEN WLED AND CHARGER) BOARD_TEMP2 NET_SPACING_TYPE=ANLG M24 TDEV2
1 GPIO6 D20 BATTERY_SWI (2.5V ALWAYS ON PU IN BMU) E5 VSS_BUCK5 D2
(H4P) BOARD_TEMP3 L22 IN 5 33
1 NET_SPACING_TYPE=ANLG TDEV3 D15 E6 D10
CRITICAL (PANEL) GPIO7 PM_BT_HOST_WAKE IN 30 (INTERNAL PD) VSSA_BUCK0
BOARD_TEMP4 L24 TDEV4
R8216 CRITICAL 1 TP294
16 NET_SPACING_TYPE=ANLG
GPIO8 D17 PM_WLAN_HOST_WAKE IN 30 (INTERNAL PD) E7 VSSA_BUCK2 D8
BATTERY_NTC N24 TBAT
10KOHM-1% R8222 CRITICAL NOTE: TDEV4 NTC ON PANEL
33 IN
GPIO9 E20 PM_BB_HOST_WAKE IN 31 (INTERNAL PD; CANT BE USED FOR 32K CLK OUTPUT) E8 VSSA_BUCK3 B16
PMU_TCAL N25 TCAL
0201 10KOHM-1% R8218 NET_SPACING_TYPE=ANLG
D21 AUD_MIK_HS1_INT_L E9 B14
C8215 1 2 CRITICAL GPIO10 IN 19 (INTERNAL PU TO PP1V8_S2R) VSSA_BUCK4
100PF
2 0201 10KOHM-1% R8219 GPIO11 B22 DOCK_BB_EN 11 (1.8_S2R;EXT PD BY BB MUXES) E10 VSSA_BUCK5 C1
C8221 1 C8220 1
3.92K PM_KEEPACT C24 KEEPACT OUT

WDOG
5% 2 0201 5 IN B23 CLK_32K_GPS E11 E22
100PF 100PF 0.1% GPIO12 (1.8 PUSH-PULL) PVSS_CHG_A
C C
(INTERNAL PULL-DOWN) OUT 31 39
6.3V 2
CERM 5% C8217 1
2 5% 402 37 IN PMU_SHDWN B1 SHDN
L18 NC_PMU_GPIO13 E12 J22
01005 6.3V 100PF C8223 1 6.3V 1/16W NET_SPACING_TYPE=ANLG GPIO13 PVSS_CHG_B
CERM 2 5% 100PF CERM 2 1 MF GPIO14 L19 RST_L63_L E13 N14
01005 6.3V 01005 RST_PMU_IN (INTERNAL PULL-DOWN) F20 RESET_IN OUT 19
CERM 2 5% 4 IN E14 VSS_WLED
L20 P14

RESET
6.3V TP354
GPIO15 IRQ_HALL IN 25 (EXTERNAL PU)
01005 CERM 2 XW8203 PLACE CLOSE TO PMU 31 28 4 OUT RST_AP_L D24 RESET*
01005 GPIO16 K20 NC_PMU_GPIO16 E15 VSS_LCM N16
16 BOARD_TEMP4_N 1 2 5 IRQ_PMU_L (PULLUP INSIDE H4P) B25 IRQ*
OUT K21 NC_PMU_GPIO17 E16
XW8202 SM RESISTOR FOR TEMP CALIBRATION GPIO17 TP29 N3
BOARD_TEMP3_N 1 2 NOSTUFF TP360 GPIO18 L21 NC_PMU_GPIO18 E17
I2C0_SCL_1V8 A25 SCL L8
XW8201 SM PLACE CLOSE TO PMU 39 19 10 5 IN E18

I2C & DWI


BOARD_TEMP2_N 1 2 NOSTUFF 39 19 10 5 BI I2C0_SDA_1V8 A24 SDA L6
E24 NC_PMU_AMUX_A0 E19
XW8200 SM
TP342 PLACE CLOSE TO PMU AMUX_A0 K18
BOARD_TEMP1_N 1 2 NOSTUFF DWI_AP_CLK (INTERNAL PULL-DOWN) F21 DWI_CK AMUX_A1 E25 NC_PMU_AMUX_A1 F4
39 5 IN K16
SM TP355 PLACE CLOSE TO PMU DWI NAMING RELATIVE TO AP (INTERNAL PULL-DOWN) D22 DWI_DI G21 F5
DWI_AP_DO AMUX_A2 NC_PMU_AMUX_A2
NOSTUFF 39 5 IN (WHAT SIGNALS DO YOU WANT MEASURED DICK,COCK?) K14
PLACE CLOSE TO PMU DWI_AP_DI E21 DWI_DO AMUX_A3 D25 NC_PMU_AMUX_A3 F6
TP227 39 5 OUT K12

ANALOG MUX
CRITICAL CRITICAL TP378
AMUX_AY G20 NC_PMU_AMUX_AY F7
TP376 TP377 K10
L8225 D8228 WLED_LX N15 AMUX_B0 H21 NC_PMU_AMUX_B0 F8
K8
4.7UH-3.2A PMEG4010BEA
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
P15 WLED_LX AMUX_B1 H20 NC_PMU_AMUX_B1 CRITICAL SHIT! F9
(NOTE: 2MHZ) K6
=PPVCC_MAIN_LED 1 2 1 2 N23 AMUX_B2 J20 NC_PMU_AMUX_B2 F10
32 VOUT_LED
L8229 J19

BACKLIGHT
PIME051E-SM LED_IO1_R L11 J21 NC_PMU_AMUX_B3 F11 VSS
DCR=106MOHM MAX SOD-323 R8227 WLED1 AMUX_B3 TP356
2.2UH-1.05A-0.195OHM J17
C8226

LED
1 1.00 LED_IO2_R L12 WLED2 AMUX_BY K19 NC_PMU_AMUX_BY CRITICAL F12
10UF 16 OUT LED_IO_1 1 2 1 2 J15
LED_IO3_R N13 WLED3 D8230 F13
20% MIN_LINE_WIDTH=0.3 MM
1%
MIN_LINE_WIDTH=0.3 MM MAKE_BASE=TRUE
VLS201612E-SM
MIN_LINE_WIDTH=0.4 MM
J13
10V MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
P13 VOLTAGE=5V MIN_NECK_WIDTH=0.2 MM
F14
X5R 2 R8231 1/20W LED_IO4_R WLED4 VDD_LCM N21 PPVCC_MAIN 32 34 35 MIN_LINE_WIDTH=0.4MM NET_SPACING_TYPE=SWITCHNODE PMEG2005AEL
J11

LCM/GRAPE
603 MF MIN_NECK_WIDTH=0.2MM DIDT=TRUE
1.00 201
TP331
LED_IO5_R L13 WLED5 VDD_LCM_SW P21 PP6V0_LCM_HI NET_SPACING_TYPE=PWR 1 2 F15
16 OUT LED_IO_2 1 2 MAX_NECK_LENGTH=3 MM J9
TP357
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM LED_IO6_R L14 WLED6 LCM_LX P16 LCM_LX F16
MIN_NECK_WIDTH=0.2 MM 1% MIN_NECK_WIDTH=0.2 MM SOD882 J7
VBOOST_LCM N12 PP6V0_LCM_VBOOST F17
32 PPLED_OUT
1/20W
MF R8232 TP332
PLACEMENT_NOTE=PLACE NEAR U8100.N23
(INTERNAL PULLDOWN; TE ENABLE) MAKE_BASE=TRUE
F18
J5
LED_IO_3
201 1.00 C8201 1 LCM2_EN C25 NC_LCM2_EN VOLTAGE=6V
H19
CRITICAL 16 OUT 1 2
1UF MIN_LINE_WIDTH=0.4MM
F19 VSS
VLCM2 N11 NC_VLCM2
C8233 C8234 C8235 C8232 MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2MM

VIB
1 1 1 1 MIN_NECK_WIDTH=0.2 MM 1% MIN_NECK_WIDTH=0.2 MM
10% NET_SPACING_TYPE=PWR H13
25V G5
22UF 1UF 1UF 1UF R8235 1/20W
X5R 2 VLCM1 P12 NC_VLCM1 MAX_NECK_LENGTH=3 MM
H14
MF TP365
20% 10% 10% 10% 1.00 201 402 VLCM3 L10 BB_VBUS_DET OUT 31
G6
25V 25V 25V 25V LED_IO_4 1 2 H15
B
2 X5R-CERM
0805
2 X5R
402
2 X5R
402
2 X5R
402
16 OUT
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM 1%
1/20W
R8239
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM C8236
2.2UF
1 1 C8237
10UF TP83
1 C8238
1UF
G7
G8
H16 B
MF
201 1.00
TP327 I2C ADDRESS: 0111100X (0X78) 20% 20% 10% G9
H17
LED_IO_5 1 2 10V 10V 6.3V H18
16 OUT X5R-CERM 2 2 X5R 2 CERM G10
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM
402 603 402
MIN_NECK_WIDTH=0.2 MM 1% MIN_NECK_WIDTH=0.2 MM J4
G11
R8240 1/20W
MF TP366
G12
J6
1.00 201
LED_IO_6 1 2 J8
16 OUT G13
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM 1% MIN_NECK_WIDTH=0.2 MM J10
1/20W G14
MF TP324 J12
201 G15
J14
G16
J16
G17
J18
G18
K5
G19
K7
H4
K9
H5
K11
H6
TP408 K13
H7
K15
H8
TP413 K17
H9
L5
H10
TP375 L7
H11
L9
H12
TP84

A SYNC_MASTER=YOSH SYNC_DATE=N/A A
PAGE TITLE

POWER: PMU
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
82 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 35 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C
K48
POWER BUDGET
CRITICAL PEAK=0.12A
Q8350 AVG=0.12A
CSD68803W15
BGA TP379

C3 C1 PP3V3_MLC_OUT

S
=PP3V3_MLC_HI

D
32 32
C2 B2
B3 B1
A3 A2
1 C8352 1 C8353
4.7UF 1000PF

G
10% 10%
NOSTUFF 6.3V 16V
A1 2 X5R-CERM 2 X7R
1
R8351 1
R8353 603 201
10K 39K
1% 1%
1/20W 1/20W
MF
MF
2 201 R8352 201
R8354 C8351
2 0.015UF
47K 0 1 2
TP76 PM_P3V3MLC_EN 1 2 1 2
R8354_SS PM_P3V3MLCWR_SS
1% 5%

D 3
1/20W
MF
201 TP77
1/20W
MF
201 TP79
10%
6.3V
X5R
0201
CSD68803
Q8351 MOSFET CSD68803W15
SSM3K15FV CHANNEL P-TYPE
SOD-VESM-HF

B TP72
1 G S 2 RDS(ON) 52MOHM @-1.8V B
6 IN PM_MLC_PWR_EN IMAX 4 A
1 VGS MAX +/- 6V
R8350
100K
1%
1/20W
MF
2 201 TP66

TP78

TP80

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_ALT_ITEM

376S0972 376S0612 Q8351 RADAR:8537160

A SYNC_MASTER=YOSH SYNC_DATE=N/A A
PAGE TITLE

POWER: 3.3V MLC & 1.2V VR


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
83 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 36 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DEBUG RESET ACCESS D


D

PLACE OUTSIDE OF CAN?


34 32 PPBATT_VCC

NOSTUFF
1
R9002
TP38 1.5K TP374
1%
1/20W
5 OUT FORCE_DFU MF
2 201 35 OUT PMU_SHDWN

NOSTUFF PWR_ON_LED TP33 NOSTUFF


1
1 R9001
R9000 NOSTUFF 300
300 A 5%
5% LED9000 1/20W
1/20W RED-50MCD-20MA MF
MF 0603 2 201
2 201
C K
C

B B
LEFT AND RIGHT MOUNTING TABS
MT1
BRKT-MTG-TAB-MLB-K93K94
SM

1 2

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

DEBUG AND MISC


DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
90 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 37 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

PLATED THROUGH HOLES C


C DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM

SL9300
TH-NSP
1

SL-1.1X0.4-1.4X0.7

SL9302
TH-NSP
1

SL-1.1X0.4-1.4X0.7

SL9303
TH-NSP
1

SL-1.1X0.4-1.4X0.7

SL9304
TH-NSP

B 1

SL-1.1X0.4-1.4X0.7
B
SL9305
TH-NSP
1

SL-1.1X0.4-1.4X0.7

SL9306
TH-NSP
1

SL-1.1X0.4-1.4X0.7

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

FCT/ICT TEST/BRACKETS
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
93 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 38 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Clock Signal Constraints


USB
TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET


TABLE_PHYSICAL_ASSIGNMENT_ITEM

CLK_50S * 50_OHM_SE
JTAG
TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET


TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD

USB_90D * 90_OHM_DIFF

D CLK * *
TABLE_SPACING_ASSIGNMENT_ITEM

5:1_SPACING
NET_SPACING_TYPE1

JTAG
NET_SPACING_TYPE2

*
AREA_TYPE

*
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING TABLE_SPACING_ASSIGNMENT_HEAD
D
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

NET_TYPE USB * * 5:1_SPACING


NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
NET_TYPE
CLK_50S CLK CLK_32K_PMU
I63 18 35
JTAG JTAG_AP_TCK ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CLK_50S CLK CLK_32K_WLAN 30 35
I16 4 28
I162
JTAG JTAG_AP_TMS
CLK_50S CLK CLK_32K_GPS 31 35
I15 4 28
USB_90D USB USB_D_P
I81
JTAG JTAG_AP_TDI I5 4 28

CLK_50S CLK CLK_CAM_FF I14 4 10


USB_90D USB USB_D_N
I88 7 26
JTAG JTAG_AP_TDO I6 4 28

CLK_50S CLK CLK_CAM_FF_FILT I13 4 10


USB_90D USB USB_PT_DK_CON_D_P
I89
JTAG JTAG_AP_TRST_L I7 28 29

I95 CLK_50S CLK CLK_CAM_FF_CONN 25 26


I20 4 10
I8 USB_90D USB USB_PT_DK_CON_D_N 28 29

I96 CLK_50S CLK CLK_CAM_RF 7 27

I94 CLK_50S CLK CLK_CAM_RF_FILT 25 27 I82 USB_90D USB USB_BB_D_P 11 31

I83 USB_90D USB USB_BB_D_N 11 31

I130 CLK_50S CLK I2S_AP_0_MCK 5 I84 USB_90D USB USB_FS_D_P 4 11

I131 CLK_50S CLK I2S_AP_0_MCK_R 5 19 I85 USB_90D USB USB_FS_D_N 4 11

CLK_50S CLK CLK_CAM_FF_R


I157 7
USB_90D USB USB_FS_N_ACC_TX
CLK_50S CLK CLK_CAM_RF_R 7
I128 11 28
I158
I129 USB_90D USB USB_FS_P_ACC_RX 11 28

I2C I171 USB_90D USB ACC_PT_DK_CON_TX 28 29

I172 USB_90D USB ACC_PT_DK_CON_RX 28 29

NAND
TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET


TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I2C_50S * 50_OHM_SE


TABLE_PHYSICAL_ASSIGNMENT_ITEM

NAND_50S * 50_OHM_SE TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

I2S
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


C
I2C * * 1.5:1_SPACING

C NAND * *
TABLE_SPACING_ASSIGNMENT_ITEM

2:1_SPACING
NET_TYPE NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_HEAD

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_TYPE I2S_90S * 45_OHM_SE


ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I1 I2C_50S I2C I2C1_SDA_1V8 5 25

I2 I2C_50S I2C I2C1_SCL_1V8 5 25


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


I2C_50S I2C I2C0_SDA_1V8
NAND_50S NAND F0AD<7..0> 6 12
I3 5 10 19 35

I2C0_SCL_1V8
TABLE_SPACING_ASSIGNMENT_ITEM

I50
I2C_50S I2C I2S * * 3:1_SPACING
NAND_50S NAND F0CE0_L I4 5 10 19 35
I45 6 12
I2C_50S I2C I2C2_SDA_3V0
F0CE1_L 5 25 26
TABLE_SPACING_ASSIGNMENT_ITEM

I61
NAND_50S NAND I2S I2S * 2:1_SPACING
I48 6 12
I2C_50S I2C I2C2_SCL_3V0
NAND_50S NAND F0CE2_L 6 12
I62 5 25 26
I47
I2C_50S I2C ISP_AP_0_SCL
NAND_50S NAND F0CE3_L I98 7 25
I46 6 12
I2C_50S I2C ISP_AP_0_SDA
NAND_50S NAND F0CE4_L I99 7 25
NET_TYPE
I163 6 12
I2C_50S I2C ISP_AP_1_SCL
NAND_50S NAND F0CE5_L 6 12
I100 7 26
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I164
I2C_50S I2C ISP_AP_1_SDA
NAND_50S NAND F0CE6_L I101 7 26
I166 6 12
I2C_50S I2C I2C2_SCL_3V0_ALS I2S_50S I2S I2S_AP_0_BCLK
NAND_50S NAND F0CE7_L 6 12
I102 25 26 I140 5 19
I165
I2C_50S I2C I2C2_SDA_3V0_ALS I2S_50S I2S I2S_AP_0_LRCK
I41 NAND_50S NAND F0CLE 6 12
I103 25 26 I143 5 19

I2S_50S I2S I2S_AP_0_DIN


I42 NAND_50S NAND F0ALE 6 12
I142 5 19

I2S_50S I2S I2S_AP_0_DOUT


NAND_50S NAND F0RE_L 6 12
I141 5 19
I43
I2C_50S I2C ISP_CAM_1_SCL I2S_50S I2S L63_ASP_SDOUT
NAND_50S NAND F0WE_L I124 25 26 I159 19
I44 6 12
I2C_50S I2C ISP_CAM_1_SDA I2S_50S I2S I2S_AP_2_BCLK
I37 NAND_50S NAND F0WP_L I125 25 26 I144 5 19 30

I2S_50S I2S I2S_AP_2_LRCK


I49 NAND_50S NAND F1AD<7..0> 6 12
I148 5 19 30

I2S_50S I2S I2S_AP_2_DIN


I51 NAND_50S NAND F1CE0_L 6 12
I147 5 19 30

I2S_50S I2S I2S_AP_2_DOUT


I52 NAND_50S NAND F1CE1_L 6 12
I146 5 19 30

I2S_50S I2S L63_VSP_SDOUT


I53 NAND_50S NAND F1CE2_L 6 12
I160 19

I2S_50S I2S I2S_AP_3_BCLK


I54 NAND_50S NAND F1CE3_L 6 12 XTAL I145
I2S_50S I2S I2S_AP_3_LRCK
5 19

I167 NAND_50S NAND F1CE4_L 6 12


I149 5 19

I2S_AP_3_DIN
B F1CE5_L I2S_50S I2S 5 19

B
TABLE_SPACING_ASSIGNMENT_HEAD

I150
I168 NAND_50S NAND 6 12 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
I2S_50S I2S I2S_AP_3_DOUT
I169 NAND_50S NAND F1CE6_L 6 12
TABLE_SPACING_ASSIGNMENT_ITEM
I151 5 19

CRYSTAL * * 5:1_SPACING I2S_50S I2S L63_XSP_SDOUT


I170 NAND_50S NAND F1CE7_L 6 12
I161 19

I55 NAND_50S NAND F1CLE 6 12


NET_TYPE
I56 NAND_50S NAND F1ALE 6 12
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I57 NAND_50S NAND F1RE_L 6 12

I58 NAND_50S NAND F1WE_L 6 12 I92 CRYSTAL XTAL_24M_I 4 DWI


I59 NAND_50S NAND F1WP_L I90 CRYSTAL XTAL_24M_O 4

CRYSTAL 24M_O 4 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


TABLE_SPACING_ASSIGNMENT_HEAD

I93
TABLE_SPACING_ASSIGNMENT_ITEM

DWI * * 2:1_SPACING

I105 NAND_50S NAND F2AD<7..0>


I104 NAND_50S NAND F2CE0_L NET_TYPE

I106 NAND_50S NAND F2CE1_L ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

I108 NAND_50S NAND F2CE2_L VREF DWI DWI_AP_CLK


I107 NAND_50S NAND F2CE3_L I152 5 35

DWI DWI_AP_DI
F2CLE 5 35
TABLE_SPACING_ASSIGNMENT_HEAD

I153
I109 NAND_50S NAND NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
DWI DWI_AP_DO
I110 NAND_50S NAND F2ALE TABLE_SPACING_ASSIGNMENT_ITEM
I156 5 35

VREF * * 5:1_SPACING
I111 NAND_50S NAND F2RE_L
I113 NAND_50S NAND F2WE_L
NET_TYPE
I112 NAND_50S NAND F2WP_L
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I114 NAND_50S NAND F3AD<7..0>
NAND_50S NAND F3CE0_L
I115
VREF PPVREF_DDR0_CA
NAND_50S NAND F3CE1_L I136 8
I116
VREF PPVREF_DDR0_DQ
NAND_50S NAND F3CE2_L I137 8
I117
VREF PPVREF_DDR1_CA
NAND_50S NAND F3CE3_L I139 8

A PPVREF_DDR1_DQ
I118

I119

I120
NAND_50S
NAND_50S
NAND
NAND
F3CLE
F3ALE
I138 VREF 8

SYNC_MASTER=MIKE
PAGE TITLE
SYNC_DATE=N/A A
I121

I122
NAND_50S
NAND_50S
NAND
NAND
F3RE_L
F3WE_L CONSTRAINTS: ASSIGNMENTS
DRAWING NUMBER SIZE
NAND_50S NAND F3WP_L
I123
Apple Inc. 051-8962 D
REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
100 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 39 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO/SPEAKER
ANALOG VIDEO CONSTRAINTS TABLE_PHYSICAL_ASSIGNMENT_HEAD

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET


PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

AUDIO * 1:1_DIFFPAIR
VID_50S * Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD
SPEAKER * SPEAKER
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


ANALOG_VIDEO * * 5:1_SPACING
TABLE_SPACING_ASSIGNMENT_ITEM
LVDS AUDIO * *
TABLE_SPACING_ASSIGNMENT_ITEM

3:1_SPACING
ANALOG_VIDEO ANALOG_VIDEO * 3:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

D NET_TYPE
LVDS_100D * 90_OHM_DIFF
TABLE_PHYSICAL_ASSIGNMENT_ITEM

ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE

SPACING
D
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I287 AUDIO AUDIO LEFT_CH_OUT_P 19 20

AUDIO AUDIO LEFT_CH_OUT_REF


DAC_AP_OUT1
TABLE_SPACING_ASSIGNMENT_ITEM

I288 19 20
VID_50S ANALOG_VIDEO LVDS * * 4:1_SPACING
I213 7 11
AUDIO AUDIO LEFT_CH_P
VID_50S ANALOG_VIDEO DAC_AP_OUT2 I289 20
I214 7 11
AUDIO AUDIO SSM2375_L_IN_P
VID_50S ANALOG_VIDEO DAC_AP_OUT3 7 11 NET_TYPE
I290 20
I215
I359 AUDIO AUDIO SSM2375_L_IN_N 20
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I232 VID_50S ANALOG_VIDEO BUF_C_Y 11 I291 AUDIO AUDIO RIGHT_CH_OUT_P 19 20

VID_50S ANALOG_VIDEO BUF_CVBS_PB AUDIO AUDIO RIGHT_CH_OUT_REF


I231 11
LVDS_100D LVDS LVDS_DATA_P<2..0> 14 16 I292 19 20

VID_50S ANALOG_VIDEO BUF_Y_PR 11


I175
AUDIO AUDIO RIGHT_CH_P
I233
LVDS_100D LVDS LVDS_DATA_N<2..0> 14 16 I293 20
I174
AUDIO AUDIO SSM2375_R_IN_P
VID_50S ANALOG_VIDEO VIDEO_EMI_CVBS_PB 10 11 28 LVDS_100D LVDS LVDS_DATA_CONN_P<2..0> 16
I294 20
I219 I245
AUDIO AUDIO SSM2375_R_IN_N
I220 VID_50S ANALOG_VIDEO VIDEO_EMI_C_Y 10 11 28 I244 LVDS_100D LVDS LVDS_DATA_CONN_N<2..0> 16
I357 20

I221 VID_50S ANALOG_VIDEO VIDEO_EMI_Y_PR 10 11 28 I371 AUDIO AUDIO EXT_MIC_P 19 23

LVDS_100D LVDS LVDS_CLK_P AUDIO AUDIO EXT_MIC_REF


VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_CVBS_PB 28 29
I176 14 16 I372 19 23
I222
LVDS_100D LVDS LVDS_CLK_N
VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_C_Y 28 29 I178 14 16
I224
LVDS_100D LVDS LVDS_CLK_CONN_P 16
VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PR 28 29 I234
I223
I235 LVDS_100D LVDS LVDS_CLK_CONN_N 16

DISPLAYPORT
TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET


MIPI
C C
TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD
DP_100D * 90_OHM_DIFF
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
SDIO
TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


MIPI_100D * 90_OHM_DIFF TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_HEAD
DP * * 5:1_SPACING NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM
NET_TYPE SDIO_50S * 50_OHM_SE
MIPI * * 4:1_SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


I247 DP_100D DP DP_AP_TX_P<0> 7 10 13
NET_TYPE
DP_AP_TX_N<0> 7 10 13
TABLE_SPACING_ASSIGNMENT_ITEM

I249 DP_100D DP SDIO * * 2:1_SPACING


ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I248 DP_100D DP DP_AP_TX_P<1> 7 10 13 TABLE_SPACING_ASSIGNMENT_ITEM

SDIO_CLK * * 4:1_SPACING
I91 MIPI_100D MIPI MIPID_AP_DATA_P<0> 7 14
I250 DP_100D DP DP_AP_TX_N<1> 7 10 13
I92 MIPI_100D MIPI MIPID_AP_DATA_N<0> 7 14
I251 DP_100D DP DP_AP_AUX_P 7 13
I93 MIPI_100D MIPI MIPID_AP_DATA_P<1> 7 14
I252 DP_100D DP DP_AP_AUX_N 7 13
NET_TYPE
I94 MIPI_100D MIPI MIPID_AP_DATA_N<1> 7 14
I273 DP_100D DP DP_EMI_TX_P<0> 13 28
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I95 MIPI_100D MIPI MIPID_AP_DATA_P<2> 7 14
I274 DP_100D DP DP_EMI_TX_N<0> 13 28
I96 MIPI_100D MIPI MIPID_AP_DATA_N<2> 7 14
I275 DP_100D DP DP_EMI_TX_P<1> 13 28 I200 SDIO_50S SDIO_CLK SDIO_WL_CLK 5 30

I271 MIPI_100D MIPI MIPID_AP_DATA_P<3> 7 14


I276 DP_100D DP DP_EMI_TX_N<1> 13 28 I280 SDIO_50S SDIO_CLK SDIO_WL_CLK_R
MIPI_100D MIPI MIPID_AP_DATA_N<3> 7 14 DP_100D DP DP_EMI_AUX_P 13 28
I270 I277
SDIO_50S SDIO SDIO_WL_CMD
MIPI_100D MIPI MIPID_AP_CLK_P 7 14 DP_100D DP DP_EMI_AUX_N 13 28 I201 5 30
I97 I272
SDIO_50S SDIO SDIO_WL_DATA<3..0> 5 30
I98 MIPI_100D MIPI MIPID_AP_CLK_N 7 14 I327 DP_100D DP DP_PT_DK_CON_TX_P<0> 28 29
I202

I329 DP_100D DP DP_PT_DK_CON_TX_N<0> 28 29

I311 MIPI_100D MIPI MIPI0C_AP_DATA_P<0> 7 27


DP_100D DP DP_PT_DK_CON_TX_P<1> 28 29
I328
I312 MIPI_100D MIPI MIPI0C_AP_DATA_N<0> 7 27
DP_100D DP DP_PT_DK_CON_TX_N<1> 28 29
I331
I315 MIPI_100D MIPI MIPI0C_AP_CLK_P 7 27 DP_100D DP DP_PT_DK_CON_AUX_P 28 29
I330
MIPI_100D MIPI MIPI0C_AP_CLK_N 7 27 DP_100D DP DP_PT_DK_CON_AUX_N 28 29
I316

I341 MIPI_100D MIPI MIPI0C_CAM_DATA_P<0> 25 27


I332
SPI
B MIPI_100D MIPI MIPI0C_CAM_DATA_N<0>
B
TABLE_PHYSICAL_ASSIGNMENT_HEAD

25 27
I344 NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
I343 MIPI_100D MIPI MIPI0C_CAM_CLK_P 25 27 TABLE_PHYSICAL_ASSIGNMENT_ITEM

I342 MIPI_100D MIPI MIPI0C_CAM_CLK_N 25 27 SPI_50S * 45_OHM_SE


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET


TABLE_SPACING_ASSIGNMENT_ITEM

SPI * * 2:1_SPACING

NET_TYPE
I345 MIPI_100D MIPI MIPI1C_AP_DATA_P<0> 7 26
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I346 MIPI_100D MIPI MIPI1C_AP_DATA_N<0> 7 26

MIPI_100D MIPI MIPI1C_AP_CLK_P 7 26 I360 SPI_50S SPI SPI_GRAPE_MISO 5 17


I347
MIPI_100D MIPI MIPI1C_AP_CLK_N 7 26 I363 SPI_50S SPI SPI_GRAPE_MOSI 5 17
I348
MIPI_100D MIPI MIPI1C_CAM_DATA_P<0> 25 26 I361 SPI_50S SPI SPI_GRAPE_SCLK 5 17
I353
MIPI1C_CAM_DATA_N<0> SPI_50S SPI SPI_GRAPE_CS_L 5 17
I355 MIPI_100D MIPI 25 26 I362

I354 MIPI_100D MIPI MIPI1C_CAM_CLK_P 25 26 SPI_50S SPI SPI_IPC_MISO 5 31


I364
I356 MIPI_100D MIPI MIPI1C_CAM_CLK_N 25 26 SPI_50S SPI SPI_IPC_MOSI 5 31
I365

I366 SPI_50S SPI SPI_IPC_SCLK 5 31

I367 SPI_50S SPI SPI_IPC_MRDY 5 31

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

CONSTRAINTS: ASSIGNMENTS
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
101 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 40 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MLB CONSTRAINTS
BOARD UNITS ALLEGRO
TABLE_BOARD_INFO

BOARD LAYERS BOARD AREAS (MIL or MM) VERSION


TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM NO_TYPE,BGA,BGA06-06 MM 15.2

D D
PHYSICAL CONSTRAINTS SPACING CONSTRAINTS
DEFAULT/BGA SPACING RULES
TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM

ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT * * BGA BGA_SPA


TABLE_PHYSICAL_RULE_ITEM

DEFAULT * Y =45_OHM_SE =45_OHM_SE 30 MM 0 MM 0 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM
DEFAULT * 0.08 MM ? CLK * BGA BGA_SPA
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

STANDARD * =DEFAULT ? PWR * * PWR_P1SPACING


TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

BGA_SPA * =DEFAULT ? GND * * GND_P1SPACING


TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE * * SWITCHNODE
TABLE_SPACING_ASSIGNMENT_ITEM

REGULAR SPACING RULES ANLG * * 3:1_SPACING

SINGLE-ENDED PHYSICAL RULES TABLE_SPACING_RULE_HEAD

45 OHMS SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT


TABLE_SPACING_RULE_ITEM

1:1_SPACING * 0.060 MM ?
NOTES:
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

0P08_SPACING * 0.080 MM ?
45_OHM_SE ISL2,ISL3,ISL8,ISL9 Y 0.055 MM 0.055 MM 3.0 MM
0.075 MM ~ 3 MIL
TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

1.5:1_SPACING * 0.090 MM ?
45_OHM_SE ISL4,ISL5,ISL6,ISL7 Y 0.060 MM 0.060 MM 3.0 MM TABLE_SPACING_RULE_ITEM

2:1_SPACING * 0.120 MM ?
0.089 MM ~ 3.5 MIL
TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE * N 0.060 MM 0.060 MM 3.0 MM TABLE_SPACING_RULE_ITEM

2.5:1_SPACING * 0.150 MM ?

3:1_SPACING * 0.180 MM ?
TABLE_SPACING_RULE_ITEM

0.102 MM ~ 4 MIL

C 50 OHMS
4:1_SPACING * 0.240 MM ?
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM
0.114 MM ~ 4.5 MIL C
5:1_SPACING * 0.300 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM


0.125 MM ~ 5 MIL
ON LAYER? 0P5MM_SPACING * 0.5 MM ?
0.140 MM ~ 5.5 MIL
TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE TOP,BOTTOM Y 0.085 MM 0.085 MM 3.0 MM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
0P64MM_SPACING * 0.64 MM ?
50_OHM_SE * N 0.050 MM 0.050 MM 3.0 MM
*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS 0.15 MM ~ 6 MIL
50 OHMS - CLEAR ON LAYER 2 AND 5 0.18 MM ~ 7 MIL
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
0.2 MM ~ 8 MIL
50_OHM_SE_RF TOP Y 0.240 MM 0.240 MM 3.0 MM

50_OHM_SE ISL4 Y 0.060 MM 0.060 MM 3.0 MM


TABLE_PHYSICAL_RULE_ITEM

0.25 MM ~ 10 MIL
50 OHMS - CLEAR ON TOP AND BOTTOM POWER/GND SPACING RULES 0.3 MM ~ 12 MIL
TABLE_SPACING_RULE_HEAD

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT


PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

PWR_P1SPACING * 0.1 MM 900


TABLE_SPACING_RULE_ITEM

0.33 MM ~ 13 MIL
50_OHM_SE ISL2,ISL9 Y 0.090 MM 0.090 MM 3.0 MM
0.4 MM ~ 16 MIL
TABLE_SPACING_RULE_ITEM

GND_P1SPACING * 0.1 MM 950


TABLE_SPACING_RULE_ITEM

SWITCHNODE * 0.5 MM 1000


TABLE_SPACING_RULE_ITEM
1.0 MM = 39.37 MIL
SWITCHNODE TOP,BOTTOM 0.2 MM 1000
DIFFERENTIAL PAIR PHYSICAL RULES
100 OHMS
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?

B 100_OHM_DIFF TOP,BOTTOM Y 0.076 MM 0.076 MM 0.210 MM 0.210 MM


TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
B
100_OHM_DIFF N Y 0.057 MM 0.057 MM =STANDARD 0.300 MM 0.300 MM

90 OHMS
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF TOP,BOTTOM Y 0.095 MM 0.095 MM 0.200 MM 0.200 MM


TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF ISL2,ISL3,ISL8,ISL9 Y 0.054 MM 0.054 MM =STANDARD 0.200 MM 0.100 MM


TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF ISL4,ISL5,ISL6,ISL7 Y 0.060 MM 0.060 MM =STANDARD 0.200 MM 0.100 MM

AUDIO PHYSICAL RULES


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.08 MM 0.08 MM


TABLE_PHYSICAL_RULE_ITEM

SPEAKER * Y 0.3 MM 0.19MM 10 MM 0.08 MM 0.08 MM

BGA AREA PHYSICAL RULES


TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

A
TABLE_PHYSICAL_ASSIGNMENT_ITEM

* BGA BGA_PHY
SYNC_MASTER=MIKE
PAGE TITLE
SYNC_DATE=N/A A
CONSTRAINTS: MLB RULES
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

BGA_PHY * Y 0.060 MM 0.060 MM =STANDARD 0.076 MM 0.075 MM DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
102 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 41 OF 42
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE

CONSTRAINTS: RF RULES
DRAWING NUMBER SIZE

Apple Inc. 051-8962 D


REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
106 OF 106
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 42 OF 42
8 7 6 5 4 3 2 1

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