Itautec w7535 - Clevo 6-71-W24h0-D02a GP

E5120Q/E5120Q-C, E5125/E5125-C, E5128Q, E5128Q-C
Preface
Notebook Computer
E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Preface
Version 1.0
November 2010
Trademarks
Intel, Intel Core, Intel Pentium and Intel Celeron are trademarks of Intel Corporation.
Windows is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II
Preface
About this Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the E5120Q/
E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Appendix A, Part Lists
Preface
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS
III
Preface
IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.
Preface
CAUTION
This Computers Optical Device is a Laser Class 1 Product
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1. Dont drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer Do not place it on an unstable Do not place anything heavy
to any shock or vibration. surface. on the computer.
2. Keep it dry, and dont overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not expose it to excessive Do not leave it in a place Dont use or store the com- Do not place the computer on
Preface
heat or direct sunlight. where foreign matter or mois- puter in a humid environment. any surface which will block
ture may affect the system. the vents.
3. Follow the proper working procedures for the computer. Shut the computer down properly and dont forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power Do not turn off any peripheral Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is puter by yourself. on your computer.
all programs. on.
V
Preface
4. Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.
Use only approved brands of Unplug the power cord before

peripherals. attaching peripheral devices.
Power Safety
Preface
The computer has specific power requirements:

Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
Power Safety The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals Do not plug in the power Do not use the power cord if Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.
VI
Preface
Battery Precautions
Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
Recharge the batteries using the notebooks system. Incorrect recharging may make the battery explode.
Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
Keep the battery away from metal appliances.
Affix tape to the battery contacts before disposing of the battery.
Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
The following can also apply to any backup batteries you may have.
Preface
If you do not use the battery for an extended period, then remove the battery from the computer for storage.
Before removing the battery for storage charge it to 60% - 70%.
Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturers instructions.
Battery Level
Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
Users Manual on CD/DVD

This describes the notebook PCs features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.
System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
Preface
5. Attach the AC/DC adapter to the DC-In jack on the left of the
computer, then plug the AC power cord into an outlet, and connect
the AC power cord to the AC/DC adapter.
6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 135 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never lift the computer
by the lid/LCD).
7. Press the power button to turn the computer on.
Shut Down
Note that you should al-

ways shut your com-
puter down by
choosing Shut Down
135 from the Start Menu.
This will help prevent
Figure 1 hard disk or system
Opening the Lid/LCD/Computer with AC/DC Adapter problems.
Plugged-In
VIII
Preface
Contents
Introduction ..............................................1-1 Top (E5125) ................................................................................... A-4
Top (E5128Q) ................................................................................ A-5
Overview .........................................................................................1-1 Bottom ........................................................................................... A-6
Specifications ..................................................................................1-2 DVD Dual Drive ............................................................................ A-7
External Locator - Top View with LCD Panel Open ......................1-4 LCD ............................................................................................... A-8
External Locator - Front & Right Side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6 Schematic Diagrams................................. B-1
External Locator - Bottom View .....................................................1-7 System Block Diagram ...................................................................B-2
Mainboard Overview - Top (Key Parts) .........................................1-8 Clock Generator ..............................................................................B-3
Mainboard Overview - Bottom (Key Parts) ....................................1-9 CPU 1/7 (DMI, PEG, FDI) .............................................................B-4
Mainboard Overview - Top (Connectors) .....................................1-10 CPU 2/7 (CLK, MISC, JTAG) .......................................................B-5
Mainboard Overview - Bottom (Connectors) ...............................1-11 CPU 3/7 (DDR3) ............................................................................B-6
Disassembly ...............................................2-1 CPU 4/7 (Power) .............................................................................B-7
Preface
CPU 5/7 (Graphics Power) .............................................................B-8
Overview .........................................................................................2-1
CPU 6/7 (GND) ..............................................................................B-9
Maintenance Tools ..........................................................................2-2 CPU 7/7 (RESERVED) ................................................................B-10
Connections .....................................................................................2-2
DDR3 SO-DIMM_0 .....................................................................B-11
Maintenance Precautions .................................................................2-3 DDR3 SO-DIMM_1 .....................................................................B-12
Disassembly Steps ...........................................................................2-4 LVDS, Inverter .............................................................................B-13
Removing the Battery ......................................................................2-5
HDMI, CRT ..................................................................................B-14
Removing the Hard Disk Drive .......................................................2-6 IBEXPEAK- M 1/9 .......................................................................B-15
Removing the Optical (CD/DVD) Device ......................................2-8 IBEXPEAK - M 2/9 ......................................................................B-16
Removing the System Memory (RAM) ..........................................2-9 IBEXPEAK - M 3/9 ......................................................................B-17
Removing and Installing a Processor ............................................2-11
IBEXPEAK - M 4/9 ......................................................................B-18
Removing the 3G Module .............................................................2-14 IBEXPEAK - M 5/9 ......................................................................B-19
Removing the Wireless LAN Module ...........................................2-15 IBEXPEAK - M 6/9 ......................................................................B-20
Removing the Bluetooth Module ..................................................2-16
IBEXPEAK - M 7/9 ......................................................................B-21
Removing the Keyboard ................................................................2-17 IBEXPEAK - M 8/9 ......................................................................B-22
Part Lists ..................................................A-1 IBEXPEAK - M 9/9 ......................................................................B-23
Part List Illustration Location ........................................................ A-2 New Card, Mini PCIE ...................................................................B-24
Top (E5120Q) ................................................................................ A-3 3G, CCD, TPM .............................................................................B-25
IX
Preface
Card Reader/LAN JMB251C ....................................................... B-26

LAN (JMC251C), SATA HDD, ODD ......................................... B-27
Audio Codec VIA1812 ................................................................. B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, Fan, TP, Multi-Conn ........................................................... B-31
5VS, 3VS, 1.5VS .......................................................................... B-32
Power 3.3V/5V ............................................................................. B-33
Power 1.5V/0.75V, 1.8VS ............................................................ B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_Core ...................................................................... B-36
V-Core .......................................................................................... B-37
AC_IN, Charger ........................................................................... B-38
Click Board .................................................................................. B-39
Preface
Audio Board/USB ........................................................................ B-40

Power Switch & LED Board ........................................................ B-41
External ODD Board .................................................................... B-42
Sequence ....................................................................................... B-43
Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
Use the flash tools to update the BIOS .......................................... C-2
Restart the computer (booting from the HDD) .............................. C-2
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/
E5128Q-C series notebook computer. Information about operating the computer (e.g. getting started, and the Setup util-
ity) is in the Users Manual. Information about dri-vers (e.g. VGA & audio) is also found in the Users Manual. The
manual is shipped with the computer.
Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application softwares (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook is designed to be upgradeable. See Dis-
assembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note
of the warning and safety information indicated by the symbol.
The balance of this chapter reviews the computers technical specifications and features.
Overview 1 - 1
Introduction
Specifications Processor Options BIOS
Intel Core i7 Processor One 32Mb SPI Flash ROM

i7-640M (2.80GHz), i7-620M (2.66GHz) Phoenix BIOS
4MB L3 Cache & 1066MHz FSB

Storage
Intel Core i5 Processor
Latest Specification Information
i5-540M (2.53GHz), i5-520M (2.4GHz), (Factory Option) One Changeable 12.7mm(h) Super Multi
The specifications listed here are correct at the i5-450M (2.4GHz), i5-430M (2.26GHz) Optical Device Drive
time of sending them to the press. Certain items 3MB L3 Cache & 1066MHz FSB One Changeable 2.5" 9.5 mm (h) SATA HDD
(particularly processor types/speeds) may be
changed, delayed or updated due to the manu- Intel Core i3 Processor Audio
facturer's release schedule. Check with your i3-370M (2.4GHz), i3-350M (2.26GHz), i3-330M (2.13GHz)
service center for more details. High Definition Audio Compliant Interface
3MB L3 Cache & 1066MHz FSB
2 * Built-In Speakers
Intel Pentium Processor
Built-In Microphone
P6000 (1.86GHz)
1.Introduction
3MB L3 Cache & 1066MHz FSB Keyboard

Intel Celeron Processor
Full-size WinKey keyboard (with numeric keypad)
P4500 (1.86GHz)
CPU 2MB L3 Cache & 1066MHz FSB Pointing Device
The CPU is not a user serviceable part. Ac- LCD Built-in Touchpad
cessing the CPU in any way may violate your
warranty. 15.6" (39.62) HD TFT LCD Security
Memory Security (Kensington Type) Lock Slot

BIOS Password
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1066/
1333 MHz Memory Interface
Memory Expandable up to 8GB
Three USB 2.0 Ports
Core Logic One HDMI-Out Port
One Headphone-Out Jack
Intel HM55 Chipset
One Microphone-In Jack
Video Adapter One RJ-45 LAN Jack
One DC-in Jack
Intel HM55 Integrated Video
One External Monitor Port
Shared Memory Architecture of up to 1748MB
MS DirectX 10 compatible
1 - 2 Specifications
Introduction
Card Reader Environmental Spec
Embedded Multi-In-1 Card Reader Temperature

MMC (MultiMedia Card) / RS MMC Operating: 5C - 35C
SD (Secure Digital) / Mini SD / SDHC/ SDXC Non-Operating: -20C - 60C
Compatible Relative Humidity
MS (Memory Stick) / MS Pro / MS Duo Operating: 20% - 80%
Communication Non-Operating: 10% - 90%
Built-In Gigabit Ethernet LAN Dimensions & Weight

(Factory Option) 300K/ 1.3M Pixel USB PC Camera Mod- 374mm (w) * 250mm (d) * 14.3 - 34.1mm (h)
ule
2.3 kg (with 48.84WH Battery and ODD)
(Factory Option) Bluetooth 2.1 + EDR Module
(Factory Option) 3.75G/HSPA Half Mini-Card Module
(Factory Option) Combo WLAN (802.11b/g/n) and Blue-
1.Introduction
tooth 3.0 Module
(Factory Option) Intel WiFi Link 1000 (802.11b/g/n) Wire-
less LAN Half Mini-Card Module
(Factory Option) Third-Party 802.11b/g/n Wireless LAN Half
Mini-Card Module
Power
6 Cell Smart Lithium-Ion Battery Pack, 48.84WH

(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
(Factory Option) 4 Cell Smart Lithium-Ion Battery Pack,
32.56WH
Full Range AC/DC Adapter

AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)
Energy Star 5.0 Compliant
Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
Top View
1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. LED Status
Indicators
5. Keyboard 2
6. Built-In
Microphone
1.Introduction
7. Touchpad &
Buttons
4 3
1 - 4 External Locator - Top View with LCD Panel Open

Introduction
External Locator - Front & Right Side Views Figure 2

Front View
1. LED Indicators
FRONT VIEW
1.Introduction
Figure 3
Right Side View
1. Microphone-In
RIGHT SIDE VIEW Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. Optical Device
1 2 3 Drive Bay
4 5 5. Emergency Eject
Hole
External Locator - Front & Right Side Views 1 - 5

Introduction
External Locator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor /
Port LEFT SIDE VIEW
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. 2 * USB 2.0 Ports
6. Vent
7. Multi-in-1 Card 1 2 3 4 5 5 7
Reader 6
1.Introduction
Figure 5 REAR VIEW

Rear View
1. Security Lock Slot
2. Battery
1 2
1 - 6 External Locator - Left Side & Rear View

Introduction
External Locator - Bottom View

Figure 6
Bottom View
1. Battery
2. Component Bay
Cover
3. Vent
4. Hard Disk Bay
1 Cover
5. Speakers
6. USIM Card
1.Introduction
Cover
3
3 2
3 6
3 3
4
Overheating
5 5 To prevent your com-
puter from overhea-
ting, make sure no-
thing blocks any vent
while the computer is
in use.
External Locator - Bottom View 1 - 7

Introduction
Figure 7 Mainboard Overview - Top (Key Parts)

Mainboard Top
Key Parts
1. JMC251C
2. Clock Generator
3. KBC-ITE IT8502E
1.Introduction
1 - 8 Mainboard Overview - Top (Key Parts)

Introduction
Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Bottom
Key Parts
1. Memory Slots
DDR3 SO-DIMM
2. Mini-Card
Connector (3.5G
Module)
3. Audio Codec
4. USIM Card
5. Mini-Card
Connector (WLAN
1.Introduction
1 Module)
8 6. Multi-in-1 Card
Reader
7. Platform Controller
Hub
8. CPU Socket (CPU
installed)
7
2 4 6
5
Mainboard Overview - Bottom (Key Parts) 1 - 9

Introduction
Figure 9 Mainboard Overview - Top (Connectors)

Mainboard Top
Connectors
1. HDMI-Out Port
2. USB Ports
3. Speaker Cable
Connector
4. Microphone
Cable Connector
9
5. TouchPad Cable
Connector
6. Click Board
1.Introduction
Connector
7. Audio Board 1
Connector 8
8. Keyboard Cable
Connector
2
9. Switch Board
Cable Connector
4 6
5
1 - 10 Mainboard Overview - Top (Connectors)

Introduction
Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
8 Connectors
1. Battery
10 9 7 Connector
2. ODD Connector
1 3. HDD Connector
4. Bluetooth Cable
6 Connector
5. CPU Fan Cable
Connector
6. RJ-45 LAN Jack
1.Introduction
7. External Monitor
Port
8. DC-In Jack
9. CCD Cable
11 Connector
10. LCD Cable
2
Connector
11. CMOS Battery
Connector
5
4
Mainboard Overview - Bottom (Connectors) 1 - 11

Introduction
1.Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/
E5128Q-C series notebooks parts and subsystems. When it comes to reassembly, reverse the procedures (unless other-
wise indicated).
We suggest you completely review any procedure before you take the computer apart.
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the Users Manual but are
2.Disassembly
repeated here for your convenience.
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-
Information
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
ous disassembly procedure. The amount of screws you should be left with will be listed here also.
A box with a will also provide any possible helpful information. A box with a contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap
2.Disassembly
Connections
Connections within the computer are one of four types:
Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replac-
ing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
placing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
2 - 2 Overview
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re-
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
the position of magnetized tools (i.e. screwdrivers). nected all peripherals
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power. Avoid accidental shocks, discharges or explosions. move your battery in
2.Disassembly
Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
6. Peripherals Turn off and detach any peripherals. machine on.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery: To remove the Bluetooth Module:

1. Remove the battery page 2 - 5 1. Remove the battery page 2 - 5
2. Remove the Bluetooth Module page 2 - 16
To remove the HDD:
1. Remove the battery page 2 - 5 To remove the Keyboard:
2. Remove the HDD page 2 - 6 1. Remove the battery page 2 - 5
2. Remove the keyboard page 2 - 17
To remove the Optical Device:
2.Disassembly
1. Remove the battery page 2 - 5

2. Remove the Optical device page 2 - 8
To remove the System Memory:
2. Remove the system memory page 2 - 9
To remove and install a Processor:
2. Remove the processor page 2 - 11
3. Install the processor page 2 - 13
To remove the 3G Module:
2. Remove the 3G module page 2 - 14
To remove the Wireless LAN Module:

2. Remove the WLAN module page 2 - 15
2 - 4 Disassembly Steps
Disassembly
Removing the Battery Figure 1

1. Turn the computer off, and turn it over. Battery Removal
2. Slide the latch 1 in the direction of the arrow (Figure 1a).
a. Slide latch at point 1 to-
3. Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a). wards the unlock symbol
4. Slide the battery 63 in the direction of the arrow 4 (Figure 1b). and hold it in place.
b. Slide the battery in the di-
rection of the arrow.
a. b.
2
1 3
2.Disassembly
4

3. Battery
Removing the Battery 2 - 5

Disassembly
Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating systems installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the Users Manual) when setting up a new hard disk.
a. Locate the HDD bay cover Hard Disk Upgrade Process

and remove the screws.
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).

2.Disassembly
a.
HDD System Warning
New HDDs are blank. Before you

begin make sure:
You have backed up any data

you want to keep from your old
HDD.
You have all the CD-ROMs and

FDDs required to install your op-
1 2 erating system and programs.
If you have access to the internet,

download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a remov-
able medium.
2 Screws
2 - 6 Removing the Hard Disk Drive

Disassembly
3. Remove the hard disk bay cover 63 (Figure 3b).

4. Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c). Figure 3
HDD Assembly
5. Lift the hard disk 5 out of the bay 6 (Figure 3d).
Removal (contd.)
6. Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 (Figure 3e).
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
b. d. c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
6 5 e. Remove the screws and
mylar cover.
2.Disassembly
e.
c. e.
7

8 3. HDD Bay Cover
10 11. Adhesive Cover
11
12. HDD
4 9
4 Screws
12
Removing the Hard Disk Drive 2 - 7

Disassembly
Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
1. Turn off the computer, remove the battery (page 2 - 5) and hard disk (page 2 - 6).
Removal
2. Remove the screw at point 1 (Figure 4a).
a. Remove the screw at 3. Use a screwdriver to carefully push out the optical device 3 at point 2 (Figure 4b).
point 1 . 4. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
b. Use a screwdriver to screw holes should line up).
carefully push out the 5. Restart the computer to allow it to automatically detect the new device.
optical device at point
2 .
a. b.
2.Disassembly
2 2

3. Optical Device
1 Screw
2 - 8 Removing the Optical (CD/DVD) Device

Disassembly
Removing the System Memory (RAM) Figure 5

RAM Module
The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting Removal
DDRIII (DDR3) Up to 1066/1333 MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules sup-
ported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST rou- a. Remove the screws
tine once you turn on your computer. from the component
bay cover.
Memory Upgrade Process b. The RAM modules will
1. Turn off the computer, turn it over and remove the battery (page 2 - 5). be visible at point 5
2. Remove screws 1 - 4 from the component bay cover (Figure 5a). on the mainboard.
c. Pull the release lat-
3. The RAM modules will be visible at point 5 on the mainboard (Figure 5b). ches.
4. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the d. Remove the module.
arrows (Figure 5c). The RAM module 8 will pop-up (Figure 5d), and you can then remove it.
2.Disassembly
a. c. d.
1
2
Contact Warning
6 Be careful not to touch
the metal pins on the
3
modules connecting
8 edge. Even the cleanest
4 hands have oils which
can attract particles, and
7 degrade the modules
b. performance.
5
8. RAM Module
4 Screws
Removing the System Memory (RAM) 2 - 9

Disassembly
5. Pull the latches to release the second module if necessary.

6. Insert a new module holding it at about a 30 angle and fit the connectors firmly into the memory slot.
7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot
as it will go. DO NOT FORCE IT; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
9. Replace the component bay cover and the screws (see page 2 - 8).
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2.Disassembly
2 - 10 Removing the System Memory (RAM)

Disassembly
Removing and Installing a Processor Figure 6

Processor Removal Procedure Processor Removal
1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8). a. Locate the heat sink.
2. Locate the heat sink. b. Remove the screws from
3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure the CPU heatsink.
6b). c. Remove the CPU heat
4. Carefully lift up the heat sink 4 (Figure 6c) off the computer. sink.
a. c.
2.Disassembly
A
b.

2 4. Heat Sink
3 Screws
Removing and Installing a Processor 2 - 11

Disassembly
5. Turn the release latch 5 towards the unlock symbol to release the CPU (Figure 7d).
Figure 7 6. Carefully (it may be hot) lift the CPU 6 up and out of the socket (Figure 7e).
Processor Removal 7. Reverse the process to install a new CPU.
(contd) 8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.
5
5
2.Disassembly
Unlock Lock
e.

Caution
6 The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Allow
the area time to cool before remov-
ing these parts.

6. CPU
2 - 12 Removing and Installing a Processor

Disassembly
Processor Installation Procedure Figure 8

1. Insert the CPU A (Figure 8a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE Processor
IT!), and turn the release latch B towards the lock symbol (Figure 8b). Installation
2. Remove the sticker C (Figure 8c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 8d. a. Insert the CPU.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 8d). b. Turn the release latch to-
wards the lock symbol.
5. Replace the component bay cover (dont forget to replace the fan cable) and tighten the screws (page 2 - 9).
c. Remove the sticker from
the heat sink and insert
a. c. the heat sink.
d. Tighten the screws.
A
C
2.Disassembly
b. d.
3 D
B

2 Note: A. CPU
Tighten the screws D. Heat Sink
in the order as indi-
cated on the label. 3 Screws
Removing and Installing a Processor 2 - 13

Disassembly
Figure 9 Removing the 3G Module

3G Module Removal
1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
2. The 3G module will be visible at point 1 on the mainboard (Figure 9a).
a. Locate the 3G module.
b. Disconnect the cable
3. Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 9b).
and remove the screw. 4. The 3G module 4 (Figure 9c) will pop-up, and you can remove it from the computer (Figure 9d).
c. Remove the 3G module.
a. c. d.
Note: Make sure you
reconnect the antenna
cable to socket (Fig-
ure 9b).
2.Disassembly
no 3g
b.
4
2
4. 3G Module
1 Screw
3
2 - 14 Removing the 3G Module

Disassembly
Removing the Wireless LAN Module Figure 10

Wireless LAN
1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
Module Removal
2. The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a).
3. Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b).
a. Locate the WLAN.
4. The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer (Figure 10d). b. Disconnect the cables
and remove the screw.
c. c. The WLAN module will
a. pop up.
d. Remove the Wireless
LAN module.
Note: Make sure you
2.Disassembly
5 reconnect the antenna
cable to the 1 + 2
socket (Figure 10b).
b. d.
4
3
5

5.Wireless LAN Module
2 1 Screw
Removing the Wireless LAN Module 2 - 15

Disassembly
Figure 11 Removing the Bluetooth Module

Bluetooth Module 1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
Removal 2. The Bluetooth module will be visible at point 1 on the mainboard (Figure 11a).
3. Remove screw 2 (Figure 11b) and turn the module over (Figure 11c).
a. Locate the Bluetooth 4. Carefully disconnect the cable 3 and separate the connector 4 (Figure 11c) from the Bluetooth Module.
module.
5. Lift the Bluetooth Module 5 (Figure 11d) up and off the computer.
b. Remove the screw and
turn the module over.
c. Disconnect the cable a. c. d.
and the connector from
the Bluetooth module.
d. Lift the Bluetooth module
out. 3
2.Disassembly
1 4
b.

5. Bluetooth Module
2
1 Screw
2 - 16 Removing the Bluetooth Module

Disassembly
Removing the Keyboard Figure 12

Keyboard Removal
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Remove screws 1 - 2 from the bottom of the computer. Press at point 3 to unsnap the LED cover module (you a. Remove screws from the
may need to use a small screwdriver to do this Figure 12a). bottom of the computer.
b. Turn the computer over,
3. Turn the computer over, unsnap up the LED cover module 4 from point 5 on the left of the computer, towards the
unsnap up the LED cov-
right (Figure 12b). er module from point 5
4. Remove screws 6 - 10 from the keyboard (Figure 12c). towards the right .
5. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable 11 . Disconnect the keyboard c. Remove screws from
ribbon cable 11 from the locking collar socket 12 (Figure 12d) the keyboard.
6. Carefully lift up the keyboard 13 (Figure 12e) off the computer. d. Carefully lift the key-
board up and disconnect
a. d. the keyboard ribbon ca-
11 ble from the locking col-
2.Disassembly
lar socket.
e. Remove the keyboard.
12
1 3 2
b.

5
Re-Inserting the
4 Keyboard
e.
When re-inserting the
keyboard firstly align the
four keyboard tabs at the
bottom (Figure 12c) at
the bottom of the key-
c. board with the slots in the
case.
6 7 8 9 10
13

4. LED Cover Module
13. Keyboard
7 Screws
Keyboard Tabs
Removing the Keyboard 2 - 17

Disassembly
2.Disassembly
2 - 18
Appendix A:Part Lists
This appendix breaks down the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebooks construc-
tion into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturers part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
A.Part Lists
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
E5120Q/E5120Q-C/E5125/
Location Part
E5125-C/E5128Q/E5128Q-C
Top (E5120Q) page A - 3

Top (E5125) page A - 4
Top (E5128Q) page A - 5
Bottom page A - 6
A.Part Lists
DVD Dual Drive page A - 7

LCD page A - 8
A - 2
Top (E5120Q)
Figure A - 1
A.Part Lists
Top (E5120Q)
Top (E5120Q) A - 3
Top (E5125)
Figure A - 2
A.Part Lists
Top (E5125)
A - 4 Top (E5125)
Top (E5128Q)
Figure 3
A.Part Lists
Top (E5128Q)
Top (E5128Q) A - 5
Bottom
Figure A - 4
A.Part Lists
Bottom
A - 6 Bottom
DVD Dual Drive
Figure A - 5
DVD Dual Drive
A.Part Lists

DVD Dual Drive A - 7

LCD
Figure A - 6
A.Part Lists
LCD

A - 8 LCD
Schematic Diagrams
Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C notebooks PCBs.
The following table indicates where to find the appropriate schematic diagram.
Table B - 1
Diagram - Page Diagram - Page Diagram - Page
SCHEMATIC
DIAGRAMS
System Block Diagram - Page B - 2 IBEXPEAK - M 2/9 - Page B - 16 LED, MDC, BT - Page B - 30
B.Schematic Diagrams
Clock Generator - Page B - 3 IBEXPEAK - M 3/9 - Page B - 17 USB, Fan, TP, Multi-Conn - Page B - 31
CPU 1/7 (DMI, PEG, FDI) - Page B - 4 IBEXPEAK - M 4/9 - Page B - 18 5VS, 3VS, 1.5VS - Page B - 32
CPU 2/7 (CLK, MISC, JTAG) - Page B - 5 IBEXPEAK - M 5/9 - Page B - 19 Power 3.3V/5V - Page B - 33
CPU 3/7 (DDR3) - Page B - 6 IBEXPEAK - M 6/9 - Page B - 20 Power 1.5V/0.75V, 1.8VS - Page B - 34
CPU 4/7 (Power) - Page B - 7 IBEXPEAK - M 7/9 - Page B - 21 Power 1.1VS_VTT - Page B - 35

CPU 5/7 (Graphics Power) - Page B - 8 IBEXPEAK - M 8/9 - Page B - 22 Power VGFX_Core - Page B - 36
Version Note
CPU 6/7 (GND) - Page B - 9 IBEXPEAK - M 9/9 - Page B - 23 V-Core - Page B - 37
CPU 7/7 (RESERVED) - Page B - 10 New Card, Mini PCIE - Page B - 24 AC_IN, Charger - Page B - 38
The schematic dia-
grams in this chapter
DDR3 SO-DIMM_0 - Page B - 11 3G, CCD, TPM - Page B - 25 Click Board - Page B - 39 are based upon ver-
DDR3 SO-DIMM_1 - Page B - 12 Card Reader/LAN JMB251C - Page B - 26 Audio Board/USB - Page B - 40
sion 6-7P-E51Q5-003.
If your mainboard (or
LVDS, Inverter - Page B - 13 LAN (JMC251C), SATA HDD, ODD - Page B - 27 Power Switch & LED Board - Page B - 41 other boards) are a la-
HDMI, CRT - Page B - 14 Audio Codec VIA1812 - Page B - 28 External ODD Board - Page B - 42 ter version, please
check with the Service
IBEXPEAK- M 1/9 - Page B - 15 KBC-ITE IT8502E - Page B - 29 Center for updated di-
agrams (if required).
B - 1
Schematic Diagrams
System Block Diagram

CLICK BOARD
6-71-E51Q2-D01A Calpella System Block Diagram VDD3,VDD5
POWER SWITCH BOARD 14.318 MHz

POWER SWITCH+HOTKEY X 3 POWER GPU 1.8VS
6-71-E51QS-D01A Clock Generator
RTM875N-632-VB-GRT
Memory Termination
AUDIO BOARD Arrandale 800/1067 MHz 5V,3V,5VS,3VS,1.5VS,
USB+EARPHONE+EXT.MIC DDR3 / 1.5V
6-71-C4508-D02A PROCESSOR DDRIII
SO-DIMM0
EXTERNAL ODD BOARD rPGA989/988 SYSTEM SMBUS 1.5V,0.75VS(VTT_MEM)
EXT. ODD
0.1"~13 DDRIII
6-71-E51QN-D01
SO-DIMM1
SHEET 11 VCORE 1.1VS_VTT
FDI DMI*4
HDMI
0.5"~6.5" <=8"
<15" AUDIO BOARD

CLICK BOARD CRT CONNECTOR
Sheet 1 of 42 TOUCH PAD CRT SWITCH
INTERNAL
GRAPHICS Ibex Peak-M
Synaptic MIC HP
System Block 810602-1703 Platform RJ-11 IN OUT
LCD CONNECTOR, <8"
Diagram LV DS S WI TC H
INTERNAL
GRAPHICS Controller
Hub (PCH) AZALIA INT SPK R
32.768 KHz AMP
MDC
EC Azalia Codec N7101
SPI TPM MODULE INT SPK L
ITE 8502E VIA VT1812
128pins LQFP
MDC CON
1 4*14 *1.6 mm 33 MHz
INT MIC
LPC 27x27mm
0.5"~11" BIOS 1071 Ball FCBGA AZALIA LINK 24 MHz
SPI
INT. K/B EC SMBUS
PCIE 100 MHz <12"
THERMAL SMART SMART
SENSOR FAN BATTERY
32.768KHz
W83L771AWG
New Card 3G CARD Mini PCIE JMICRO
SOCKET SOCKET
USB2.0 (USB9) JMC251 C
SATA I/II 3.0Gb/s <12" (USB3) (USB2)
480 Mbps
LAN CARD READER 25
1"~16"
MHz
7IN1
RJ-45
SOCKET
SATA HDD SATA ODD USB0 USB1 USB4 Bluetooth CCD
(USB11) (USB5)
AUDIO
BOARD
B - 2 System Block Diagram

Schematic Diagrams
Clock Generator
CLKGEN POWER
CLOCK GENERATOR
CL K _ V CC 1 CL K _ V CC 2 3 .3 VS
CL K _ V CC1
U7
1 15 L15 * 15 m i _l s ho rt _ 0 6
5 VD D_ DO T V DD_ S R C_ I/O 18
17 VD D_ 2 7 V DD_ CP U_ I/O C2 0 5 C 19 7 C 2 07
24 VD D_ S RC
29 VD D_ CPU 3 0 . 1u _ 1 6V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5V _ 0 4 1u _ 6. 3 V _ X 5R _0 4
VD D_ REF D OT _ 96 4 C LK _B U F _D OT 9 6_ P 1 5
D O T_ 9 6# C LK _B U F _D OT 9 6_ N 15
6
27M 7
XO U T 27 2 7 M_ S S
XI N 28 X T A L _O U T
X T A L _I N 0. 1 u F n e ar t he e ve r y p o we r pi n
10
S R C _1 / S A T A C LK _S A T A 1 5
11
S R C _ 1 #/ S A TA # 13 C LK _S A T A # 1 5
30 S R C _2 14 C LK _P C I E _ I C H 1 5
15 C L K _ B U F _ R E F 14 R1 3 4 3 3_ 0 4 RE F _ 0 /CP U_ S E L C LK _P C I E _ I C H # 1 5
R E F _ 0/ C P U _ S E L S R C _ 2#
CL K _ SDAT A 31
CL K _ SCL K 32 SD A 16 C P U _S T O P # R 1 48 2. 2 1 K _1 % _ 04
SC L C P U _ S T OP # 3 .3 VS 1 . 1 V S _V TT
2 20 C LK _V C C 2
8 V S S _D OT C P U _1 19
9 V S S _2 7 C P U _ 1# 23 L 14 *1 5 mi l _ sh o rt _0 6
V S S _S A T A C P U _0 C LK _B U F _B C L K _P 15
12 22
21 V S S _S R C C P U _ 0# C LK _B U F _B C L K _N 15
C 2 06 C1 9 6
26 V S S _C P U 25 CL K _ P W RG D
V S S _R E F C K P W R GD / P D # V D D_ I / O c a n b e
33
G ND
S L G 8S P 5 8 5 3 .3 VS
0. 1 u _ 16 V _ Y 5 V _ 04 1 u_ 6 . 3 V _X 5 R _ 0 4
r a ng i n g f r om
1 . 05 V to 3 .3 V
Sheet 2 of 42
Sl e g o S L G8 S P 58 5 6- 0 2 -0 8 58 5 - EQ 0
Re a l te k RT M 8 75 N - 63 2 - VB - GR T
R 14 9
Clock Generator
0 . 1u F ne a r t h e e v er y po w e r p i n
1 0 K _1 % _ 04
D
Q1 2 R 14 6
G
SMBus 36 CL KE N #
MT N 7 00 2 Z H S 3 1 M_ 0 4
S
Q1 1A
MT D N 70 0 2Z H S 6 R EMI
2
D
CL K _ SCL K
15 S MB _ C L K C L K _ S C L K 1 0 , 11
6 -22 -1 4R3 1- 1B7
6
3 . 3V S 6 -22 -1 4R3 1- 1B6

G
X1 H S X 5 30 G_ 1 4 . 31 8 18 M H z
5 VS 1 4 2 1
R N 15 XIN X OU T
2 3 2 . 2K _ 4 P 2 R _ 04 R E F _ 0/ C P U _ S E L C 19 4 *1 0 p_ 5 0V _N P O_ 0 6
G
C 1 99 C 20 2
3
CL K _ SDAT A
15 S MB _ D A T A C L K _ S D A T A 1 0 , 11
33 p _5 0 V _ N P O_ 0 4 3 3 p_ 5 0 V _N P O_ 0 4 E MI C ap a ct i o r
D
S
5
Q1 1B
MT D N 70 0 2Z H S 6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 . 3V S
P IN _ 3 0 C P U_ 0 C P U_ 1
R1 3 6 *4 . 7 K _0 4 R E F _0 / C P U _ S E L
0 ( d ef a u lt ) 1 3 3M H z 1 3 3M H z
R1 3 7 1 0K _ 0 4
1 ( 0 .7 V - 1. 5 V ) 1 0 0M H z 1 0 0M H z 5V S 1 3 , 17 , 2 0, 2 1 , 2 6, 2 7 , 3 0, 3 1 , 35 , 3 6
3. 3 V 3 , 4 , 12 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 21 , 2 3 , 24 , 2 5 , 29 , 3 0, 31 , 3 3, 3 4 , 3 5
3. 3 V S 1 0 , 11 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4, 2 5 , 2 6, 2 7 , 2 8, 2 9 , 30 , 3 1 , 35 , 3 6
1. 1 V S _ V T T 4 , 6 , 7 , 14 , 1 5 , 16 , 1 9, 20 , 2 1, 3 4 , 3 5, 3 6
Clock Generator B - 3
Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)

PROCESSOR 1/7 ( DMI,PEG,FDI )
U 16 A
B2 6 20 mil P E G_ I R C O MP _ R R2 0 9 4 9. 9 _ 1 % _0 4
P E G_ I C OM P I A2 6
A2 4 P E G _ I C O MP O B2 7
16 D M I _T X N 0 C2 3 DM I_ RX # [0 ] P E G_ R C O MP O A2 5 E XP _R B I A S R2 0 8 7 50 _ 1 % _0 4
16 D M I _T X N 1 B2 2 DM I_ RX # [1 ] P E G_ R B I A S
16 D M I _T X N 2 A2 1 DM I_ RX # [2 ] K3 5
16 D M I _T X N 3 DM I_ RX # [3 ] P E G_ R X # [ 0 ] J34
B2 4 P E G_ R X # [ 1 ] J33
16 D M I _T X P 0 D2 3 DM I_ RX [0 ] P E G_ R X # [ 2 ] G 35
16 D M I _T X P 1 B2 3 DM I_ RX [1 ] P E G_ R X # [ 3 ] G 32
DMI
16 D M I _T X P 2 A2 2 DM I_ RX [2 ] P E G_ R X # [ 4 ] F3 4
16 D M I _T X P 3 DM I_ RX [3 ] P E G_ R X # [ 5 ] F3 1
D2 4 P E G_ R X # [ 6 ] D 35
16 D MI _ R XN 0 G2 4 DM I _ T X# [ 0 ] P E G_ R X # [ 7 ] E3 3
16 D MI _ R XN 1 F23 DM I _ T X# [ 1 ] P E G_ R X # [ 8 ] C 33
16 D MI _ R XN 2 H2 3 DM I _ T X# [ 2 ] P E G_ R X # [ 9 ] D 32
16 D MI _ R XN 3 DM I _ T X# [ 3 ] P E G_ R X# [ 1 0 ] B3 2
D2 5 P E G_ R X# [ 1 1 ] C 31
16 D MI _ R XP 0 F24 DM I _ T X[ 0 ] P E G_ R X# [ 1 2 ] B2 8
16 D MI _ R XP 1 DM I _ T X[ 1 ] P E G_ R X# [ 1 3 ]
E2 3 B3 0
16 D MI _ R XP 2 G2 3 DM I _ T X[ 2 ] P E G_ R X# [ 1 4 ] A3 1
16 D MI _ R XP 3 DM I _ T X[ 3 ] P E G_ R X# [ 1 5 ]
J35
P E G _ RX [0 ] H 34
P E G _ RX [1 ] H 33
E2 2 P E G _ RX [2 ] F3 5
16 FD I _ T XN 0 FD I _T X # [ 0 ] P E G _ RX [3 ]
D2 1 G 33
16 FD I _ T XN 1 D1 9 FD I _T X # [ 1 ] P E G _ RX [4 ] E3 4
16 FD I _ T XN 2 D1 8 FD I _T X # [ 2 ] P E G _ RX [5 ] F3 2
16 FD I _ T XN 3 G2 1 FD I _T X # [ 3 ] P E G _ RX [6 ] D 34
16 FD I _ T XN 4 E1 9 FD I _T X # [ 4 ] P E G _ RX [7 ] F3 3
16 FD I _ T XN 5
PCI EXPRESS -- GRAPHICS

F21 FD I _T X # [ 5 ] P E G _ RX [8 ] B3 3
16 FD I _ T XN 6 G1 8 FD I _T X # [ 6 ] P E G _ RX [9 ] D 31
Intel(R) FDI
Sheet 3 of 42 16 FD I _ T XN 7
D2 2
FD I _T X # [ 7 ] P E G_ R X [ 1 0 ]
P E G_ R X [ 1 1 ]
P E G_ R X [ 1 2 ]
A3 2
C 30
A2 8
16 FD I _ T XP 0
CPU 1/7 16
16
FD
FD
I _ T XP 1
I _ T XP 2
C2 1
D2 0
C1 8
FD
FD
FD
I _T X [ 0 ]
I _T X [ 1 ]
I _T X [ 2 ]
P E G_ R X [ 1 3 ]
P E G_ R X [ 1 4 ]
P E G_ R X [ 1 5 ]
B2 9
A3 0
16 FD I _ T XP 3 G2 2 FD I _T X [ 3 ] L33
(DMI, PEG, FDI) 16
16
16
FD
FD
FD
I _ T XP 4
I _ T XP 5
I _ T XP 6
E2 0
F20
G1 9
FD
FD
FD
I _T X [ 4 ]
I _T X [ 5 ]
I _T X [ 6 ]
P E G _ TX # [ 0 ]
P E G _ TX # [ 1 ]
P E G _ TX # [ 2 ]
M 35
M 33
M 30
16 FD I _ T XP 7 FD I _T X [ 7 ] P E G _ TX # [ 3 ] L31
It applies to Auburndale and Clarksfield discrete graphic designs. F17 P E G _ TX # [ 4 ] K3 2
16 F DI_ F S Y NC 0 E1 7 F D I _F S Y N C [ 0 ] P E G _ TX # [ 5 ] M 29
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected 16 F DI_ F S Y NC 1 F D I _F S Y N C [ 1 ] P E G _ TX # [ 6 ] J31
to GND if motherboard only supports discrete graphics and also in a common C1 7 P E G _ TX # [ 7 ] K2 9
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed, 16 F DI_ IN T F D I _I N T P E G _ TX # [ 8 ] H 30
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from F18 P E G _ TX # [ 9 ] H 29
16 F DI_ L S Y N C0 D1 7 F D I _L S Y N C [ 0 ] P E G_ T X# [ 1 0 ] F2 9
floating).
16 F DI_ L S Y N C1 F D I _L S Y N C [ 1 ] P E G_ T X# [ 1 1 ] E2 8
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
P E G_ T X# [ 1 2 ] D 29
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale. P E G_ T X# [ 1 3 ] D 27
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and P E G_ T X# [ 1 4 ] C 26
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common P E G_ T X# [ 1 5 ]
motherboard design case. Please not that if these signals are left floating, there are no L34
P E G _T X [ 0 ] M 34
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE P E G _T X [ 1 ] M 32
and VSSAXG_SENSE on Auburndale can be left as no connect. P E G _T X [ 2 ] L30
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale P E G _T X [ 3 ] M 31
directly if motherboard only supports discrete graphics. In a common motherboard P E G _T X [ 4 ] K3 1
P E G _T X [ 5 ] M 28
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
P E G _T X [ 6 ] H 31
external termination is required. P E G _T X [ 7 ] K2 8
P E G _T X [ 8 ] G 30
P E G _T X [ 9 ] G 29
P E G _ TX [ 1 0 ] F2 8
P E G _ TX [ 1 1 ] E2 7
Thermal Sensor near U16 P E G _ TX [ 1 2 ] D 28
P E G _ TX [ 1 3 ] C 27
P E G _ TX [ 1 4 ] C 25
P E G _ TX [ 1 5 ]
P Z 9 8 9 2 7-3 6 4 1 -01 F
3 .3 V
Analog Thermal Sensor

C 35 7 R 22 8 * 1 0m i l _s h o rt _ 0 4 3 .3 V
C R I T _ TE MP _ R E P # 19
Q 14
* 0. 1 u _ 16 V _ Y 5V _0 4 2 1 1 :2 ( 4m il s: 8m il s)
V CC OU T T H E R M_ V O L T 2 8
T H E R M_ A L E R T # 2 8 4 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9 , 20 , 2 1 , 2 3, 2 4 , 2 5 , 2 9, 3 0 , 3 1 , 33 , 3 4 , 3 5 3. 3 V
U1 8
1 4 C A C 359 3 C3 6 0
2 VDD T HE RM 6 P M _E X T T S # _ E C 4 GN D
C
D+ AL ER T D1 6 *C D B U 0 03 4 0 0 . 1 u _ 16 V _ Y 5V _0 4 0. 1u _ 1 6V _Y 5 V _ 04
B G7 1 1 S T9 U
1
Q 10 3
*2 N 3 9 0 4 3 7
5 D- S D A TA 8 S M D_ CPU _ T HER M 1 5 ,2 8
E
GN D S C LK S M C_ CPU _ T HER M 1 5 ,2 8
2
*W 8 3 L 7 71 A W G PLACE NEAR U16
B - 4 CPU 1/7 (DMI, PEG, FDI)

Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)

PROCESSOR 2/7 ( CLK,MISC,JTAG ) 1. 5 V
Processor Compensation
R 2 03
Signals * 1 K _ 1% _ 0 4
R 2 38 4 9 . 9 _1 % _ 0 4 H _ C O MP 0 R2 0 6 *1 0 m il _ s h ort _ 0 4
R 2 13 4 9 . 9 _1 % _ 0 4 H _ C O MP 1 DDR3 Compensation Signals BSS138 ( VGS 1.5V )
S M _R C O MP _ 0 R2 2 9 1 0 0 _1 % _ 0 4 Q1 3
*R J U 0 0 3N 0 3T 1 0 6
S M _R C O MP _ 1 R2 3 0 2 4 . 9 _1 % _ 0 4 S M_ D R A MR S T # S D
H _ C O MP 2 D D R 3 _ D R A M R S T # 1 0, 1 1
R 2 37 2 0 _ 1% _ 0 4
S M _R C O MP _ 2 R2 3 1 1 3 0 _1 % _ 0 4
R 2 36 2 0 _ 1% _ 0 4 H _ C O MP 3 R2 0 7
G
*1 0 0K _1 % _ 04
D R A MR S T _C T R L 9 , 1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
C3 1 1 ? ? IBEX CONTROL
*4 7 n _5 0 V _ 0 4
U 1 6B
H _ C OM P 3 A T2 3
C OM P 3 A1 6
BC L K B CL K _ CP U_ P 1 9
MISC
H _ C OM P 2 A T2 4 B1 6
Processor Pullups C OM P 2 B CL K # B CL K _ CP U_ N 1 9
H _ C OM P 1 G1 6 A R 30
C OM P 1 B CL K _ IT P AT3 0
CLOCKS
1 .1 V S _ V T T H _ C OM P 0 A T2 6 B CL K _ IT P #
R 2 19 4 9 . 9 _1 % _ 0 4 H _ C A TE R R # A H2 4
C OM P 0
P E G _C L K
P E G _ CL K #
E1 6
D 16 CL K_ EXP_ P 1 5
CL K_ EXP_ N 1 5 Sheet 4 of 42
S K T O CC # A1 8
R 2 39 6 8 _ 04 H _ P R OC H O T# _ D
H_ C A T E RR # AK1 4
C A TE R R #
DP L L _ RE F _ S S C L K
D P LL _ R E F _S S C L K #
A1 7
CL K _ DP _ P
CL K _ DP _ N
15
15 CPU 2/7
THERMAL
R 2 47 * 68 _ 0 4 H _ C P U R S T#
A T1 5 S M_ D R A M R S T #
F6 S M_ D R A MR S T #
1. 1 V S _ V T T
(CLK, MISC, JTAG)
19 , 2 8 H _ P E C I PEC I AL 1 S M_ R C OM P _ 0
S M_ R C OM P [ 0 ] AM 1 S M_ R C OM P _ 1 R2 3 3 10 K _ 0 4
S M_ R C OM P [ 1 ] AN 1 S M_ R C OM P _ 2 R5 4 10 K _ 0 4
R2 4 8 *1 0 m i _l s h ort _ 0 4 H _ P R O C H OT # _ D A N2 6 S M_ R C OM P [ 2 ]
DDR3
MISC
3 6 H _ P R O C H OT # P R OC H O T# A N 15 P M_ E X TT S # [ 0 ] R5 3 *0 _0 4 P M _E X T T S # _E C 3
If PROCHOT# is not used, then it must be terminated P M_ E X T_ T S # [ 0 ] AP1 5 P M_ E X TT S # [ 1 ] R2 3 2 *0 _0 4
P M_ E X T_ T S # [ 1 ] T S # _D I MM 0 _1 1 0 , 1 1
with a 50-O pull-up resistor to VTT_1.1 rail.
AK1 5 R2 3 4 *1 2. 4K _ 1 % _ 04
1 9 H _ T H R MT R I P # T H E R MT R I P #
AT2 8
P RD Y # AP2 7 X D P _ P RE Q #
P R E Q#
A N 28 X D P _ TC L K
H_ C P UR S T # AP2 6 TC K AP2 8 X D P _ TM S
R E S E T _O B S # TM S AT2 7
PWR MANAGEMENT
X D P _ TR S T #
T RS T #
A L1 5 AT2 9 XD P _ TD I_ R
JTAG & BPM

1 6 H_ PM _ S YN C P M _S Y N C TD I A R 27 XD P _ TD O_ R
T DO A R 29 XD P _ TD I_ M 1. 1 V S _ V T T
S Y S _ A GE N T_ P W R O K A N 1 4 T D I _M AP2 9 XD P _ TD O_ M
1 6, 3 6 D E LA Y _ P W R GD R2 4 9 * 0 _0 4
V C C P W R GO OD _ 1 T D O _M XD P _ T MS R2 5 2 *5 1_ 0 4
R2 5 0 *1 0 m li _ s ho rt _ 0 4 A N 25 XD P _ T D O _M R2 4 4 51 _ 0 4
A N2 7 DB R# XD P _ T DI_ R R2 5 1 *5 1_ 0 4
19 H _C P U P W R G D V C C P W R GO OD _ 0 XD P _ P R E Q# R2 4 2 *5 1_ 0 4
AJ 2 2 XD P _ T D O _R R2 4 1 *5 1_ 0 4
AK1 3 B P M# [ 0 ] AK2 2
1 6 P M_ D R A M _ P W R G D R5 2 *1 0 m li _ s ho rt _ 0 4 V D D P W R GO OD _ R
S M _D R A MP W R OK B P M# [ 1 ] AK2 4
B P M# [ 2 ] AJ 2 4
A M1 5 B P M# [ 3 ] AJ 2 5
16 H _V TT P W R GD V T T P W R GOO D B P M# [ 4 ] A H 22
B P M# [ 5 ] AK2 3 XD P _ T C L K
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power R2 4 5 *5 1_ 0 4
good signal to processor. Signal voltage level is 1.1 V. H_ P W RG D_ X DP A M2 6 B P M# [ 6 ] A H 23 XD P _ T R S T # R2 4 0 51 _ 0 4
T A P P W R GO OD B P M# [ 7 ]
R6 0 1 . 5 K _ 1 % _0 4 P L T _R S T # _R A L1 4
1 8 , 23 , 2 5 , 2 8 B U F _ P L T _R S T # R S TI N #
Signal from PCH to Processor
Connect to PCH (PLT_RST#) R 61
(needs to be level translated 7 5 0 _1 % _ 04 P Z 98 9 2 7-3 6 4 1 -01 F
from 3.3 V to 1.1 V).
XD P _ T D O _M R2 4 3 *1 0 m il _ s h ort _ 0 4X D P _ T D I _ M
1 .5 V S _ CP U
3. 3 V
R5 0
1 . 1 K _1 % _ 0 4 R 2 35 *8 . 2 K _ 04
3 . 3V 3 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9, 2 0 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5
V D D P W R GO OD _ R
1 . 5V 9 , 1 0, 1 1 , 2 1 , 23 , 2 7 , 2 9, 3 1 , 3 3 , 36
5
U 17 1 . 5V S _C P U 7, 3 1
1 I N 3 . 3V
4 1 . 1V S _V TT 2 , 6 , 7 , 1 4, 1 5 , 1 6, 19 , 2 0 , 2 1, 3 4 , 3 5, 36
R6 2 R2 4 6 *1 . 5 K _ 1 % _0 4 D R A MP W R GD _ C P U
2
1 . 1 V S _ V T T _P W R G D 1 6 , 3 3 , 34
3 K _ 1% _ 0 4
* MC 7 4V H C 1 G 08 D F T 1G
3
Intel change
4.75K -->1.1K
12K -->3K
CPU 2/7 (CLK, MISC, JTAG) B - 5

Schematic Diagrams
CPU 3/7 (DDR3)

PROCESSOR 3/7 ( DDR3 )
U16C
U16D
AA6
SA_CK[0] AA7 M_CLK_DDR0 10 W8
10 M_A_DQ[63:0] SA_CK#[0] M_CLK_DDR#0 10 11 M_B_DQ[ 63
: 0] SB_CK[ 0] M_CL
K_DDR2 11
P7 W9
SA_CKE[0] M_CKE0 10 SB_CK#[ 0] M_CL
K_DDR#2 11
M_A_DQ0 A10 M_
B_DQ0 B5 M3
SA_DQ[0] SB_DQ[0] SB_CKE[ 0] M_CKE2 11
M_A_DQ1 C10 M_
B_DQ1 A5
M_A_DQ2 C7 SA_DQ[1] M_
B_DQ2 C3 SB_DQ[1]
M_A_DQ3 A7 SA_DQ[2] Y6 M_
B_DQ3 B3 SB_DQ[2] V7
B10 SA_DQ[3] SA_CK[1] Y5 M_CLK_DDR1 10 E4 SB_DQ[3] SB_CK[ 1] V6 M_CL
K_DDR3 11
M_A_DQ4 M_
B_DQ4
D10 SA_DQ[4] SA_CK#[1] P6 M_CLK_DDR#1 10 A6 SB_DQ[4] SB_CK#[ 1] M2 M_CL
K_DDR#3 11
M_A_DQ5 M_
B_DQ5
M_A_DQ6 E10 SA_DQ[5] SA_CKE[1] M_CKE1 10 M_
B_DQ6 A4 SB_DQ[5] SB_CKE[ 1] M_CKE3 11
M_A_DQ7 A8 SA_DQ[6] M_
B_DQ7 C4 SB_DQ[6]
M_A_DQ8 D8 SA_DQ[7] M_
B_DQ8 D1 SB_DQ[7]
M_A_DQ9 F10 SA_DQ[8] AE2 M_
B_DQ9 D2 SB_DQ[8]
SA_DQ[9] SA_CS#[0] M_CS#0 10 SB_DQ[9]
M_A_DQ10 E6 AE8 M_
B_DQ10 F2 AB8
F7 SA_DQ[10] SA_CS#[1] M_CS#1 10 F1 SB_DQ[10] SB_CS#[ 0] AD6 M_CS#2 11
M_A_DQ11 M_
B_DQ11
E9 SA_DQ[11] C2 SB_DQ[11] SB_CS#[ 1] M_CS#3 11
M_A_DQ12 M_
B_DQ12
B7 SA_DQ[12] F5 SB_DQ[12]
M_A_DQ13 M_
B_DQ13
M_A_DQ14 E7 SA_DQ[13] AD8 M_
B_DQ14 F3 SB_DQ[13]
SA_DQ[14] SA_ODT[0] M_ODT
0 10 SB_DQ[14]
M_A_DQ15 C6 AF9 M_
B_DQ15 G4 AC7
SA_DQ[15] SA_ODT[1] M_ODT
1 10 SB_DQ[15] SB_ODT[ 0] M_ODT2 11
M_A_DQ16 H10 M_
B_DQ16 H6 AD1
SA_DQ[16] SB_DQ[16] SB_ODT[ 1] M_ODT3 11
M_A_DQ17 G8 M_
B_DQ17 G2
M_A_DQ18 K7 SA_DQ[17] M_
B_DQ18 J6 SB_DQ[17]
M_A_DQ19 J8 SA_DQ[18] M_
B_DQ19 J3 SB_DQ[18]
G7 SA_DQ[19] G1 SB_DQ[19]
M_A_DQ20 M_
B_DQ20 M_B_DM[7:0] 11
M_A_DQ21 G10 SA_DQ[20] M_
B_DQ21 G5 SB_DQ[20] D4 M_B_DM0
SA_DQ[21] M_A_DM[7
: 0] 10 SB_DQ[21] SB_DM[ 0]
M_A_DQ22 J7 B9 M_A_DM0 M_
B_DQ22 J2 E1 M_B_DM1
M_A_DQ23 J10 SA_DQ[22] SA_DM[0] D7 M_A_DM1 M_
B_DQ23 J1 SB_DQ[22] SB_DM[ 1] H3 M_B_DM2
Sheet 5 of 42 M_A_DQ
M_A_DQ
M_A_DQ
24
25
26
L7
M
M
6
8
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DM[1]
SA_DM[2]
SA_DM[3]
H7
M7
AG6
M_A_DM2
M_A_DM3
M_A_DM4
M_
B_DQ24
M_
B_DQ25
M_
B_DQ26
J5
K2
L3
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DM
SB_DM
SB_DM
[ 2]
[ 3]
[ 4]
K1
AH1
AL
2
M
M
M
_B_DM3
_B_DM4
_B_DM5
CPU 3/7 L9 SA_DQ[26] SA_DM[4] AM7 M1 SB_DQ[26] SB_DM[ 5] AR4

M_A_DQ27 M_A_DM5 M_
B_DQ27 M_B_DM6
M_A_DQ28 L6 SA_DQ[27] SA_DM[5] AN10 M_A_DM6 M_
B_DQ28 K5 SB_DQ[27] SB_DM[ 6] AT
8 M_B_DM7
M_A_DQ29 K8 SA_DQ[28] SA_DM[6] AN13 M_A_DM7 M_
B_DQ29 K4 SB_DQ[28] SB_DM[ 7]
SA_DQ[29] SA_DM[7] SB_DQ[29]
(DDR3)
M_A_DQ30 N8 M_
B_DQ30 M4
M_A_DQ31 P9 SA_DQ[30] M_
B_DQ31 N5 SB_DQ[30]
M_A_DQ32 AH5 SA_DQ[31] M_
B_DQ32 AF3 SB_DQ[31]
M_A_DQ33 AF5 SA_DQ[32] M_
B_DQ33 AG1 SB_DQ[32]
AK6 SA_DQ[33] C9 M_A_DQS#[7:0] 10 AJ3 SB_DQ[33] D5 M_B_DQS#[7:0] 11
M_A_DQ34 M_A_DQS#0 M_
B_DQ34 M_B_DQS#0
AK7 SA_DQ[34] SA_DQS#[0] F8 AK1 SB_DQ[34] SB_DQS#[ 0] F4
M_A_DQ35 M_A_DQS#1 M_
B_DQ35 M_B_DQS#1
D DR S YSTE M ME MORY A
M_A_DQ36 AF6 SA_DQ[35] SA_DQS#[1] J9 M_A_DQS#2 M_
B_DQ36 AG4 SB_DQ[35] SB_DQS#[ 1] J4 M_B_DQS#2
M_A_DQ37 AG 5 SA_DQ[36] SA_DQS#[2] N9 M_A_DQS#3 M_
B_DQ37 AG3 SB_DQ[36] SB_DQS#[ 2] L4 M_B_DQS#3
M_A_DQ38 AJ7 SA_DQ[37] SA_DQS#[3] AH7 M_A_DQS#4 M_
B_DQ38 AJ4 SB_DQ[37] SB_DQS#[ 3] AH2 M_B_DQS#4
M_A_DQ39 AJ6 SA_DQ[38] SA_DQS#[4] AK9 M_A_DQS#5 M_
B_DQ39 AH4 SB_DQ[38] SB_DQS#[ 4] AL4 M_B_DQS#5
D DR S YSTE M ME MORY - B
M_A_DQ40 AJ10 SA_DQ[39] SA_DQS#[5] AP11 M_A_DQS#6 M_
B_DQ40 AK3 SB_DQ[39] SB_DQS#[ 5] AR5 M_B_DQS#6
M_A_DQ41 AJ9 SA_DQ[40] SA_DQS#[6] AT13 M_A_DQS#7 M_
B_DQ41 AK4 SB_DQ[40] SB_DQS#[ 6] AR8 M_B_DQS#7
AL10 SA_DQ[41] SA_DQS#[7] AM6 SB_DQ[41] SB_DQS#[ 7]
M_A_DQ42 M_
B_DQ42
M_A_DQ43 AK12 SA_DQ[42] M_
B_DQ43 AN2 SB_DQ[42]
M_A_DQ44 AK8 SA_DQ[43] M_
B_DQ44 AK5 SB_DQ[43]
M_A_DQ45 AL7 SA_DQ[44] M_
B_DQ45 AK2 SB_DQ[44]
SA_DQ[45] M_A_DQS[7:0] 10 SB_DQ[45]
M_A_DQ46 AK11 C8 M_A_DQS0 M_
B_DQ46 AM4
M_A_DQ47 AL8 SA_DQ[46] SA_DQS[0] F9 M_A_DQS1 M_
B_DQ47 AM3 SB_DQ[46]
AN8 SA_DQ[47] SA_DQS[1] H9 AP3 SB_DQ[47] C5 M_B_DQS[7: 0] 11
M_A_DQ48 M_A_DQS2 M_
B_DQ48 M_B_DQS0
AM10 SA_DQ[48] SA_DQS[2] M9 AN5 SB_DQ[48] SB_DQS[ 0] E3
M_A_DQ49 M_A_DQS3 M_
B_DQ49 M_B_DQS1
M_A_DQ50 AR11 SA_DQ[49] SA_DQS[3] AH8 M_A_DQS4 M_
B_DQ50 AT4 SB_DQ[49] SB_DQS[ 1] H4 M_B_DQS2
M_A_DQ51 AL11 SA_DQ[50] SA_DQS[4] AK10 M_A_DQS5 M_
B_DQ51 AN6 SB_DQ[50] SB_DQS[ 2] M5 M_B_DQS3
M_A_DQ52 AM 9 SA_DQ[51] SA_DQS[5] AN11 M_A_DQS6 M_
B_DQ52 AN4 SB_DQ[51] SB_DQS[ 3] AG2 M_B_DQS4
M_A_DQ53 AN9 SA_DQ[52] SA_DQS[6] AR13 M_A_DQS7 M_
B_DQ53 AN3 SB_DQ[52] SB_DQS[ 4] AL
5 M_B_DQS5
M_A_DQ54 AT11 SA_DQ[53] SA_DQS[7] M_
B_DQ54 AT5 SB_DQ[53] SB_DQS[ 5] AP5 M_B_DQS6
M_A_DQ55 AP12 SA_DQ[54] M_
B_DQ55 AT6 SB_DQ[54] SB_DQS[ 6] AR7 M_B_DQS7
AM12 SA_DQ[55] AN7 SB_DQ[55] SB_DQS[ 7]
M_A_DQ56 M_
B_DQ56
M_A_DQ57 AN12 SA_DQ[56] M_
B_DQ57 AP6 SB_DQ[56]
SA_DQ[57] M_A_A[15:0] 10 SB_DQ[57]
M_A_DQ58 AM13 Y3 M_A_A0 M_
B_DQ58 AP8
M_A_DQ59 AT14 SA_DQ[58] SA_MA[0] W1 M_A_A1 M_
B_DQ59 AT9 SB_DQ[58]
M_A_DQ60 AT12 SA_DQ[59] SA_MA[1] AA8 M_A_A2 M_
B_DQ60 AT7 SB_DQ[59]
M_A_DQ61 AL13 SA_DQ[60] SA_MA[2] AA3 M_A_A3 M_
B_DQ61 AP9 SB_DQ[60]
M_A_DQ62 AR14 SA_DQ[61] SA_MA[3] V1 M_A_A4 M_
B_DQ62 AR10 SB_DQ[61]
AP14 SA_DQ[62] SA_MA[4] AA9 AT10 SB_DQ[62] U5 M_B_A[15:0] 11
M_A_DQ63 M_A_A5 M_
B_DQ63 M_B_A0
SA_DQ[63] SA_MA[5] V8 SB_DQ[63] SB_MA[ 0] V2
M_A_A6 M_B_A1
SA_MA[6] T1 M_A_A7 SB_MA[ 1] T5 M_B_A2
SA_MA[7] Y9 M_A_A8 SB_MA[ 2] V3 M_B_A3
AC3 SA_MA[8] U6 M_A_A9 SB_MA[ 3] R1 M_B_A4
10 M_A_BS0 SA_BS[0] SA_MA[9] SB_MA[ 4]
AB2 AD4 M_A_A10 AB1 T8 M_B_A5
10 M_A_BS1 U7 SA_BS[1] SA_MA[10] T2 11 M_B_BS0 W5 SB_BS[0] SB_MA[ 5] R2
M_A_A11 M_B_A6
10 M_A_BS2 SA_BS[2] SA_MA[11] U3 11 M_B_BS1 R7 SB_BS[1] SB_MA[ 6] R6
M_A_A12 M_B_A7
SA_MA[12] AG 8 11 M_B_BS2 SB_BS[2] SB_MA[ 7] R4
M_A_A13 M_B_A8
SA_MA[13] T3 M_A_A14 SB_MA[ 8] R5 M_B_A9
AE1 SA_MA[14] V9 M_A_A15 AC5 SB_MA[ 9] AB5 M_B_A10
10 M_A_CAS# SA_CAS# SA_MA[15] 11 M_B_CAS# SB_CAS# SB_MA[ 10]
AB3 Y7 P3 M_B_A11
10 M_A_RAS# SA_RAS# 11 M_B_RAS# SB_RAS# SB_MA[ 11]
AE9 AC6 R3 M_B_A12
10 M_A_WE# SA_WE# 11 M_B_WE# SB_WE# SB_MA[ 12] AF7 M_B_A13
SB_MA[ 13] P5 M_B_A14
SB_MA[ 14] N1 M_B_A15
SB_MA[ 15]
PZ98927-3641-01F
PZ98927-3641-01F
B - 6 CPU 3/7 (DDR3)

Schematic Diagrams
CPU 4/7 (Power)

P ROCES SOR 4/7 ( PO WER )
U 1 6F
PRO CESSOR CORE POWER PROCESS OR UNCORE POWER

V C O RE 1 . 1 V S _ V TT
48A AG 3 5 A H1 4 V TT TOTAL 2 1A
AG 3 4 VC C1 VTT0 _ 1 A H1 2
I CC M AX M a xi m um P r oc es s or SV 4 8 VC C2 VTT0 _ 2
AG 3 3 A H1 1 C 29 C3 0 C 3 24 C3 5 C 33 C 301 C 334
AG 3 2 VC C3 VTT0 _ 3 A H1 0
AG 3 1 VC C4 VTT0 _ 4 J14 1 0 u _ 6. 3V _X 5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6 . 3 V _ X 5 R _ 0 6 2 2 u _ 6 . 3V _ X5 R _ 0 8 2 2 u _ 6 .3 V _ X 5 R_ 0 8
V CO RE AG 3 0 VC C5 VTT0 _ 5 J13
AG 2 9 VC C6 VTT0 _ 6 H 14
C3 2 3 C 331 C 335 C 337 AG 2 8 VC C7 VTT0 _ 7 H 12
AG 2 7 VC C8 VTT0 _ 8 G 14
VC C9 VTT0 _ 9
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5 R _0 8
2 2 u _ 6 . 3 V _ X 5 R_ 0 8 AG 2 6 G 13
22 u _ 6 .3 V _ X 5 R _ 08
A F3 5 VC C1 0 V TT 0 _ 1 0 G 12
A F3 4 VC C1 1 V TT 0 _ 1 1 G 11
A F3 3 VC C1 2 V TT 0 _ 1 2 F 14 C 36 C 303 C3 4 C3 2 8 ICCMAX_VTT Max Current
A F3 2 VC C1 3 V TT 0 _ 1 3 F 13
A F3 1 VC C1 4 V TT 0 _ 1 4 F 12 1 0 u _ 6. 3V _X 5 R _ 0 6 1 0 u _ 6 . 3 V _ X 5R _ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6 *1 0 u _ 6 . 3 V _ X 5R _ 0 6 for VTT Rail
A F3 0 VC C1 5 V TT 0 _ 1 5 F 11
A F2 9 VC C1 6 V TT 0 _ 1 6 E 14 SV 18
A F2 8 VC C1 7 V TT 0 _ 1 7 E 12
A F2 7 VC C1 8 V TT 0 _ 1 8 D 14
A F2 6 VC C1 9 V TT 0 _ 1 9 D 13
AD 3 5 VC C2 0 V TT 0 _ 2 0 D 12
VC C2 1 V TT 0 _ 2 1
1.1V RAIL POWER

C3 4 2 C 352 C 329 C 318 AD 3 4 D 11
AD 3 3 VC C2 2 V TT 0 _ 2 2 C 14
VC C2 3 V TT 0 _ 2 3
2 2 u _ 6 . 3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5 R_ 0 8
AD 3 2 C 13
*2 2 u _ 6. 3V _X 5 R_ 0 8
AD 3 1 VC C2 4 V TT 0 _ 2 4 C 12
AD 3 0 VC C2 5 V TT 0 _ 2 5 C 11
AD 2 9 VC C2 6 V TT 0 _ 2 6 B 14
The decoupling capacitors, filter
AD 2 8 VC C2 7 V TT 0 _ 2 7 B 12 recommendations and sense resistors on the
AD 2 7
AD 2 6
AC 3 5
VC
VC
VC
C2 8
C2 9
C3 0
V TT 0 _ 2 8
V TT 0 _ 2 9
V TT 0 _ 3 0
A 14
A 13
A 12
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
Sheet 6 of 42
VC C3 1 V TT 0 _ 3 1
CPU 4/7
AC 3 4 A 11
AC 3 3 VC C3 2 V TT 0 _ 3 2 recommendations in the Calpella Platform
AC 3 2 VC C3 3 1. 1V S _ V T T
AC 3 1 VC C3 4 Design Guide
(Power)
AC 3 0 VC C3 5 A F10
C3 3 2 C 356 C 355 C 354
AC 2 9 VC C3 6 V TT 0 _ 3 3 A E1 0
AC 2 8 VC C3 7 V TT 0 _ 3 4 A C1 0
2 2 u _ 6 .3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 08
C 304 C3 0 5 C3 1 2
AC 2 7 VC C3 8 V TT 0 _ 3 5 A B1 0
CPU CORE SUPPLY

AC 2 6 VC C3 9 V TT 0 _ 3 6 Y 10 2 2 u _ 6 . 3 V _ X 5R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X 5 R _0 8
A A3 5 VC C4 0 V TT 0 _ 3 7 W 10
A A3 4 VC C4 1 V TT 0 _ 3 8 U 10
A A3 3
A A3 2
VC
VC
C4 2
C4 3
V
V
TT 0 _ 3 9
TT 0 _ 4 0
T10
J12
1.1VS_VTT
A A3 1 VC C4 4 V TT 0 _ 4 1 J11
A A3 0 VC C4 5 V TT 0 _ 4 2 J16
Please note that the
+ V T T_ 4 3 R 216 *1 5 m li _ s h o rt _ 0 6
A A2 9 VC C4 6 V TT 0 _ 4 3 J15 + V T T_ 4 4 VTT Rail Values are
R 215 *1 5 m li _ s h o rt _ 0 6
A A2 8 VC C4 7 V TT 0 _ 4 4
A A2 7 VC C4 8
A A2 6 VC C4 9
VC C5 0
Auburndale VTT=1.05V
Y 35
Y 34 VC C5 1
Y 33 VC C5 2 1 .1 V S_ VT T
V CO RE Y 32 VC C5 3
Y 31 VC C5 4
1K PU t o V TT an d 1 K P D to GN D
Y 30 VC C5 5
Y 29 VC C5 6 fo r P OC
C3 4 8 C 346 C 345 C 344 R 2 25
Y 28 VC C5 7
* 1 0 u _6 .3 V _X 5R _ 0 6
VC C5 8 VCORE
*1 0 u _ 6. 3V _X 5 R_ 0 6
1 0 u _ 6 .3 V _ X 5 R_ 0 6
1 0 u _ 6 .3 V _ X 5 R_ 0 6
Y 27 * 1 K _ 1% _ 0 4
Y 26 VC C5 9
V3 5 VC C6 0 A N3 3 PSI #
VC C6 1 P SI# P S I# 36
V3 4
V3 3 VC C6 2 1 .1 V S_ VT T
V3 2 VC C6 3 A K3 5 R 2 26
POWER
V3 1 VC C6 4 V ID [0 ] A K3 3 H _V ID0 36
V3 0 VC C6 5 V ID [1 ] A K3 4 H _V ID1 36 1 K_ 1 % _ 0 4
V2 9 VC C6 6 V ID [2 ] A L3 5 H _V ID2 36
R2 2 3
V2 8 VC C6 7 V ID [3 ] A L3 3 H _V ID3 36
CPU VIDS
V2 7 VC C6 8 V ID [4 ] A M3 3 H _V ID4 36
1 K _ 1 % _0 4
V2 6 VC C6 9 V ID [5 ] A M3 5 H _V ID5 36
U 35 VC C7 0 V ID [6 ] A M3 4 H _V ID6 36
C3 2 6 C 325 C 327 C 347
U 34 VC C7 1 P R O C_ D P R S L P V R P M _ D P R S LP V R 36
* 1 0 u _6 .3 V _X 5R _ 0 6
* 1 0 u_ 6 .3 V _ X 5R _ 0 6
VC C7 2
1 0 u _ 6 .3 V _ X 5 R_ 0 6
U 33
10 u _ 6 .3 V _ X 5 R _ 06
U 32 VC C7 3 R2 2 2
U 31 VC C7 4 G 15 H _ V T TV I D 1
U 30 VC C7 5 VT T_ SEL EC T
*1 K _ 1 % _ 0 4
U 29 VC C7 6
U 28 VC C7 7
U 27 VC C7 8
U 26 VC C7 9
R 35 VC C8 0
R 34 VC C8 1 TO VCORE POWER CONTROL
R 33 VC C8 2
R 32 VC C8 3 A N3 5
VC C8 4 IS E NS E IM O N 36
C3 4 0 C 339 C 338 C 333 R 31
0 .0 1 u _ 5 0 V _ X 7 R_ 0 4
R 30 VC C8 5
VC C8 6
1 0 u _ 6 . 3 V _ X 5 R _0 6
1 0 u _ 6 . 3 V _ X 5 R_ 0 6
R 29
0. 1u _ 1 0 V _ X 7 R _ 04
R 28 VC C8 7 A J3 4
VC C8 8 V C C_ S E NS E VC C _ SEN SE 3 6
SENSE LINES
R 27 A J3 5
R 26 VC C8 9 V S S _ S E NS E V S S _ S E N S E 36
P3 5 VC C9 0
P3 4 VC C9 1 B 15
P3 3 VC C9 2 V T T_ S E N S E A 15 VT T_ SEN SE 34
P3 2 VC C9 3 V S S _S E N S E _ V T T
P3 1 VC C9 4
P3 0 VC C9 5
P2 9 VC C9 6
P2 8 VC C9 7 V CO R E 36
VC C9 8 1 . 1V S _ V T T 2 , 4 , 7 , 1 4 , 1 5 , 1 6, 1 9 , 2 0 , 2 1 , 3 4 , 3 5 , 3 6
P2 7
P2 6 VC C9 9
VC C1 0 0
P Z 98 9 2 7 -3 6 4 1- 01 F
CPU 4/7 (Power) B - 7

Schematic Diagrams
CPU 5/7 (Graphics Power)
PROCESSOR 5/7 ( GRAPHICS POWER )
VG F X_ CO RE U 1 6G
AT 2 1
AT 1 9 VAXG 1 A R2 2
AT 1 8 VAXG 2 VAXG _ SEN SE AT2 2 GP U V C C S E N S E 3 5
C 364 C 34 9 GP U V S S S E N S E 35
AT 1 6 VAXG 3 VSSAXG _ SEN SE
5 6 0 u _ 2. 5V _6 . 6 * 6 . 6 *5 . 9
SENSE
LINES
1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _6 . 3 V _ X 5 R _0 6 AR 2 1 VAXG 4
AR 1 9 VAXG 5
AR 1 8 VAXG 6
AR 1 6 VAXG 7 A M2 2
A P2 1 VAXG 8 GF X_ V I D[0 ] AP2 2 DF GT _ V I D _0 35
VAXG 9 GF X_ V I D[1 ] DF GT _ V I D _1 35
A P1 9 A N2 2
GRAPHICS VIDs
VAXG 10 GF X_ V I D[2 ] DF GT _ V I D _2 35
A P1 8 AP2 3
A P1 6 VAXG 11 GF X_ V I D[3 ] A M2 3 DF GT _ V I D _3 35
C 3 50 C3 6 2
AN 2 1 VAXG 12 GF X_ V I D[4 ] AP2 4 DF GT _ V I D _4 35

+ DF GT _ V I D _5 35
AN 1 9 VAXG 13 GF X_ V I D[5 ] A N2 4
GRAPHICS
2 2 u _ 6. 3V _X 5 R _ 08 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 DF GT _ V I D _6 35
AN 1 8 VAXG 14 GF X_ V I D[6 ]
AN 1 6 VAXG 15
C 371
AM 2 1 VAXG 16 A R2 5 1 .1 V S_ V T T
VAXG 17 G F X _ V R _E N D F GT _ V R _ E N 35
AM 1 9 AT2 5 GF X V R _ D P R S LP V R R3 6 1 *1 K _ 0 4
AM 1 8 VAXG 18 G F X _ DP RS L P V R A M2 4 T P _ GF X _ I M ON R4 5 1 00 _ 1 % _ 0 4
AM 1 6 VAXG 19 GF X_ I M O N GF X_ I M O N 3 5
AL 2 1 VAXG 20
AL 1 9 VAXG 21
AL 1 8 VAXG 22 1. 5V S _ C P U
Sheet 7 of 42 AL 1 6
A K2 1
A K1 9
VAXG
VAXG
VAXG
23
24
25 V D D Q1
AJ 1
AF1
VDDQ 6A
A K1 8 VAXG 26 V D D Q2 AE7
CPU 5/7 VAXG 27 V D D Q3
C5 5 C3 3 6 C 330 C6 1 C5 8
- 1.5V RAILS
A K1 6 AE4
AJ 2 1 VAXG 28 V D D Q4 A C1 1u _ 6 . 3 V _ X 5 R _ 0 4 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6. 3V _ X5 R _ 08 10 u _ 6 . 3 V _ X 5 R _ 0 6 1 0 u_ 6 . 3 V _ X 5 R _ 0 6
Please note that the AJ 1 9 VAXG 29 V D D Q5 AB7
(Graphics Power) VTT Rail Values are AJ 1 8

AJ 1 6
AH 2 1
VAXG
VAXG
VAXG
30
31
32
V D D Q6
V D D Q7
V D D Q8
AB4
Y1
W7
AH 1 9 VAXG 33 V D D Q9 W4
Auburndale VTT=1.05V AH 1 8 VAXG 34 V D D Q1 0 U1 C3 4 1 C3 4 3 C 39 C6 0 + C5 3
Clarksfield VTT=1.1V AH 1 6 VAXG 35 V D D Q1 1 T7
POWER
VAXG 36 V D D Q1 2 T4 1u _ 6 . 3 V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5 R _0 4 1 u _ 6 . 3 V _ X 5R _ 0 4 1u _ 6 . 3 V _ X 5 R _ 0 4 10 0 u _ 6 . 3 V _ B _ A
V D D Q1 3 P1
V D D Q1 4 N7
V D D Q1 5 N4
V D D Q1 6 L1
V D D Q1 7
DDR3
J24 H1
1 .1 VS_ VT T J23 V T T 1 _ 45 V D D Q1 8 1 . 1 V S _V TT
FDI
H 25 V T T 1 _ 46
C3 1 4 C3 0 8
V T T 1 _ 47
22 u _ 6 . 3 V _ X 5 R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8
P1 0 C3 2 0 C6 4
V T T 0 _5 9 N1 0
V T T 0 _6 0 L1 0 10 u _ 6 . 3 V _ X 5 R _ 0 6 1 0 u_ 6 . 3 V _ X 5 R _ 0 6
V T T 0 _6 1 K1 0
V T T 0 _6 2
1 .1 VS_ VT T
J2 2
K2 6 V T T 1 _6 3 J2 0
1.1V
1 .1 VS_ VT T J27 V T T 1 _ 48 V T T 1 _6 4 J1 8 C3 1 5 C3 1 3
J26 V T T 1 _ 49 V T T 1 _6 5 H2 1
PEG & DMI

C3 0 6 C3 0 7
J25 V T T 1 _ 50 V T T 1 _6 6 H2 0 22 u _ 6 . 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8 H 27 V T T 1 _ 51 V T T 1 _6 7 H1 9
1 . 1 V S _V T T G 28 V T T 1 _ 52 V T T 1 _6 8
G 27 V T T 1 _ 53
G 26 V T T 1 _ 54 1 .8 VS
F26 V T T 1 _ 55
V T T 1 _ 56 VCCPLL 0.6A
E2 6 L2 6
C3 0 9 C3 0 2 E2 5 V T T 1 _ 57 V C C P LL 1 L2 7
V T T 1 _ 58 V C C P LL 2 M2 6
1.8V
C3 9 6 C3 5 1 C4 1 C3 7 C 38 C 52 C 56 C5 4
V C C P LL 3
0 . 0 1u _ 5 0 V _ X 7 R _ 0 4 0. 01 u _ 5 0 V _ X 7R _ 0 4 22 u _ 6 . 3 V _ X 5 R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8
1u _ 6 . 3 V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5 R _0 4 2 . 2 u _ 1 6V _ X5 R _ 06 4 . 7 u _ 6 . 3 V _ X5 R _ 0 6 1 0 u _ 6 . 3V _ X5 R _ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6
P Z 98 9 2 7 -3 6 41 -0 1 F
1 .5 VS _ CP U 4 ,3 1
1 .8 VS 2 0 ,3 3
V GF X _ C OR E 35
1 .1 VS _ V T T 2 , 4, 6, 14 , 1 5 , 1 6 , 1 9 , 2 0 , 21 , 3 4 , 3 5 , 3 6
1 .5 V 4 , 9 , 1 0 , 1 1, 2 1 , 2 3 , 2 7 , 2 9 , 3 1, 33 , 3 6
B - 8 CPU 5/7 (Graphics Power)

Schematic Diagrams
CPU 6/7 (GND)
PROCESSOR 6/7 ( GND )

U1 6H U16 I
AT20 AE3 4
AT17 VSS1 VSS81 AE3 3
AR31 VSS2 VSS82 AE3 2 K2 7
AR28 VSS3 VSS83 AE3 1 K9 VSS161
AR23 VSS6 VSS86 AE2 8 J3 2 VSS164
AR15 VSS9 VSS89 AE6 J1 9 VSS167
AR12 VSS1 0 VSS90 AD 10 H3 5 VSS168
AR9 VSS1 1 VSS91 AC 8 H3 2 VSS169
AP20 VSS1 4 VSS94 AB3 5 H2 4 VSS172
AP2 VSS2 0 VSS100 AB2 9 H8 VSS178
AN34 VSS2 1 VSS101 AB2 8 H5 VSS179
AN31 VSS2 2 VSS102 AB2 7 H2 VSS180
VSS2 3 VSS103 VSS181
AN23
AN20
AN17
VSS2 4
VSS2 5
VSS104
VSS105
AB2 6
AB6
AA1 0
G3 4
G3 1
G2 0
VSS182
VSS183
Sheet 8 of 42
VSS2 6 VSS106 VSS184
AM29
AM27
AM25
VSS2 7
VSS2 8
VSS107
VSS108
Y8
Y4
Y2
G9
G6
G3
VSS185
VSS186
CPU 6/7 (GND)
AM20 VSS2 9 VSS109 W35 F3 0 VSS187
AM17 VSS3 0 VSS110 W34 F2 7 VSS188
AM14 VSS3 1 VSS111 W33 F2 5 VSS189
AM11 VSS3 2 VSS112 W32 F2 2 VSS190
AM8 VSS3 3 VSS113 W31 F1 9 VSS191
AM5 VSS3 4 VSS114 W30 F1 6 VSS192
AM2 VSS3 5 VSS115 W29 E3 5 VSS193
AL34 VSS3 6 VSS116 W28 E3 2 VSS194
AL31
AL23
AL20
VSS3 7
VSS3 8
VSS3 9
VSS VSS117
VSS118
VSS119
W27
W26
W6
E2 9
E2 4
E2 1
VSS195
VSS196
VSS197
VSS
AL17 VSS4 0 VSS120 V1 0 E1 8 VSS198
AL12 VSS4 1 VSS121 U8 E1 3 VSS199
AL9 VSS4 2 VSS122 U4 E1 1 VSS200
AL6 VSS4 3 VSS123 U2 E8 VSS201
AL3 VSS4 4 VSS124 T35 E5 VSS202
AK29 VSS4 5 VSS125 T34 E2 VSS203 AT3 5
AK27 VSS4 6 VSS126 T33 D3 3 VSS204 VSS_ NC TF1 AT1
AK25 VSS4 7 VSS127 T32 D3 0 VSS205 VSS_ NC TF2 AR3 4
AK20 VSS4 8 VSS128 T31 D2 6 VSS206 VSS_ NC TF3 B34
AK17 VSS4 9 VSS129 T30 D9 VSS207 VSS_ NC TF4 B2
AJ31 VSS5 0 VSS130 T29 D6 VSS208 VSS_ NC TF5 B1
NCTF
AJ23 VSS5 1 VSS131 T28 D3 VSS209 VSS_ NC TF6 A35
AJ20 VSS5 2 VSS132 T27 C3 4 VSS210 VSS_ NC TF7
AJ17 VSS5 3 VSS133 T26 C3 2 VSS211
AJ14 VSS5 4 VSS134 T6 C2 9 VSS212
AJ11 VSS5 5 VSS135 R10 C2 8 VSS213
AJ8 VSS5 6 VSS136 P8 C2 4 VSS214
AH35 VSS5 9 VSS139 N35 C1 9 VSS217
AH34 VSS6 0 VSS140 N34 C1 6 VSS218
AH33 VSS6 1 VSS141 N33 B3 1 VSS219
AH32 VSS6 2 VSS142 N32 B2 5 VSS220
AH31 VSS6 3 VSS143 N31 B2 1 VSS221
AH30 VSS6 4 VSS144 N30 B1 8 VSS222
AH29 VSS6 5 VSS145 N29 B1 7 VSS223
AH28 VSS6 6 VSS146 N28 B1 3 VSS224
AH27 VSS6 7 VSS147 N27 B1 1 VSS225
AH26 VSS6 8 VSS148 N26 B8 VSS226
AH20 VSS6 9 VSS149 N6 B6 VSS227
AH17 VSS7 0 VSS150 M10 B4 VSS228
AH13 VSS7 1 VSS151 L35 A2 9 VSS229
AH9 VSS7 2 VSS152 L32 A2 7 VSS230
AH6 VSS7 3 VSS153 L29 A2 3 VSS231
AH3 VSS7 4 VSS154 L8 A9 VSS232
AG10 VSS7 5 VSS155 L5 VSS233
AF8 VSS7 6 VSS156 L2
AF4 VSS7 7 VSS157 K3 4
AF2 VSS7 8 VSS158 K3 3
AE35 VSS7 9 VSS159 K3 0
VSS8 0 VSS160
PZ98 927 -3 641 -0 1F PZ9 892 7- 364 1- 01F
CPU 6/7 (GND) B - 9

Schematic Diagrams
CPU 7/7 (RESERVED)
PROCESSOR 7/7 ( RESERVED )
1 .5 V
U1 6 E
AP2302GN
A J1 3 R 36
RS V D3 2 A J1 2
RS V D3 3 Q 8 * 1 K _ 1% _ 0 4
PCI-Express Configuration Select AP2 5 *A O3 4 0 2L
A L2 5 R SVD 1 A H2 5 V R E F _ CH _ A _ DIM M S D MV R E F _ D Q_ D I M 0
A L2 4 R SVD 2 RS V D3 4 A K 26
1 : Single PEG
CFG0 0 : Bifurcation enable
A L2 2
A J3 3
R
R
SVD
SVD
3
4
RS V D3 5
A L2 6 R 2 12 R 37
G
A G9 R SVD 5 RS V D3 6 A R2 * 1 00 K _ 1 % _ 0 4
M2 7 R SVD 6 R S V D _ N C TF _3 7
* 1 K _ 1% _ 0 4
L2 8 R SVD 7 A J2 6
J1 7 R SVD 8 RS V D3 8 A J2 7 D R A MR S T _ C T R L 4, 1 9
C FG 0 R 2 27 * 3 . 01 K _ 0 4 R 35 *0 _ 04 V R E F _ C H _ A _ D I MM
1 0 MV R E F _ D Q_ D I M0 R SVD 9 RS V D3 9
R 39 *0 _ 04 V R E F _ C H _ B _ D I MM H1 7
1 1 MV R E F _ D Q_ D I M1 G2 5 R SVD 10 ? ? IBEX CONTROL
G1 7 R SVD 11
E3 1 R SVD 12 A P1
CFG3 - PCI-Express Static Lane Reversal E3 0 R SVD 13 R S V D _ N C TF _4 0 A T2
R SVD 14 R S V D _ N C TF _4 1 1 .5 V
1 : Normal Operation A T3
CFG3 0 : Lane Numbers Reversed R S V D _ N C TF _4 2
R S V D _ N C TF _4 3
A R1
Sheet 9 of 42 15 -> 0, 14 -> 1, ... AP2302GN R 38
A L2 8 Q 9 * 1 K _ 1% _ 0 4
CPU 7/7 C FG 3 R 2 21 * 3 . 01 K _ 0 4 C F G0 A M3 0
A M2 8
AP3 1
C
C
F G [ 0]
F G [ 1]
RS V D4 5
RS V D4 6
RS V D4 7
A
A
A
L2 9
P 30
P 32
V R E F _ CH _ B _ DIM M S
*A O3 4 0 2L
D MV R E F _ D Q_ D I M 1
A L3 2 C F G [ 2] RS V D4 8 A L2 7
(RESERVED) CFG4 - Display Port Presence

C F G3
C F G4 A L3 0 C
C
F G [ 3]
F G [ 4]
RS V D4 9
RS V D5 0
A T3 1 R 2 14 R 40
G
A M3 1 A T3 2 * 1 00 K _ 1 % _ 0 4
A N2 9 C F G [ 5] RS V D5 1 A P 33 * 1 K _ 1% _ 0 4
C F G7 A M3 2 C F G [ 6] RS V D5 2 A R3 3
1 : Di sa bl le d ; No p hy si ca l D is pl ay P or t AK3 2 C F G [ 7] RS V D5 3 A T3 3 D R A MR S T _ C T R L 4, 1 9
a tt ac he d to Em be dd ed D is pl a y Po rt AK3 1 C F G [ 8] R S V D _ N C TF _5 4 A T3 4
AK2 8 C F G [ 9] R S V D _ N C TF _5 5 A P 35 ? ? IBEX CONTROL
CFG4
RESERVED
A J2 8 C F G [ 10 ] R S V D _ N C TF _5 6 A R3 5
0 : En ab le d; An e xt er na l Di s pl ay P or t A N3 0 C F G [ 11 ] R S V D _ N C TF _5 7 A R3 2
de vi ce i s co n ne ct ed t o th e E mb ed de d A N3 2 C F G [ 12 ] RS V D5 8
A J3 2 C F G [ 13 ]
is pl ay P or t C F G [ 14 ]
A J2 9 E 15
A J3 0 C F G [ 15 ] R S V D _ TP _5 9 F 15
AK3 0 C F G [ 16 ] R S V D _ TP _6 0 A 2
C FG 4 R 2 20 * 3 . 01 K _ 0 4 R 211 *0 _ 0 4 R SVD8 6 H1 6 C F G [ 17 ] KEY D 15
R S V D _ TP _8 6 RS V D6 2 C 15
RS V D6 3 A J1 5 R S V D 6 4 _R
RSVD86 R 2 17 *1 5 m i l_ s h o rt _ 06
Connect to GND RS V D6 4 A H1 5 R S V D 6 5 _R R 2 18 *1 5 m i l_ s h o rt _ 06
RS V D6 5
B1 9
A1 9 R SVD 1 5
R SVD 1 6
C FG 7 R 2 24 * 3 . 01 K _ 0 4
R 20 5 *1 5 m il _ s h ort _0 6 H _R S V D 1 7_ R A2 0
R 20 4 *1 5 m il _ s h ort _0 6 H _R S V D 1 8_ R B2 0 R SVD 1 7
CFG7 R SVD 1 8 A A5
Clar ksfi eld (onl y f or e arly sam ples U9 R SVD _ TP _6 6 A A4
T9 R SVD 1 9 R SVD _ TP _6 7 R 8
pre- ES1) - C onne ct to G ND w ith 3.01 K Oh m/5% R SVD 2 0 R SVD _ TP _6 8 A D3
A C9 R SVD _ TP _6 9 A D2
resi stor AB9 R SVD 2 1 R SVD _ TP _7 0 A A2
R SVD 2 2 R SVD _ TP _7 1 A A1
R SVD _ TP _7 2 R 9
R SVD _ TP _7 3 A G7
C1 R SVD _ TP _7 4 A E3
A3 R S V D _ N C TF _2 3 R SVD _ TP _7 5
R S V D _ N C TF _2 4
V 4
R SVD _ TP _7 6 V 5
R SVD _ TP _7 7 N 2
J2 9 R SVD _ TP _7 8 A D5
J2 8 R SVD 2 6 R SVD _ TP _7 9 A D7
R SVD 2 7 R SVD _ TP _8 0 W 3
A3 4 R SVD _ TP _8 1 W 2
A3 3 R S V D _ N C TF _2 8 R SVD _ TP _8 2 N 3
R S V D _ N C TF _2 9 R SVD _ TP _8 3 A E5
C3 5 R SVD _ TP _8 4 A D9
B3 5 R S V D _ N C TF _3 0 R SVD _ TP _8 5
R S V D _ N C TF _3 1
A P 34 TP _R S V D 8 6
V SS VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
P Z 9 89 2 7 -3 6 41 -0 1 F
1. 5 V 4 , 1 0, 11 , 2 1 , 2 3 , 2 7, 2 9 , 3 1 , 3 3, 36
B - 10 CPU 7/7 (RESERVED)

Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A CHANGE TO STANDARD
J D I M M2 A
5 M_ A _ A [ 1 5 : 0 ] M _A _ A 0 98 5 M _A _D Q0 M_ A _ D Q [ 6 3 : 0] 5
J D I M M2 B
M _A _ A 1 97 A0 DQ 0 7 M _A _D Q1
M _A _ A 2 96 A1 DQ 1 15 M _A _D Q2
M _A _ A 3 95 A2 DQ 2 17 M _A _D Q3 1 . 5V
M _A _ A 4 92 A3 DQ 3 4 M _A _D Q4
M _A _ A 5 91 A4 DQ 4 6 M _A _D Q5 75 44
M _A _ A 6 90 A5 DQ 5 16 M _A _D Q6 76 V DD 1 VS S1 6 48
La yout Note : M _A _ A 9 85 A8 DQ 8 23 M _A _D Q9 87 V DD 4 VS S1 9 55
M _A _ A 1 0 107 A9 DQ 9 33 M _A _D Q1 0 88 V DD 5 VS S2 0 60
si gna l /spa ce / signa l: M _A _ A 1 1 84 A 1 0 /A P D Q1 0 35 M _A _D Q1 1 93 V DD 6 VS S2 1 61
M _A _ A 1 2 83 A1 1 D Q1 1 22 M _A _D Q1 2 94 V DD 7 VS S2 2 65
8/4/8 M _A _ A 1 3 119 A 1 2 /B C# D Q1 2 24 M _A _D Q1 3 3 .3 VS 99 V DD 8 VS S2 3 66
M _A _ A 1 4 80 A1 3 D Q1 3 34 M _A _D Q1 4 1 00 V DD 9 VS S2 4 71
M _A _ A 1 5 78 A1 4 D Q1 4 36 M _A _D Q1 5 20mils 1 05 V DD 10 VS S2 5 72
A1 5 D Q1 5 39 M _A _D Q1 6 1 06 V DD 11 VS S2 6 12 7
109 D Q1 6 41 M _A _D Q1 7 1 11 V DD 12 VS S2 7 12 8
5 M_ A _ B S 0 C 96 C9 7
108 BA0 D Q1 7 51 M _A _D Q1 8 1 12 V DD 13 VS S2 8 13 3
5 M_ A _ B S 1 79 BA1 D Q1 8 53 M _A _D Q1 9 1 17 V DD 14 VS S2 9 13 4
1 u _ 6 . 3V _X 5 R _ 0 4 0. 1 u _ 1 0V _X 7 R _ 0 4
5 M_ A _ B S 2 114 BA2 D Q1 9 40 M _A _D Q2 0 1 18 V DD 15 VS S3 0 13 8
5 M_ C S # 0 121 S0 # D Q2 0 42 1 23 V DD 16 VS S3 1 13 9
M _A _D Q2 1
5 M_ C S # 1 101 S1 # D Q2 1 50 M _A _D Q2 2 1 24 V DD 17 VS S3 2 14 4
5 M _ CL K _ DD R0 103 CK 0 D Q2 2 52 V DD 18 VS S3 3 14 5
M _A _D Q2 3
5
5
5
M
M
M
_ CL K _ DD R# 0
_ CL K _ DD R1
_ CL K _ DD R# 1
102
104
73
C K 0#
CK 1
C K 1#
D Q2 3
D Q2 4
D Q2 5
57
59
67
M
M
M
_A
_A
_A
_D
_D
_D
Q2 4
Q2 5
Q2 6 3 .3 V S
1 99
77
V DD SP D
VS
VS
VS
S3 4
S3 5
S3 6
15 0
15 1
15 5
Sheet 10 of 42
5 M_ C K E 0 CK E0 D Q2 6 NC 1 VS S3 7
DDR3 SO-DIMM_0
74 69 M _A _D Q2 7 1 22 15 6
5 M_ C K E 1 115 CK E1 D Q2 7 56 1 25 NC 2 VS S3 8 16 1
M _A _D Q2 8 R 72 1 0 K _ 1% _ 0 4
5 M _A _C A S # 110 CA S# D Q2 8 58 M _A _D Q2 9 N C TE S T VS S3 9 16 2
5 M _A _R A S # RA S# D Q2 9 VS S4 0
113 68 M _A _D Q3 0 1 98 16 7
5 M _A _W E # S A0 _ DIM 0 197 W E# D Q3 0 70 M _A _D Q3 1 4, 1 1 T S # _ D I M M0 _ 1 30 E V E N T# VS S4 1 16 8
S A1 _ DIM 0 201 SA0 D Q3 1 129 M _A _D Q3 2 4, 1 1 D D R 3_ D R A M R S T# R E S E T# VS S4 2 17 2
202 SA1 D Q3 2 131 M _A _D Q3 3
20mils C 18 2 . 2 u _ 6. 3 V _ X 5 R _ 0 6 VS S4 3 17 3
2 ,1 1 C L K _ SCL K SC L D Q3 3 VS S4 4
200 141 M _A _D Q3 4 C 19 0 . 1 u _ 10 V _ X 7 R _ 0 4 1 17 8
2, 1 1 C LK _S D A T A SD A D Q3 4 143 1 26 V R E F _D Q VS S4 5 17 9
M _A _D Q3 5
3 .3 VS 116 D Q3 5 130 M _A _D Q3 6 V R E F _C A VS S4 6 18 4
5 M_ O D T 0 120 OD T 0 D Q3 6 132 M _A _D Q3 7 R2 0 *0 _ 0 4 R1 9 * 15 m i l _s h o rt _ 06 VS S4 7 18 5
5 M_ O D T 1 OD T 1 D Q3 7 140 9 M V R E F _ D Q _D I M 0 2 VS S4 8 18 9
M _A _D Q3 8
5 M_ A _ D M[ 7 : 0 ] M _A _ D M0 11 D Q3 8 142 M _A _D Q3 9 M V R E F _D I M0 3 VSS1 VS S4 9 19 0
R N3
1 0 K _ 8 P 4R _ 0 4 M _A _ D M1 28 DM 0 D Q3 9 147 M _A _D Q4 0 C8 2 2 . 2u _ 6 . 3 V _ X5 R _0 6 8 VSS2 VS S5 0 19 5
1 8 S A1 _ DIM 1 M _A _ D M2 46 DM 1 D Q4 0 149 M _A _D Q4 1 9 VSS3 VS S5 1 19 6
S A 1 _D I M 1 1 1 C8 1 0 . 1u _ 1 0 V _ X7 R _0 4
2 7 S A0 _ DIM 1 M _A _ D M3 63 DM 2 D Q4 1 157 M _A _D Q4 2 13 VSS4 VS S5 2
3 6 S A 0 _D I M 1 1 1 136 DM 3 D Q4 2 159 14 VSS5
S A1 _ DIM 0 M _A _ D M4 M _A _D Q4 3
4 5 S A0 _ DIM 0 M _A _ D M5 153 DM 4 D Q4 3 146 M _A _D Q4 4 19 VSS6
M _A _ D M6 170 DM 5 D Q4 4 148 M _A _D Q4 5 20 VSS7 V TT _ M E M
M _A _ D M7 187 DM 6 D Q4 5 158 M _A _D Q4 6 25 VSS8
DM 7 D Q4 6 160 M _A _D Q4 7 26 VSS9 20 3
5 M_ A _ D QS [ 7 : 0 ] M _A _ D QS 0 12 D Q4 7 163 M _A _D Q4 8 31 VSS1 0 VT T 1 20 4
M _A _ D QS 1 29 DQ S0 D Q4 8 165 M _A _D Q4 9 32 VSS1 1 VT T 2
M _A _ D QS 2 47 DQ S1 D Q4 9 175 M _A _D Q5 0 37 VSS1 2 GN D 1
M _A _ D QS 3 64 DQ S2 D Q5 0 177 M _A _D Q5 1 38 VSS1 3 G1 GN D 2
M _A _ D QS 4 137 DQ S3 D Q5 1 164 M _A _D Q5 2 43 VSS1 4 G2
M _A _ D QS 5 154 DQ S4 D Q5 2 166 M _A _D Q5 3 VSS1 5
M _A _ D QS 6 171 DQ S5 D Q5 3 174 M _A _D Q5 4 A S 0 A 6 2 1-U 2 S N -7 F
188 DQ S6 D Q5 4 176
M _A _ D QS 7 M _A _D Q5 5
DQ S7 D Q5 5 181 M _A _D Q5 6
5 M_ A _ D QS # [ 7 : 0 ] 10 D Q5 6 183
M _A _ D QS # 0 M _A _D Q5 7
M _A _ D QS # 1 27 DQ S0 # D Q5 7 191 M _A _D Q5 8
M _A _ D QS # 2 45 DQ S1 # D Q5 8 193 M _A _D Q5 9
M _A _ D QS # 3 62 DQ S2 # D Q5 9 180 M _A _D Q6 0
M _A _ D QS # 4 135 DQ S3 # D Q6 0 182 M _A _D Q6 1
M _A _ D QS # 5 152 DQ S4 # D Q6 1 192 M _A _D Q6 2
M _A _ D QS # 6 169 DQ S5 # D Q6 2 194 M _A _D Q6 3
M _A _ D QS # 7 186 DQ S6 # D Q6 3
DQ S7 # CLO SE TO SO -DI MM _0
1 .5 V A S 0 A 6 2 1 -U 2 S N -7 F
R6 3 1K _1 % _ 0 4 M V R E F _ DIM 0
1. 5 V
C3 5 3 + C3 2 1 C 57 C6 2 C7 8 C 47 C 68 C 70 + C 3 16
+ 5 60 u _ 2 . 5V _6 . 6 * 6. 6 * 5. 9 R 65 C8 6
*2 2 0 u_ 2 . 5 V _ B _ A 1 0 u _ 6. 3 V _ X 5 R _ 0 6 10 u _ 6 . 3V _X 5 R _ 0 6 *1 0 u _6 . 3 V _ X 5 R _ 0 6 1 u _6 . 3 V _ X 5 R _ 0 4 1 u _ 6. 3V _ X 5 R _ 0 4 * 1 u_ 6 . 3 V _ X 5R _ 0 4 * 5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
1 K _ 1 % _0 4 0 . 1 u_ 1 0 V _ X7 R _ 04
1. 5 V
C7 3 C4 8 C 44 C 67 C4 6 C7 5 C 43
4 , 9 , 1 1, 21 , 2 3 , 2 7, 2 9 , 3 1 , 3 3, 3 6 1 . 5 V
1 1, 3 3 V T T _ ME M
0 . 1u _ 1 0 V _ X7 R _0 4 0 . 1 u_ 1 0 V _ X 7R _ 04 * 0. 1 u _ 1 0V _X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0. 1 u _ 1 0V _X 7 R _ 0 4 0 . 1u _ 1 0 V _ X7 R _0 4 *0 . 1 u _ 1 0V _ X 7 R _ 0 4
2 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 1 6 , 17 , 1 8 , 1 9 , 20 , 2 1 , 2 3 , 24 , 2 5 , 2 6, 27 , 2 8 , 2 9, 3 0 , 3 1 , 3 5, 3 6 3 . 3 V S
V T T _M E M
C1 0 1 C1 0 5 C 10 4 C 106
1 0u _ 6 . 3 V _ X5 R _0 6 *1 u _ 6 . 3V _X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 1 u _ 6 . 3V _X 5 R _ 0 4
DDR3 SO-DIMM_0 B - 11
Schematic Diagrams
DDR3 SO-DIMM_1
SO-DIMM B CHANGE TO STANDARD
J DI M M1 A
5 M_ B _ A [ 1 5 : 0] M _B _A 0 98 5 M_ B _ D Q 0 M_ B _ D Q[ 6 3 : 0 ] 5 J D I M M1 B
97 A0 DQ 0 7
M _B _A 1 M_ B _ D Q 1
M _B _A 2 96 A1 DQ 1 15 M_ B _ D Q 2 1 . 5V
M _B _A 3 95 A2 DQ 2 17 M_ B _ D Q 3
M _B _A 4 92 A3 DQ 3 4 M_ B _ D Q 4
M _B _A 5 91 A4 DQ 4 6 M_ B _ D Q 5 75 44
M _B _A 6 90 A5 DQ 5 16 M_ B _ D Q 6 76 VD D1 VSS1 6 48
La yout Not e: M _B _A 9 85 A8 DQ 8 23 M_ B _ D Q 9 87 VD D4 VSS1 9 55
si gnal /spa c e/ signa l: M _B _A 11 84 A1 0 /A P DQ 1 0 35 M_ B _ D Q 11 93 VD D6 VSS2 1 61
M _B _A 12 83 A1 1 DQ 1 1 22 M_ B _ D Q 12 94 VD D7 VSS2 2 65
8/4/8 M _B _A 13 119 A1 2 /B C# DQ 1 2 24 M_ B _ D Q 13 99 VD D8 VSS2 3 66
M _B _A 14 80 A1 3 DQ 1 3 34 M_ B _ D Q 14 100 VD D9 VSS2 4 71
M _B _A 15 78 A1 4 DQ 1 4 36 M_ B _ D Q 15 105 VD D1 0 VSS2 5 72
A1 5 DQ 1 5 39 M_ B _ D Q 16 106 VD D1 1 VSS2 6 1 27
109 DQ 1 6 41 M_ B _ D Q 17 111 VD D1 2 VSS2 7 1 28
5 M _ B_ BS0 108 BA0 DQ 1 7 51 M_ B _ D Q 18 112 VD D1 3 VSS2 8 1 33
5 M _ B_ BS1 79 BA1 DQ 1 8 53 117 VD D1 4 VSS2 9 1 34
M_ B _ D Q 19
5 M _ B_ BS2 114 BA2 DQ 1 9 40 M_ B _ D Q 20 118 VD D1 5 VSS3 0 1 38
5 M _ CS # 2 S0 # DQ 2 0 VD D1 6 VSS3 1
121 42 M_ B _ D Q 21 123 1 39
5 M _ CS # 3 101 S1 # DQ 2 1 50 M_ B _ D Q 22 124 VD D1 7 VSS3 2 1 44

3. 3 V S
5 M_ C LK _ D D R 2 103 CK 0 DQ 2 2 52 M_ B _ D Q 23 VD D1 8 VSS3 3 1 45
5 M_ C LK _ D D R # 2 102 CK 0# DQ 2 3 57 M_ B _ D Q 24
20 m ils 199 VSS3 4 1 50
5 M_ C LK _ D D R 3 104 CK 1 DQ 2 4 59 M_ B _ D Q 25 V D DS P D VSS3 5 1 51
5 M_ C LK _ D D R # 3 73 CK 1# DQ 2 5 67 77 VSS3 6 1 55
M_ B _ D Q 26 C9 8 C 99
5 M _ CK E 2 74 CK E 0 DQ 2 6 69 M_ B _ D Q 27 122 NC 1 VSS3 7 1 56
5 M _ CK E 3 CK E 1 DQ 2 7 NC 2 VSS3 8
115 56 M_ B _ D Q 28 1 u_ 6 . 3 V _ X5 R _0 4 0 . 1 u _ 10 V _ X 7 R_ 0 4 125 1 61
5 M_ B _ CA S # 110 CA S # DQ 2 8 58 M_ B _ D Q 29 NC T E S T VSS3 9 1 62
Sheet 11 of 42 5
5
M_ B _ RA S #
M_ B _ W E #
10 S A 0 _D I M 1
S A 0 _ D I M1
S A 1 _ D I M1
113
197
201
RA S #
W E#
SA0
DQ 2 9
DQ 3 0
DQ 3 1
68
70
1 29
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
30
31
32
4 , 1 0 TS # _ D I MM 0_ 1
4 , 1 0 D D R 3 _ DR A MR S T #
198
30 EVEN T#
RE S E T #
VSS4 0
VSS4 1
VSS4 2
1 67
1 68
1 72
10 S A 1 _D I M 1
DDR3 SO-DIMM_1 2, 1 0 C L K _ S C LK
2 , 1 0 CL K _ S D A TA
202
200
SA1
SC L
SD A
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
1 31
1 41
1 43
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
33
34
35
C2 2
C2 3
2 . 2u _ 6 . 3 V _ X5 R _0 6
0 . 1u _ 1 0 V _X 7 R _0 4 1
126 V R E F _ DQ
V R E F _ CA
VSS4 3
VSS4 4
VSS4 5
VSS4 6
1 73
1 78
1 79
116 1 30 M_ B _ D Q 36 1 84
5 M _ OD T2 120 OD T 0 DQ 3 6 1 32 M_ B _ D Q 37 R 23 * 0_ 0 4 R2 2 *1 5 m il _ s h ort _ 0 6 VSS4 7 1 85
5 M _ OD T3 OD T 1 DQ 3 7 1 40 9 M V R E F _D Q_ D I M1 2 VSS4 8 1 89
M_ B _ D Q 38
5 M _B _D M[ 7 : 0 ] M _B _D M0 11 DQ 3 8 1 42 M_ B _ D Q 39 MV RE F _ D I M1 3 VSS1 VSS4 9 1 90
M _B _D M1 28 DM 0 DQ 3 9 1 47 M_ B _ D Q 40 C8 4 2 . 2u _ 6 . 3 V _ X5 R _0 6 8 VSS2 VSS5 0 1 95
M _B _D M2 46 DM 1 DQ 4 0 1 49 M_ B _ D Q 41 9 VSS3 VSS5 1 1 96
C8 3 0 . 1u _ 1 0 V _X 7 R _0 4
M _B _D M3 63 DM 2 DQ 4 1 1 57 M_ B _ D Q 42 13 VSS4 VSS5 2
M _B _D M4 136 DM 3 DQ 4 2 1 59 M_ B _ D Q 43 14 VSS5
2010/01/08
M _B _D M6 170 DM 5 DQ 4 4 1 48 M_ B _ D Q 45 20 VSS7 V T T_ M E M
DM 7 DQ 4 6 1 60 M_ B _ D Q 47 26 VSS9 2 03
5 M _B _D QS [ 7: 0 ] M _B _D QS 0 12 DQ 4 7 1 63 M_ B _ D Q 48 31 VSS1 0 VTT1 2 04
M _B _D QS 1 29 DQ S0 DQ 4 8 1 65 M_ B _ D Q 49 32 VSS1 1 VTT2
M _B _D QS 2 47 DQ S1 DQ 4 9 1 75 M_ B _ D Q 50 37 VSS1 2 GN D 1
M _B _D QS 3 64 DQ S2 DQ 5 0 1 77 M_ B _ D Q 51 38 VSS1 3 G1 GN D 2
M _B _D QS 4 137 DQ S3 DQ 5 1 1 64 M_ B _ D Q 52 43 VSS1 4 G2
M _B _D QS 5 154 DQ S4 DQ 5 2 1 66 M_ B _ D Q 53 VSS1 5
M _B _D QS 6 171 DQ S5 DQ 5 3 1 74 M_ B _ D Q 54 A S 0 A 6 2 1 -U A S N -7 F
M _B _D QS 7 188 DQ S6 DQ 5 4 1 76 M_ B _ D Q 55
DQ S7 DQ 5 5 1 81 M_ B _ D Q 56
5 M _ B _ DQ S # [ 7: 0 ] M _B _D QS #0 10 DQ 5 6 1 83 M_ B _ D Q 57
M _B _D QS #1 27 DQ S0 # DQ 5 7 1 91 M_ B _ D Q 58
45 DQ S1 # DQ 5 8 1 93
M _B _D QS #2 M_ B _ D Q 59
M _B _D QS #3 62 DQ S2 # DQ 5 9 1 80 M_ B _ D Q 60
M _B _D QS #4 135 DQ S3 # DQ 6 0 1 82 M_ B _ D Q 61
M _B _D QS #5 152 DQ S4 # DQ 6 1 1 92 M_ B _ D Q 62
M _B _D QS #6 169 DQ S5 # DQ 6 2 1 94 M_ B _ D Q 63
M _B _D QS #7 186 DQ S6 # DQ 6 3
DQ S7 #
A S 0 A 6 2 1 -UA S N -7 F
CLO SE TO SO -D IMM _1
La yout Note :
R6 4 1 K _ 1% _ 0 4 MV R E F _ D I M 1
1 .5 V SO -D IM M_1 i s pl ac e d fa rthe r f rom t he GMCH tha n S O- DIMM _ 0 1. 5 V
R 66 C8 7
C8 5 C 63 C 42 C 51 C 71 C 76 C 79 1 K _ 1 % _0 4 0 . 1 u_ 1 0 V _ X7 R _0 4
*1 0 u _ 6. 3 V _ X 5 R _ 0 6 1 0 u_ 6 . 3 V _ X5 R _ 06 1 0 u_ 6 . 3 V _ X 5R _ 06 1 u _6 . 3 V _ X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 * 1u _ 6 . 3 V _ X5 R _0 4
1 . 5V
C1 0 9 C 25 C 66 C 22 8 C 49 C 69 C 72 C 77 C 50 C 45
4 , 9 , 1 0, 2 1 , 2 3 , 2 7, 2 9 , 3 1 , 33 , 3 6 1 . 5 V
10 , 3 3 V T T _M E M
0 . 1 u_ 1 0 V _ X7 R _0 4 0 . 1 u_ 1 0 V _ X7 R _ 04 0 . 1 u_ 1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7R _ 04 0 . 1 u _1 0 V _ X 7R _ 0 4 0 . 1 u _1 0 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R _ 0 4 0 . 1 u _ 10 V _ X 7 R_ 0 4
2 , 1 0 , 12 , 1 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 1 9 , 20 , 2 1 , 2 3 , 24 , 2 5 , 2 6, 2 7 , 2 8 , 2 9, 3 0 , 3 1 , 35 , 3 6 3 . 3 V S
V T T _ ME M
C1 0 2 C 10 7 C 10 8 C 10 3
1 0 u_ 6 . 3 V _ X5 R _0 6 1 u _6 . 3 V _ X 5R _ 0 4 *1 u _ 6 . 3V _X 5 R _ 0 4 1 u _6 . 3 V _ X 5 R _ 0 4
B - 12 DDR3 SO-DIMM_1
Schematic Diagrams
LVDS, Inverter
3 .3 V S
EDID Mode
PANEL CONNECTOR 2
1
3 R N6
4 2 . 2 K _ 4P 2 R _0 4
V IN V I N _L C D
J _ LC D 1
L 25 *1 5 mi l _ sh o rt _ 06
80m ils 1 2 P _ DD C_ DA T A
3 1 2 4 P _ DD C_ CL K P _ D D C _ D A TA 17
5 3 4 6 P _ D D C _ C LK 17
7 5 6 8 B R I GH T N E S S
9 7 8 10 B RIG HT NE S S 28
C3 0 0 C2 9 7 C2 9 4
11 9 10 12 I N V _ B L ON
13 11 12 14
0 . 1 u_ 5 0V _Y 5V _0 6 0 . 1 u_ 5 0V _Y 5V _0 6 0. 1u _ 50 V _ Y 5 V _ 0 6
LV D S -L C L K N 15 13 14 16 LV D S -L 2N
17 LV D S -L C L K N LV D S -L C L K P 17 15 16 18 LV D S -L 2P LV D S -L 2N 17
17 L V D S -L C L K P 19 17 18 20 LV D S -L 2P 17
LV D S -L 1 N 21 19 20 22
17 L V D S -L 1 N 23 21 22 24
LV D S -L 1 P 3. 3 V S
17 L V D S -L 1P 25 23 24 26
LV D S -L 0 N 27 25 26 28
CLOSE TO LVDS CONN. 17
17
L V D S -L 0 N
L V D S -L 0P
LV D S -L 0 P 29 27
29
28
30
30
PIN 87 2 1 6-3 0 0 6 C 2 91
0 . 1 u _1 6 V _ Y 5 V _ 04
P LV D D
C4 C 6
4. 7 u _ 6. 3 V _ X 5R _ 06 0 . 1 u _1 6 V _ Y 5 V _ 04
Sheet 12 of 42
LVDS, Inverter
3 . 3V S
PANEL POWER
2A R 16 *1 5 m li _ s ho rt _ 0 6
C1 5
C1 7
0 . 1 u_ 1 6 V _Y 5 V _0 4
*0 . 01 u _ 50 V _ X 7R _ 04 3 . 3V
P L V DD D1 5
U 1 C
4 1 2A B RIG HT NE S S AC C2 9 0
5 VIN VO UT A *0 . 1 u_ 1 6 V _Y 5 V _0 4
VIN
*B A V 9 9 R E C TI F I E R
3 2
1 7 NB _ E NAV DD EN GN D
R1 3 A P L 3 51 2 A
10 0 K _ 1% _ 0 4
G5243A 6-02-05243-9C0
APL3512A 6-02-03512-9C0
INVERTER CONNECTOR
R6 8 *1 0 mi l _ sh o rt _ 04 BK L _ E N_ R
28 B K L _E N
R 67 C 90
*1 0 0 K _ 1% _ 04 * 0 . 47 u _ 10 V _ Y 5 V _ 0 4
3. 3 V 3. 3 V 3. 3V
U3 A
14
7 4L V C 08 P W U 3B
14
1 7 4 LV C 0 8P W C8 9
3 Z 1 2 01 4
B L ON 2 6 *0 . 1 u _1 6 V _ Y 5 V _ 04
1 7 B L ON 5
7
R 69
7
1 0 0K _ 1 % _0 4 U 3C
14
7 4 LV C 0 8P W
19 S B _B LO N Z 1 2 02 9
3. 3 V 8 I N V _B L O N
R7 0 1 00 K _ 1 %_ 0 4 Z 1 2 03 1 0
U 3D
14
7 4 LV C 0 8P W R 71 C9 3
7
12
2 8, 3 0 L ID_ S W # 11 1 M _0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4
13
1 6, 2 8 A L L _S Y S _ P W R G D
7
3 0, 31 , 3 2 , 33 , 3 4 , 35 , 3 6 , 37 V IN
3 , 4 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 2 1, 23 , 2 4, 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 35 3 .3 V
2 , 1 0, 1 1 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 25 , 2 6, 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 36 3 .3 VS
3 1 , 32 S Y S 15 V
LVDS, Inverter B - 13
Schematic Diagrams
HDMI, CRT
L 27
For ESD 1 _0 4 5 VS
5V S
HDMI PORT RD2 RD3

B A V 99 R E C T FI I E R B A V 99 R E C T I FI E R
R 210
FOR INTEL GRAPHIC
C
A
A
RD1 1_0 4
J_ H D MI 1
U2 B A V 99 R E C T I FI E R
AC
AC
AC
C 319 C 31 7
17 H D MI B_ D 2B P 39 22 H D MI B _D A TA 2 P
17 H D MI B_ D 2B N 3 8 I N _ D 1+ OU T _D 1 + 23 H D MI B _D A TA 2 N 10u _6 . 3V _X 5R _ 06 22 u_6 . 3V _X 5R _ 08
I N _ D 1- OU T _D 1- 5V S 19 H D MI B _E XT 1_ H P D
42 19 H D MI B _D A TA 1 P RN2 18 H OT P LU G D E T EC T
17 H D MI B_ D 1B P 4 1 I N _ D 2+ OU T _D 2 + 20 +5 V 17
17 H D MI B_ D 1B N H D MI B _D A TA 1 N 2 . 2K _4 P2 R _0 4
I N _ D 2- OU T _D 2- H D MIB _ EX T1 _S D A 16 D D C / C E C GN D
45 16 H D MI B _D A TA 0 P 1 4 S DA 15 H D MI B _E XT 1_ S C L
17 H D MI B_ D 0B P 4 4 I N _ D 3+ OU T _D 3 + 17 H D MI B _D A TA 0 N 2 3 14 SC L
17 H D MI B_ D 0B N I N _ D 3- OU T _D 3- F OR E MI R E S ER V E D FO R EM I
L5 13 H D MI _C E C
48 13 H D MI B _C L OC K P H D MI B _C LO C KN 1 2 12 CE C
17 H D MI B_ C LK B P 4 7 I N _ D 4+ OU T _D 4 + 14 H D MI B _C L OC K N TMD S C L OC K- 11
17 H D MI B_ C LK B N I N _ D 4- OU T _D 4- H D MI B _C LO C KP 4 3 10 C LK S H I EL D
H D MI _C T R LC L K 9 28 H D MI B _E XT 1_ S C L * H D MI 201 2F 2 SF -90 0T 04 -s ho rt TMD S C L OC K+ 9 4 3 H D MI B _D AT A0 N
1 7 H D MI _C T R LC L K
8 S CL S C L_ S I N K T MD S D A T A0 -
* LV A R 04 02- 2 40 E0 R 05 P -L F
H D MI _C T R LD A TA 29 H D MI B _E XT 1_ S D A 8
*L VA R 0 402 - 24 0E 0R 0 5P - LF
17 H D MI _C T R LD A TA S DA S D A_ S I N K S H I EL D 0 7 1 2 H D MI B_ D A TA 0P
7 30 6 TMD S D A TA 0+
R4 2
M_P OR TB _ H PD # _R H D MI B _E XT 1_ H P D
R 41
HP D H PD _ S I N K TMD S D A TA 1 - 5 L6
R4 3
*L VA R 0 402 - 24 0E 0R 0 5P - LF
*LV A R 04 02- 2 40 E0 R 05 P -L F
R 44
Z 4 304 25 2 4 S H I E LD 1
3 . 3V S R5 6 *4. 7K _ 04 OE # V C C [ 1] 3 . 3V S TMD S D A TA 1 + *H DMI 2 01 2F 2S F -90 0T 04-s ho rt

R4 7 *0_ 04 11 R4 8 3
DCC_ E N# 32 V C C [ 2] 15 2 T MD S D A T A2 -
C1 C4 0 C3 2
1 0 D C C _E N # V C C [ 3] 21 2 0K _1 %_ 04 S H I EL D 2 1
R T _E N # V C C [ 4] 26 0. 1 u_ 16 V_ Y 5V _0 4 *0 . 1u _16 V _Y 5 V_ 04 0 . 1u _16 V _Y 5 V_ 04 TMD S D A TA 2+
P C0 3 V C C [ 5] 33
P C1 4 P C0 V C C [ 6] 40 L7
R2 9 499 _1 %_ 04 Z 4 305 6 P C1 V C C [ 7] 46 H D MI B _D A TA 1N 1 2
RE X T V C C [ 8]
1 H D MI B _D A TA 1P 4 3
Sheet 13 of 42 3. 3 VS R4 9 *4. 7 K_ 04 Z 4 306

Z 4 307
34
3 5 OE _ 1
GN D [ 1]
GN D [ 2]
5
12
C 27 C 65 * H D MI 20 12F 2 SF -90 0T 04 -sho rt C 12 81 7-1 19A 5 -L 4 3 H D MI B _D AT A2 N
* LV A R 04 02- 2 40 E0 R 05 P -L F
R5 8 *4. 7 K_ 04
*L VA R 0 402 - 24 0E 0R 0 5P -LF
QE _ 2 GN D [ 3] 18 1 2 H D MI B_ D A TA 2P
GN D [ 4] 0. 1 u_1 6V _ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _0 4
24
R5 1
R 46
GN D [ 5]
HDMI, CRT 27 L8
*LV A R 04 02- 2 40 E0 R 05 P -L F
*L VA R 0 402 -24 0E 0R 0 5P - LF
GN D [ 6]
R5 5
31 *H DMI 2 01 2F 2S F -90 0T 04-s ho rt
R 59
GN D [ 7] 36
49 GN D [ 8] 37
GN D GN D [ 9] 43
GN D [ 10]
P TN 3 36 0B B S
P I N 4 9= GN D R2 7
POR T C _H P D M_P OR TB _ H PD # _R
17 P OR T C _H P D 3 3. V S
PTN336 0BBS 6 -03 -03360 -030
*1 0m li _s ho rt_ 04
PS8101 6-03- 081 01-032
C 3 10 C 59
3. 3V S R 57 4. 7K _ 04 D C C _E N #
0 . 1u _16 V _Y 5 V_ 04 * 0. 1u _1 6V _Y 5 V _0 4
R 31 4. 7K _ 04 PC 0
R 30 *4. 7 K_ 04 PC 1
J_ C R T1
6-19-31001-266 10 8A H 1 5F S T04 A 1C C
CRT PORT 3 . 3V S 5V S
L4 F C M100 5MF -6 00T 01

RE D 1
2
9
2410 mil
17 D A C _ R ED . GR N
17 D A C _ GR EE N L3 . F C M100 5MF -6 00T 01
B LU E 3
4
3
4
3
17 D A C _ BL U E L2 . F C M100 5MF -6 00T 01
RN7 RN1 11
4
1 0p _5 0V _N P O _0 4
10 p_ 50 V_ N P O _0 4
1 0p _5 0V _N P O _0 4
10 p_ 50 V_ N P O _0 4
2 . 2K _4 P 2R _ 04 2. 2 K_ 4P 2 R _04
10 p_ 50V _ N PO _ 04
10 p_ 50V _ N PO _ 04
12 D D C D AT A
U 15 R1 2 R 11 R 10 5
1
2
1
2
10 9 D D C D A TA 13 HS Y NC
1 7 D A C _D D C A D A TA DDC_ IN1 D D C _OU T 1 1 50 _1% _0 4 150 _1 %_ 04 15 0_ 1%_ 04 6
11 12 DDCL K 14 V S Y NC
1 7 D A C _D D C A C L K DDC_ IN2 D D C _OU T 2 7
13 14 C R T_ H S Y N C R 15 33 _0 4 HS Y NC 15 DDCL K
1 7 D A C _H S Y N C S Y N C _I N 1 S Y N C _OU T 1 8
15 16 C R T_ VS Y N C V SY N C
C1 0
C1 2
C1 1
C1 4
C 2 95 1 000 p_ 50 V_ X 7R _ 04
C 29 3 22 0p _50 V _N P O _0 4
C 2 92 2 20 p_ 50 V_ N P O _04
C 7 10 00 p_ 50 V_ X 7R _0 4
R 14 33 _0 4
C 13
C 16
1 7 D A C _ VS Y N C S Y N C _I N 2 S Y N C _OU T 2
GND 1
GND 2
1 3 B LU E
5V S V C C _S Y N C VI D E O_ 1
2 4 GR N
3 . 3V S V C C _V I D E O VI D E O_ 2
7 5 RE D
3. 3V S V C C _D D C VI D E O_ 3
8 6
BYP GN D
TP D 7S 0 19
0. 2 2u_ 10 V _Y 5V _0 4
0 . 22 u_ 10V _ Y5 V _04
0. 2 2u _1 0V _Y 5V _ 04
IP4772C Z16 6- 02-47721- B60

C 29 8
C 29 9
C 2 96
TPD7S01 9 6-0 2-07019-B 20
2 , 10 ,1 1, 1 2, 14 , 15 , 16, 1 7, 1 8, 19 , 20 2, 1, 2 3, 24 , 25 , 26, 2 7, 2 8, 29 , 30 3, 1, 3 5, 36 3. 3V S
2 , 17 , 20, 2 1, 2 6, 27 , 30 ,3 1, 3 5, 36 5V S
B - 14 HDMI, CRT
Schematic Diagrams
IBEXPEAK- M 1/9
RT CV CC
6 -2 2- 32 R7 6 -0 B2
IBEXPEAK - M (HDA,JTAG,SATA)
R T C_ X 1
2 0m ils 1
6 -2 2- 32 R7 6 -0 BG
VD D3 A
20m ils C 40 2
1
2
1 5p _ 5 0 V _ N P O _ 04 X8
C 3 C 36 9 2 . 2 u _1 6 V _ X 5R _ 0 6
1 T JS 12 5 D J 4 A 4 2 0 P _ 32 . 7 6 8 K H z
R T C _ V B A T_ 1 2 A
2
1
4
3
R 30 4 6 -2 2- 32 R7 6- 0 B4 R T C_ X 2 C o- la yo ut X 7, X 8
2 0 K _ 1% _ 0 4 X7 R 3 02
D1 7 * MC -1 46 _ 3 2 . 7 68 K H z
B A T 5 4C S 3 1 0 M_ 0 4 U2 0 A
3
4
1
RTC CLEAR C 39 7
R 253 C3 9 9 J O PEN 2 1 5p _ 5 0 V _ N P O _ 04 R T C _X 1 B1 3 D 33
D1 3 RT C X 1 F W H0 / LA D 0 B3 3 LP C_ A D 0 24 , 2 8
* OP E N _ 1 0 m li -1 MM R T C _X 2 LP C_ A D 1 24 , 2 8
RT C X 2 F W H1 / LA D 1
10m ils 1 K _ 1 % _ 04 2 . 2 u_ 1 6 V _ X5 R _ 06 Zo= 50O ? 5% F W H2 / LA D 2
C 32
A3 2 LP C_ A D 2 24 , 2 8
2
RT C _ V B A T 1 R T C _R S T # C1 4 F W H3 / LA D 3 LP C_ A D 3 24 , 2 8
R 30 5
J _ RT C1 2 0 K _ 1% _ 0 4 RT C RS T # C 34
D1 7 F W H 4 / LF R A M E # LP C _ F R A ME # 2 4 , 2 8
S R T C _R T C #
1 S R TC R S T# A3 4
J_RTC1
A1 6 L D R Q0 # F34
RTC
LPC
TPM CLEAR S M_ I N T R U D E R #
2 I N TR U D E R # L D R Q1 # / GP I O2 3
R 299 C4 0 0 J O PEN 1
* OP E N _ 1 0 m li -1 MM R 29 8 3 3 0 K _ 04 P C H _ I N T V R ME N A1 4 AB9 S E R IRQ
R T CVC C I N TV R M E N S E R IRQ S E RI RQ 2 4, 2 8
1 2 8 5 20 5 -0 2 70 1 1 M _ 04 2 . 2 u_ 1 6 V _ X5 R _ 06
A3 0
2 7 ,2 9 HD A _ B IT CL K H D A _ B C LK AK7 S A T A R XN 0
3 .3 V S
BIOS ROM 2 7 ,2 9 HD A _ S Y N C
27 HD A_ SPK R
HD A _ S P K R
D2 9
P1
HD A _ S Y NC
SPKR
S A T A 0 RX N
S A TA 0R X P
S A T A 0 TX N
SATA0 TXP
AK6
AK1 1
AK9
S A T A R XP 0
S AT A T XN0
SATATXP0
S A T A R XN 0
S A T A R XP 0
S A T A T X N0
SAT AT XP0
26
26
26
26
SATA HDD
NC 1
C 2 09 C3 0
S H O R T 0 . 1 u _1 6 V _ Y 5V _0 4
32Mbit
2 7 ,2 9 HD A _ RS T # H D A _ R S T#
S A T A 1 RX N
AH
AH
6
5
S A T A R XN 1
S A T A R XP 1
S A T A R XN 1 2 6
S A T A R XP 1 26
Sheet 14 of 42
S P I_ V D D 8
U 10
VD D S I
5
2
S PI_ S I R3 8 1 *0 _ 0 4 8 51 8 _ S P I _ S I 2 8
27
29
HD A _ S D IN0
HD A _ S D IN1
G3 0
F30
HD A _ S D IN0
HD A _ S D IN1
S A TA 1R X P
S A T A 1 TX N
SATA1 TXP
AH
AH
AF1 1
9
8
S AT A T XN1
SATATXP1 S A T A T X N1 2 6
SAT AT XP1 2 6 SATA ODD IBEXPEAK - M 1/9
R1 6 3 S PI_ S O R3 8 2 *0 _ 0 4 8 51 8 _ S P I _ S O 28
SO E3 2 S A T A 2 RX N AF9
3. 3 K _ 1 % _ 0 4
HD A _ S D IN2 S A TA 2R X P
IHDA
S P I_ W P # 3 1 S P I_ CS 0 # R3 8 3 *0 _ 0 4 AF7
W P# C E# 8 51 8 _ S P I _ C S 0 # 28 F32 S A T A 2 TX N AF6
R1 5 6 6 S P I_ S CL K R3 8 4 *0 _ 0 4 HD A _ S D IN3 SATA2 TXP
SCK 8 51 8 _ S P I _ S C L K 2 8 AH 3
3. 3 K _ 1 % _ 0 4
S P I_ HO L D# 7 4 B2 9 S A T A 3 RX N AH 1
H OL D # VSS 2 7 ,2 9 HD A _ S DO UT HD A _ S D O S A TA 3R X P AF3
S A T A 3 TX N AF1
M X 25 L 3 2 05 D M2 I -1 2 G D 18 S C D3 4 0
C A R3 0 7 HD A _ DO CK _ E N # H3 2 SATA3 TXP
SATA
28 ME _W E # H D A _ D O C K _E N # / G P I O 33 AD 9 S A T A R XN 2
6-04-25320-A70 J30 S A T A 4 RX N AD 8 S A T A R XP 2
6-04-02532-470 *1 0 m li _ s ho rt _ 0 4
R 303 1 K _1 % _ 0 4 H D A _ D O C K _R S T # / G P I O1 3 S A TA 4R X P AD 6 S AT A T XN2
6-04-26321-470 S A T A 4 TX N AD 5 SATATXP2
SATA4 TXP
P C H _ JT A G _ T C K _ B U F M 3 AD 3
1
J T A G_ T C K S A T A 5 RX N AD 1
SPI_* = 1.5"~6.5" J OP E N 3
* OP E N _ 10 m i l -1 MM P C H _ JT A G _ T MS K3 S A TA 5R X P AB3
Flash Descriptor J T A G_ T MS S A T A 5 TX N AB1
SATA5 TXP
2
Security Overide P C H _ JT A G _ T D I K1
J T A G_ T D I 1 .1 VS _ VT T
JTAG
3 .3 V P C H _ JT A G _ T D O J2 AF1 6 S A T A I C OM P R 89 3 7 . 4 _ 1 %_ 0 4
J T A G_ T D O S A TA I C O MP O
3 .3 VS P C H _ JT A G _ R S T # J4 AF1 5
J T A G_ R S T # S A T A I C OM P I
R2 9 5 R 29 3 R2 9 0 R 2 87 R 93 10 K _ 0 4 S E RIR Q
R 282 *1 K _ 1 % _0 4 H D A _S P K R
*2 0 K _ 1 %_ 0 4 *2 0 0 _ 06 *2 0 0_ 0 6 * 20 0 _ 0 6 S P I _ S C LK BA2 3 .3 V S
NO REBOOT STRAP: HDA_SPKR High Enable S P I _ C LK
P C H _ JT A G _ TM S S P I _ C S 0# AV3 R 2 78 * 1 0K _0 4
P C H _ JT A G _ TD I S P I_ C S 0 #
P C H _ JT A G _ TD O S P I _ C S 1# AY 3 T3 S A T A _ L E D#
P C H _ JT A G _ R S T # S P I_ C S 1 # S A TA LE D # S A TA _L E D # 2 9 3 .3 VS
3 .3 VS iTPM ENABLE/DISABLE S PI_ S I AY 1 Y 9 O D D _ D E T E C T# R 1 08 1 0 K_ 4

R2 9 4 R 28 9 R2 8 8 R 2 86 S P I _ M OS I S A T A 0 G P / GP I O2 1
AV1 V1
SPI
R 263 *1 K _ 1 % _0 4 S P I _ S I S PI_ S O R2 6 4 3 3 _0 4 S P I _ S O _R O D D _ D E T E C T # 26
*1 0 K _ 1 %_ 0 4 *1 0 0_ 1 % _ 04 *1 0 0_ 1 % _ 04 * 10 0 _ 1 % _0 4 S P I_ M IS O S A T A 1 G P / GP I O1 9
TPM FUNCTION:SPI_SI High Enable
I b e x P e ak -M _ R e v 0 _ 9 S A T A _ D E T# 1 R 2 74 1 0 K_ 0 4
R2 8 5 *4 . 7 K _ 0 4 P C H _J T A G _T C K _ B U F
ESATA
SATATXP2 C 16 8 *0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A T X N2 C 16 5 *0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A R XN 2 C 15 5 *0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A R XP 2 C 16 4 *0 . 0 1 u _ 50 V _ X 7 R _ 0 4
2 3 , 2 5 , 28 , 2 9 , 3 1 , 3 2, 3 7 V D D 3
21 R TC V C C
2 , 4 , 6 , 7 , 1 5 , 1 6, 1 9 , 2 0 , 2 1, 3 4 , 3 5 , 3 6 1. 1 V S _V TT
3 , 4 , 1 2 , 1 5, 16 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 30 , 3 1 , 3 3 , 3 4, 3 5 3 . 3 V
2 , 10 , 1 1 , 1 2 , 1 3, 1 5 , 1 6 , 1 7, 1 8 , 1 9 , 2 0, 2 1 , 2 3 , 2 4, 25 , 2 6 , 2 7 , 28 , 2 9 , 3 0 , 31 , 3 5 , 3 6 3 . 3V S
IBEXPEAK- M 1/9 B - 15
Schematic Diagrams
IBEXPEAK - M 2/9
IBEXPEAK - M (PCI-E,SMBUS,CLK) S MB _C L K 3
RN 1 6
2 . 2K _ 4P 2R _ 0 4
2
3 .3 V
S MB _D A T A 4 1
U 20 B RN 1 1
2 . 2K _ 4P 2R _ 0 4
BG 3 0 B9 PC H_ BT _ EN # S ML 0 _ D A T A 3 2
BJ 3 0 PER N1 S MB A L E R T # / G P I O 1 1 P C H _ B T _E N # 2 3 , 2 9 4 1
S ML 0 _ C L K
B F2 9 PER P1 H 14 S M B _ CL K S M B _ CL K 2
BH 2 9 PET N 1 S M B C LK
RN 1 3
PET P1 C 8 S M B _ D A TA 1 0K _8 P 4 R _ 0 4
AW 3 0 S M B D A TA S M B _ DA T A 2 1 8
PCH _ BT _ EN#
23 P C I E _ R X N 2_ N E W _ C A R D B A3 0 PER N2 U S B _ OC # 8 9 2 7
23 P CIE _ RX P 2 _ NE W _ CA RD PER P2 18 U S B _ OC # 8 9
C 1 17 0. 1u _ 1 0 V _ X 7 R _ 0 4 P C IE _ T X N2 _ C BC 3 0 J14 PC H_ U PE K_ IN IT # LP D _ S P I _I N T R # 3 6
23 P C I E _ T X N 2_ N E W _ C A R D BD 3 0 PET N 2 S M L 0 A L E RT # / G P IO 6 0 PC H_ U PE K_ IN IT # 1 8 4 5
C 1 18 0. 1u _ 1 0 V _ X 7 R _ 0 4 PC IE_ T XP2 _ C
23 P CIE _ T X P 2 _ NE W _ CA RD PET P2 C 6 S M L 0_ C L K
S ML 0 C LK S ML 0 _ C L K 23
AU 3 0 RN 1 0
2 3 P C IE _ R X N3 _ W L A N AT3 0 PER N3 G8
SMBus
S M L 0_ D A T A 2 . 2K _ 4P 2R _ 0 4
2 3 P C I E _ R X P 3 _W L A N P C IE _ T X N3 _ C AU 3 2 PER P3 S ML 0 D A TA S ML 0 _ D A T A 23 S MD _ C P U _ T H E R M 3 2
C 1 24 0. 1u _ 1 0 V _ X 7 R _ 0 4
2 3 PC IE_ T XN3 _ W L AN PC IE_ T XP3 _ C A V3 2 PET N 3 S MC _ C P U _ T H E R M 4 1
2 3 P C I E _ T X P 3 _W L A N C 1 23 0. 1u _ 1 0 V _ X 7 R _ 0 4
PET P3 M 14 L P D _S P I _ I N T R #
B A3 2 S M L 1 A L E RT # / G P IO 7 4
2 5 P C I E _ R X N 4_ G L A N B B3 2 PER N4 E1 0 SM C_ C PU_ T H E R M
2 5 P C I E _ R X P 4 _ GL A N S MC _ C P U _ T H E R M 3 , 2 8
C 1 19 0. 1u _ 1 0 V _ X 7 R _ 0 4 P C IE _ T X N4 _ C BD 3 2 PER P4 S M L 1 CL K / G P IO 5 8
2 5 P C I E _ T X N 4_ G L A N B E3 2 PET N 4 G 12
C 1 20 0. 1u _ 1 0 V _ X 7 R _ 0 4 PC IE_ T XP4 _ C SM D_ C PU_ T H E R M
2 5 P C I E _ T X P 4 _ GL A N PET P4 S M L1 D A T A / G P I O 7 5 S MD _ C P U _ T H E R M 3 , 2 8
PCI-E*
B F3 3 P E G _ CL K R E Q # R2 9 1 1 0K _ 04
BH 3 3 PER N5 T13
BG 3 2 PER P5 CL _ C L K 1 L A N _C L K R E Q# R1 1 2 1 0K _ 04
PCI-E x1 Usage BJ 3 2 PET N 5 Controller T11
PET P5 CL _ D A T A1
Link
Sheet 15 of 42 Lane 1 WLAN
B A3 4
AW 3 4
BC 3 4
PER N6
PER P6
C L_ R S T 1 #
T9
10K pull-down to
IBEXPEAK - M 2/9 Lane 2 NEW CARD BD 3 4 PET N 6 GND

PET P6 H 1 P E G _ CL K R E Q # 100-MHz Gen2 differential clock to PCIe Graphics
Lane 3 3G AT3 4 P E G _A _ C L K R Q# / G P I O 4 7 device.
AU 3 4 PER N7
Lane 4 GLAN / CARD READER PER P7
AU 3 6 AD 4 3
Lane 5 X PET N 7 C L K O U T _ P E G_ A _ N
PEG
A V3 6 AD 4 5
PET P7 C LK OU T _ P E G _A _P
Lane 6 X BG 3 4 AN 4
PER N8 C L K O U T _ D MI _ N C LK _E XP _ N 4
Lane 7 X BJ 3 4 AN 2
C LK _E XP _ P 4
BG 3 6 PER P8 C L K O U T_ D MI _P
Lane 8 X BJ 3 6 PET N 8
PET P8 AT1 P C H_ C L K _ DP _ N _ R R2 6 6 *1 0 m i l_ s h o rt _ 0 4 C L K _ D P _N 4
C LK OU T _ D P _ N / C LK OU T _ B C L K 1 _ N AT3 P C H_ C L K _ DP _ P _ R R2 6 7 *1 0 m i _l s h o rt _ 0 4
3 .3 V 3 .3 VS A K4 8 C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _P C L K _ D P _P 4
A K4 7 C L K O U T_ P C I E 0 N
RN 8 C L K O U T_ P C I E 0 P A W 24 100-MHz differential clock from PCH to Processor.
P 9 C L K I N _ D MI _ N BA2 4 C LK _ P C I E _I C H # 2 Connect to PEG_CLK#/PEG_CLK pins of the
1 0 K _ 8P 4 R _ 0 4 P C I E C L K R Q0 # C LK _ P C I E _I C H 2
From CLK BUFFER

1 8 PC IE C L K RQ 1# P C I E C L K R Q 0 # / GP I O7 3 C L K I N _ D MI _P processo
2 7 PC IE C L K RQ 0#
3 6 PC IE C L K RQ 5# AM 4 3 AP3
4 5 PE G_ B _ C LK RQ # AM 4 5 C L K O U T_ P C I E 1 N C L K I N _B C L K _ N AP1 C LK _ B U F _B C L K _ N 2
C L K O U T_ P C I E 1 P C L K I N _ B C LK _P C LK _ B U F _B C L K _ P 2
P C I E C L K R Q1 # U 4
P C I E C L K R Q 1 # / GP I O1 8 F18
C L K I N _ D O T _9 6 N C LK _ B U F _D O T9 6 _ N 2
E1 8
AM 4 7 C L K I N _ D O T _ 9 6P C LK _ B U F _D O T9 6 _ P 2
2 3 C L K _ P C IE _ NE W _ CA R D # AM 4 8 C L K O U T_ P C I E 2 N
2 3 C L K _ P CI E _ NE W _ CA R D C L K O U T_ P C I E 2 P AH 1 3
C LK _ S A T A # 2 C3 9 1 2 2 p _ 50 V _N P O _ 04
R 2 83 * 1 0m i l _ s ho rt _ 0 4 C L K _ S L O T2 _ O E # N 4 C L K IN _ S A T A _ N / CK S S C D_ N AH 1 2
2 3 N E W C A R D _ C L K R E Q# P C I E C L K R Q 2 # / GP I O2 0 C L K I N _S A T A _ P / C K S S C D _P C LK _ S A T A 2
AH 4 2 P4 1
2 3 CL K _ P CIE _ M IN I# AH 4 1 C L K O U T_ P C I E 3 N RE F CL K 1 4 IN C LK _ B U F _R E F 1 4 2
1
R2 6 8
2 3 CL K _ P C IE _ M INI C L K O U T_ P C I E 3 P
X6 6 -2 2- 2 5R 00 -1 B 4
A 8 J42 1 M_ 0 4 F S X 5 L _2 5 M H z
2 3 W L A N _ CL K R E Q # P C I E C L K R Q 3 # / GP I O2 5 C L K I N _ P C I L O OP B A C K C LK _ P C I _ F B 18 6 -2 2- 2 5R 00 -1 B 5
2
AM 5 1 AH 5 1 X T A L 25 _ I N
2 5 C LK _P C I E _G L A N # AM 5 3 C L K O U T_ P C I E 4 N X TA L2 5 _ I N AH 5 3 X T A L 25 _ O U T C3 8 7 2 2 p _ 50 V _N P O _ 04
2 5 CL K _ P CIE _ G L A N C L K O U T_ P C I E 4 P X T A L 2 5 _ OU T
LA N _ C LK R E Q # M9 AF3 8 X CL K _ R CO M P R8 7 9 0 . 9 _ 1 % _ 04 90.9-O ? % pullup
P C I E C L K R Q 4 # / GP I O2 6 X C L K _ R C O MP 1 .1 V S_ V T T
to +VccIO
(1.05V, S0 rail)
AJ 5 0 T45
Clock Flex
AJ 5 2 C L K O U T_ P C I E 5 N CL K O UT F L E X 0 / G P IO 6 4
C L K O U T_ P C I E 5 P
P C I E C LK R Q 5 # H 6 P4 3
P C I E C L K R Q 5 # / GP I O4 4 CL K O UT F L E X 1 / G P IO 6 5
A K5 3 T42
A K5 1 C L K O U T_ P E G_ B _ N CL K O UT F L E X 2 / G P IO 6 6
C L K O U T_ P E G_ B _ P
P E G _ B _ CL K R Q # P1 3 N 50
P E G _ B _ C L K R Q# / GP I O5 6 CL K O UT F L E X 3 / G P IO 6 7
I b e x P e ak -M _ R e v 0 _ 9
3 .3 VS 2, 1 0 , 1 1 , 1 2 , 1 3 , 14 , 1 6 , 1 7 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8 , 2 9 , 3 0, 3 1 , 3 5 , 3 6
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4, 16 , 1 9 , 2 0 , 2 1 , 3 4, 35 , 3 6
3 .3 V 3, 4 , 1 2 , 1 4 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 2 4, 25 , 2 9 , 3 0 , 3 1 , 3 3, 3 4 , 3 5
B - 16 IBEXPEAK - M 2/9
Schematic Diagrams
IBEXPEAK - M 3/9
IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C
BA1 8
B C 24 F DI_ R XN 0 B H1 7 F DI _T X N 0 3
3 D MI _ R X N 0 D MI 0 R XN F DI_ R XN 1 F DI _T X N 1 3
B J 22 B D1 6
3 D MI _ R X N 1 A W 20 D MI 1 R XN F DI_ R XN 2 BJ 1 6 F DI _T X N 2 3
3 D MI _ R X N 2 B J 20 D MI 2 R XN F DI_ R XN 3 BA1 6 F DI _T X N 3 3
3 D MI _ R X N 3 D MI 3 R XN F DI_ R XN 4 BE1 4 F DI _T X N 4 3
B D 24 F DI_ R XN 5 BA1 4 F DI _T X N 5 3
3 D MI _ R X P 0 D MI 0 R XP F DI_ R XN 6 F DI _T X N 6 3
B G 22 B C1 2
3 D MI _ R X P 1 B A 20 D MI 1 R XP F DI_ R XN 7 F DI _T X N 7 3
3 D MI _ R X P 2 B G 20 D MI 2 R XP BB1 8
3 D MI _ R X P 3 D MI 3 R XP FD I_ RX P 0 BF1 7 F DI _T X P 0 3
FD I_ RX P 1 F DI _T X P 1 3
B E 22 B C1 6
3 DM I _ TX N 0 B F 21 D MI 0 T X N FD I_ RX P 2 B G1 6 F DI _T X P 2 3
3 DM I _ TX N 1 D MI 1 T X N FD I_ RX P 3 F DI _T X P 3 3
B D 20 AW 1 6
3 DM I _ TX N 2 B E 18 D MI 2 T X N FD I_ RX P 4 B D1 4 F DI _T X P 4 3
3 DM I _ TX N 3 D MI 3 T X N FD I_ RX P 5 F DI _T X P 5 3
BB1 4
B D 22 FD I_ RX P 6 B D1 2 F DI _T X P 6 3
3 DM I _ TX P 0 B H 21 D MI 0 T X P FD I_ RX P 7 F DI _T X P 7 3
3 DM I _ TX P 1 B C 20 D MI 1 T X P
3 DM I _ TX P 2 B D 18 D MI 2 T X P BJ 1 4
3 DM I _ TX P 3 D MI 3 T X P F D I _I N T F D I _I N T 3
DMI
FDI
BF1 3
F DI_ F S Y NC 0 F D I _F S Y N C 0 3
R2 6 1 49 . 9 _ 1 %_ 0 4 D MI _C OM P _ R B H 25
1 .1 VS _ VT T D MI _ Z C OM P B H1 3
F DI_ F S Y NC 1 F D I _F S Y N C 1 3
B F 25
D MI _ I R C O MP BJ 1 2
F D I _ LS Y N C 0 F D I _L S Y N C 0 3
B G1 4
F D I _ LS Y N C 1 F D I _L S Y N C 1 3
Sheet 16 of 42
IBEXPEAK - M 3/9
R1 1 1 1 0 K _ 04 S Y S _ RE S E T # T6 J 12 P C I E _W A K E #
3. 3 V S S Y S _ RE S E T # W AKE# P C I E _W A K E # 2 3, 2 5
S Y S _ P W R OK M6 Y1 P M_ C LK R U N #
S Y S _ P W R OK C L K R U N # / GP I O3 2 P M _C L K R U N # 2 4
System Power Management

3 .3 V
S B _ P W RO K B 17
P W RO K P CIE _ W A K E # R1 2 1 1 K _ 1% _ 0 4
P M_ MP W R O K K5 P8 S 4 _S TA T E # P M_ S L P _ L A N # R1 2 7 *1 0 K _ 0 4
M E P W R OK S U S _S T A T # / GP I O6 1 S 4 _ S TA TE # 2 4
S W I# R1 3 0 1 0K _0 4
R2 9 7 10 K _ 0 4 A U X P P W R OK _ R A 10 F3
L A N _ RS T # S U S C L K / GP I O6 2 S US _ P W R _ A CK R2 8 4 1 0K _0 4
EXT-LAN
D9 E4 P W R_ B T N # R1 0 9 *1 0 K _ 0 4
4 P M_ D R A M _P W R G D D R A M P W R OK S LP _ S 5 # / GP I O6 3
A C_ P R E S E NT R1 1 5 1 0K _0 4
R S M R S T# C 16 H7
28 R S MR S T# R S MR S T # SL P_ S4 # S U S C # 2 8 , 33
R3 0 0 10 K _ 0 4
P M_ B A T L OW # R2 9 6 8 . 2 K _0 4
S U S _P W R _ A C K M1 P1 2 S US B #
28 S U S _ P W R _ A C K S U S _ P W R _A C K / G P I O3 0 SL P_ S3 # S US B # 2 3 , 28 , 3 1 3 .3 VS
P W R _B T N # P5 K8 P M _C L K R U N # R2 7 1 8 . 2 K _0 4
28 P W R _B T N # P W RB T N # S L P _M #
A C _P R E S E N T P7 N2 A L L _ S Y S _ P W R GD R1 4 3 1 0K _0 4
1 8, 2 8 A C _P R E S E N T A C P R E S E N T / G P I O 31 T P2 3
P M_ B A T L OW # A6 BJ 1 0
B A TL O W # / GP I O 7 2 PM SY N CH H_ P M _ S Y N C 4
S W I# F 14 F6 P M_ S L P _ L A N #
28 SW I# R I# S L P _ LA N #
R1 3 9 *1 0 m il _ s ho rt _ 0 4 P M_ M P W R O K
2 8, 36 V C OR E _ ON
I be x P e a k- M_ R e v 0 _ 9
3 .3 V
3 .3 V
3. 3 V 3 . 3V
U8 D
14
U 8A U 8C 7 4 LV C 0 8P W R1 4 4 *1 0 m il _ s ho rt _ 0 4 S B _P W R O K
14
7 4 L V C0 8 P W U8 B 7 4 LV C 0 8 P W 12
14
9 4 ,3 6 DE L A Y _ P W RG D 11 S Y S _ P W R OK
74 L V C 08 P W R1 4 2 *1 0 m il _ s ho rt _ 0 4
14
4 4 , 3 3, 3 4 1 . 1 V S _ V T T_ P W R GD 8 13
A L L_ S Y S _ P W R G D
1 3 3 1. 8 V S _ P W R GD 6 1 . 1 V S _ V T T_ E N 10
3 3 D D R 1 . 5 V _ P W R GD
3 5 R1 4 5
7
SU SB# 2
7
10 K _ 0 4
A L L _ S Y S _ P W R GD 1 2 , 28
7
34 1 . 1 V S _ V T T _E N
7
R1 4 1 2K _1 % _ 04
H _ V T T P W R GD 4
C 4 70
ON R 13 8
1 u _ 6. 3 V _ X 5 R _ 0 4
1 K _ 1% _ 0 4
3 . 3V S 2 , 10 , 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 7 , 1 8, 1 9 , 2 0, 21 , 2 3 , 2 4, 2 5 , 2 6, 27 , 2 8 , 29 , 3 0 , 3 1, 3 5 , 3 6
3 . 3V 3 , 4, 1 2 , 1 4 , 15 , 1 8 , 1 9, 2 0 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5
1 . 1V S _V TT 2 , 4 , 6 , 7, 14 , 1 5 , 19 , 2 0 , 2 1, 3 4 , 3 5 , 36
IBEXPEAK - M 3/9 B - 17
Schematic Diagrams
IBEXPEAK - M 4/9
IBEXPEAK - M (LVDS,DDI)
U20D
T48 BJ46
12 BLON L_BKLTEN SDVO_TVCLKI NN BG46
T47
12 NB_ENAVDD L_VDD_EN SDVO_TVCLKINP
Y48 BJ48
L_BKLTCTL SDVO_STALLN BG48
AB48 SDVO_STALLP
12 P_DDC_CLK Y45 L_DDC_CLK BF45
3.3VS
12 P_DDC_DATA L_DDC_DATA SDVO_INTN BH45
L_CTRL_CLK AB46 SDVO_INTP
R96 *10K_04
L_CTRL_DATA V48 L_CTRL_CLK
R97 *10K_04
L_CTRL_DATA
R83 2. 37K_1%_04 LVDS_I BG AP39 T51
AP41 LVD_IBG SDVO_CTRLCLK T53
LVD_VBG SDVO_CTRLDATA
AT43
AT42 LVD_VREFH BG44
LVD_VREFL DDPB_AUXN BJ44
DDPB_AUXP AU38
AV53 DDPB_HPD
12 LVDS-LCLKN
LVDS
AV51 LVDSA_CLK# BD42
Dis play Port B

Sheet 17 of 42
SDVO
12 LVDS-LCLKP LVDSA_CLK DDPB_0N BC42
BB47 DDPB_0P BJ42
12 LVDS-L0N BA52 LVDSA_DATA#0 DDPB_1N BG42
Digital Display Interface

IBEXPEAK - M 4/9 12 LVDS-L1N
12 LVDS-L2N
AY48
AV47
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_1P
DDPB_2N
DDPB_2P
BB40
BA40
AW38
RN5
2.2K_4P2R_04
BB48 DDPB_3N BA38 3 2
12 LVDS-L0P LVDSA_DATA0 DDPB_3P 3.3VS
BA50 4 1
12 LVDS-L1P LVDSA_DATA1
AY49
12 LVDS-L2P AV48 LVDSA_DATA2 Y49
LVDSA_DATA3 DDPC_CTRLCLK AB49 HDMI_CTRLCLK 13
DDPC_CTRLDATA HDMI_CTRLDATA 13
AP48
AP47 LVDSB_CLK# BE44
LVDSB_CLK DDPC_AUXN BD44
AY53 DDPC_AUXP AV40 PCH_DDPC_HPD
AT49 LVDSB_DATA#0 DDPC_HPD
EMI AU52 LVDSB_DATA#1 BE40 HDMIB_D2BN_C C125 0.1u_10V_X7R_04
Dis play Port C

AT53 LVDSB_DATA#2 DDPC_0N BD40 HDMIB_D2BN 13
R105 0_04 DAC_BLUE_R HDMIB_D2BP_C C126 0.1u_10V_X7R_04
13 DAC_BLUE LVDSB_DATA#3 DDPC_0P BF41 HDMIB_D2BP 13
C174 HDMIB_D1BN_C C111 0.1u_10V_X7R_04
DAC_GREEN_R AY51 DDPC_1N BH41 HDMIB_D1BP_C HDMIB_D1BN 13
*33p_50V_NPO_04 R99 0_04 C112 0.1u_10V_X7R_04
13 DAC_GREEN AT48 LVDSB_DATA0 DDPC_1P BD38 HDMIB_D0BN_C HDMIB_D1BP 13
C170 C113 0.1u_10V_X7R_04 HDMIB_D0BN 13
*33p_50V_NPO_04 R91 0_04 DAC_RED_R AU50 LVDSB_DATA1 DDPC_2N BC38 HDMIB_D0BP_C C114 0.1u_10V_X7R_04
13 DAC_RED AT51 LVDSB_DATA2 DDPC_2P BB36 HDMIB_D0BP 13
C166 HDMIB_CLKBN_C C115 0.1u_10V_X7R_04
LVDSB_DATA3 DDPC_3N BA36 HDMIB_CLKBP_C HDMIB_CLKBN 13
*33p_50V_NPO_04 C116 0.1u_10V_X7R_04
DDPC_3P HDMIB_CLKBP 13
NEAR PCH R104

R98
150_1%_04
150_1%_04
DAC_BLUE_R
DAC_GREEN_R
AA52
AB53 CRT_BLUE
CRT_GREEN
DDPD_CT
U50
RLCLK U52
DDPD_CTRLDATA
R92 150_1%_04 DAC_RED_R AD53 5VS
CRT_RED
BC46 Q7
G
V51 DDPD_AUXN BD46 MTN7002ZHS3
13 DAC_DDCACLK V53 CRT_DDC_CLK DDPD_AUXP AT38
13 DAC_DDCADATA CRT_DDC_DATA DDPD_HPD PCH_DDPC_HPD S D
PORTC_HPD 13
BJ40
Dis play Port D

Y53 DDPD_0N BG40
13 DAC_HSYNC Y51 CRT_HSYNC DDPD_0P BJ38 R34
13 DAC_VSYNC CRT_VSYNC DDPD_1N BG38
DDPD_1P BF37 100K_1%_04
CRT
R88 1K_1%_04 DAC_IREF_R AD48 DDPD_2N BH37
AB51 DAC_I REF DDPD_2P BE36
CRT_IRTN DDPD_3N BD36
DDPD_3P
IbexPeak-M_Rev0_9
Connect to GND
PCH_DDPC_HPD R33 *0_04 PORTC_HPD
No Connect
External Graphics (PCH Integrated Graphics Disable)
External Graphics (PCH Integrated Graphics Disable)
2,10,11,12,13,14, 15,16,18,19,20,21,23,24,25,26,27, 28,29,30,31,35,36 3.3VS

2,13,20,21, 26,27,30,31,35,36 5VS
Schematic Diagrams
IBEXPEAK - M 5/9
IBEXPEAK - M (PCI,USB,NVRAM)
U2 0E
H40 AY9
N34 AD 0 NV_C E#0 BD1
C44 AD 1 NV_C E#1 AP15
B o o t B I O S S t r ap A38 AD 2 NV_C E#2 BD8
C36 AD 3 NV_C E#3
J34 AD 4 AV9
PCI _GN T#0 P CI _GN T#1 Boo t B IOS Lo cat ion A40 AD 5 NV_D QS0 BG8
D45 AD 6 NV_D QS1
E36 AD 7 AP7
0 0 LP C H48 AD 8 NV_D Q0 / NV_I O0 AP6
E40 AD 9 NV_D Q1 / NV_I O1 AT6
0 1 Re ser ved ( NAN D) AD 10 NV_D Q2 / NV_I O2
C40 AT9
1 0 PC I M48 AD 11 NV_D Q3 / NV_I O3 BB1
M45 AD 12 NV_D Q4 / NV_I O4 AV6
1 1 SP I F53 AD 13 NV_D Q5 / NV_I O5 BB3
M40 AD 14 NV_D Q6 / NV_I O6 BA4
M43 AD 15 NV_D Q7 / NV_I O7 BE4
NVRAM
R 117 *1K_ 1%_0 4 PC I_ GNT#0 J36 AD 16 NV_D Q8 / NV_I O8 BB6
K48 AD 17 NV_D Q9 / NV_I O9 BD6
F40 AD 18 NV_D Q1 0 / N V_ IO 10 BB7
R 119 *1K_ 1%_0 4 PC I_ GNT#1
C42 AD 19 NV_D Q1 1 / N V_ IO 11 BC8
K46 AD 20 NV_D Q1 2 / N V_ IO 12 BJ8
M51 AD 21 NV_D Q1 3 / N V_ IO 13 BJ6
J52 AD 22 NV_D Q1 4 / N V_ IO 14 BG6
K51 AD 23 NV_D Q1 5 / N V_ IO 15
L34 AD 24 BD3
F42 AD 25 NV_ALE AY6
J40 AD 26 N V_ CLE
Understand the RED FONT define G46 AD 27
F44 AD 28 AU2 NV_R COMP R2 65 3 2. 4_1 %_04
R12 2 *1 K_ 1%_0PC
4 I_G NT# 3 M47 AD 29 NV_RC OMP
H36 AD 30 AV7
PCI
AD 31 N V_ RB#
J50
G42
H47
C/BE0#
C/BE1#
N V_WR #0_ RE#
N V_WR #1_ RE#
AY8
AY5 Sheet 18 of 42
C/BE2#
3. 3VS IN T_ PI RQ A#
G34
G38
C/BE3#
PI RQ A#
N V_ WE#_ CK0
N V_ WE#_ CK1
AV11
BF5
IBEXPEAK - M 5/9
IN T_ PI RQ B# H51
4 5 I NT_ PIRQ E# IN T_ PI RQ C# B37 PI RQ B# H1 8
PI RQ C# USBP0N USB_PN0 30
R N2 3 3 6 PCI _I RDY # IN T_ PI RQ D# A44
PI RQ D# U SBP0P
J1 8 USB_PP0 30 USB PORT0
8 .2 K_8P4 R_0 4 2 7 IN T_PI RQD # A18
USB_PN1 30
1 8 F51 USBP1N C1 8 USB PORT1
PC I_FR AME# PCI _REQ #0 USB_PP1 30
4 5 PCI _PERR # PCI _REQ #1 A46 REQ0# U SBP1P N2 0
REQ1# / GPI O5 0 USBP2N USB_PN2 23
R N1 2 3 6 PCI_ LOC K# B45 P20
USB_PP2 23
WLAN
8 .2 K_8P4 R_0 4 2 7 PC I_D EVSEL # PCI _REQ #3 M53 REQ2# / GPI O5 2 U SBP2P J2 0
REQ3# / GPI O5 4 USBP3N USB_PN3 23
1 8 PCI _SERR # L2 0
USB_PP3 23
NEW CARD
4 5 PCI_ REQ# 1 PCI _GN T# 0 F48 U SBP3P F20
GNT0# USBP4N USB_PN4 30 USB PORT2
R N2 2 3 6 PCI _TRDY # PCI _GN T# 1 K45 G2 0
GNT1# / GPIO 51 U SBP4P USB_PP4 30
8 .2 K_8P4 R_0 4 2 7 IN T_PI RQH # B ACK LI GHT C ONT RO L F ROM I GPU /D GPU D GPU_ PW M_SEL EC T# F36 A20
1 8 H53 GNT2# / GPIO 53 USBP5N C2 0 USB_PN5 24
PCI_ REQ# 0 PCI _GN T# 3
GNT3# / GPIO 55 U SBP5P USB_PP5 24 CCD
M2 2
4 5 B41 USBP6N N2 2
IN T_PI RQG # IN T_ PI RQ E#
3 6 IN T_PI RQC # IN T_ PI RQ F# K53 PI RQ E# / GPI O2 U SBP6P B21
R N2 4
PI RQ F# / GPI O3 USBP7N
8 .2 K_8P4 R_0 4 2 7 I NT_ PIRQ A# IN T_ PI RQ G# A36 D2 1
1 8 A48 PI RQ G# / GPIO 4 U SBP7P H2 2
PCI _STO P# IN T_ PI RQ H#
4 5 PI RQ H# / GPIO 5 USBP8N J2 2
I NT_ PIRQ B#
3 6 K6 U SBP8P E22
R N2 0 I NT_ PIRQ F#
USB
PC IR ST# USBP9N USB_PN9 24
8 .2 K_8P4 R_0 4 2 7 PCI_ REQ# 3 F22
USB_PP9 24
3G
1 8 DGPU _PWM_SELECT# PCI _SERR# E44 U SBP9P A22
E50 SER R# U SBP1 0N C2 2
PCI _PERR#
PER R# USBP10P G2 4
U SBP1 1N USB_PN1 1 29
H2 4
USB_PP11 2 9
BT
PCI _IR DY # A42 USBP11P L2 4
H44 IRD Y# U SBP1 2N M2 4
PCI _DEVSEL# F46 PAR USBP12P A24
PCI _FRAME# C46 DEVSEL # U SBP1 3N C2 4
FR AME# USBP13P
PCI _LO CK# D49
PL OCK# B25 USB_BIAS R3 01 2 1_ 1%_0 4
D41 USBRBIAS#
PCI _STO P#
C48 STOP# D2 5
PCI _TR DY#
TRD Y# USBRBI AS
M7
28 PME# PME# N1 6
P IN PLT _RST # t o B uffe r PLT_RST# D5 OC 0# / GPIO 59 J1 6 USB_OC #2 3
USB_ OC# 01 3 0
24 PL T_ RST# PL TR ST# OC 1# / GPIO 40 F16 USB_ OC# 23 2 3 3. 3V
USB_OC #4 5
N52 OC 2# / GPIO 41 L1 6 USB_OC #6 7
CLKOU T_ PC I0 OC 3# / GPIO 42
R 124 22 _1 %_ 04CL K_PCI _FB_R P53 E14 USB_OC #8 9
15 CLK_ PC I_ FB CLKOU T_ PC I1 OC 4# / GPIO 43 USB_ OC# 89 1 5
28 PCLK_KBC R 120 22 _1 %_ 04CL K_PCI _KBC_R P46 G1 6 USB_OC #1 011
P51 CLKOU T_ PC I2 O C5# / GPI O9 F12 USB_OC #1 213 R1 25 1 0K_ 04
P48 CLKOU T_ PC I3 OC 6# / GPIO 10 T1 5
24 PCLK_TPM R 133 *22 _1%_ 04 PCLK_ TPM_ PC H R1 10 1 0K_ 04
CLKOU T_ PC I4 OC 7# / GPIO 14 G PIO1 4 R1 13 *0 _0 4
AC_ PRESENT 1 6,2 8
I bex Peak -M_Re v 0_9
3.3 V
3. 3VS
USB_ OC# 67 5 4
C18 5 *0. 1u_ 10V_ X7R _0 4 USB_ OC# 101 1 6 3 RN1 4
USB_ OC# 45 7 2 10 K_ 8P4R _0 4
5
U6 PC H_ UPEK_ IN IT# 8 1
15 PCH _U PEK_ INI T#
PLT_R ST# 1 MC 74VH C1G 08D FT1G
4
2 BU F_ PLT_ RST# 4, 23, 25 ,28
R11 8
3
10 0K_1 %_ 04
2,1 0, 11, 12 ,1 3,1 4, 15, 16 ,17 ,1 9,2 0, 21, 23 ,24 ,2 5,2 6, 27, 28 ,29 ,3 0,3 1, 35, 36 3.3 VS
3, 4, 12 ,14 ,1 5,1 6, 19, 20 ,21 ,2 3,2 4, 25, 29 ,30 ,3 1,3 3, 34, 35 3.3 V
Schematic Diagrams
IBEXPEAK - M 6/9
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
U 20F
E D P _ C A R D _D E T # Y 3 AH 4 5
0213 S_GPIO CHANGE TO EDP_CARD_DET# B MB U S Y # / G P I O 0 C LK OU T _ P C I E 6 N AH 4 6
S MI # C 38 C L K O UT _ P C IE 6 P
28 S M I# T A C H 1 / G PIO 1
3 .3 V S R2 7 2 1 K _ 1 % _ 04 ED P_ C ARD _ D E T #
D G P U _ H P D _ I N TR # D 37
T A C H 2 / G PIO 6 AF4 8
MISC
R 273 S CI # J32 C LK OU T _ P C I E 7 N AF4 7
28 S C I# T A C H 3 / G PIO 7 C L K O UT _ P C IE 7 P
* 0 _ 04 P CH _ M UT E # F1 0 R 27 6 1 0 K_ 0 4
27 P C H _ MU T E # G PIO 8 3. 3V S
R1 2 6 * 10 K _0 4 K9 U2
3. 3V L A N _ P H Y _ P W R _C T R L / GP I O1 2 A 2 0G A T E G A2 0 28
H O S T _ A L E R T #1 T7
BIO S_ R EC G PIO 1 5
3 .3 V S R1 0 1 1 0 K_ 0 4
R 2 70 * 1 0 K_ 0 4 A A2 AM 3
3 .3 V S S A T A 4 GP / G P IO 1 6 C L K O U T _ B C L K 0 _ N / C LK OU T _ P C I E 8 N B C LK _ C P U _ N 4
R 102 GP I O1 7 F3 8 AM 1 R 256 *1 0 K _ 0 4
BIOS RECOVERY T A C H 0 / G P I O 17 C L K O UT _ B C L K 0 _ P / C L K O UT _ P C IE 8 P B C LK _ C P U _ P 4 1 .1 V S _ V T T
DISABLE----NO STUFF (DEFAULT) * 0 _ 04 B IO S _ RE C Y 7 BG 1 0 H _ P E C I_ R R 260 *1 0 m i l _s h o rt _ 0 4
GPIO
S C L O C K / G P I O 22 P E CI H_ P E CI 4 ,2 8
ENABLE-----STUFF
H 10 T1 R 27 7 1 0 K_ 0 4
M E M _ L E D / GP I O2 4 R C IN # 3 .3 VS
K B C_ R S T # 2 8
SB_ BL O N AB1 2 BE1 0
12 S B _B L ON G PIO 2 7 P R OC P W R G D H _ CP U P W RG D 4
R2 8 1 *1 0 K _ 0 4 C R B _S V _ D E T
CPU
3 .3 V S S P I_ C S # 2 V1 3 BD 1 0 R 25 9 56_04 R 255 56 _ 0 4
Sheet 19 of 42 CRB/SV DETECT R 280 S T P_ PC I# M 11
G PIO 2 8
S TP _ P C I # / GP I O3 4
T H R M T R IP #
H _ TH R MT R I P # 4
1. 1V S _ V T T
IBEXPEAK - M 6/9 NO STUFF [DETECT] 1 0 0 K_ 1 % _ 0 4
R 2 79
GP I O3 5
* 1 K _ 1 % _ 04
V6
A B7
S A T A C LK R E Q# / G P I O 3 5
BA2 2
Connected to PCH (THRMTRIP#)
Routing guidelines available in
3 .3 V S S A T A 2 GP / G P IO 3 6 TP1 Calpella Design Guide.
DG P U _ P RS NT # AB1 3 AW 2 2 NOTE: CRB uses a 54.9 O ? %
S V _S E T _ U P S A T A 3 GP / G P IO 3 7 TP2 series resistor and 56-O pull-up.
3 .3 V S R9 5 1 0 K_ 0 4
MF G _ M OD E V3 BB2 2
S LO A D / G P I O 3 8 TP3
R 100 CR B _ SV_ D E T P3 AY 4 5
S D A T A OU T 0 / G P I O 39 TP4
* 0 _ 04 H 3 AY 4 6
P C I E C L K R Q 6# / GP I O4 5 TP5
D R A M R S T_ C T R L F1 AV4 3
4 , 9 D R A MR S T _ C TR L P C I E C L K R Q 7# / GP I O4 6 TP6
SV_ SET _ U P A B6 AV4 5
S D A T A OU T 1 / G P I O 48 TP7
R2 6 9 *0 _ 0 4 C R I T _ T E MP _R E P #_ R A A4 AF1 3
3. 3V 3 C R I T_ T E M P _ R E P # S A T A 5 GP / G P IO 4 9 TP8
R1 2 8 1 0 K_ 0 4 P C H _ GP I O5 7 F8 M1 8
G PIO 5 7 TP9
R1 0 7 1 K_ 0 4 H OS T_ A L E R T # 1 N1 8
TP 10
R N9 A4 AJ 2 4
1 0 K _ 8 P 4 R _0 4 A4 9 V SS_ N CT F _ 1 TP 11
RSVD
1 8 A5 V SS_ N CT F _ 2 AK4 1
P C H _ MU T E #
2 7 S P I_ C S #2 A5 0 V SS_ N CT F _ 3 TP 12
3 6 D R A MR S T _ C TR L A5 2 V SS_ N CT F _ 4 AK4 2
4 5 A5 3 V SS_ N CT F _ 5 TP 13
B2 V SS_ N CT F _ 6 M3 2
B4 V SS_ N CT F _ 7 TP 14
B5 2 V SS_ N CT F _ 8 N3 2
B5 3 V SS_ N CT F _ 9 TP 15
B E1 V SS_ N CT F _ 1 0 M3 0
3 .3 V S BE5 3 V SS_ N CT F _ 1 1 TP 16
B F1 V SS_ N CT F _ 1 2 N3 0
BF5 3 V SS_ N CT F _ 1 3 TP 17
BH 1 V SS_ N CT F _ 1 4 H1 2
R 1 14 * 1 0 K_ 0 4 G P IO 1 7
BH 2 V SS_ N CT F _ 1 5 TP 18
NCTF
BH 5 2 V SS_ N CT F _ 1 6 AA2 3
R N2 1
1 0 K _ 8 P 4 R _0 4 BH 5 3 V SS_ N CT F _ 1 7 TP 19
1 8 SC I# BJ 1 V SS_ N CT F _ 1 8 AB4 5
2 7 SM I# BJ 2 V SS_ N CT F _ 1 9 N C _1
3 6 MF G_ M OD E BJ 4 V SS_ N CT F _ 2 0 AB3 8
4 5 ST P_ PC I# BJ 4 9 V SS_ N CT F _ 2 1 N C _2
BJ 5 V SS_ N CT F _ 2 2 AB4 2
BJ 5 0 V SS_ N CT F _ 2 3 N C _3
R N4
BJ 5 2 V SS_ N CT F _ 2 4 AB4 1
1 0 K _ 8 P 4 R _0 4
1 8 DG P U _ HP D_ IN T R# BJ 5 3 V SS_ N CT F _ 2 5 N C _4
2 7 CR IT _ T E M P _ RE P # _ R D 1 V SS_ N CT F _ 2 6 T39
3 6 DG P U _ P R S NT # D 2 V SS_ N CT F _ 2 7 N C _5
4 5 GP I O3 5 D 53 V SS_ N CT F _ 2 8
E1 V SS_ N CT F _ 2 9 P6
E5 3 V SS_ N CT F _ 3 0 I N I T 3 _3 V #
V SS_ N CT F _ 3 1 C1 0
TP 24
I be x P e a k -M _ R e v 0 _ 9
R1 0 3 *1 0 K _ 0 4 DG P U _ P R S NT #
LOW: DGPU PRESENT 2 , 4 , 6 ,7 ,1 4 ,1 5 ,1 6 ,2 0 ,2 1, 34 , 3 5 , 3 6 1 .1 V S _V T T

3 , 4 ,1 2 , 1 4 , 1 5 , 1 6 , 1 8, 20 ,2 1 ,2 3 ,2 4 ,2 5 ,2 9 ,3 0 ,3 1, 33 , 3 4 , 3 5 3 .3 V
2 , 1 0 , 1 1 , 1 2 , 1 3, 14 ,1 5 ,1 6 , 1 7 , 1 8 , 2 0 , 2 1, 23 , 2 4 ,2 5 ,2 6 ,2 7 ,2 8 ,2 9 ,3 0, 31 , 3 5 , 3 6 3 .3 V S
Schematic Diagrams
IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
R 90 3 .3 V S
H C B 1 6 0 8K F -1 2 1 T2 5
.
1 .1 V S_ V T T V C C A _ D A C _ 3. 3V S L12 5 VS
U 20G POWER H C B 1 6 0 8 K F - 12 1 T 2 5 U 5
AB2 4
AB2 6 VC C CO R E[1 ] V C CA DA C [1 ]
AE5 0 . 5
OU T IN
1
C 17 6 C 1 51 AB2 8 VC C CO R E[2 ] AE5 2 C 3 93 C 392 C1 3 2 C 145 C 13 3 C1 4 6 R8 0 C 15 0

AD 2 6 VC C CO R E[3 ] V C CA DA C [2 ] 3
* 1u _ 6 . 3 V _ X 5 R _ 0 4
AD 2 8 VC C CO R E[4 ] AF5 3 S HD N #
2 2 u_ 6 . 3 V _ X 5R _ 0 8
1 0 u _6 . 3 V _X 5 R _ 0 6 1u _ 6 . 3 V _ X 5 R _0 4 0 . 0 1 u _ 50 V _X 7 R _ 04 1 0 u _ 6 . 3 V _ X 5R _ 0 6 *2 3 . 7 K _ 1 % _ 0 4
0 .1 u _ 1 6 V _ Y 5 V _ 0 4
22 u _ 6 . 3 V _ X 5 R _ 08
CRT
0 . 1 u _1 6 V _ Y 5V _ 04
AF2 6 VC C CO R E[5 ] V S S A _ DA C [1 ] 4 2
AF2 8 VC C CO R E[6 ] AF5 1 SET GN D
VCC CORE
AF3 0 VC C CO R E[7 ] V S S A _ DA C [2 ]
R8 1 * A P L 5 6 0 3 -33 B
AF3 1 VC C CO R E[8 ]
AH 2 6 VC C CO R E[9 ] *1 0 K _ 1 % _ 0 4
AH 2 8 VC C CO R E[1 0 ] 3 .3 V S _ V C CA _ L V D 3 .3 VS
AH 3 0 VC C CO R E[1 1 ]
AH 3 1 VC C CO R E[1 2 ] A H3 8
APL5603-33B 6-02-56033-4C0
R 86 *1 5 m i _l s h o rt _ 0 6
AJ 3 0 VC C CO R E[1 3 ] V CC A L V D S G9091-330T11UF 6-02-90913-4C0
AJ 3 1 VC C CO R E[1 4 ] A H3 9 C1 5 6
1 .1 V S _ V T T VC C CO R E[1 5 ] V SSA_ L VD S
1 0 u_ 6 . 3 V _ X 5 R _0 6
AP4 3 1 . 8 V S _V C C T X _ LV D 1 .8 VS
V C CT X _ L V D S [1 ] AP4 5 L 11
V C CT X _ L V D S [2 ] AT4 6 H C B 1 6 0 8 K F -1 2 1 T 2 5
V C CT X _ L V D S [3 ]
1. 1V S _ V C C A P L L_ E XP AK2 4 AT4 5 .
LVDS
L29 V C C I O[ 24 ] V C CT X _ L V D S [4 ]
* B K P 1 0 0 5 H S 12 1 _ 0 4 C1 4 0 C1 3 9 C 135 C1 3 4
BJ 2 4
.
C3 7 2
VC C APL L EXP
VC C3 _ 3 [2 ]
AB3 4 0. 01 u _ 5 0 V _ X 7 R _ 0 4 0 . 0 1u _ 5 0 V _ X 7 R _ 0 4 1 0 u _ 6 .3 V _ X5 R_ 0 6 10 u _ 6 . 3 V _ X 5 R _ 0 6 Sheet 20 of 42
AN 2 0 AB3 5
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6 AN 2 2 VC
VC
C
C
I O[
I O[
25 ]
26 ]
VC C3 _ 3 [3 ]
IBEXPEAK - M 7/9
HVCMOS
AN 2 3 A D3 5 3 .3 V S
AN 2 4 VC C I O[ 27 ] VC C3 _ 3 [4 ]
AN 2 6 VC C I O[ 28 ]
AN 2 8 VC C I O[ 29 ]
1 .1 VS _ VT T BJ 2 6 VC C I O[ 30 ] C1 5 9
BJ 2 8 VC C I O[ 31 ]
AT2 6 VC C I O[ 32 ]
0. 1u _ 1 6 V _ Y 5V _ 04
AT2 8 VC C I O[ 33 ]
C3 7 5 C 160 C 1 61 C1 3 6 C 141 AU 2 6 VC C I O[ 34 ]
AU 2 8 VC C I O[ 35 ] 1 . 5 V S _ 1. 8V S
AV2 6 VC C I O[ 36 ]
1 0 u_ 6 . 3 V _ X 5 R _ 06 1 u _ 6 .3 V _ X 5 R_ 0 4 1 u _ 6 . 3 V _ X 5R _ 0 4 1 u_ 6 . 3 V _ X 5 R _ 04 1 u _ 6 .3 V _ X5 R_ 0 4
AV2 8 VC C I O[ 37 ] AT2 4
A W26 VC C I O[ 38 ] V C C V RM [2 ]
A W28 VC C I O[ 39 ]
BA2 6 VC C I O[ 40 ] AT1 6 1 .1 VS _ V T T
DMI
BA2 8 VC C I O[ 41 ] V C C DM I[1 ]
BB2 6 VC C I O[ 42 ] A U1 6
BB2 8 VC C I O[ 43 ] V C C DM I[2 ]
BC 2 6 VC C I O[ 44 ]
C1 2 7
BC 2 8 VC C I O[ 45 ] PCI E*
BD 2 6 VC C I O[ 46 ] 1 u _ 6 .3 V _ X 5 R_ 0 4
BD 2 8 VC C I O[ 47 ]
BE2 6 VC C I O[ 48 ] A M1 6
BE2 8 VC C I O[ 49 ] VC C PN A ND [1 ] AK1 6
BG 2 6 VC C I O[ 50 ] VC C PN A ND [2 ] AK2 0 V _ NV RA M _ V C CQ 1 .8 V S 3 .3 V S
BG 2 8 VC C I O[ 51 ] VC C PN A ND [3 ] AK1 9
BH 2 7 VC C I O[ 52 ] VC C PN A ND [4 ] AK1 5 R7 5 *0 _ 0 4
VC C I O[ 53 ] VC C PN A ND [5 ] AK1 3
AN 3 0 VC C PN A ND [6 ] A M1 2 C1 5 2 R7 6 * 15 m i l _ sh o rt _ 0 6
AN 3 1 V C C I O[ 54 ] VC C PN A ND [7 ] A M1 3
NAND / SPI
1 .5 V S _ 1 .8 V S 3 .3 VS V C C I O[ 55 ] VC C PN A ND [8 ] A M1 5 0. 1u _ 1 6 V _ Y 5V _ 04
VC C PN A ND [9 ]
AN 3 5
1 .1 V S _ V T T 1. 1V S _ V C C A P L L_ F D I V C C 3 _3 [ 1 ]
L 28 AT2 2
* H C B 1 0 0 5 K F -1 2 1 T 2 0 V C C V R M[ 1 ] 3. 3V S 3 .3 V
BJ 1 8 A M8 V C CM E3 .3 V
VC C F D IPL L VC C ME 3 _ 3 [ 1 ] A M9 R 79 * 1 5 m li _ s h o rt _ 06
C3 7 0 AM 2 3 VC C ME 3 _ 3 [ 2 ] AP1 1
FDI
V C C I O[ 1] VC C ME 3 _ 3 [ 3 ] AP9 R 82 * 0_ 0 4
VC C ME 3 _ 3 [ 4 ]
*1 0 u _ 6. 3V _ X5 R _ 0 6
C1 3 8
I b e x P e a k -M _ R e v 0 _ 9 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
1 . 1 V S _ V TT 1 .1 V S _ V C CD P L L _ F D I
R2 5 7 *1 5 m i l _ sh o rt _ 0 6
3 , 4 , 1 2 , 1 4 , 1 5 , 1 6, 18 , 1 9 , 2 1 , 2 3 , 2 4 , 2 5 , 2 9, 30 , 3 1 , 3 3 , 3 4 , 3 5 3 .3 V
2 3 ,3 1 ,3 6 1 .5 VS
2 , 1 3 , 1 7 , 2 1 , 2 6, 27 , 3 0 , 3 1 , 3 5 , 3 6 5 VS
21 1 .5 VS_ 1 .8 VS
7 ,3 3 1 .8 VS
2 , 1 0 , 1 1 , 1 2, 13 , 1 4 , 1 5 , 1 6 , 1 7 , 1 8 , 1 9, 21 , 2 3 , 2 4 , 2 5 , 2 6 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 5 , 3 6 3 .3 VS
2 , 4 , 6 , 7 , 1 4 , 1 5 , 1 6, 19 , 2 1 , 3 4 , 3 5 , 3 6 1 .1 VS_ VT T
1 .5 VS 1 .8 VS 1 . 5 V S _ 1. 8 V S
R 2 58 *1 5 m li _ s h o rt _ 0 6
R 2 54 * 0 _0 4
Schematic Diagrams
IBEXPEAK - M 8/9
Vo lt age R ai l Vol ta ge S0 I ccm ax C urr en t (A )
IBEXPEAK - M (POWER) V_ CP U_I O
V5 RE F
1. 1/ 1. 05
5
< 1 (mA )
< 1 (mA )
V5 RE F_S us 5 < 1 (mA )
L3 2 1 . 1 V S _ V C C A _C LK U2 0 J POWER 1 .1 V S _ V T T
Vc c3 _3 3. 3 0. 35 7
*H C B 1 0 05 K F -1 2 1T 2 0 52mA AP5 1 V2 4
1 . 1 V S _ V TT V CC A CL K [1 ] VC CIO [5 ] Vc cA Clk 1. 05 0. 05 2
V2 6
C3 8 3 C3 8 4 AP5 3 VC CIO [6 ] Y2 4 C1 4 7 Vc cA DAC 3. 3 0. 06 9
V CC A CL K [2 ] VC CIO [7 ] Y2 6
VC CIO [8 ] Vc cA DPL LA 1. 05 0. 06 8
*1 0 u _6 . 3 V _ X5 R _0 6 *0 . 1 u_ 1 6 V _Y 5 V _0 4 1 u_ 6 . 3 V _X 5 R _ 0 4
AF2 3 V2 8 Vc cA DPL LB 1. 05 0. 06 9
V C C LA N [ 1 ] V C C S U S 3_ 3 [ 1 ] U2 8 3 . 3V
320mA AF2 4 V C C S U S 3_ 3 [ 2 ] U2 6
Vc ca pll EX P 1. 05 0. 04 0
1 . 1V S _V T T V C C LA N [ 2 ] V C C S U S 3_ 3 [ 3 ] U2 4
142.6mA
V C C S U S 3_ 3 [ 4 ]
Vc cC ore 1. 05 1. 43 2
C1 4 3 P2 8
T P _ P CH _ V CC DS W Y2 0 V C C S U S 3_ 3 [ 5 ] P2 6 Vc cD MI 1. 05 0. 05 8
C1 8 1
1 u_ 6 . 3 V _X 5 R _ 0 4 DCP S US B Y P V C C S U S 3_ 3 [ 6 ] N2 8
V C C S U S 3_ 3 [ 7 ] N2 6 Vc cD MI 1. 1 0. 06 1
C1 7 2 0 . 1u _ 1 6V _ Y 5V _ 0 4
A D3 8 V C C S U S 3_ 3 [ 8 ] M2 8
V C C ME [ 1 ] V C C S U S 3_ 3 [ 9 ] Vc cF DIP LL 1. 05 0. 03 7
0. 1 u _ 16 V _ Y 5 V _ 0 4 M2 6
A D3 9 V C C S U S 3 _3 [ 1 0 ] L2 8 Vc cI O 1. 05 3. 06 2
V C C ME [ 2 ] V C C S U S 3 _3 [ 1 1 ] L2 6
1849mA Vc cL AN 1. 05 0. 32 0
US B
A D4 1 V C C S U S 3 _3 [ 1 2 ] J2 8
1 . 1V S _V T T V C C ME [ 3 ] V C C S U S 3 _3 [ 1 3 ] J2 6 3 .3 V _ V CC P US B Vc cM E 1. 05 1. 84 9
AF4 3 V C C S U S 3 _3 [ 1 4 ] H2 8
C3 7 3 C1 4 8
V C C ME [ 4 ] V C C S U S 3 _3 [ 1 5 ] H2 6
Vc cM E3_ 3 3. 3 0. 08 5
R1 0 6 *1 5 mi l _ sh o rt _ 06
2 2u _ 6 . 3V _ X 5 R _ 0 8 1u _ 6 . 3V _ X 5 R _ 0 4 AF4 1 V C C S U S 3 _3 [ 1 6 ] G2 8 Vc cp NAN D 1. 8 0. 15 6
V C C ME [ 5 ] V C C S U S 3 _3 [ 1 7 ] G2 6 C1 7 8
AF4 2 V C C S U S 3 _3 [ 1 8 ] F28 Vc cR TC 3. 3 2 (m A)
V C C ME [ 6 ] V C C S U S 3 _3 [ 1 9 ] F26 0 . 1u _ 1 6V _ Y 5V _ 0 4 Vc cS ATA PL L 1. 05 0. 03 1
V3 9 V C C S U S 3 _3 [ 2 0 ] E2 8
V C C ME [ 7 ] V C C S U S 3 _3 [ 2 1 ] E2 6 Vc cS us3 _3 3. 3 0. 16 3
Cl oc k and M is ce ll an eo us
V4 1 V C C S U S 3 _3 [ 2 2 ] C2 8
Sheet 21 of 42 C3 7 4
2 2u _ 6 . 3V _ X 5 R _ 0 8
C1 4 2
1u _ 6 . 3V _ X 5 R _ 0 4 V4 2
V C C ME [ 8 ]
V C C ME [ 9 ]
V C C S U S 3 _3 [ 2 3 ]
V C C S U S 3 _3 [ 2 4 ]
V C C S U S 3 _3 [ 2 5 ]
C2 6
B2 7
A2 8
1. 1 V S _ V T T
Vc cS usH DA
Vc cV RM
3. 3
1. 8/ 1. 5
0. 00 6
0. 19 6
Vc cV RM 1. 05 < 1 (mA )
IBEXPEAK - M 8/9 Y3 9
Y4 1
V C C ME [ 1 0 ]
V C C ME [ 1 1 ]
V C C S U S 3 _3 [ 2 6 ]
V C C S U S 3 _3 [ 2 7 ]
V C C S U S 3 _3 [ 2 8 ]
A2 6
U2 3
5 V _P C H _ V C C 5 R E F S U S
D 11
C
S C D3 4 0
A
3. 3 V
Vc cA LVD S 3. 3 < 1 (mA )
Vc cT X_L VD S 1. 8 0. 05 9
Y4 2 V2 3 R 12 3
V C C ME [ 1 2 ] V C C I O[ 5 6 ] 5V
1 .1 VS_ VT T C1 7 7 0 . 1 u _1 6 V _ Y 5 V _ 04 10 0 _ 1% _ 0 4
L3 1 1. 1 V S _ V C C A _ A _ D P L F24 C1 8 2
H C B 10 0 5 K F -1 21 T 2 0 V 5 RE F _ S US
V CC RT CE X T V9 1 u_ 6 . 3 V _X 5 R _ 0 4 D 10 S C D3 4 0
DCP RT C V CC 5 RE F C A
1 . 5 V S _ 1 . 8V S 3 .3 V S
C 3 86 C 38 1
R 2 62 K4 9 R1 1 6 1 0 0_ 1 % _0 4
A U2 4 V 5 RE F 5V S
2 2 u _6 . 3 V _ X5 R _0 8 1 u _6 . 3 V _ X5 R _0 4 68mA
* 0 _0 4 V C C V R M [ 3] C 1 83
PC I/G PI O/ LP C
L3 0 J3 8
1. 1 V S _ V C C A _ B _ D P L BB5 1 V C C 3_ 3 [ 8 ] 3. 3V S
H C B 10 0 5 K F -1 21 T 2 0 69mA 1 u _ 6. 3 V _ X 5R _ 04
BB5 3 V CC A DP L L A [1 ] L3 8 C1 6 9
V CC A DP L L A [2 ] V C C 3_ 3 [ 9 ]
C 3 85 C 37 8 M3 6 0 . 1u _ 1 6V _ Y 5V _ 0 4
+ C 3 82 B D5 1 V C C 3 _3 [ 1 0 ]
B D5 3 V CC A DP L L B [1 ] N3 6
2 2 u _6 . 3 V _ X5 R _0 8 1 u _6 . 3 V _ X5 R _0 4
*2 20 u _ 4V _ V _ B V CC A DP L L B [2 ] V C C 3 _3 [ 1 1 ]
C 1 54 1u _ 6 . 3V _X 5 R _ 0 4 A H2 3 P3 6
AJ 3 5 V C C I O[ 2 1 ] V C C 3 _3 [ 1 2 ] 3. 3V S
A H3 5 V C C I O[ 2 2 ] U3 5 C1 8 0
V C C I O[ 2 3 ] V C C 3 _3 [ 1 3 ]
C 1 31 1u _ 6 . 3V _X 5 R _ 0 4 AF3 4 0 . 1u _ 1 6V _ Y 5V _ 0 4
V C C I O[ 2 ] A D1 3
VCCIO 3062mA A H3 4 V C C 3 _3 [ 1 4 ]
1 .1 V S _ V T T V C C I O[ 3 ] L3 3
C 1 57 1u _ 6 . 3V _X 5 R _ 0 4 AF3 2 1. 1 V S _ V C C A P L L *H C B 1 00 5 K F -1 2 1T 2 0
V C C I O[ 4 ] AK3
V C CS A T A P L L [1 ] 1 . 1V S _ V T T
V1 2 AK1
DCP S S T V C CS A T A P L L [2 ]
C3 8 8 C3 8 9
C1 7 5 0 . 1 u _1 6 V _ Y 5 V _ 04 V CC S S T
*1 u _ 6. 3 V _ X 5R _ 04 *1 0 u_ 6 . 3 V _X 5 R _ 0 6
C1 7 3 0 . 1 u _1 6 V _ Y 5 V _ 04 1 . 1V _ I N T_ V C C S U S Y2 2
DCP S US A H2 2
V C CIO [9 ]
20.4mA P1 8 A T 20
3 .3 V V C C S U S 3 _ 3[ 2 9 ] V CC V RM [4 ] 1 . 5 V S _ 1 . 8V S
C1 8 8 U1 9
V C C S U S 3 _ 3[ 3 0 ] A H1 9
SATA
PC I/ GP IO/ LP C
0. 1 u _ 16 V _ Y 5 V _ 0 4 U2 0 V C C I O[ 1 0 ]
V C C S U S 3 _ 3[ 3 1 ] A D2 0
U2 2 V C C I O[ 1 1 ]
V C C S U S 3 _ 3[ 3 2 ] AF2 2 1 .1 V S _ V T T
V C C I O[ 1 2 ]
A D1 9
357mA V1 5 V CC I O[ 1 3 ] AF2 0
3 .3 VS V C C 3_ 3 [ 5 ] V CC I O[ 1 4 ] AF1 9 C1 6 7
C1 7 9 V1 6 V CC I O[ 1 5 ] A H2 0
V C C 3_ 3 [ 6 ] V CC I O[ 1 6 ] 1 u_ 6 . 3 V _X 5 R _ 0 4
Y1 6 AB1 9 1 4 RT C V CC
0. 1 u _ 16 V _ Y 5 V _ 0 4
V C C 3_ 3 [ 7 ] V C C I O[ 1 7 ] AB2 0 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 6 , 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 3 6 3 . 3 V S
V C C I O[ 1 8 ] AB2 2 2 0 1 . 5 V S _ 1 . 8V S
V C C I O[ 1 9 ] A D2 2 2 , 13 , 1 7 , 20 , 2 6 , 27 , 3 0 , 31 , 3 5 , 3 6 5 V S
<1mA AT1 8 V C C I O[ 2 0 ] 4, 9 , 1 0 , 11 , 2 3 , 27 , 2 9 , 31 , 3 3 , 3 6 1 . 5 V
1 . 1V S _ V T T V _C P U _ I O [ 1] 24 , 3 0 , 31 , 3 3 , 3 4 5 V
AA3 4
V CCM E [1 3 ] Y3 4 1. 1 V S _ V T T 3 , 4 , 1 2, 14 , 1 5 , 16 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 3 5 3 . 3 V
CP U
C1 4 4 C1 3 7 C1 6 2
A U1 8 V CCM E [1 4 ] Y3 5 2 , 4 , 6, 7 , 1 4 , 15 , 1 6 , 19 , 2 0 , 34 , 3 5 , 3 6 1 . 1 V S _ V T T
V _C P U _ I O [ 2] V CCM E [1 5 ] AA3 5
1u _ 6 . 3V _ X 5 R _ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4
V CCM E [1 6 ] 1. 5 V _ V C C S U S H D A 1 .5 V 3 . 3V
2mA A1 2 L3 0 R1 2 9 *1 5 mi l _ sh o rt _ 06
RT CV C C V CC RT C RT C V C CS U S HDA
C1 8 6 C1 8 7 HD A C1 8 9 R1 3 1 * 0_ 0 4
I b ex P e a k-M _ R e v 0 _9
0 . 1u _ 1 6V _ Y 5V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 1 u _6 . 3 V _ X5 R _0 4
Schematic Diagrams
IBEXPEAK - M 9/9
U 20I
IBEXPEAK - M (GND) AY 7
B1 1
B1 5
V SS
V SS
[ 1 59 ]
[ 1 60 ]
VS
VS
S[ 2 5 9 ]
S[ 2 6 0 ]
H 49
H5
J 24
B1 9 V SS [ 1 61 ] VS S[ 2 6 1 ] K1 1
B2 3 V SS [ 1 62 ] VS S[ 2 6 2 ] K4 3
B3 1 V SS [ 1 63 ] VS S[ 2 6 3 ] K4 7
B3 5 V SS [ 1 64 ] VS S[ 2 6 4 ] K7
B3 9 V SS [ 1 65 ] VS S[ 2 6 5 ] L 14
B4 3 V SS [ 1 66 ] VS S[ 2 6 6 ] L 18
B4 7 V SS [ 1 67 ] VS S[ 2 6 7 ] L2
B7 V SS [ 1 68 ] VS S[ 2 6 8 ] L 22
BG 1 2 V SS [ 1 69 ] VS S[ 2 6 9 ] L 32
U 20H
AB 1 6 B B1 2 V SS [ 1 70 ] VS S[ 2 7 0 ] L 36
VS S[ 0 ] B B1 6 V SS [ 1 71 ] VS S[ 2 7 1 ] L 40
AA 1 9 A K3 0 B B2 0 V SS [ 1 72 ] VS S[ 2 7 2 ] L 52
AA 2 0 VS S[ 1 ] V SS [8 0 ] A K3 1 B B2 4 V SS [ 1 73 ] VS S[ 2 7 3 ] M1 2
A M1 9 VS S[ 3 ] V SS [8 2 ] A K3 4 B B3 4 V SS [ 1 75 ] VS S[ 2 7 5 ] M2 0
AA 2 4 VS S[ 4 ] V SS [8 3 ] A K3 5 B B3 8 V SS [ 1 76 ] VS S[ 2 7 6 ] N 38
AA 3 0 VS S[ 7 ] V SS [8 6 ] A K4 6 B B5 V SS [ 1 79 ] VS S[ 2 7 9 ] M4 2
AA 3 1 VS S[ 8 ] V SS [8 7 ] A K4 9 BC 1 0 V SS [ 1 80 ] VS S[ 2 8 0 ] M4 6
AA 3 2 VS S[ 9 ] V SS [8 8 ] A K5 BC 1 4 V SS [ 1 81 ] VS S[ 2 8 1 ] M4 9
AB 1 1 VS S[ 1 0 ] V SS [8 9 ] A K8 BC 1 8 V SS [ 1 82 ] VS S[ 2 8 2 ] M5
AB 1 5 VS S[ 1 1 ] V SS [9 0 ] A L2 BC 2 V SS [ 1 83 ] VS S[ 2 8 3 ] M8
AB 2 3 VS S[ 1 2 ] V SS [9 1 ] A L 52 BC 2 2 V SS [ 1 84 ] VS S[ 2 8 4 ] N 24
AB 3 0 VS S[ 1 3 ] V SS [9 2 ] A M1 1 BC 3 2 V SS [ 1 85 ] VS S[ 2 8 5 ] P1 1
AB 3 1 VS S[ 1 4 ] V SS [9 3 ] B B4 4 BC 3 6 V SS [ 1 86 ] VS S[ 2 8 6 ] AD 1 5
AB 3 2 VS S[ 1 5 ] V SS [9 4 ] A D 24 BC 4 0 V SS [ 1 87 ] VS S[ 2 8 7 ] P2 2
AB 4 7 VS S[ 1 8 ] V SS [9 7 ] A M2 4 BH 9 V SS [ 1 90 ] VS S[ 2 9 0 ] P3 4
AB 5
AB 8
VS
VS
VS
S[ 1 9 ]
S[ 2 0 ]
S[ 2 1 ]
V SS [9 8 ]
V SS [9 9 ]
V SS [1 0 0 ]
A
A
M2 6
M2 8
BD 4 8
BD 4 9
V SS
V SS
V SS
[ 1 91 ]
[ 1 92 ]
[ 1 93 ]
VS
VS
VS
S[ 2 9 1 ]
S[ 2 9 2 ]
S[ 2 9 3 ]
P4 2
P4 5
Sheet 22 of 42
AC2 B A4 2 BD 5 P4 7
A C 52
A D 11
A D 12
VS
VS
VS
S[ 2 2 ]
S[ 2 3 ]
S[ 2 4 ]
V SS [1 0 1 ]
V SS [1 0 2 ]
V SS [1 0 3 ]
A
A
A
M3 0
M3 1
M3 2
B E1 2
B E1 6
B E2 0
V SS
V SS
V SS
[ 1 94 ]
[ 1 95 ]
[ 1 96 ]
VS
VS
VS
S[ 2 9 4 ]
S[ 2 9 5 ]
S[ 2 9 6 ]
R2
R 52
T12
IBEXPEAK - M 9/9
A D 16 VS S[ 2 5 ] V SS [1 0 4 ] A M3 4 B E2 4 V SS [ 1 97 ] VS S[ 2 9 7 ] T41
A D 34 VS S[ 3 0 ] V SS [1 0 9 ] A U 20 B E4 6 V SS [ 2 02 ] VS S[ 3 0 2 ] U 30
A U 22 VS S[ 3 1 ] V SS [1 1 0 ] A M4 6 B E4 8 V SS [ 2 03 ] VS S[ 3 0 3 ] U 31
A D 42 VS S[ 3 2 ] V SS [1 1 1 ] A V2 2 B E5 0 V SS [ 2 04 ] VS S[ 3 0 4 ] U 32
A D 46 VS S[ 3 3 ] V SS [1 1 2 ] A M4 9 B E6 V SS [ 2 05 ] VS S[ 3 0 5 ] U 34
A D 49 VS S[ 3 4 ] V SS [1 1 3 ] A M7 B E8 V SS [ 2 06 ] VS S[ 3 0 6 ] P3 8
AD7 VS S[ 3 5 ] V SS [1 1 4 ] A A5 0 B F3 V SS [ 2 07 ] VS S[ 3 0 7 ] V1 1
AE 2 VS S[ 3 6 ] V SS [1 1 5 ] B B1 0 B F4 9 V SS [ 2 08 ] VS S[ 3 0 8 ] P1 6
AE 4 VS S[ 3 7 ] V SS [1 1 6 ] A N 32 B F5 1 V SS [ 2 09 ] VS S[ 3 0 9 ] V1 9
AF 1 2 VS S[ 3 8 ] V SS [1 1 7 ] A N 50 BG 1 8 V SS [ 2 10 ] VS S[ 3 1 0 ] V2 0
Y 13 VS S[ 3 9 ] V SS [1 1 8 ] A N 52 BG 2 4 V SS [ 2 11 ] VS S[ 3 1 1 ] V2 2
A H 49 VS S[ 4 0 ] V SS [1 1 9 ] A P1 2 BG 4 V SS [ 2 12 ] VS S[ 3 1 2 ] V3 0
AU4 VS S[ 4 1 ] V SS [1 2 0 ] A P4 2 BG 5 0 V SS [ 2 13 ] VS S[ 3 1 3 ] V3 1
AF 3 5 VS S[ 4 2 ] V SS [1 2 1 ] A P4 6 BH 1 1 V SS [ 2 14 ] VS S[ 3 1 4 ] V3 2
AP 1 3 VS S[ 4 3 ] V SS [1 2 2 ] A P4 9 BH 1 5 V SS [ 2 15 ] VS S[ 3 1 5 ] V3 4
A N 34 VS S[ 4 4 ] V SS [1 2 3 ] A P5 BH 1 9 V SS [ 2 16 ] VS S[ 3 1 6 ] V3 5
AF 4 5 VS S[ 4 5 ] V SS [1 2 4 ] A P8 BH 2 3 V SS [ 2 17 ] VS S[ 3 1 7 ] V3 8
AF 4 6 VS S[ 4 6 ] V SS [1 2 5 ] A R2 BH 3 1 V SS [ 2 18 ] VS S[ 3 1 8 ] V4 3
AF 4 9 VS S[ 4 7 ] V SS [1 2 6 ] A R 52 BH 3 5 V SS [ 2 19 ] VS S[ 3 1 9 ] V4 5
AF 5 VS S[ 4 8 ] V SS [1 2 7 ] A T11 BH 3 9 V SS [ 2 20 ] VS S[ 3 2 0 ] V4 6
AF 8 VS S[ 4 9 ] V SS [1 2 8 ] B A1 2 BH 4 3 V SS [ 2 21 ] VS S[ 3 2 1 ] V4 7
A G2 VS S[ 5 0 ] V SS [1 2 9 ] A H 48 BH 4 7 V SS [ 2 22 ] VS S[ 3 2 2 ] V4 9
A G52 VS S[ 5 1 ] V SS [1 3 0 ] A T32 BH 7 V SS [ 2 23 ] VS S[ 3 2 3 ] V5
A H 11 VS S[ 5 2 ] V SS [1 3 1 ] A T36 C 12 V SS [ 2 24 ] VS S[ 3 2 4 ] V7
A H 15 VS S[ 5 3 ] V SS [1 3 2 ] A T41 C 50 V SS [ 2 25 ] VS S[ 3 2 5 ] V8
A H 16 VS S[ 5 4 ] V SS [1 3 3 ] A T47 D 51 V SS [ 2 26 ] VS S[ 3 2 6 ] W2
A H 24 VS S[ 5 5 ] V SS [1 3 4 ] A T7 E1 2 V SS [ 2 27 ] VS S[ 3 2 7 ] W 52
A H 32 VS S[ 5 6 ] V SS [1 3 5 ] A V1 2 E1 6 V SS [ 2 28 ] VS S[ 3 2 8 ] Y 11
AV 1 8 VS S[ 5 7 ] V SS [1 3 6 ] A V1 6 E2 0 V SS [ 2 29 ] VS S[ 3 2 9 ] Y 12
AH7 VS S[ 6 0 ] V SS [1 3 9 ] A V3 0 E3 4 V SS [ 2 32 ] VS S[ 3 3 2 ] Y 23
A J 19 VS S[ 6 1 ] V SS [1 4 0 ] A V3 4 E3 8 V SS [ 2 33 ] VS S[ 3 3 3 ] Y 28
A J2 VS S[ 6 2 ] V SS [1 4 1 ] A V3 8 E4 2 V SS [ 2 34 ] VS S[ 3 3 4 ] Y 30
A J 23 VS S[ 6 5 ] V SS [1 4 4 ] A V4 9 E6 V SS [ 2 37 ] VS S[ 3 3 7 ] Y 38
A J 26 VS S[ 6 6 ] V SS [1 4 5 ] A V5 E8 V SS [ 2 38 ] VS S[ 3 3 8 ] Y 43
A J 28 VS S[ 6 7 ] V SS [1 4 6 ] A V8 F4 9 V SS [ 2 39 ] VS S[ 3 3 9 ] Y 46
A J 32 VS S[ 6 8 ] V SS [1 4 7 ] A W 14 F5 V SS [ 2 40 ] VS S[ 3 4 0 ] P4 9
A J 34 VS S[ 6 9 ] V SS [1 4 8 ] A W 18 G10 V SS [ 2 41 ] VS S[ 3 4 1 ] Y5
A T5 VS S[ 7 0 ] V SS [1 4 9 ] A W2 G14 V SS [ 2 42 ] VS S[ 3 4 2 ] Y6
A J4 VS S[ 7 1 ] V SS [1 5 0 ] B F9 G18 V SS [ 2 43 ] VS S[ 3 4 3 ] Y8
AK 1 2 VS S[ 7 2 ] V SS [1 5 1 ] A W 32 G2 V SS [ 2 44 ] VS S[ 3 4 4 ] P2 4
A M4 1 VS S[ 7 3 ] V SS [1 5 2 ] A W 36 G22 V SS [ 2 45 ] VS S[ 3 4 5 ] T43
A N 19 VS S[ 7 4 ] V SS [1 5 3 ] A W 40 G32 V SS [ 2 46 ] VS S[ 3 4 6 ] AD 5 1
AK 2 6 VS S[ 7 5 ] V SS [1 5 4 ] A W 52 G36 V SS [ 2 47 ] VS S[ 3 4 7 ] AT8
AK 2 2 VS S[ 7 6 ] V SS [1 5 5 ] A Y 11 G40 V SS [ 2 48 ] VS S[ 3 4 8 ] AD 4 7
AK 2 3 VS S[ 7 7 ] V SS [1 5 6 ] A Y 43 G44 V SS [ 2 49 ] VS S[ 3 4 9 ] Y 47
AK 2 8 VS S[ 7 8 ] V SS [1 5 7 ] A Y 47 G52 V SS [ 2 50 ] VS S[ 3 5 0 ] AT1 2
VS S[ 7 9 ] V SS [1 5 8 ] A F3 9 V SS [ 2 51 ] VS S[ 3 5 1 ] AM6
I be x P e a k -M _ R e v 0 _ 9 H 16 V SS [ 2 52 ] VS S[ 3 5 2 ] AT1 3
H 20 V SS [ 2 53 ] VS S[ 3 5 3 ] AM5
H 30 V SS [ 2 54 ] VS S[ 3 5 4 ] AK 4 5
H 34 V SS [ 2 55 ] VS S[ 3 5 5 ] AK 3 9
H 38 V SS [ 2 56 ] VS S[ 3 5 6 ] AV 1 4
H 42 V SS [ 2 57 ] VS S[ 3 6 6 ]
V SS [ 2 58 ]
I b e x Pe a k - M_ R e v 0 _ 9
Schematic Diagrams
New Card, Mini PCIE

3 .3 V
C 45 9 *0 . 1 u_ 1 6 V _Y 5 V _0 4 3 .3 V
NEW CARD(Port 8)
5
B U F _ P L T _R S T # 1 U2 6
4 *M C 7 4V H C 1 G 08 D F T1 G
2 R 3 36 R 33 8 C2 1 0 C 2 24 C2 2 0
* 1 00 K _ 1 %_ 0 4 * 10 0 K _ 1% _ 0 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4 * 0 . 1u _ 1 0V _ X 7 R _ 0 4 *0 . 1 u_ 1 0 V _X 7 R _ 0 4
3
1 . 5 V S 3. 3 V S 3 .3 V
U 25 J _ NE W 1
17 8 N C_ RS T # N C_ P E RS T # 13
A U XI N PER ST# P E R S T#
15 N C _ 3 . 3V A U X 36mils 12
A U X OU T + 3. 3 V A U X
2 3 N C _ 3 . 3V 48mils 14
3 .3 V IN 3 . 3 V OU T 15 + 3. 3 V
+ 3. 3 V
1 . 5 V OU T
11 N C _ 1 . 5V 48mils 10
+ 1. 5 V
9
12 + 1. 5 V
1 .5 V IN 10 N C _C P P E # 17
CP P E # 9 N C _C P U S B # 4 CP P E #
CP US B # P CIE _ W A K E # 11 CP U S B #
6 1 6 , 25 P C I E _ W A K E # 16 W AKE#
4 , 1 8 , 25 , 2 8 B U F _ P L T _R S T # 19 S Y S RS T # 1 5 N E W C A R D _ C L K R E Q# C L K R E Q#
1 8 U S B _ OC# 2 3 3 .3 VS R 1 70 1 0 K _ 04
OC # 19
1 1 5 C L K _ P C I E _N E W _ C A R D 18 RE F CL K +
1 6 , 2 8, 3 1 S US B # STBY# 1 5 CL K _ P CIE _ N E W _ CA R D# RE F CL K -
R3 4 7 1 0 K _0 4
3. 3 V 4 18 22
N C _ R C L K E N R 3 39 *1 0 K _ 04
5 NC R CL K E N 20 N C _ S H D N # R 3 55 *1 0 K _ 04 3 . 3V 15 P CIE _ RX P2 _ NE W _ CA RD 21 PETp 0
15 P C I E _ R X N2 _ N E W _C A R D
Sheet 23 of 42 1 .5 V S 3 .3 VS 3 . 3V
13
14
16
NC
NC
NC
S H DN #
G ND
7
21
15
15
P C I E _ T X P 2_ N E W _ C A R D
P CIE _ T X N2 _ NE W _ CA R D
25
24
PETn 0
P E R p0
P E R n0
R ESER VED
R ESER VED
5
6
NC G ND 3
New Card, Mini PCIE C4 4 3 C4 6 4 C 45 1

* W 8 3L 3 5 1Y G Port 3 1 8 U SB_ PP3
1 8 U S B _ P N3
2 U S B _D +
U S B _D -
GN D
1
20
6-02-83351-9Q0 GN D
GN D
23
*0 . 1 u _1 6 V _ Y 5 V _ 04 *0 . 1 u_ 1 6 V _ Y 5 V _ 04 *0 . 1 u _1 6 V _ Y 5 V _ 0 4 8 26
1 5 S M L0 _ D A T A 7 S MB _D A T A GN D G ND 1
E NE P 223 1 pi n3 ,4, 15 ,2 2 1 5 S M L0 _ C L K S MB _C LK G ND1 G ND 2
h as i nte rn al ly G ND2
* 13 0 8 01 -0 2
p ul le d h ig h (1 70K oh m)
MINI CARD (WLAN,Port 5)

La you t Sh ow "WLAN(Wima x, 802.11N)" No te
20 mil 3 .3 V
J _ MI N I 1 W LA N 1 . 5V 1. 5 V
PC IE_ W AKE# 1 2
3 W AKE# 3 . 3V A U X _0 6 20 mil R3 2 5 *1 5 mi l _s h o rt _ 06
R3 1 2 1 0K _0 4 5 CO E X 1 1 . 5 V _0 8
3 . 3V S CO E X 2 UIM _ P W R 10 P C H_ B T _ E N#
R3 9 7 0_ 0 4 C4 3 8
7 U I M_ DA T A 12
1 5 W L A N _C L K R E Q # 11 C L K R E Q# U I M_ CL K 14
1 5 C L K _P C I E _ MI N I # *0 . 1 u _1 6 V _ Y 5 V _ 04
13 RE F CL K - U I M_ R E S E T 16
1 5 C L K _P C I E _ MI N I 9 RE F CL K + U I M_ V P P
15 GN D 0 4
GN D 1 G ND5
KEY
21 18
27 GN D 2 G ND6 26
29 GN D 3 G ND7 34 R 32 6
GN D 4 G ND8 40 3. 3V S
* 10 K _ 0 4
35 G ND9 50
28 W L A N _ D E T# 23 GN D 1 1 G N D 10
15 P C I E _ R X N 3 _ W L A N 25 PETn 0 20
1 5 P C I E _R XP 3_ W L A N 31 PETp 0 W _ D I S A B LE # 22 W L A N _E N 2 8, 2 9
B U F _P LT _ R S T #
1 5 P C I E _T X N 3 _ W L A N 33 P E R n0 P E R S E T# 30
1 5 P C I E _ T XP 3_ W L A N P E R p0 S MB _ CL K 32
17 S MB _ DA T A 36 B T _ DE T # 28 , 2 9
28 3 IN1
R 36 2 * 0_ 0 4
28 8 0 DE T # 19
37
R e s e rv e d0
R e s e rv e d1
GN D 1 2
U S B _ D-
US B_ D+
38
20 mil
U S B _P N 2 1 8
U S B _P P 2 1 8 Port 2
39 24 3 .3 V A UX _ 1 R 32 9 * 15 m li _ s ho rt _ 0 6
3. 3 V 3 . 3V A U X _ 3 3 . 3V A U X _1 3 .3 V
R 35 9 0 _ 04 41 28
2 8 , 29 B T_ E N 43 3 . 3V A U X _ 4 1 . 5 V _1 48
GN D 1 3 1 . 5 V _2
40 mil W LA N1 . 5 V
M INI_ CL K 1 45 52
M INI_ DA T A 1 47 R e s e rv e d2 3 . 3V A U X _2 42 3 . 3V
M INI_ RS T # 1 49 R e s e rv e d3 LE D _ W W A N # 44
20 mil
51 R e s e rv e d4 L E D_ W L A N# 46 W L A N _ L E D # 2 8 , 29
R 31 5 * 0_ 0 4
V D D3 R e s e rv e d5 LE D _ W P A N # 8 0 CL K 28
8 8 91 0 -5 20 4 M-0 1
R 39 6 0 _ 04
15 , 2 9 P C H _B T _ E N #
4 , 9, 1 0 , 1 1, 2 1 , 2 7, 2 9 , 3 1, 33 , 3 6 1. 5 V
2 0, 31 , 3 6 1. 5 V S
3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9 , 20 , 2 1 , 2 4, 2 5 , 2 9, 3 0 , 3 1, 3 3 , 3 4, 3 5 3 .3 V
2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 24 , 2 5 , 2 6, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 5, 3 6 3 .3 VS
1 4 , 2 5, 2 8 , 2 9, 3 1 , 3 2, 3 7 V D D3
B - 24 New Card, Mini PCIE

Schematic Diagrams
3G, CCD, TPM

MINI CARD 3G(Port 6) 3G POWER
G5243A 6-02-05243-9C0
Layo ut Sho w "3.5G(HSDPA) " Not e APL3512A 6-02-03512-9C0
3 G_ 3. 3 V 3 . 3V 3 G_ 3 . 3V
3A 120mils U 12 3A 120mils
J _ 3G 1 5 1
6 0mi ls VIN V OU T
1 2
3 W AKE# 3. 3 V A U X_ 0 6 2
5 CO E X 1 1. 5V _ 0 8 U I M_ P W R G ND
CO E X 2 U I M_ P W R 10 U I M_ D A T A 4 3
C 1 90 R1 76 * 15 m il _ s ho rt _ 0 6 R1 7 3 C2 3 1
7 UI M _D A T A 12 U I M_ C L K C 1 93 + C2 34 C2 4 1 SS EN
11 CL K R E Q# UIM _ CL K 14 U I M_ R S T A P L3 5 12 A *1 0 0K _1 % _0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4
13 RE F C L K - UI M _R E S E T 16 U I M_ V P P 0. 1 u _ 16 V _ Y 5 V _ 04 0. 1 u _1 6 V _ Y 5 V _ 04 22 0 u_ 4 V _ V _B 1 0u _ 6. 3 V _ X 5R _0 6 C 2 30
9 RE F C L K + UIM _ V PP
15 GN D 0 4 *0 . 01 u _ 50 V _ X7 R _0 4
GN D 1 GN D5
KEY
21 18
27 GN D 2 GN D6 26
29 GN D 3 GN D7 34 2 8 3 G _P O W E R
GN D 4 GN D8 40
35 GN D9 50
28 3 G_ D E T# GN D 1 1 GN D 1 0 F ro m SB G PIO Pin de fa u lt HI
23
25 PET n 0 20 Po w er P la ne : Su sp en d
31 PET p 0 W _ DIS AB L E# 22 3 G_ E N 28
L19
33 P E R n0 P E RS E T # 30 S3: De fi n ed
*W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt
P E R p0 S M B_ CL K 32 3 4
US B _ P N9 18
3 G_ 3 . 3V 17 S M B _D A T A 36
19 Re s e rv ed 0 U S B _D - 38 2 1
Re s e rv ed 1 U S B _ D+ US B _ P P 9 18
37
39 GN D 1 2 24
C 2 13 C4 14
41
43
45
3 . 3V A UX _3
3 . 3V A UX _4
GN D 1 3
3. 3 V A U X_ 1
1. 5V _ 1
1. 5V _ 2
28
48
52
R 16 0 *1 5 mi l _ sh o rt _0 6
6 0mi ls
3 G_ 3 . 3V
SIM CONN Sheet 24 of 42

3G, CCD, TPM
47 Re s e rv ed 2 3. 3 V A U X_ 2 42 3 G_ 3 . 3 V
0. 1 u _ 16 V _ Y 5 V _ 04 10 u _6 . 3 V _ X5 R _0 6
49 Re s e rv ed 3 L E D _W W A N# 44 R 14 0 4. 7 K _ 0 4
51 Re s e rv ed 4 L E D _ W L A N# 46 C4 1 5
Re s e rv ed 5 L E D _W P A N# +C 19 8
8 8 91 0 -5 20 4 M-0 1 *0 . 1 u _1 6 V _Y 5 V _0 4
2 2 0u _ 4 V _V _ B J_ S I M 1
R 32 2 LOCK R 31 0
* 10 m il _ s ho rt _ 0 4 (TOP VIEW) * 10 m i l_ s ho rt _ 0 4
U I M_ C L K C3 C 7 U I M_ D A T A
U I M_ RS T C2 U I M_ CL K U I M_ DA T A C 6 U I M_ V P P
U I M_ P W R C1 U I M_ RS T U I M_ V P P C 5
C 42 4 U I M_ P W R U I M_ GN D
C 4 04 C 40 3 C4 0 5
2 2 p_ 5 0 V _N P O_ 0 4 OPEN
C 1 77 0 6 61 -1 2 2 p _5 0 V _N P O_ 0 4 2 2 p _5 0 V _N P O_ 0 4 22 p _ 50 V _ N P O _0 4
S I ML OC K
3 .3 V S
TPM 1.2
A sse rte d bef ore e nte rin g S3
* 0. 1 u _ 16 V _ Y 5 V _0 4
*0 . 1 u_ 1 6 V _Y 5 V _ 0 4
*0 . 1u _ 1 6V _ Y 5 V _ 04
L PC r es et timing :
L PCPD# ina ct ive t o L RST# in act ive 3 2~96 us [PV T- 1 ] CCD
U 14 5V Q4 5 V_ CC D
26 10 C 27 2 MT P 3 4 03 N 3
1 4, 2 8 L PC_ AD 0 23 L A D0 V DD1 19 S D 48 mil
L1 * 15 m il _ s ho rt _ 0 6
1 4, 2 8 L PC_ AD 1 20 L A D1 V DD2 24 *1 u _ 6. 3 V _ X 5R _0 4
C 27 7
C2 8 0
C 2 56
1 4, 2 8 L PC_ AD 2 17 L A D2 V DD3
1 4, 2 8 L PC_ AD 3 L A D3 MJ_CCD1
C 3 C2 R9 C5 C8 C9
G
21 1
18 P C LK _T P M L CL K TPM
3 .3 VS 1 u _6 . 3 V _ X5 R _ 0 4 1 00 K _ 1 %_ 0 4 1 u _6 . 3 V _X 5 R _ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 1 u_ 6 . 3 V _X 5 R_ 0 4
22 5 0 . 1 u _1 6 V _ Y 5 V _0 4
1 4 , 28 L P C _ F R A ME # 16 L F RA M E # VSB R8 5
18 P L T _R S T # 27 L R E S E T#
1 4 , 28 S E R I RQ C 25 5
15 S E R IRQ 1 00 K _ 1% _ 0 4
16 P M _C L K R U N # C LK R U N #
* 0. 1 u _1 6 V _ Y 5 V _ 04 J _C C D1
R 19 9 * 0_ 0 4 T P M_ L P C P D # 28 6 T P M 30 0 4 R7 3 3 0K _ 0 4
1 6 S 4 _ S T A TE # L P CP D # G PIO 2 T P M 30 0 5 1
G P I O2 18 US B _ P N 5 2
D
T P M_ B A D D 9
T E ST B I/B A DD 18 US B _P P 5 3
13 XTALI Q5 CC D _D E T #
TP M _ P P 7 X TA L I CC D _ E N G 2 8 C CD _D E T # 4
28 C C D_ E N MT N7 0 02 Z H S 3
PP X4 5
14 XTALO 4 1
S
* MC -14 6 _ 32 . 7 68 K H z 8 52 0 5-0 5 0 01
HI: ACCESS TP M 30 0 1 1 XTAL O 3 2
6-22-32R76-0B4 From H8 default HI
TP M 30 0 2 3 N C_ 1 4
T PM _PP C2 4 4 C 2 50
L OW: NORMAL ( Int ernal PD) TP M 30 0 3 12 N C_ 2 G ND _1 11
N C_ 3 G ND _2 18 *1 8p _ 5 0V _ N P O _ 04 * 1 8p _ 50 V _ N P O _ 04
HI: 4E/ 4F H
8 G ND _3 25
T PM _BADD L OW: 2E/ 2F H T EST I G ND _4
* S L B 96 3 5 TT
3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9, 2 0 , 2 1, 2 3 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 3 4 , 35 3 . 3 V
X TA L O
P C LK _ T P M 2 , 1 0, 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1, 2 3 , 2 5, 2 6 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 36 3 . 3 V S
R1 8 6 *3 3 _0 4 C 26 6 * 10 p _ 50 V _ N P O _0 6 2 1, 3 0 , 3 1, 3 3 , 34 5 V
X TA L I Co-layout X4, X9
3 . 3V S
1 4 X9
T P M _L P C P D # R2 0 0 *1 0 K _0 4 2 3
*1 T J S 12 5 D J 4 A 4 20 P _ 32 . 7 6 8K H z
T P M _P P R1 9 0 *1 0 K _0 4
6-22-32R76-0B2
T P M _B A D D R1 8 8 *1 0 K _1 % _ 04 6-22-32R76-0BG
R1 8 5 *1 0 K _1 % _ 04
3G, CCD, TPM B - 25

Schematic Diagrams
Card Reader/LAN JMB251C

S D _C L K
JMC251C C2 7 0 near Pin#41

S wi tc hi ng R eg ul at or
c lo se t o PI N3 3
3 .3 V _ L A N
*1 0 p _5 0 V _ N P O _ 06 D VDD R 31 7 * 4 . 7K _0 4
3 .3 V S S D_ CL K R1 8 7 2 2 _ 1 %_ 0 4 L3 5 U2 1
(> 20 mi l)
R E GL X . D V DD L A N _S C L R 31 8 * 4 . 7K _0 4 8 7
R3 1 4 * 4 . 7K _0 4 S D _ C D # VC C W P
(> 20 mi l)
S D X C _ P OW E R S W F 2 5 20 C F -4 R 7 M-M C4 5 0 C 45 7 6
V C C_ C A RD L A N _S D A 5 SC L 1
SD XC_ PO W ER
C2 7 1 10 u _ 6. 3V _ X 5 R _ 0 6 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 SD A A0 2
L A N _ LE D 0
L A N_ L ED 1
Fo r JM C2 51 /2 61 o nl y A1
3. 3V _ L A N
C 276 Pin#33 Pin#33 4 3
M DIO 1 1
G ND A2
SD _ BS
R E GL X
SD_ D 3
S D_ D2
S D _D 1
R 31 1 1 0K _0 4 S D_ W P 0 . 1u _ 1 6 V _Y 5 V _ 04 VDD 3 3 .3 V
SD_ D0
D VDD
2 . 2 u _ 6. 3 V _ X 5 R _ 0 6
I S ON
R 31 3 *1 0 K _ 0 4 M S _ INS # * A T 24 C 02 B N
V DD3 3 .3 V
Card Reader Pull High/Low R 3 48 R 3 58
Resistors * 1 5m i l _s h o rt _ 06 * 0 _0 6
47
45
44
43
42
41
40
38
36
34
33
48
46
39
37
35
U 13 U 27
R 1 77 R 3 54 DV DD 5 1 3. 3 V S V D D 3
M D IO1 1
L AN_ L ED 0
IS O N
GN D
G ND
O UT IN
LA N _ LE D 1
M D I O5
M DIO 4
M D I O3
M DIO 2
M D I O1
M DIO 0
FB1 2
V D DIO
VDD O
LX
* 1 5m i l _s h o rt _ 06 * 0_ 0 6
R 2 01 C 4 69
3
(> 20 mi l) S HD N#
M DIO 1 0 49 32 * 2 K _ 1% _ 0 4 M PD R3 2 0 1 0 0 K _ 1% _ 0 4
1 u _ 6. 3 V _ X 5 R _0 4
M DIO 9 50 MD I O1 0 V DD RE G 31 4 2
MD I O9 VC C3 V 3 .3 V S (> 20 mi l) SET G ND
M DIO 8 51 30 R3 2 1 * 4 . 7 K _0 4
52 MD I O8 P W RC R 29 VC C_ CAR D
R3 5 1 *1 5 m il _ s ho rt _ 0 6 A V D D 12 _ 5 2 R 1 98 *G 91 4 1
DV D D 53 V DD TEST 28 MP D
26 L A N_ M DIP 0 V IP_ 1 MP D
54 27 * 1 0K _1 % _ 04 C2 3 9 0 . 1 u _ 16 V _ Y 5V _ 0 4
26 L A N_ M DIN 0 A V D D 12 _ 5 5 55 V I N _1 W AKE N 26 LA N _ S C L L A N_ P C IE _ W A K E # 2 8
DV D D R3 5 0 *1 5 m il _ s ho rt _ 0 6
56 A VD D1 2 LA N _ L E D 2 25 LA N _ S D A G9141
26
26
L A N_ M DIP 1
L A N_ M DIN 1
57
58
V IP_ 2
V I N _2 JMC251 C C R _ LE D
R STN
24
23 B U F _P L T _ R S T # 4 , 1 8, 2 3 , 2 8 APL5603-12B(no R201,R198)
59 GN D CP P E N 22
Sheet 25 of 42 R3 4 9
26
26
3 . 3 V _ LA N
L A N_ M DIP 2
L A N_ M DIN 2
*1 5 m il _ s ho rt _ 0 6
L A N _ MD I P 2
L A N _ MD I N 2
A V D D 12 _ 6 2
60
61
62
A VD D3 3
V IP_ 3
V I N _3
(LQFP 64)
GN D
V DDI O
MD I O6
21
20
19
SD_ W P
M D I O 12
3 . 3 V _L A N
( >2 0m il )
V D D3
(> 20 mi l)
3. 3 V S
DV D D
Card Reader/LAN 26
26
L A N_ M DIP 3
L A N_ M DIN 3
L A N _ MD I P 3
L A N _ MD I N 3
63
64
A VD D1 2
V IP_ 4
V I N _4
MD I O1 2
MD I O1 4
C R_ CD 0 N
18
17
MD I O1 4
SD_ C D# C4 5 3 C 2 33 C 42 5 C2 3 7
C R_ CD 1 N
A V D D 33
AV D D1 2
A V D D 12
M DIO 1 3
1 0u _ 6 . 3 V _X 5 R _ 0 6 0 . 1 u _1 6 V _ Y 5 V _ 0 4 1 0 u _6 . 3 V _ X 5R _ 06 0. 1u _ 1 6V _Y 5 V _0 4
JMB251C
MD I O 7
RE X T
X OU T
C LK N
Pin#32 Pin#32 Pin#31 Pin#31
CL KP
R XN
GN D
TX N
RX P
TXP
3 . 3V _L A N 3. 3 V
X IN
J MC 25 1 _ C P CI e Di ff er en ti al R 35 7 *0 _ 0 6
10
12
14
16
1
2
3
4
5
6
7
*1 5 mi l _ sh o rt _ 0 6 8
9
11
13
15
P ai rs = 1 00 O hm V DD 3
A V D D 1 2 _ 13
L A N X OU T
A V D D 1 2_ 7
I S ON 3. 3V _ L A N
MS _I N S #
R 34 4 1 00 K _ 1 % _0 4
L A N X IN
28 I S ON
MD I O 1 3
M DIO 7
R 19 2 *1 0 0 K _ 1% _ 0 4
R 20 2 R3 1 9 10 K _ 0 4
1 2 K _ 1% _ 0 4 D1 9
P C IE _ W A K E # A C LA N _ P C I E _W A K E #
1 6, 2 3 P C I E _ W A K E # LA N _ P C I E _W A K E # 2 8
R 33 7
D V D D R 3 28
*1 5 m li _ s ho rt _ 0 6
A V D D 1 2_ 7 A V D D 1 2 _ 13
S CD 3 4 0
3 . 3 V _ LA N
DVD D
C 44 9 C4 4 4
4 IN 1 SOCKET SD/MMC/MS/MS Pro
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 0. 1 u _ 16 V _ Y 5V _0 4 C 23 5 0 . 1u _ 1 0 V _X 7 R _ 0 4
P C I E _ R X P 4 _ GL A N 15
Pin#7 Pin#13 C 23 6 0 . 1u _ 1 0 V _X 7 R _ 0 4
P C I E _ R XN 4 _G L A N 1 5 J _C A R D -R E V 1
SD _C D # P1
SD _D 2 P2 CD_ S D
A V D D 1 2_ 5 2 A V D D 1 2 _ 55 A V D D 1 2_ 6 2 A V D D 12 _ 7 SD _D 3 P3 D A T 2 _S D
P C I E _ T X N 4 _ GL A N 15 Card Reader SD _B S P4 C D / D A T 3 _S D
P C I E _ TX P 4 _ GL A N 1 5 P5 C MD _ S D
C L K _ P C I E _ G LA N 1 5 Power P6 VSS_ SD
C 28 6 C2 8 7 C 28 9 C4 4 7 C LK _ P C I E _ GL A N # 15 V C C_ CA RD V C C_ C A RD S D _C L K P7 V D D _S D
C4 2 0 P8 CL K _ S D
S D _D 0 P9 VSS_ SD
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 0. 1 u _ 16 V _ Y 5V _0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 *1 0 u _6 . 3 V _ X 5 R _ 0 6
Pin#52 Pin#55 Pin#62 Pin#7 0 . 1u _ 1 6V _Y 5 V _ 04 S D _D 1 P 10 D A T 0 _S D
S D _W P P 11 D A T 1 _S D
Reserved
L A NX O UT R 31 6 P 12 W P_ SD
P 13 V S S _ MS
Fo r JM C2 51 C 7 5 _1 % _ 0 4
V C C_ C A RD SD _C L K P 14 V C C _M S
3 . 3 V _L A N P 15 S C L K _ MS
R 18 4 *1 M _0 4 LA N X I N C4 1 3 SD _D 3
MS _I N S # P 16 D A T 3 _M S
3 . 3 V _ LA N P 17 I N S _ MS
X5 0 . 1u _ 1 6V _Y 5 V _ 04 SD _D 2
2 1 SD _D 0 P 18 D A T 2 _M S
C 28 8 C4 6 3 C 26 8 C 42 2 SD _D 1 P 19 S D I O / D A T 0 _ MS
SD _B S P 20 D A T 1 _M S P2 2
F S X 5L _ 2 5 MH z
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 *0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 C2 4 8 0 . 1 u _ 16 V _ Y 5 V _ 0 4 1 0u _ 6 . 3 V _X 5 R _ 0 6 P 21 B S _ MS GN D P2 3
C2 6 1 V S S _ MS GN D
Pin#43 Pin#43
2 2p _ 5 0 V _N P O _0 4 Pin#2 Pin#2 MD R 0 1 9 -C 0 -1 04 2
22 p _ 5 0V _ N P O_ 0 4
3 . 3 V _L A N
6- 22 -2 5R 00 -1 B4
6- 22 -2 5R 00 -1 B5 VC C_ CAR D V C C _C A R D
C 28 5 C4 6 0 C 46 1 C2 4 0
*1 0 u _ 6. 3 V _ X 5 R _ 0 6 0. 1 u _ 16 V _ Y 5V _0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#59 Pin#59 Pin#2 Pin#21 C4 2 3 C4 1 0 C 2 38 C4 1 9
Reserved
0 . 1u _ 1 6V _Y 5 V _ 04 4. 7u _ 6 . 3V _X 5 R _ 0 6 0 . 1 u _1 6 V _ Y 5 V _ 0 4 0 . 1u _ 1 6V _Y 5 V _ 04
Pl ace all ca pacit ors closed t o chip.

The s ubscript in each CAP inci cates the pin Near Cardreader CONN
number of JMC251/ JMC261 t hat should be 1 4, 2 3 , 2 8 , 29 , 3 1 , 3 2, 37 V D D 3
26 D VD D
closed t o. 2, 10 , 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9 , 20 , 2 1 , 2 3, 24 , 2 6 , 2 7, 2 8 , 2 9 , 30 , 3 1 , 3 5, 3 6 3 . 3 V S
3, 4 , 1 2 , 1 4, 1 5 , 1 6 , 18 , 1 9 , 2 0, 21 , 2 3 , 2 4, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5 3 . 3 V
B - 26 Card Reader/LAN JMB251C

Schematic Diagrams
LAN (JMC251C), SATA HDD, ODD
GIGA LAN (JMC251C)

L2 6 LP 2
* S B 0 40 2 TL -0 4 0- sh o rt J _ RJ 1
L A N_ MD IP 0 12 13 L MX 1 + 1 8 D LM X1 + 1 G ND1
25 L A N_ M DIP 0 11 T D4 + M X 4+ 14 2 7 2 DA + sh i el d G ND2
L A N_ MD IN0 L MX 1 - D LM X1 -
25 L A N_ M DIN 0 L A N_ MD IP 1 9 T D4 - M X 4- 16 L MX 2 + 3 6 D LM X2 + 3 DA - sh i el d
25 L A N_ M DIP 1 8 T D3 + M X 3+ 17 4 5 6 DB +
L A N_ MD IN1 L MX 2 - D LM X2 -
25 L A N_ M DIN 1 T D3 - M X3 - DB - GN D
L A N_ MD IP 2 6 19 L MX 3 + R 36 7 0 _ 04 D LM X3 + 4
25 L A N_ M D I P 2 5 T D2 + MX 2 + 20 5 DC +
L A N_ MD IN2 L MX 3 - R 36 8 0 _ 04 D LM X3 -
25 L A N_ M D I N 2 L A N_ MD IP 3 3 T D2 - M X 2- 22 L MX 4 + R 36 9 0 _ 04 D LM X4 + 7 DC -
25 L A N_ M D I P 3 L A N_ MD IN3 2 T D1 + MX 1 + 23 L MX 4 - D LM X4 - 8 DD +
T D1 - MX 1 - R 37 0 0 _ 04
25 L A N_ M D I N 3 DD -
DV D D 10 15 P J S -0 8 S O1 B
7 T CT 4 MC T4 18
4 T CT 3 MC T3 21 D LM X3 + R 36 5 D LM X 3-
* 0_ 0 4
1 T CT 2
T CT 1
MC
MC
T2
T1
24 D LM X4 + R 36 6 * 0_ 0 4 D LM X 4- E4120 PJS-08SL3B
R 28
P 10 1 2
E5120Q PJS-08S01B
* 0_ 0 4 6-21-B4010-008
4 0 mil
GST5009 LF N MC T_ 1 R 24 7 5 _1 % _ 04 N MC T _ R R 36 3 * 75 _ 1 %_ 0 4 D LM X 3-
N MC T_ 2 R 25 7 5 _1 % _ 04 R 36 4 * 75 _ 1 %_ 0 4 D LM X 4-
N MC T_ 3 R 26 7 5 _1 % _ 04
N MC T_ 4
0 . 0 1u _ 5 0V _X 7 R _0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
0 . 0 1u _ 50 V _ X 7 R _ 0 4 L6 2 R 32 7 5 _1 % _ 04
L A N_ MD I N 0 7 10 L MX 1 - C3 2 2
L A N_ MD I P 0 8
4
T D+
T D-
TX+
TX-
9
12
L MX 1 +
1 00 0 p _2 K V _ X 7R _ 12 Sheet 26 of 42
5 N C NC 13
L A N_ MD I N 1
L A N_ MD I P 1
1
2
N C
R D+
NC
RX +
16
15
L MX 2 -
L MX 2 +
LAN (JMC251C),
3
R D- R X-
14 NM CT _ 2 NOTICE: SATA HDD, ODD
C 31
C 28
C2 6
C2 4
6 R D_ CT R X _C T 11 NM CT _ 1
T D_ C T T X _C T
*P 3 0 12
FOR JMB251C GIGA LAN PARTS FOR JMB261C 10M/100M LAN PARTS
L26,LP1 L62,LP2
L26,L62 CO-LAYOUT C31,C28,C26,C24,C322 C26,C24
R24,R25,R26,R32,R367,R368,R369,R370 R24,R25,R363,R364
SATA HDD
SATA ODD
J _ HD D1
S1
S2 S A TA _ T X P 0 C 42 1 0 . 0 1 u _5 0 V _ X7 R _ 0 4 J _ OD D 1
S3 S A TA _ T X N 0 C 41 8 0 . 0 1 u _5 0 V _ X7 R _ 0 4 S A TA TX P 0 1 4 S1
S4 S A TA TX N 0 1 4 S2 S A T A _ T XP 1 C3 8 0 0 . 0 1 u_ 5 0 V _X 7 R_ 0 4 S A T A T X P 1 14
S5 S A TA _ R XN 0 C 41 7 0 . 0 1 u _5 0 V _ X7 R _ 0 4 S3 S A T A _ T XN 1 C3 7 9 0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
S6 S A TA _ R XP 0 S A TA R X N 0 1 4 S4 S A T A T X N1 1 4
C 41 6 0 . 0 1 u _5 0 V _ X7 R _ 0 4 S A TA R X P 0 14
S7 S5 S A T A _ RXN 1 C3 7 7 0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
S6 S A T A _ RXP 1 S A T A R X N1 1 4
3 . 3V S C3 7 6 0 . 0 1 u_ 5 0 V _X 7 R_ 0 4 SATAR XP1 1 4
S7
P1
P2
P3 C 41 2 C4 1 1
P4 P1 5 VS
P5 P2 OD D _ D E T E C T# 1 4
*0 . 0 1 u_ 5 0 V _ X7 R _ 0 4 *1 0 u _6 . 3 V _ X5 R _0 6
P6 P3
P7 5V S P4
P8 P5 C3 6 1 C3 6 3 C 35 8 C 3 68 C3 6 6 C 36 5 C3 6 7
P9 P6 +
P1 0 *0 . 1 u _1 6 V _ Y 5 V _ 04 0. 1u _ 1 6V _ Y 5V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 1 u _ 6. 3 V _ X 5R _ 04 1 0u _ 6. 3V _ X 5 R _ 06 1 0 0u _ 6 . 3V _ B _ A *0 . 1 u _1 6 V _ Y 5 V _ 04
P1 1 H D D _N C 0
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
0 . 1u _ 1 6V _Y 5 V _ 0 4
1 u_ 6 . 3 V _X 5R _0 4
2 2u _ 6 . 3V _ X 5 R _ 0 8
22 u _ 6. 3 V _ X 5 R _ 0 8
C 1 8 55 3 -1 13 0 5 -L
P1 2 P I N GN D 1 ~ 2 = G ND
P1 3 H D D _N C 1
P1 4 H D D _N C 2
P1 5 H D D _N C 3
+C 2 0 3
1 -16 2 -1 00 5 6 1
P IN G N D1 ~ 2 = G N D *1 00 u _ 6. 3V _ B _ A
5V S 2 , 1 3 , 17 , 2 0 , 21 , 2 7 , 30 , 3 1 , 35 , 3 6
C 40 9
C4 0 8
C4 0 6
C4 0 7
C1 9 2
C1 9 1
6-20-43740-022 5 VS DV D D
3. 3 V
25
3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 21 , 2 3 , 24 , 2 5 , 29 , 3 0 , 31 , 3 3 , 34 , 3 5
1. 5 V 4 , 9 , 1 0, 1 1 , 2 1, 2 3 , 2 7, 2 9 , 3 1, 33 , 3 6
3. 3 V S 2 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 30 , 3 1 , 35 , 3 6
C 2 74 C 74 C 4 32
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4 0 . 0 1u _ 5 0V _ X 7 R _ 0 4 0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
LAN (JMC251C), SATA HDD, ODD B - 27

Schematic Diagrams
Audio Codec VIA1812

CODEC (VIA1812 ) 1 .5 V
R 3 42 * 15 m i _l s ho rt _ 0 6
C 28 1 C 4 39
5 VS_ AU D
0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u _6 . 3 V _ X5 R _0 6
PC BEEP D2 0
B A T 54 C S 3
3 .3 VS 3 . 3V S _ A U D
C 43 3 C 4 65
L 23 . H C B 16 0 8 K F -1 21 T 2 5
5 VS
L2 1 . H C B 1 60 8 K F -1 21 T 2 5 A U DG
0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u _6 . 3 V _ X5 R _0 6 C4 2 8 C 2 84
1 A C2 7 8 C 28 2 C 2 83 C 26 2 *0 . 1 u _1 0 V _ X7 R _0 4
28 KBC_ BEEP
* 1 u_ 6 . 3 V _X 5 R _ 0 4
C 3 BEEP 0 . 1 u_ 1 6V _Y 5V _0 4 1 0 u_ 6 . 3 V _X 5 R _ 0 6 0 . 1 u _1 6 V _ Y 5 V _ 04 0 . 1 u_ 1 6 V _Y 5 V _0 4 L 36 *1 5 mi l _ sh o rt _ 06
A UD G C4 6 7 0 . 1 u _1 6 V _ Y 5 V _ 04
2 A C4 6 6 0 . 1 u _1 6 V _ Y 5 V _ 04
14 H D A _S P K R
C4 4 1 * 0 . 1u _ 1 6V _ Y 5V _ 0 4 C2 5 7 0 . 1 u _1 6 V _ Y 5 V _ 04
C4 2 6 0 . 1 u _1 6 V _ Y 5 V _ 04
38
25
4
7
1
9
U2 4 C4 3 7 0 . 1 u _1 6 V _ Y 5 V _ 04
A LC _V R E F C4 4 8 10 u _ 6. 3 V _ X 5R _ 06
D VSS2
AV DD1
AVDD 2
D V D D -I O
DVSS1
DVDD
C 4 54 2 2p _ 5 0V _ N P O_ 0 4
FOR EMI
C 2 69 *2 2 p_ 5 0 V _N P O_ 0 4
MI C 2_ L C2 5 8 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 A L C _ GP I O 0 2 AUD G AUD G
MI C 2_ R A L C _ GP I O 1 3 G P I O0 / D MI C -D A T A 1 / 2 27
C2 5 9 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 C 2 63 *2 2 p_ 5 0 V _N P O_ 0 4
G P I O1 / D MI C -D A T A 3 / 4 V RE F
MI C 1_ L C2 5 3 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 R 3 45 2 2_ 1 % _0 4 A Z _ S D OU T _ R 5
MI C 1_ R C2 4 2 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 14 , 2 9 H D A _S D OU T
14 , 2 9 H D A _B I T C LK
R 3 41 2 2_ 1 % _0 4 A Z _ B IT CL K _ R 6 S
B
D A T A -OU T
I T-C L K M I C 1 -V R E F O
28 M I C 1 -V R E F O A 1 MI C 1 -V R E F O-R R 33 2 4 .7 K _ 0 4 M I C 1 -R La you t No te :
R 3 34 2 2_ 1 % _0 4 A Z _ S D IN0 _ R 8
Ver y cl ose t o Aud io C ode c
Sheet 27 of 42
14 HD A _ S DIN 0 S D A T A -I N
R 3 33 2 2_ 1 % _0 4 A Z _ S Y NC_ R 10 3 C D 23
14 , 2 9 H D A _S Y N C A Z _ R S T# _ R 11 S Y NC 37
AUD G 1 4, 29 H D A _ R S T # R 3 30 2 2_ 1 % _0 4 B A T5 4 A S 3
R ESET# MO N O -OU T A 2 MI C 1 -V R E F O-L R3 3 1 4 .7 K _ 0 4 M I C 1 -L
E A P D _ MOD E 47 DIGITAL
Audio Codec La you t No te : C 4 40
C 4 46
2 2p _ 50 V _ N P O_ 04
2 2p _ 50 V _ N P O_ 04
48
45
E APD
S P DIF O 1 C PVEE
31
30
C4 5 6
C4 5 2
2 . 2 u_ 1 6 V _ X5 R _ 0 6
2 . 2 u_ 1 6 V _ X5 R _ 0 6 L ay out N ot e:
Ver y cl ose t o Aud io C ode c
VIA1812
S P DIF O 2 C BN 29
46 CB P
N ear M IC co nn ec t
44 D MI C -C L K 1 / 2 A U DG
D MI C -C L K 3 / 4
43 35 F R ON T -L
BEEP R3 2 3 10 K _ 0 4 P C B E E P _C C4 3 0 1 u _6 . 3 V _ X5 R _ 0 4 PC BEEP_ R 12 N C L O U T 1- L 36 F R ON T -R
R3 2 4 5. 1 K _ 1 % _0 4 P C B E E P -I N LO U T 1 -R
C4 2 9 10 0 p _5 0 V _ N P O _0 4 MI C _S E N S E R 1 8 2 20 K _ 1 %_ 0 4 JD 1 13 39
AUD G 3 0 M IC_ S E NS E HP _ S E N S E R3 5 2 5. 1 K _ 1 %_ 0 4 JD 2 34 S en s e A (JD 1 ) L O U T 2- L 41
3 0 H P _S E N S E S en s e B (JD 2 ) LO U T 2 -R
C 2 52 *1 0 0p _ 5 0V _ N P O_ 0 4
R324 C2 4 5 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 C 2 79 *1 0 0p _ 5 0V _ N P O_ 0 4 14 33
3. 3V VI A1 81 2 10 K C2 7 5 * 0. 1 u _ 16 V _ Y 5 V _ 0 4 15 L I N E 2- L
L I N E 2- R
ANALOG H P OU T- L
H P O U T -R
32 H E A D P H O N E -L 3 0
H E A D P H O N E -R 3 0
M IC2 _ L 16 23
1. 5V VI A1 81 2 5. 1K I N T _ MI C R 1 7 8 1K _1 % _ 04I N T_ M I C _ R
C 2 46
C 2 47
1 u _6 . 3 V _ X 5R _0 4
1 u _6 . 3 V _ X 5R _0 4 M IC2 _ R 17 M I C 2 -L L I N E 1- L 24
M I C 2 -R LI N E 1 -R
A LC 27 2 1K 18 NEAR CODEC
M I C 2 -V R E F O J_INTMIC1
M I C 2 -V R E F O 19 L I N E 1- V R E F O 40 J DR E F R1 9 1 5. 1 K _ 1 %_ 0 4 2 1
20 M I C 2 -V R E F O J D RE F R 78
L I N E 2- V R E F O
MI C 1 -L R1 8 3 75 _ 1 %_ 0 4 MI C 1_ L _ C C 2 51 1 u _6 . 3 V _ X 5R _0 4 M IC1 _ L 21 C2 6 7 *1 0 0 p_ 5 0 V _N P O_ 0 4 2 . 2 1 K _1 % _ 04
AV SS2
30 M I C 1 -L M I C 1 -L
AVSS1
MI C 1 -R R1 7 9 75 _ 1 %_ 0 4 MI C 1_ R _C C 2 43 1 u _6 . 3 V _ X 5R _0 4 M IC1 _ R 22 J_ I N T M I C 1
30 MI C 1 -R M I C 1 -R I N T_ M I C
1
C4 3 6 C4 3 5 V T1 8 1 2 A UDG C 12 2 2
La yo ut No te :
26
88 2 66 -0 2 00 1
42
68 0 p _5 0 V _ X7 R _0 4 6 80 p _ 50 V _ X 7R _ 04 Ve ry cl os e t o Au dio C od ec 3 3 0 p_ 5 0V _X 7 R _ 0 4 P C B F o o t pr in t = 8 82 6 6- 2L
R191 VIA1812 5.1K_1%_04
A U DG AUD G
A UDG
ALC272 20K_1%_04
5 V S _ RE A R L 34 5 VS
H C B 1 00 5 K F -1 2 1T 2 0
L ayo ut N ot e:
Co de c pin 1 ~ p in 11 a nd pi n 44 ~ pi n 4 8 AMP (N7010) 10/16 change C2 4 9 C4 4 2 C 43 1 C 4 45
ar e Di git al s ig nal s.
Th e ot her s ar e Ana lo g sig na ls . footprinter 0 . 1u _ 1 6V _ Y 5V _ 0 4 *1 u _ 6. 3 V _ X 5R _ 04 1 0 u _6 . 3 V _ X5 R _ 0 6 *1 0u _ 6 . 3V _ X 5 R _ 0 6 J_SPK1
2 1
U 22
F R ON T-L R3 5 3 10 K _ 0 4 C4 5 8 0 . 1 u _1 0 V _ X7 R _ 0 4 LI N - 5 6
C2 5 4 0 . 1 u _1 0 V _ X7 R _ 0 4 LI N + 9 L IN- PVDD 15 A U DG
AU DG L IN+ PVDD 16
F R ON T-R R3 5 6 10 K _ 0 4 C4 6 2 0 . 1 u _1 0 V _ X7 R _ 0 4 RIN - 17 VDD J _ SPKL 1
C2 6 0 0 . 1 u _1 0 V _ X7 R _ 0 4 RIN + 7 RI N- 4 S P K O UT L + L2 2 F C M1 0 0 5K F -12 1 T 03 S P K OU T L+ _ R
AU DG RI N+ LO U T + . S P K OU T L-_ R 1
Thermal Pad
8 S P K O UT L - L2 0 F C M1 0 0 5K F -12 1 T 03 2
SPK_ EN 19 L O UT - .
3 .3 VS 85 2 0 4-0 2 0 01
R 3 46 1 0 0 K _1 % _ 04 SD # P C B F o ot pri n t = 85 2 0 4-0 2 R
A UD G GA I N 0 2 18
5 VS R 1 97 * 1 00 K _ 1 %_ 0 4 S P K O UT R+ 3 0 C 26 5 C2 7 3
GA I N 1 3 GA I N 0 RO UT + L 24
GA I N 1 14
R 1 89 1 0 0 K _1 % _ 04 S P K O UT R- 3 0 * 1 0m i _l s h ort _0 4 1 8 0p _ 5 0V _ N P O_ 0 4 1 80 p _ 50 V _ N P O _ 04
R 3 40 * 1 00 K _ 1 %_ 0 4 1 RO UT -
A UD G 11 GN D
R 32 7
13 GN D 10 A MP _ B Y P A S S
GN D BYP ASS F OR EM I
1 0 0K _1 % _ 04 C4 3 4 20
Low mute! D2 2 *C D B U 00 3 4 0 21 GN D 12 C 42 7
C A E X P OS E D P A D NC
1 9 P C H _ MU T E # *0 . 1 u _1 0 V _ X7 R _0 4
Gain Settings N 70 1 0 4 . 7 u_ 6 . 3 V _ X5 R _ 0 6
5
GAIN0 GAIN1 AV(inv) INPUT IMPEDANCE

E A P D _ M OD E R 3 3 5 *1 0 mi l _s h o rt _ 04 E A P D _ M OD E _ R 1
0 0 6 dB 90 k
4 SPK_ EN A UD G AUD G
2 0 1 10 dB 70 k
2 8 K B C _M U T E # 1 0 15.6 dB 45 k
N7010 6-02-07010-AL0
U2 3 1 1 21.6 dB 25 k APA2031RI-TRG 6-02-02031-AL1
3
MC 7 4 V H C 1 G0 8 D F T 1 G
1 .5 V 4 , 9, 1 0 , 1 1, 21 , 2 3, 29 , 3 1 , 33 , 3 6
3 .3 V 3 , 4, 1 2 , 1 4, 15 , 1 6, 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 35
3 .3 V S 2 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 8, 2 9 , 3 0, 3 1 , 3 5, 3 6
5V 2 1, 2 4 , 3 0, 3 1 , 3 3, 3 4
5 VS 2 , 13 , 1 7 , 20 , 2 1 , 26 , 3 0 , 3 1, 3 5 , 3 6
B - 28 Audio Codec VIA1812

Schematic Diagrams
KBC-ITE IT8502E
R1 7 1 *1 5 mi l _s h o rt _0 6 K BC _ A V DD L17
V D D3 H C B 1 0 0 5K F - 12 1 T2 0
C 2 08 C 2 32 C2 2 9 C2 2 5 C 19 5
. V D D3 V DD 3 V D D3
C2 1 8 C2 1 9 C2 2 2 U2 8
0 . 1 u _1 6 V _ Y 5 V _ 04 10 u _ 6. 3 V _ X 5R _0 6 0 . 1u _ 1 6V _ Y 5V _ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 8 5 KB C_ SP I_ S I_ R
VD D SI 2 KB C _ S P I _ S O_ R
0 . 1u _ 1 6V _ Y 5 V _ 0 4 *0 . 1 u _1 6 V _ Y 5 V _ 04 *0 . 1 u_ 1 6 V _Y 5 V _0 4
SO 1 KB C_ SP I_ CE # _ R R 15 8
CE # 6 KB C_ SP I_ S CL K _ R
C 22 6
L1 8 K B C_ F L A S H 3 S CK 1 0 0K _ 1 % _0 4
W P#
H C B 10 0 5 K F -12 1 T 20 0 . 1 u_ 1 6 V _Y 5 V _0 4 K B C _ A GN D
3 .3 VS . EC_ V CC FOR E4120 FOR E5120Q KB C_ W R E S E T #
K B C _ H O LD # 7 4 C 21 6
H OL D # VSS
114
127
1 21
J_ K B 1 J _ KB2
26
92
11
50
74
3
U1 1 * 85 2 0 1-2 4 0 51 8 52 0 1- 24 0 51 E N 2 5 P 05 -5 0 GC P 1 u _6 . 3 V _ X5 R _0 4
For 8502E
V CC
VST BY
VSTB Y
VSTB Y
AVCC
VSTBY
VSTBY
VSTBY
10 58 4 4
VBAT
K B -S I 0 K B -S I 0
14 , 2 4 L P C_ A D 0 9 L A D0 K S I0 /S T B # 59 K B -S I 1 5 K B -S I 1 5
14 , 2 4 L P C_ A D 1 8 L A D1 KSI1 /AF D # 60 K B -S I 2 6 K B -S I 2 6 U9 U28 Co-layout
14 , 2 4 L P C_ A D 2 7 L A D2 K S I 2/ I N I T # 61 K B -S I 3 8 K B -S I 3 8
14 , 2 4 L P C_ A D 3 13 L A D3 K S I 3/ S LI N # 62 11 11
P C LK _ K B C K B -S I 4 K B -S I 4
18 P C L K _K B C 6 L P CC L K KSI4 63 K B -S I 5 12 K B -S I 5 12
1 4, 2 4 L P C _ F R A M E # 5 L F R A ME # KSI5 64 14 14
LPC K/B MATRIX K B -S I 6 K B -S I 6 EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
14 , 2 4 S E RIR Q 22 S E R IRQ KSI6 65 K B -S I 7 15 K B -S I 7 15
4 , 1 8, 2 3 , 2 5 B U F _ P L T_ R S T# L P C R S T #/ W U I 4 / GP D 2 ( P U ) KSI7
K B C _W R E S E T # 14 36 K B -S O0 1 K B -S O0 1 1 J_KB1 24
W R ST# K S O0 / P D 0 VE R. RX VO LTA GE MO DE L_ ID
37 K B -S O1 2 K B -S O1 2
1 26 K S O1 / P D 1 38 K B -S O2 3 K B -S O2 3
19 GA 2 0 4 G A 20 / G P B 5 K S O2 / P D 2 39 K B -S O3 7 K B -S O3 7
V1 .0 R 157 1 0K / R 15 3 X 3 .3V E4120
37 A C_ IN# 16 K B R S T #/ G P B 6 ( P U ) K S O3 / P D 3 40 K B -S O4 9 K B -S O4 9
29 L E D _A C I N # 20 P W U R E Q # / GP C 7( P U ) K S O4 / P D 4 41 K B -S O5 10 K B -S O5 10
R 157 X / R15 3 10 K 0V E5120Q
3 T H E R M _A L E R T# L 8 0L L A T / GP E 7 ( P U ) K S O5 / P D 5 42 K B -S O6 13 K B -S O6 13
23 K S O6 / P D 6 43 K B -S O7 16 K B -S O7 16
30 AP_ KEY # E C S CI# /G P D3 ( P U ) K S O7 / P D 7
15 44 K B -S O8 17 K B -S O8 17 M OD E L_ I D R 15 7 *1 0 K _ 04
30 W E B _E M A I L # E C S MI # / G P D 4 ( P U ) K S O8 / A C K # V DD 3
Sheet 28 of 42
45 K B -S O9 18 K B -S O9 18
K S O 9/ B U S Y 46 K B -S O1 0 19 K B -S O1 0 19 R 15 3 1 0 K _0 4
85 0 2_ C P U _ F A N 76
DAC K S O 1 0/ P E 51 K B -S O1 1 20 K B -S O1 1 20
85 1 8_ D D _ ON 77 D A C 0 / GP J 0 K S O1 1 / E R R # 52 K B -S O1 2 21 K B -S O1 2 21 RX
2 3, 2 9 W L A N _ E N
24 3 G_ P OW E R
85 0 2_ I S O N
W LA N _ E N
78
79
80
D
D
D
A C 1 / GP J 1
A C 2 / GP J 2
A C 3 / GP J 3 ITE 8502E
K S O1 2/ S LC T
K S O1 3
K S O1 4
53
54
55
K B -S O1 3
K B -S O1 4
K B -S O1 5
22
23
24
K B -S O1 3
K B -S O1 4
K B -S O1 5
22
23
24
KBC-ITE IT8502E
81 D A C 4 / GP J 4 K S O1 5
27 K B C _M U T E # D A C 5 / GP J 5 ITE 8518E V DD 3
ADC FLASH RN 1 9 V DD 3
B A T _ DET 66 10 0 2 . 2K _4 P 2 R _ 0 4
37 B A T _D E T 67 AD C 0 / GP I 0 F L F R A ME # / GP G 2 10 1 3 2
B A T _ V OL T K B C_ S P I_ CE # SM D_ B A T 3 G_ D E T # R1 4 7 10 K _ 0 4
W L A N_ L E D# 68 AD C 1 / GP I 1 F L A D0 /S C E # 10 2 K B C_ S P I_ S I SM C_ B A T 4 1 CC D_ DE T # R1 5 0 10 K _ 0 4
2 3 , 2 9 W LA N _ LE D # 69 AD C 2 / GP I 2 F L A D 1/ S I 10 3 K B C_ S P I_ S O
3 T H E R M _V O L T P CIE _ W A K E # 70 AD C 3 / GP I 3 F L AD2 /S O 10 4 8 51 8 _D D _ ON _ LA T C H
2 5 LA N _ P C I E _ W A K E # 3 G_ D E T # 71 AD C 4 / GP I 4 F L A D 3 / GP G 6 10 5 K B C _ S P I _ S C LK 3 . 3V S
24 3 G_ D E T # C C D _ D E T# 72 AD C 5 / GP I 5 F L CL K /SCK 10 6
24 C C D _D E T # MO D E L _ I D 73 AD C 6 / GP I 6 ( P D )F L R S T# / W U I 7 / TM / GP G 0 CC D_ E N 24 ITE 8502E W L A N _L E D # R3 6 0 *1 0K _0 4
AD C 7 / GP I 7 85 0 2 _D D _ ON _L A T C H R3 7 1 0_04
GPIO 56 85 0 2 _W L A N _D E T # D D _O N _ L A T C H 3 1
SMBUS S US B # 16 , 2 3 , 31 R3 7 2 0_04 W L A N_ DE T # 2 3
S M C_ B A T 1 10 ( P D )K S O1 6 / GP C 3 57 85 0 2 _B T _ D E T # R3 7 3 0_04
37 S MC _ B A T S M D_ B A T 1 11 SM C L K 0 / GP B 3 ( P D )K S O1 7 / GP C 5 S US C# 16 , 3 3 85 0 2 _D D _ ON B T _D E T # 2 3 , 2 9
37 S MD _ B A T R3 7 4 0_04 D D _O N 31 C2 1 5
1 15 SM D A T 0 / GP B 4 93 85 0 2 _I S O N R3 7 5 0_04 PCL K _ KB C R1 6 4 *1 0 _0 4 P C L K _ K B C _R
1 16 SM C L K 1 / GP C 1 ( PD )I D 0 / GP H 0 94 S U S _P W R _ A C K 1 6 85 0 2 _C P U _ F A N I S ON 25
M E_ W E# 1 4 R3 7 6 0_04 C P U _F A N 3 0
S M C _ C P U _T H E R M 1 17 SM D A T 1 / GP C 2 ( PD )I D 1 / GP H 1 95 *1 0p _ 5 0V _ N P O_ 0 6
3, 1 5 S MC _ C P U _T H E R M S M D _ C P U _T H E R M 1 18 SM C L K 2 / GP F 6 ( P U ) ( PD )I D 2 / GP H 2 96 8 5 0 2_ D D _ ON _ L A T C H A C _ P R E S E N T 16 , 1 8
3, 1 5 S MD _ C P U _T H E R M SM D A T 2 / GP F 7 ( P U ) ( PD )I D 3 / GP H 3 97 8 5 0 2_ W L A N _ D E T#
( PD )I D 4 / GP H 4 98 8 5 0 2_ B T _ D E T #
0831
L C D _B R I GH T N E S S 24 PWM ( PD )I D 5 / GP H 5 99 8 5 0 2_ D D _ ON
27 KBC _ BEEP
K B C _B E E P 25 PW M 0 / GP A 0 ( PU ) ( PD )I D 6 / GP H 6 ITE 8518E
28 PW M 1 / GP A 1 ( PU ) 10 7 85 0 2 _D D _ ON _L A T C H R3 7 7 * 0_ 0 4 C2 0 0
2 9 LE D _ S C R OL L# 29 PW M 2 / GP A 2 ( PU ) ( P D )I D 7 / GP G 1 3 G_ E N 24 85 0 2 _W L A N _D E T # R3 7 8 * 0_ 0 4 8 51 8 _S P I _C S 0 # 1 4 B A T_ V O LT
29 L E D _ N U M# 30 PW M 3 / GP A 3 ( PU ) 8 51 8 _S P I _S C L K 1 4 37 B A T _ V OL T
EXT GPIO 85 0 2 _B T _ D E T # R3 7 9 * 0_ 0 4
29 L ED_ CA P# 31 PW M 4 / GP A 4 ( PU ) 82 85 0 2 _D D _ ON R3 8 0 *0 _ 0 4 8 51 8 _S P I _S O 1 4 1u _ 6. 3V _ X 5 R _ 04
LOW ACTIVE 29 L E D _ B A T _ C H G# 32 PW M 5 / GP A 5 ( PU ) ( P D )E G A D / G P E 1 83 S MI # 19 8 51 8 _S P I _S I 14
2 9 LE D _B A T_ F U LL # 34 PW M 6 / GP A 6 ( PU ) ( P D )E G C S # / G P E 2 84 S CI# 19
29 L E D _P W R # PW M 7 / GP A 7 ( PU ) ( P D )E G C L K / G P E 3 P W R _B T N # 1 6
85 1 8 _D D _ ON _L A T C H R3 8 5 * 0_ 0 4
85 1 8 _W L A N _D E T # R3 8 7 * 0_ 0 4 D D _O N _ L A T C H 3 1
8 0 CL K 85
PS/2 WAKE UP 35 85 1 8 _B T _ D E T # W L A N_ DE T # 2 3
R3 8 6 * 0_ 0 4
23 8 0 CL K 3 IN1 86 PS2 C LK 0 / G P F 0( PU ) ( P D )W U I 5 / G P E 5 17 RS M RS T # 1 6 85 1 8 _D D _ ON R3 8 8 * 0_ 0 4 B T _D E T # 2 3 , 2 9 S M C _ C P U _ TH E R M
23 3 IN 1 8 0 DE T # 87 PS2 D A T0 / G P F 1( PU ) ( P D )L P C P D # / W U I 6 / G P E 6 K B C _R S T # 1 9 85 0 2 _C P U _ F A N D D _O N 31 4 ,1 9 H_ P EC I
R3 8 9 * 0_ 0 4 R 17 5 *0 _0 4
23 8 0D E T # 88 PS2 C LK 1 / G P F 2( PU ) 85 0 2 _I S O N R3 9 0 * 0_ 0 4 I S ON 25
18 PM E# 89 PS2 D A T1 / G P F 3( PU ) PWM/COUNTER 47 C P U _F A N 3 0
30 T P _ CL K PS2 C LK 2 / G P F 4( PU ) ( P D )T A C H 0 / GP D 6 CP U _ F A NSE N 30
90 48 MC H _ T S A TN _ E C
30 T P _D A T A PS2 D A T2 / G P F 5( PU ) ( P D )T A C H 1 / GP D 7
12 0
1 25
WAKE UP ( P D )T MR I 0/ W U I 2 / GP C 4 12 4 V C O R E _ O N 1 6 , 36
37 V CHG _ S EL P W R S W / G P E 4( P U ) ( P D )T MR I 1/ W U I 3 / GP C 6 A L L_ S Y S _ P W R G D 1 2 , 16 V DD 3 C2 0 1
For 8512E
18
CIR 11 9 8 51 8 _W LA N _ D E T #
KBC_SPI_*_R = 0.1"~0.5"
31 P W R _S W # 0 . 1 u_ 1 6 V _Y 5 V _0 4
21 R I 1# / W U I 0 / GP D 0( P U ) ( P D )C R X / GP C 0 12 3 8 51 8 _B T_ D E T#
12 , 3 0 L ID_ S W # R I 2# / W U I 1 / GP D 1( P U ) ( P D )C TX / G P B 2
U 9
8 5 K B C _S P I _S I _R R3 9 1 4 7 _ 04 K B C _S P I _S I
33
GP INTERRUPT LPC/WAKE UP 19 VD D SI
30 W E B _W W W # G I N T / GP D 5 ( P U ) ( P D )L 80 H LA T / G P E 0 SW I# 16 2
?? ? K B C _S P I _S O _ R R3 9 2 1 5 _ 04 K B C _S P I _S O
11 2 R 1 3 5 1 K _ 1% _ 0 4 SO
( P D )R I N G #/ P W R F A I L # / L P C R S T# / G P B 7 C H G_ E N 37 3 1
UART K B C _ F LA S H K B C _S P I _C E # _R R3 9 3 1 5 _ 04 K B C _S P I _C E #
1 08 W P# CE #
23 , 2 9 B T_ E N 1 09 R XD / GP B 0 ( P U )
CLOCK 2 6
CK 3 2 K E K B C _S P I _S C L K _R R3 9 4 4 7 _ 04 K B C _S P I _S C L K
AVSS
12 BKL _ EN T X D/G P B 1 ( PU ) C K 3 2K E SC K
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12 8 CK 3 2 K R 1 6 2 4 . 7 K _0 4
C K 3 2K 7 4
R 1 69 * 10 M_ 0 4 K B C _ H OL D #
I T8 5 02 E HO L D# VSS
AT25F512AN for 8502 6-04-25320-A70
27
49
91
113
75
1
12
1 22
U9 U28 Co-layout * MX 2 5L 3 20 5 D M 2 I -12 G

R 3 9 5 * 0_ 0 4 X3 MX25L3205DM2I-12G for 8518 6-04-02532-470
6-04-26321-470
R 16 8 *0 _0 4 EC_ V S S 1 4
2 3 C K 3 2K E
C 22 3 0 . 1 u_ 1 6 V _Y 5 V _0 4 C 22 7 C 2 21 V D D3 1 4, 23 , 2 5 , 29 , 3 1 , 32 , 3 7
C K 3 2K Co -la yo ut X2 , X3 3 .3 V S 2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 9 , 3 0, 3 1 , 3 5, 36
0 _0 4 FOR I T8 512 CX /E X 1 2 p_ 5 0 V _N P O_ 0 4 1 2 p _5 0 V _ N P O _0 4
0 .1 U_ 04 FO R ITE 85 12 -J( IT E8 502 -J W/0 C IR ) NC 3 S H OR T 1 4 X2
* MC -14 6 _ 32 . 7 6 8K H z 2 3
E C Co st Do wn
1T J S 1 25 D J4 A 4 2 0P _ 3 2 . 76 8 K H z
6 -2 2- 32R 76 -0 B4
12 B RIG HT NES S R 1 51 *1 0 m li _ sh o rt _ 04L C D _B R I GH T N E S S K B C _A G N D 6 -22 -3 2R 76- 0B 2
6 -22 -3 2R 76- 0B G
C 2 11 * 0. 1u _ 16 V _ Y 5 V _ 0 4
KBC-ITE IT8502E B - 29
Schematic Diagrams
LED, MDC, BT
3 V_ BT
Bluetooth(Port8) 3 . 3V
COSTDOWN J _ B T1
Po rt 1 1 1
2
18 U S B _ P N1 1 3
MJ_MDC1
20 MIL 1. 5 V
R 2 92
18 U SB_ PP1 1 4
11 2 3 ,2 8 B T_ D E T# B T _E N # 5
12
R 1 67 * 15 m li _ s ho rt _ 0 6 4 7 K _ 1% _ 0 4 6
2 1 3 .3 V 87 2 1 2-0 6 G0
3 .3 V R 30 8 *0 _ 04
B T _D E T # 1 5 , 23 P C H _ B T _E N #
J_ MD C1
1 2 R1 6 6 *0 _ 0 6 3 .3 V
R 1 65 33 _ 0 4 H D A _S D OU T_ R 3 G ND R E S E RV E D 4 C 4 01 R 3 09
From EC default HI
1 4 , 27 H D A _ S D O U T 5 A z a il a _S D O
G ND
R E S E RV E D
3 . 3 V Ma i n / au x
6 MD C _ 3. 3 V 10mil L 16 *1 5 mi l _s h o rt _0 6
R 1 61 33 _ 0 4 H D A _S Y N C _R 7 8 *1 8 0 p_ 5 0 V _N P O_ 0 4 10 K _ 0 4 3 .3 V 3 V_ BT
1 4 , 27 H D A _ S Y N C 9 A z a il a _S Y N C GN D 10 R3 0 6
R 1 59 22 _ 1 %_ 0H 4D A _S D I N 1 _ R 5 0m il 50 mi l
1 4 H DA _ S DIN 1 R 1 55 33 _ 0 4 H D A _R S T #_ R 11 A z a il a _S D I GN D 12 HD A _B I TC LK _R R 15 2 3 3 _ 04 B T _ E N#
1 4 , 27 H D A _ R S T # A z a il a _R S T # A za il a _ B C L K H D A _B I T C LK 1 4 , 2 7
D
88 0 1 8-1 2 0G C 21 7 C 21 2 *1 5m i l _s h o rt _0 6
Q1 5 C 39 8 C 3 95
0 . 1 u_ 1 6 V _Y 5V _0 4 2 2 p_ 5 0 V _N P O_ 0 4 G MT N 7 0 02 Z H S 3
2 3, 2 8 B T _E N
1 8 0p _ 5 0V _ N P O _ 0 4
10 u _ 6. 3 V _ X 5R _0 6
S
G ND
Sheet 29 of 42 LED 3 . 3V S 3. 3 V S 3 .3 V S 3 . 3V S
3. 3 V S 3 .3 V S V DD3 V D D3 V DD 3 V DD3
LED, MDC, BT
E
R 6 R5 R 1 93 R 19 4 R 1 96 R 1 95
B R 2 R3 R4 2 2 0_ 0 4 2 20 _ 0 4 * 2 20 _ 04 * 22 0 _ 04 *2 20 _ 0 4 * 2 20 _ 04
S A TA _ L E D # 1 4
Q3 2 2 0_ 0 4 22 0 _ 04 22 0 _0 4 POWER ON BAT LED
C
D T A 1 14 E U A BT WLAN 1 LED
3
R1 LED 1 3 D 1 LED 2
D1 3 D1 4
SG
HDD/ODD NUM CAPS SCROLL
SG
SG
Y
Y
22 0 _ 04 D3 D 4 D5 2 4 R Y -S P 1 5 5 H Y Y G4 *R Y -S P 1 5 5H Y Y G4 *R Y -S P 1 5 5 H Y Y G4
LED LOCK LOCK LOCK
4
R Y - S P 1 70 Y G 34 - 5 M
R Y - S P 1 7 0 Y G 3 4 - 5M
R Y - S P 17 0 Y G 3 4 - 5 M
LED LED LED
A
R 3 43
D2
W L A N _L E D # 2 3 , 2 8
C
*1 0 m li _ sh o rt _ 04
R Y - S P 17 0 Y G 3 4 - 5 M
B L E D _P W R # 28 LE D _B A T_ F U LL # 2 8
W L A N_ E N 23 , 2 8
LE D _ A C I N # 2 8 L E D _ B A T _C H G # 28
C
Q2
*D T C 1 14 E U A
LE D _ N U M# 2 8 LE D _ C A P # 2 8 L E D _ S C R OL L # 28
E
C
6-52-52001-027 6-52-52001-027 6-52-52001-027 E4120
B
6-52-52001-027 BT_ EN 23 , 2 8
Q1 4 , 9 , 1 0, 1 1 , 2 1, 2 3 , 2 7, 3 1 , 3 3, 3 6 1 . 5V
D TC 11 4 E U A
3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 3 0 , 3 1, 3 3 , 3 4, 3 5 3 . 3V
E
1 4, 2 3 , 2 5, 2 8 , 3 1, 3 2 , 3 7 V D D 3
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 8 , 3 0, 3 1 , 3 5, 3 6 3 . 3V S
H2 5 H1 4 H1 3
M1 M5 M7 M8 M2 9 9 9
M-M A R K 1 M -MA R K 1 M-MA R K 1 M-M A R K 1 M -MA R K 1 3 8 3 8 3 8
H1 0 H 8 4 1 7 4 1 7 4 1 7
H 6 _ 3 D 3 _8 H 6_ 3 D 4 _ 4 5 6 5 6 5 6
C 46 8
MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1 *0 . 1 u_ 1 6V _Y 5V _0 4
V DD 3
H2 H1
C 1 58 D 15 8 C 1 58 D 15 8 M6 M3 M4 H5 H3 H2 4
M-MA R K 1 M-M A R K 1 M -MA R K 1 9 9 9 GN D
3 8 3 8 3 8 J _ TP4
4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 1 L E D_ P W R #
2 L E D_ A CIN #
3 L E D_ B A T _ F UL L #
MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1
H1 8 H 15 H1 7 H 12 4 L E D_ B A T _ CHG #
H6 _ 0 D3 _ 7 S1 S2 H 4_ 7 B 6 _0 D 3_ 7 H 4 _7 B 6 _ 0D 3 _7H 6_ 3 D 3 _ 8 5
S MD 80 X 8 0 S MD 8 0 X 80 H1 1 H7 H2 2 6
9 9 9 8 52 0 1 -06 0 5 1
3 8 3 8 3 8
1
4 1 7 4 1 7 4 1 7 GN D
1
5 6 5 6 5 6
MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1 M TH 31 5 D 1 1 1
H2 3 H6 H2 1 H 20 H1 9 H 16 H9 H4
C6 7 D6 7 C6 7 D 6 7 C 1 58 D 15 8 C 15 8 D 1 5 8 H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3_ 7 9 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
MT H 3 1 5 D 1 1 1 M TH 31 5 D 1 1 1
B - 30 LED, MDC, BT
Schematic Diagrams
USB, Fan, TP, Multi-Conn

USB PORT*2(Port 0,Port1) FAN CONTROL
5V S _ F A N 5 VS U 19
U 4 F ON # 1 8
5V U S B _ F L G# 5 6 U S B V C C0 1 2 FO N GN D 7
F L G# V O U T 1 3 V IN GN D 6
2 7 100 MIL 4 V O UT GN D 5
V IN 1 V O UT 2 28 C P U _F A N VSET GN D
C 94 3 8 C 1 10 C 1 21 C 1 28 G 9 90 P 1 1U
V IN 2 V O UT 3
1 0 u_ 6 . 3 V _X 5 R _ 0 6 4 1 0. 1 u _1 6 V _ Y 5 V _ 04 0. 1 u _1 6 V _ Y 5 V _ 04 *1 0u _ 6 . 3V _ X 5 R _ 06 G9 90P 1 1U 6- 02 -9 901 1 -B2 0
E N# G ND
31 , 3 3 D D _O N # U P 75 3 4 D S A 8 -2 0 P2 793 A 6- 02 -0 27 93- B 20
UP7 53 4D 6 -02 -75 3 48- 92 0

5 VS 5 VS_ FAN
RT9 71 5B GS 6- 02- 0 971 5- 92 0 J _ F A N1
APL 35 10 6 -02 -03 5 10- 92 0 1
C 3 94
U S B V C C 01 C3 9 0 2
3
0 . 1 u _1 6 V _ Y 5 V _ 04
L10 U S B _ V C C 01 _ 0 1 0u _ 6 . 3V _ X 5 R _ 06 85 2 0 5-0 3 7 01
* 15 m li _ s ho rt _ 0 6 60 mil
C 95 +C 92 C 80
+
Port 0 28 C P U _ F A N S E N
2 20 u _6 . 3 V _ 6. 3 * 6. 3 *4 . 2 * 10 0 u_ 6 . 3 V _B _ A 0 . 1 u_ 1 6 V _Y 5V _0 4
R 2 75 4. 7 K _ 0 4
3 .3 V S
JFAN
3
J _ US B 1
1
V+ 1
18 U S B _P N 0
4 L9 3 2
DA T A _ L Sheet 30 of 42
18 U SB_ PP0
1 2 3
DA T A _ H CLICK CONN FO R C LI CK B OA RD
*W C M2 01 2 F 2 S -16 1 T 03 -s h ort
USB, Fan, TP,
G ND 4
4
GN D 1
GN D 2
GN D 3
GN D
3 .3 V 3 .3 V
1 -28 4 -8 00 2 81
Multi-Conn
G ND 1
GN D 2
G ND3
GN D 4
6- 21- B 440 0- 00 4
R7 4 R7 7 5 VS_ TP
U S B _ V C C 0 1 _0
10 K _ 0 4 *1 0 K _0 4
R9 4 * 15 m i _l s ho rt _ 0 6
5V S
U S B _ F LG #
18 U S B _ OC # 0 1 C 1 58 C1 6 3
80 mil
R7 3 R8 5 R8 4
*0 _0 4 * 1 0u _ 6. 3 V _ X 5R _ 06 1 u_ 6 . 3 V _X 5 R _ 0 4
+C 1 2 9 C1 7 1 J_ T P 1 10 K _ 0 4 10 K _ 0 4
1
*1 0 0u _ 6 . 3V _ B _ A 0 . 1u _ 1 6V _ Y 5V _ 0 4 T P _D A T A 2 8
2
Port 1 3
4
8 52 0 1- 04 0 51
C1 5 3 C1 4 9
T P _C L K 2 8
J_ U S B 2 47 p _ 50 V _ N P O _0 4 47 p _ 50 V _ N P O _0 4
1
V +
4 L13 3 2
18 US B _ P N 1 D A T A _L
1 2 3
18 U SB_ PP1 D A T A _H
*W C M2 01 2 F 2 S -16 1 T 03 -s h ort
4
POWER SWITCH CONN.
GN D 1
GN D 2
GN D 3
GN D 4
G ND
1 -2 8 4-8 0 0 28 1
CLOSE TO J_SW1
G ND 2
GN D 1
GN D 3
G ND4
6 -21 -B4 4 00- 00 4

FO R PO WE R SW IT CH B OA RD AP_ KEY#
AP_ KEY# 2 8 3 .3 V S 3 .3 V
3 .3 VS 3 . 3V
D
C 21 C2 0 Q6 J_ S W 2
G 2 0m il
Audio/B CONN.(Port 2) 5V
* MT N 7 0 0 2Z H S 3 1
2
S
0 . 0 1u _ 5 0V _ X 7 R _ 04 0. 01 u _5 0 V _ X7 R _ 0 4 MB T N R1 8 *1 0 m li _ sh o rt _ 04 M_ B T N #
3 W EB_ W W W #
1.1A 60mils 4 W E B _ E MA I L #
C2 1 4 0. 01 u _5 0 V _ X7 R _0 4 J_ S W 1 5 LI D _ S W #
2 0m il R 21 6
F OR AU DI O BO AR D 1
2 M_ B TN # _R
*1 0 mi l _ sh o rt _0 4 7
8
AP_ KEY#
J _ A U D I O1
R 15 4 *1 5 mi l _ sh o rt _ 06 3 W E B _W W W # M_ B T N # 31 88 4 8 6-0 8 01
MI C 1-R 1 4 W E B _E MA I L # W EB_ W W W # 2 8
2 7 MI C 1-R 2 5 W E B _ E MA I L# 2 8
MIC 1-L LI D _S W #
2 7 MI C 1-L 3 6 L I D _ S W # 12 , 2 8
R 18 1 2 2 0 _0 4 H E A D P H ON E -R R 4 7 A P _O N
2 7 H E A D P H O N E -R H E A D P H ON E -LL 5 8 A P _ ON 31
2 7 H E A D P H O N E -L R 18 0 2 2 0 _0 4 3 , 4, 1 2 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 21 , 2 3 , 24 , 2 5 , 29 , 3 1 , 33 , 3 4 , 35 3 . 3 V
MI C _S E N S E 6 9
2 7 MI C _S E N S E S P K _ HP # 7 10 VIN 2 , 13 , 1 7 , 20 , 2 1 , 26 , 2 7 , 31 , 3 5 , 36 5 V S
8 21 , 2 4 , 31 , 3 3 , 34 5 V
18 U S B _P N 4 R 17 2 *1 0m i l _s h ort _0 4 U S B N 4 _R HP _ S E NS E
2 7 HP _ S E N S E U S B N 4_ R 9 *5 0 50 0 -0 10 4 1-0 0 1 L
10 1 2 , 31 , 3 2 , 33 , 3 4 , 35 , 3 6 , 37 V I N
18 U SB_ PP4 R 17 4 *1 0m i l _s h ort _0 4 US B P 4 _ R US B P 4 _ R
11 2, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 24 , 2 5 , 26 , 2 7 , 28 , 2 9 , 31 , 3 5 , 36 3 . 3 V S
S P K OU TR + 12
2 7 S P K OU T R + 13
S P K OU T R -
2 7 S P K OU T R - 14
8 7 2 13 -1 4 00 G
If system has APON function, uses J_SW1

If system has no APON function, uses J_SW2
USB, Fan, TP, Multi-Conn B - 31

Schematic Diagrams
5VS, 3VS, 1.5VS

VA V IN V IN1
SYS5 V SY S5 V
P C 64 P C6 3 P C6 2
0 .1 u_ 5 0 V _ Y 5 V _ 0 6 0 . 1u _ 5 0 V _Y 5 V _ 06 0.1 u _ 5 0V _Y 5 V _ 06
ON P R 2 13 PR2 1 1
DD_ON "L" TO
P U4 1 0 K _ 04 1 0K _0 4
1 8 "H" FROM EC
VA VA VIN 1 VIN 1
2 7 R1 3 2 * 1 0m i l _s h o rt _ 04 D D _ ON # S US B
V IN V IN D D _ O N _ L A TC H D D _O N _ L A T C H 2 8 D D _O N # 3 0, 3 3
3 6
30 M_ B T N # M _ B TN # P W R _S W # P W R_ S W # 2 8 P Q4 4 A 6 P Q 44 B 3
4 5 P R 98 MT D N 7 0 02 Z H S 6 R D M T D N 70 0 2 Z H S 6R D
30 AP_ O N IN S T A N T -O N GN D
1 0 K _ 04
P 28 0 8 A 1 2 G P C 1 88 5 G P C1 8 9
V D D3 28 D D _O N 16 , 2 3 , 2 8 S U S B #
S S
1 * 0.1 u _ 1 6V _ Y 5 V _0 4 4 *0 .1 u _1 6 V _ Y 5 V _ 0 4
ON
P R2 1 0 ON P R2 1 2
1 00 K _ 1 % _0 4 1 0 0 K _ 1 %_ 0 4
5V
ON
ON
C2 0 4 C 2 64 C9 1
0. 0 1 u _ 50 V _ X 7 R _ 0 4 0 .0 1 u _5 0 V _ X 7R _ 04 0 . 0 1u _ 5 0V _X 7 R _ 0 4
Sheet 31 of 42
5VS, 3VS, 1.5VS 5V 5VS 1.5VS
N MOS
S Y S 1 5 V V D D5 P Q 4 6A SYS1 5 V V DD 5 P Q 45 A 5 VS S Y S 15 V 1 .5 V
NMO S 1 .5V S
M T N N 20 N 03 Q 8 5V M TN N 2 0 N 0 3 Q8 P Q 1 6A
8 2 8 2 M TN N 2 0 N 0 3 Q 8
P R 1 13
3A 7 1 3A 5V
P R1 1 2
7 1
P R2 1 4
8
7
2
1
Power Plane
1 M_ 0 4 1M _ 04 PC1 9 2 1M _ 04
3
3
P C1 9 1 P C1 9 0 P R1 1 1
3
Z 3 5 06 Z3507 0 . 1u _ 1 6 V _ Y 5 V _ 04
1 .5 VS_ EN 0 .1 u _ 16 V _ Y 5V _0 4 10 u _ 6. 3V _ X 5 R _ 0 6 10 0 _ 1 %_ 0 4
4
4
P Q4 6 B P Q 45 B
Z 3 51 5
4
M T N N 20 N 03 Q 8 M TN N 2 0 N 0 3 Q8 PQ 1 6 B
D
P C 73 P C7 2 M TN N 2 0 N 03 Q 8 P Q1 5
5 D D _ ON # 5 P C1 9 3 MT N 7 0 0 2 Z H S 3
S US B 33 5 S US B G
4 7 0 p_ 5 0 V _ X7 R _0 4 47 0 p _5 0 V _ X 7 R _ 0 4
1
1
22 0 0 p _5 0 V _ X 7R _ 04
6
S
P J 15 P J1 6
6
4 0m i l 40 m i l
2
2
VA 37
1 .5 V S _ C P U 4 , 7
ON ON 1 .5 V 4 ,9 , 1 0, 11 , 2 1 , 2 3, 2 7 , 2 9 ,33 ,3 6
3 .3 V 3. 3V S 1 .5 V S 2 0 ,2 3, 3 6
SY S5 V 3 2 ,3 7
5V 2 1 ,2 4, 3 0 ,3 3 ,3 4
3 .3 V 3 ,4 , 1 2, 14 , 1 5 , 1 6, 1 8 , 1 9 ,20 ,2 1 ,2 3 , 24 ,2 5 , 2 9, 30 , 3 3 ,3 4, 3 5
C1 3 0 C1 0 0 C 184
0.0 1 u _ 50 V _ X 7 R _ 0 4 0 . 01 u _ 5 0V _X 7 R _ 0 4 0 .0 1 u _5 0 V _ X 7R _ 0 4 1.5VS_CPU V IN 1
V IN
V D D5
32
1 2 ,3 0, 3 2 ,3 3 ,3 4,3 5 , 3 6 , 37
32
V D D3 1 4 ,2 3, 2 5 ,2 8 ,2 9,3 2 , 3 7
3.3V 3.3VS 1 .5 V
P J7
OP E N _ 2A
1 .5 V S _ C P U
PJ3 MUST SHORT

3 .3 V S
S Y S 1 5V
2 ,1 0 ,11 ,1 2 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8 ,1 9,2 0 ,2 1 , 23 ,2 4 , 2 5, 26 , 2 7 ,2 8, 2 9 ,3 0 , 35 ,3 6
32
2 1 5 VS 2 ,1 3 ,17 ,2 0 , 2 1 , 26 , 2 7 , 3 0, 3 5 , 3 6
N MOS 3 .3 VS SYS1 5 V
S Y S 1 5 V V D D3 P Q 4 0A 3 .3 V SYS1 5 V P Q1 4 A
V DD 3
M T N N 20 N 03 Q 8 M T N N 20 N 03 Q 8 P Q 4A NM OS P R 73
3A 8
7
2
1
3A 8
7
2
1 P R7 6 8
*M T N N 20 N 0 3Q 8
2 *2 2 0 _0 4
P R 1 92 P R1 1 0 7 1
Power Plane
* 1 M_ 0 4
1 M_ 0 4 1 M _0 4 P C6 9 P C7 1 P R1 0 9 P C2 7 PC 2 6
Z 35 1 6
3
3
Z 3 5 08 Z3509 0. 1u _ 1 6V _Y 5 V _ 04 1 0u _ 6 .3 V _X 5 R _0 6 *1 0 0 _1 % _ 0 4 1 .5 V S _ CP UE N *0 .1 u_ 1 0 V _ X 7R _ 04 * 10 u _ 6 . 3V _X 5 R _ 0 6
4
4
P Q4 0 B P Q1 4 B Z 3 5 10 PQ 4 B
D
D
M T N N 20 N 03 Q 8 M T N N 20 N 0 3Q 8 P Q1 3 *M T N N 20 N 0 3Q 8 PQ 3
P C 1 67 P C7 0 *M T N 7 0 02 Z H S 3 P C2 8 *M T N 7 0 02 Z H S 3
5 D D _ ON # 5 SU SB G 5 SU SB G
2 2 0 0p _ 5 0V _X 7 R _ 0 4 2 2 0 0 p_ 5 0 V _ X7 R _0 4 * 2 20 0 p _ 50 V _ X 7 R _ 0 4
S
S
6
6
ON ON
B - 32 5VS, 3VS, 1.5VS

Schematic Diagrams
Power 3.3V/5V
S YS5 V
P D7
P C1 6 8 B A T 54 S W GH
0 . 0 1 u _ 50 V _ X 7 R _ 0 4 A 1
SY S5 V
C8 8 L GA T E 1 Z3613 3 C
A 2 SY S1 0 V
VIN 1 VIN 0. 01 u _ 5 0V _X 7 R _0 4
P D6 P C 16 2
Z 36 0 4 P R 2 04 2 _0 6 P C1 6 9 B A T 54 S W GH
A C 0 . 0 1 u _ 50 V _ X 7 R _ 0 4 A 1 2 2 00 p _ 5 0V _X 7 R _ 0 4
P C 1 83 P C 18 4 Z3614 3 C
2 . 2 u _1 6 V _ X 5 R _ 0 6 1 0 0 0 p_ 5 0 V _ X 7R _ 04 PR 1 9 6 P D 2 0 R B 0 5 4 0S 2 A 2
SY S1 5 V
I N TV C C 2
6- 13- 4223 1- 28B 2_06 P C 16 3
P R2 0 3 4 2 2K _1 % _ 0 6 S GN D 4 Z 36 0 5 2 2 00 p _ 5 0V _X 7 R _ 0 4
Z3606
P R2 0 5
PR 1 9 0 P R1 9 5 7 5 K_ 0 4 P C4 6 P C5 2 P C5 3
PU8 P C 18 1
21
5
1 0 K _ 1 %_ 0 4 2 0 K _ 1 % _0 4 1 u _2 5 V _ 0 8
4. 7u _ 2 5 V _ X 5 R _ 0 8
4 . 7 u _ 25 V _ X 5 R _ 08
0. 1u _ 5 0 V _ Y 5V _0 6
V OU T
FB
VD DA
FBL
PAD
NC
S G ND 4 S GN D 4
Z 3 6 02 20 6 Z3607
EN L V IN
Z 3 6 03 19
R T ON VL D O
7 P C1 7 2
INT V C C2
VDD5
1 u _2 5 V _ 0 8
18 8 Z3608
5
6
7
8
A G ND SC418 BST PQ 1 1 S Y S 5V V D D5
Z3601 17 9 Z3609 4 P1 2 0 3 BV PL 8
EN /PSV D H 4 . 7 U H _ 6. 8 * 7. 3* 3 . 5 PJ 2 3
16 10 Z 3 6 1 0 1 2 5A 1 2
1
2
3
P GO O D
IL IM LX
P GN D
R PSV
VD DP
PC 1 7 3 PC 1 7 9 P R1 9 8 P C1 7 5 P R1 9 3 *O P E N - 5m m
Sheet 32 of 42
D L
5
6
7
8
P Q7
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C
P 1 20 3 B V P R1 8 5 P C 18 5 P R2 0 8
1 0 0 0p _ 5 0 V _ X 7 R _ 0 4
4
15
14
13
11
L GA T E 1
12
Power 3.3V/5V
1 u _ 2 5V _ 0 8
1 0 K _ 1 % _0 4
1 3 7 K _ 1 % _0 4
PD 5 P D8 *2 . 2 _ 0 6 *2 2 0 p _ 50 V _ 0 4 9 3. 1 K _ 1 % _ 0 6
OCP
1
2
3
*S K 3 4 S A
PC 1 6 5 P C5 4 P C1 7 0
CSO D1 4 0 SH
Z 36 1 1
A
P R1 9 1 1 0 K _ 1% _ 0 4 P C1 6 1 + + P R2 0 9
0 . 1 u _ 50 V _ Y 5 V _ 06 *1 5 mi l _ s ho rt _ 0 6
P R 18 6 Z 36 1 2 P R1 8 7 *1 0 0 K _ 1 % _0 4 P C 18 6 P R2 0 1 * 1 50 u _ 6 . 3V _V _A 22 0 u _ 6 . 3V _6 . 3 * 6. 3 * 4. 2
*2 2 0 0p _ 5 0 V _ X7 R _ 04
1 1 3 K _ 1% _ 0 4 P C 16 6 P C 1 77 * 10 0 p _ 50 V _ N P O _0 4 1 0K _1 % _ 0 4
2009/12/22 S GN D 4
S G ND 4 S G ND 4 S G ND 4 S GN D 4 1 u _2 5 V _ 0 8 1 u _ 25 V _ 0 8
S GN D 4
S YS5 V I NT V C C2
P R2 0 2 PR 2 0 0
* 1 5m i l _ sh o rt _ 0 6 * 0 _0 6
P R 18 8 *9 . 1 K _ 0 4
S YS5 V
A
P R 2 07 V IN
P D2 1 *1 5 m i _l s h o rt _ 06
OCP RB 0 5 4 0 S 2
10 0 p _ 50 V _ N P O _ 0 4
P C5 7 PC 5 5 P C5 6
Ra
C
5
6
7
8
4. 7u _ 2 5 V _ X 5 R _ 0 8
P R 1 89 1 0K _1 % _ 0 4
P R1 9 4 P R1 9 9
P C1 8 7
Z3625
Z3618 4 0. 1u _ 5 0 V _ Y 5 V _ 0 6 4 . 7 u _2 5 V _ X 5 R _ 0 8
1 0 K _ 1 % _0 4 1 0K _1 % _ 0 4 P R 1 97
VDD3
1
2
3
0_04 P C1 7 8 PQ 8
P U9 P 1 2 0 3B V
13
14
15
16
S C4 1 2 A 0. 1 u _ 5 0V _Y 5 V _ 0 6 SY S3 V
PJ 2 2 V DD 3
5A
N .C
N .C
D H
IL IM
Z 3 6 15 12 1 Z3619 1 2 1 2
EN LX
11 2 Z3620 PL 9 *O P E N -5m m
PG D BST
4 . 7 U H _ 6 . 8 *7 . 3 *3 . 5
10 3
5
6
7
8
Z 3 6 16 Z3621 P Q4 1 P R 1 84
V O UT V CC
C
P 1 20 3 B V P C 44 P C 1 74
Z 3 6 17 9 4 Z3622 4 * 2. 2 _ 0 6 +
FB DL P D1 8 PD 1 7 0 . 1 u _5 0 V _ Y 5 V _ 0 6
G N D
R TN
1
2
3
N .C
17
N.C
P C1 8 2 * S K 3 4S A 2 2 0 u_ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
Rb PAD P C 1 80 P C 1 60
C S O D 1 40 S H
A
P C1 7 1 P R2 0 6 P C 1 76
*4 7 p_ 5 0 V _ N P O _ 0 4
1 u _2 5 V _ 0 8
0 . 0 1 u _5 0 V _ X 7 R _ 0 4 2 . 94 K _ 1 % _ 0 4 0 . 0 1 u_ 5 0 V _ X 7R _ 0 4 * 22 0 0 p _5 0 V _ X 7 R _ 0 4
V IN 1 31
SY S1 5 V 31
V DD 3 1 4 , 2 3 , 2 5, 28 , 2 9 , 3 1 , 37
V D D5 31
S Y S 5V 3 1 ,3 7
V IN 1 2 , 3 0 , 3 1, 33 , 3 4 , 3 5 , 36 , 3 7
Power 3.3V/5V B - 33
Schematic Diagrams
Power 1.5V/0.75V, 1.8VS

5V 3 .3 V
VD DQ VIN
P R8 8
A
P R9 4 P R 96 10 0 K _ 1% _ 0 4
PD 4
(1.5V=1.517V) 1 . 5 M_ 0 4 1 0 _0 6 R B 0 54 0 S 2
P U3
3 7
C
P R 95 10 _ 0 6 Z3801 DD R1 .5 V _ P W RG D
V D D QS P GD D D R 1 . 5 V _P W R G D 1 6
Ra VIN
P C 58 P C 59 PC 5 0
PR 9 7 Z3802 2
0 . 1 u_ 5 0 V _Y 5V _ 0 6
0 . 1 u_ 5 0 V _ Y 5V _0 6
T ON
1 0 0p _ 5 0V _N P O_ 0 4 1 K _ 1 %_ 0 4 1 u_ 2 5 V _ 08 1 u _ 25 V _ 0 8
PR9 1
Z3803 6 *1 5 m li _ s ho rt _ 0 6
8 FB 24 Z3812 Z3813
RE F BST
P C1 5 3
+ P C1 5 8
PC1 5 4
P R8 6 Z3805 9 PC 4 5
C O MP
5
6
7
8
PR8 9 0 . 1 u _5 0 V _ Y 5 V _ 0 6 P Q 37 15 u _ 25 V _ 6 . 3 *4 . 5 _E LN A
10 _ 0 6 P C4 3 *1 5 m li _ s ho rt _ 0 6
P R8 5 Rb 23 Z3814 Z 3 8 15 4 M DS 2 6 5 9
PR 9 0 * 0. 1u _ 1 0V _ X 7 R _ 0 4
Z3806 10
DH
1.5V
1
2
3
10 _ 0 6 1 0 0 K _1 % _ 0 4
VT TS
1 00 0 p _5 0 V _ X 7 R _ 0 4
P R 87
Z 3 80 8 Z3807 5 21 Z3816 V D DQ
V C CA IL IM OCP
PL 6 2 . 5 U H _ 10 * 10 * 5 PJ 9
P C4 0
P C 37
P R8 0 PC 5 1 7. 1 5 K _ 1 %_ 0 4
22 Z3817 8A 1 2
P C4 9
LX 1 .5 V
1u _ 2 5V _0 8 *0 . 0 6 8u _ 5 0V _0 6 *1 5m i l _s h o rt _ 06 19 Z3818 P Q3 5 P Q3 6 OP E N _ 8 A
D L
5
6
7
8
5
6
7
8
1 u _ 25 V _ 0 8 *M D S 2 6 55
5 6 0 u_ 2 . 5 V _ 6. 6* 6. 6 * 5. 9
VTT_MEM
C
VSSA 4 MD S 2 65 5 + P C1 4 3 P C 1 50 P C1 5 2
PC1 4 7
VSSA 4 4 +
PD 1 5
P J 20 Z3809 14 20 PD 1 6 *2 20 u _ 2 . 5V _ B _ A 0 . 0 1 u _5 0 V _ X7 R _0 4
1.5A 0 . 1u _ 5 0V _Y 5 V _0 6
Sheet 33 of 42 2 1 15 VT T V DD P 1 5V
1
2
3
1
2
3
* SK3 4 SA
V T T _ ME M VT T
*1 0 u _6 . 3 V _ X 5 R _ 0 6
P C3 9
1 0 u_ 6 . 3 V _ X 5R _ 06
CS O D1 4 0 S H
12
A
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
O P E N_ 2 A
VDD Q V D DP 2
Power 1.5V/0.75V, 13
V D DP 2 25
1u _ 2 5V _ 0 8
PC 33
*1 0 u _6 . 3 V _ X 5 R _ 0 6
P C 15 5 P R7 9
PC3 4
PC3 5
+ P C3 8 1 P GN D 2 18
PC3 6
* 22 0 u _2 . 5 V _ B _ A EN /PSV P GN D 1 16 P R1 8 1
1.8VS *2 0 K _ 1 %_ 0 4 1u _ 2 5 V _0 8 11
VT TEN
P
P
GN D
GN D
1
2
17 * 15 m i _l s h ort _ 0 6
VSSA
S C 48 6
P R9 2 47 K _ 1 % _0 4 1 .5 VEN
5V
3
D
D
P Q 10 B P C4 8
P R9 3 1 0 0K _ 1 % _ 04 Z 38 1 9 G 5 M TD N 7 0 0 2Z H S 6 R P Q9
6 S G 0 . 1 u _ 50 V _ Y 5 V _ 0 6
D 4 *M TN 7 00 2 Z H S 3
1
DDR3 VDDQ --> 1.5V ( V POWER)
S
P J1 1
G 2
1 6 ,2 8 S US C #
S 4 0m i l
2
1
P Q1 0 A
MT D N 7 00 2 Z H S 6 R
3 0, 3 1 D D _ ON #
P R8 3 1 0 0 K _1 % _ 0 4
330uF*3 , 10uF*6
5V
4 , 1 6 , 3 4 1 . 1 V S _ V T T _P W R G D
P R8 2 * 10 0 K _ 1 %_ 0 4 V T TE N VTT-->0.75V ( VS POWER)
P R1 8 2 1 0 0_ 1 % _ 04 6
V T T_ M E M
3
D S US B G
D
2 P Q 6A
P C 41
0 . 1 u_ 5 0 V _ Y 5 V _ 06
10uF*3, 1uF*4
PQ 6 B S
SU SB G 5 M T D N 70 0 2 Z H S 6 R 1 MT D N 7 0 02 Z H S 6 R
31 S US B
S
4
ON
3 .3 V
5V
1 0K _0 4
3. 3V
P C1 5 7 1.8VS
P R1 8 3 2A P U7 1u _ 2 5V _0 8
5 6 VS1 .8 1 .8 V S
9 VIN
VIN
V C N TL 3A PJ 1 0
1 .8 V S _ P W RG D 7 4 1 2
1 6 1 .8 V S _ P W RG D P OK V OU T
1 0 u _6 . 3 V _ X 5 R _ 0 6
3
1 0u _ 6 . 3V _X 5 R _0 6
0 . 1 u_ 1 0 V _X 7R _ 04
OP E N _ 3 A
P R 81 1 0 K _ 04 E N 1. 8 V S 8 V OU T P R1 7 9
5V EN
1. 2 7 K _ 1 %_ 0 4
1 2
GN D VFB
D
P C3 2 P C1 4 8
7 ,2 0 1 . 8V S
PQ 5 AX6610
PR8 4 62 K _ 1 % _0 4 G * 1 u_ 2 5 V _ 08 P C1 4 9 P C 1 56 1 2 , 30 , 3 1 , 3 2, 3 4 , 3 5 , 36 , 3 7 VIN
31 SU SB 2 1, 2 4 , 3 0 , 31 , 3 4 5V
M T N 7 00 2 Z H S 3 82 p _ 50 V _ N P O_ 0 4
3 , 4, 12 , 1 4 , 15 , 1 6 , 1 8, 1 9 , 2 0 , 21 , 2 3 , 24 , 2 5 , 2 9, 3 0 , 3 1 , 34 , 3 5 3 . 3V
S
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
0. 1 u _ 50 V _ Y 5 V _ 0 6
4, 9 , 1 0 , 11 , 2 1 , 2 3, 2 7 , 2 9 , 31 , 3 6 1 . 5V
P C4 2 P R1 8 0
P C1 4 5
P C 1 44
P C 14 6
1K _ 1 % _ 04 1 0 ,1 1 V T T_ M E M
0. 1 u _ 50 V _ Y 5V _ 0 6
GS7113 6-02-07113-320
AX6610 6-02-06610-320
APL5930KC 6-02-05930-420
B - 34 Power 1.5V/0.75V, 1.8VS

Schematic Diagrams
Power 1.1VS_VTT
5V
VIN
OCP
A
PD 9
P R 99
6 .4 9K _1 % _ 04
R B 05 4 0 S 2 1.1VS_VTT=0.75 X (1+PR101 / PR102)
C
P C 16 4
+
5
6
7
8
5
6
7
8
PQ 3 9 P Q 38 1 5u _ 2 5V _6 . 3 *4 . 5 _ E LN A
4
M D S 2 6 59
4
* IR F 7 4 13 Z P B F
V T T _S E N S E 6
1.1VS_VTT
2
3
1
2
3
1
P C6 1
ON PU 5 25A(15A)
1 .1 V S _ V T T_ E N _R S C 41 2 A 0 .1u _ 5 0V _Y 5V _0 6
15
16
13
14
PL 7 V T T 1.1 V S P J2 1 1 .1V S _V T T
P R1 0 3 1 0 K_ 0 4 0 .5 6U H _ 1 0* 1 0* 4. 1
G 0
G 1
3. 3V
D H
IL IM
12 1 1 2
EN LX
11 2
5 6 0 u_ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
5 6 0u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
4,1 6 , 3 3 1. 1 V S _ V T T _P W R GD *OP E N -1 2 mm
PG D B ST
10 3
C
5
6
7
8
5
6
7
8
P Q4 2 P Q4 3
V O UT VC C MD S 26 5 5 MD S 26 5 5 P D 19
FB 9 4 4 4
FB DL
SK3 4 SA
R TN
G ND
2
3
1
2
3
1
17
D 0
D 1
PAD
A
P C6 8
8
7
6
5
P C6 0
+ 0. 1 u _ 50 V _ Y 5 V _ 0 6 +
1 u _ 25 V _ 0 8
Sheet 34 of 42
P C 1 51
P C 15 9
P R 10 5 P R 1 01 P C6 5
Power 1.1VS_VTT
0 _ 04 1 0 K _ 1% _ 0 4 *2 0 p_ 5 0 V _ N P O_ 0 4
P R1 0 6 *9 0 . 9K _1 % _ 04
5V
P C 66
P R 1 02
0 . 1 u_ 1 0 V _X 7 R _ 0 4
2 4 K _ 1% _ 0 4
(1.1VS_VTT=1.067V)
PJ 1 4
1 2
4 0m i l PJ 1 3
P R1 0 7 1 0 K_ 0 4 1 2 1 .1V S _V TT _ E N _ R
5V
4 0 m li
D 12 P R1 0 0
3
S C D3 4 0 *1 0 0K _ 1 % _0 4
C A D
P Q 1 2B P R1 0 4
G 5 * 2N 7 00 2 K D W
6 S *1 0K _0 4
4
1
D P Q1 2 A
P R 1 08
*2 N 7 0 02 K D W PJ 1 2
G 2
1 6 1 . 1V S _V T T _ E N 4 0m i l
S
1
2
1 0 0K _1 % _ 04
P C6 7
*1 u_ 2 5 V _ 08
2 ,4,6 ,7 , 1 4 ,15 ,1 6 , 19 , 2 0 ,21 , 3 5 ,3 6 1 .1 V S _ V T T

3 , 4 ,1 2 , 14 , 1 5 ,16 ,1 8 , 19 ,2 0 , 2 1, 2 3 ,2 4,2 5 , 2 9, 3 0 , 3 1, 33 ,3 5 3.3 V
2 1, 2 4 , 3 0, 31 ,3 3 5V
1 2 ,3 0,3 1 , 3 2, 3 3 , 3 5, 36 ,3 7 V I N
Power 1.1VS_VTT B - 35
Schematic Diagrams
Power VGFX_Core
1 .1V S _ V TT
PJ 4 4 0 mi l
P R 71 10 K _0 4 2 1
3. 3 V
1 K_ 0 4
1 K _0 4
1K _ 0 4
1K _ 04
* 1K _ 04
*1K _ 0 4
*1 K _0 4
7 D F GT _V I D _0
7 D F GT _V I D _1
7 D F GT _V I D _2
7 D F GT _V I D _3
7 D F GT _V I D _4
7 D F GT _V I D _5
7 D F GT _V I D _6
PR6 9
PR6 8
P R 67
PR6 5
PR6 4
P R 70
P R 66
D F GT _V I D _ 0
D F GT _V I D _ 1
D F GT _V I D _ 2
D F GT _V I D _ 3
P J5 4 0m i l D F GT _V I D _ 4
P R7 2 1 K _0 4 2 1 D F GT _V R _ E N D F GT _V I D _ 5
3. 3 V S D F GT _V I D _ 6
3.3VS
*1 K _0 4
*1 K _0 4
*1 K _ 04
1 K _ 04
*1 K _0 4
1 K _0 4
1K _ 04
7 D F GT _V R _E N 5 VS
P R4 2 P R4 8
V IN
4 70 _ 04 1 0 K_ 0 4
PR5 8
PR5 7
P R 56
PR5 4
PR5 3
P R4 1
P R 59
P R 55
1.1 VS_ VTT
4 . 7 u_ 25 V _ X 5R _ 0 8
4 . 7 u_ 25 V _ X 5R _ 0 8
*4 . 7 u_ 25 V _ X 5R _ 0 8
1 0_ 06
0 . 1u _ 50 V _Y 5 V _0 6
*0 . 01 u_ 5 0V _ X 7R _0 4
Sheet 35 of 42 P R6 2
*10 K _ 1% _0 4 V GF X_ V OR E_ P G P C1 1 6
VGFX_CORE
Power VGFX_Core 7 GF X _IMO N
1 u_ 6 . 3V _ X5 R _ 04
15A(7A)
5
6
7
8
3. 3VS P Q18
4
P C 80
P C 83
PC9 2
P R 21 7 MD S 2 65 9 (0. 7V~1 .77V)
32
31
30
29
27
25
PC7
PC5
28
26
0_ 04
1
2
3
G N D _ 32 1 1 V GF X _C O R E
V ID 1
V ID 3
EN
V ID0
V ID2
V ID4
V ID5
V ID6
24
2
P R 34 P R 38 P C1 4 GP U
PC 18 P R6 1 1 V CC 0 _ 06 0.2 2 u_ 50 V _ 06 P J 19
*1 0K _ 0 4 P WR GD 23
BST O PE N _8 A
0.1 u_ 5 0V _ Y 5 V _0 6 4. 7 K _1 %_ 0 4 2
IMON
1
22 3 2 11 _D R V H PL 3
3 21 1_ C L K E N # 3 DRV H 1 .0 U H _1 0* 10 *4 .5
C LK E N # 21 3 2 11 _S W 1 2
4 PU2 SW
F BR TN
* 0. 1 u _1 0V _ X 5R _0 4
20
5 6 0u _2 . 5 V _6 . 6* 6. 6 *5 . 9
*0 . 01 u _5 0V _ X 7 R _0 4
5 P V CC 5VS
PC 21 22 0p _ 50 V _N P O_ 04 P R 16 5
PC 19 5 FB A D P 3 21 1 19 3 2 11 _D R V L
P C2 3 6 DR V L P C 19 4 * 2. 2 _0 6
C OMP 18
10 0 0p _5 0 V _X 7 R _ 04
C
P C1 9 7 P GN D
5
6
7
8
5
6
7
8
4 7p _ 50 V _N P O_0 4 2 .2 u_ 16 V _ X5 R _ 06
P R 43 20 K _1 % _0 4 GP U 17 P Q 23 P Q22 P D1 2
8 A GN D 4 4 MD S 2 65 5
ILIM
CS COM P
PR 50 33 MD S 2 65 5 S K 3 4S A
A GN D
CSREF
1
2
3
1
2
3
RAM P
L L INE
1K _ 1% _ 04 47 0p _ 50 V _X 7 R _0 4 P C 12 5 +
C SF B
IRE F
RPM
A
R T
* 22 00 p _5 0 V_ X 7 R _0 4
P C 13 3
P R4 9
P C 1 34
P C 13 2
0 _0 4 P R2 1 8
9
10
11
12
14
16
13
15
5VS GN D _3 2 11
GN D _3 2 11
7 .5K _ 1% _ 04
GPU App. Place RTH1 close to

PR 21 9 RT 1
3 2 11 _C S C O M P
3 2 11 _ C S C O M P
3 21 1 _C S C O M P
P R 22 0 P R2 2 1 P R2 2 2 10 0 K_ N T C _ 06 _ B inductor on the same layer
0 CPU *0_ 0 4 2 1
2 0 0K _ 1% _ 04
3 3 2K _ 1% _ 06
80 . 6K _ 1 %_ 04
1 GPU
P R 1 67
1 10 K _1 %_ 0 6
GN D _3 21 1
GN D _3 2 11 P R 22 3 P C2 0 P C 12 7 P R3 6
GP U V C C S EN S E 7 GN D _ 3 21 1
1 50 0 p_ 5 0V _ 04 2 2 0p _ 50 V _N PO _0 4 1 80 K _1 %_ 0 4 P R 24 0
4 2 2K _ 1% _ 06
G N D _ 32 1 1 16 0K _ 1 %_ 04
P R2 2 4 1 00 _ 1% _0 4
GPU distribute evenly betw een N side and Sside,
P R2 2 5 1 00 _ 1% _0 4 pref erably on secondary side.
P R2 2 6 1 K _ 1% _0 4
VIN
GP U V S S S E N S E 7
P C 19 6 P C 11 2
1 00 0p _ 50 V _X 7 R _ 04 1 0 00 p_ 5 0V _ X7 R _ 04
GN D _3 21 1GN D _ 3 21 1
2 ,4 , 6 ,7,1 4,1 5 , 16 ,19 ,2 0,2 1,3 4 ,36 1. 1 V S _V T T
3,4 , 12 , 14 ,1 5,1 6,1 8 , 19 ,20 ,2 1,2 3,2 4 ,25 ,29 ,3 0,3 1,3 3 ,34 3. 3 V
4, 9 ,1 0,1 1,2 1 , 23 ,27 ,2 9,3 1,3 3 ,36 1. 5 V
7 V G F X_ C OR E
1 2,3 0 , 31 ,32 ,3 3,3 4,3 6 ,37 V IN
2 ,1 3,1 7,2 0 , 21 ,26 ,2 7,3 0,3 1 ,36 5V S
2 , 10 , 11 , 1 2,1 3,1 4 , 15 , 16 , 17 ,1 8,1 9,2 0 , 21 ,23 ,2 4,2 5,2 6 , 27 ,28 ,2 9,3 0,3 1 ,36 3. 3 V S
B - 36 Power VGFX_Core
Schematic Diagrams
V-Core
V IN
FOR EMI
P C 1 97
*1 n_ 5 0V _ 0 4
S GN D 2
*1 5 u_ 25 V _ 6. 3 *4 . 5 _E L N A
*1 5u _ 25 V _ 6. 3 *4 . 5_ E L N A
1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
* 33 0u _ C A R 3 1 5L
0 . 1u _ 50 V _ Y 5V _ 0 6
0 . 1 u_ 5 0V _ Y 5V _ 0 6
0 . 1 u_ 5 0V _ Y 5 V _0 6
0. 1 u _5 0V _ Y 5 V _0 6
0. 1 u _5 0 V _Y 5 V _0 6
0 . 1u _5 0 V _Y 5 V _ 06
0 . 1u _ 50 V _ Y5 V _ 06
0. 1 u _5 0V _ Y 5 V _0 6
0 . 1 u_ 5 0V _ Y 5V _ 0 6
*4 . 7 u_ 2 5V _ X 5R _0 8
0 . 1u _5 0 V _Y 5 V _ 06
0. 1 u _5 0V _ Y 5 V _0 6
P R2 2 7
*4 7 K _0 4 P C1 9 8
1 u_ 2 5V _ 0 8
CS _ PH1 P R 17 3 2 00 K _1 % _0 6
CS _ PH2 P R 16 8 2 00 K _1 % _0 6
VIN +
P R 24 1 1 62 K _ 1% _ 06
P R 22 8 1 K _ 04 + +
+
PC1 4 0
RT1 close to PL6 P Q2 9 P Q 34
P C3 0
P C2 2
PC3
P C 75
P C2 5
P C 79
P C9 7
P C7 6
1
PC7 8
PC8 7
P C 13 6 P C 19 9 1 0 00 p _5 0 V _X 7R _0 4 MD U 26 5 7 * I R F H 7 92 3
P C 10 1
PC3 1
P C 88
PC9 8
RT 3 P R 24 2 1 5 00 p _5 0V _ 0 4
P C 1 28
10 0 K _N TC _0 6_ B 7 3 . 2K _ 1 %_ 0 4
P C 1 38 S GN D 2 G G
1 6 2K _ 1 %_ 0 6
47 . 5 K _1 % _0 4
8 0. 6 K _ 1% _0 4
4 70 p_ 5 0V _ X 7R _0 4
6 80 K _ 1% _ 04
VCORE
S
H DR 1
C S C O MP
CS COM P
S GN D 2 V CO RE
CSSU M
C S REF
3 .3 VS 3 . 3V S P R 1 75
1 .6 9 K _1 % _0 4 P L5
0 . 36 UH _1 2 .9 *1 4 *3 . 8
24A
PR2 2 9
P R 23 0
PR2 3 2
P R 2 31
2 2 0u _ 6. 3 V _ 6. 3 *6 . 3* 4. 2
56 0 u_ 2 .5 V _ 6. 6 *6 . 6 *5 . 9
D
33 0 u_ 2 . 5V _ V _ A
P U1 PC2 0 0 P R1 7 1
*3 3 0u _ 2. 5 V _V _ A
* 33 0 u_ 2 . 5V _ V _A
CS_ PH1
D
C
P R2 P R4 5 VS P Q2 8 5 . 1_ 0 6
ADP321 2
24
21
20
18
17
14
13
23
22
19
16
15
G MD U 2 65 4 P Q3 3 P D 14 P R 1 72
0 . 22 u _5 0 V _0 6
3 K _1 % _0 4 3K _ 1 %_ 0 4 G MD U 26 54
R T
PW M 3
O D3 #
C SSUM
RAM P
IR E F
SW FB3
I LI M
RPM
C S C O MP
LL I N E
S
CSREF
P R9 SK3 4 SA 10 _ 06
1 00 _ 1% _ 04
V R _ON 1 36
S
2_ 0 6 BST 1 P C1 3 1
EN B S T1
A
4 ,1 6 DE L A Y _ P W RG D 2 35
3 P W R GD D RVH1 34
6 I MON P R5 2 20 p _5 0 V _NP O _0 4
4 I MON SW 1 33 10 0 _0 6 C S _P H 1 VIN + + + + +
2 CL K E N# 5
6
7
CL K EN#
F B RT N
FB
SW FB1
PVC C
D R V L1
32
31
30
5 VS
CS R E F Sheet 36 of 42
P C 13 5
P C1 3 7
P C 14 1
P C2 9 P R 2 33
1 5u _ 25 V _ 6. 3 *4 . 5_ E L N A
P C 1 39
P C 1 42
C OM P P GN D
10 0 0p _ 50 V _X 7 R _ 04 PC9 3 P C 86 P C 81 T RDET # 8 29 10 0 _0 6 P C 20 1 P Q 26 P Q 31
V-Core
* 4. 7 u_ 2 5V _ X 5 R _ 08
* 4. 7 u_ 2 5V _ X 5 R _ 08
9 TR D E T # D R V L2 28 C S _ P H2
1 5 0p _ N P O_ 5 0V _1042 p_ 5 0V _ N P O_ 0 4 5V S M D U 2 6 57 * I R F H7 9 23
0 . 1u _ 50 V _ Y5 V _ 06
V A RF R SW FB2
D
27
4 . 7 u_ 2 5V _ X 5R _0 8
PR1 7 6
S GN D 2 0. 1 u_ 5 0V _ Y 5 V _ 06 P C 20 2 SW 2 26
1 5 0p _ N P O_ 5 0V _ 04 10 D RVH2 25 G G P R 1 78
T T SN S 1 1 V RT T B S T2
DPRSL P
12 TT S N S +
S
10 _ 06
V ID 6
V ID 2
PH 0
P S I#
V ID5
V ID4
V ID3
V ID1
V ID0
VCC
A GN D
PH1
RSN
PR7 7 P R 12 6 P R 12 1 49
RSP
CS _ PH2
A GN D
P C 95
P C 10 6
5. 4 9 K _1 % _0 4 1 . 6 K _1 % _0 4 39 . 2K _ 1 %_ 0 4
P C 1 29
P C 1 05
HD R 2
24A
37
40
41
43
44
47
48
38
39
42
45
46
S GN D 2 PL 4
5V S 0 . 3 6U H _ 12 . 9* 14 *3 . 8
4 H _ P R O C H O T#
P C8 2 P R1 7 0
D
D
P R2 1 6 P R 2 43 5 . 1_ 0 6
C
P Q 47 S GN D2 2 _0 6 0 . 22 u _5 0 V _0 6 P Q2 7
M TN 70 02 Z H S 3 G 1 0_ 0 6 B S T2 G MD U 26 54 P Q 32 P D 13
G M D U 2 6 54
S
S
SK3 4 SA P C1 3 0
S
1 . 1V S _ V T T
1 . 5V 1 . 5V S
A
P C6 2 20 p _5 0 V _NP O _0 4
1 u_ 2 5V _ 08
*6 4 9_ 1 %_ 0 4
64 9 _1 % _0 4
P R 2 34
1 K_ 0 4
1 K _0 4
1 K _ 04
1 K _ 04
*1 K _0 4
*1 K _ 04
*1 K _0 4
0 _0 4
S GN D 2 R SP
V C C _ S E NS E 6
P C 20 4
P R 19 0_ 0 4
6 P M _D PR S LP V R * 10 0 0p _5 0 V _X 7 R_ 04 P R 2 35
R SN 0 _0 4
6 P S I# P R6 0_ 0 4 V S S _S E N S E 6
2 PR1 5 4
PR2 6
PR2 7
P R 28
PR2 9
PR3 0
P R 31
PR3 2
P R 1 55
6 H _V I D 0
P R 23 6
P R2 0 6 H _V I D 1 PJ 1
6 H _V I D 2
*R _ 0 4 6 H _V I D 3 10 0 _1 % _0 4
4 0m i l
6 H _V I D 4
1
6 H _V I D 5
6 H _V I D 6
* 1K _ 0 4
* 1K _ 0 4
*1 K _0 4
*1 K _ 04
1K _ 0 4
1 K _0 4
1K _ 04
5 VS P R 2 37
5 VS 0_ 0 4
P R 1 43 1 0 K _0 4 V R _ ON
3. 3 V S
P R 23 8
PR1 3
PR1 4
P R 15
PR1 6
PR1 7
P R 18
PR3 3
P R 16 9 P R 15 6 P Q2 0B S GN D 2
5 . 1 K _1 % _0 4 3
7 . 3 2K _ 1 %_ 0 4 1 0 0K _ 0 4 MT D N 7 0 02 Z H S 6 R D
P R 1 19
T TS N S T R DE T # G 5
P Q 20 A S *1 0K _ 04
6 4
1
R T2 P C 20 3
P R 23 9 M TD N 7 00 2Z H S 6R D P J1 8
1 0 0K _ N T C_ 06 _ B 0 . 0 1u _5 0 V _X 7 R_ 04 4, 9 , 1 0, 1 1 , 21 , 2 3, 2 7, 2 9 , 31 , 3 3 1 .5 V
2 4 0 mi l 2 0 , 23 , 3 1 1 . 5 VS
* R _ 04 1 6, 2 8 V C OR E_ ON G 2, 4 , 6, 7 , 1 4, 1 5 , 16 , 1 9, 2 0, 2 1 , 34 , 3 5 1 . 1 VS _ V T T
2
S 6 V C OR E
1
1 2, 3 0 , 31 , 3 2, 3 3, 3 4 , 35 , 3 7 V IN
2 , 13 , 1 7, 2 0 , 21 , 2 6, 2 7, 3 0 , 31 , 3 5 5 VS
2, 1 0 , 11 , 12 , 1 3, 1 4 , 15 , 1 6, 1 7, 1 8 , 19 , 2 0, 2 1 , 23 , 24 , 2 5, 2 6 , 27 , 2 8, 2 9, 3 0 , 31 , 3 5 3 . 3 VS
P C 10 8
* 0. 1 u _1 0 V_ X 5R _0 4
V-Core B - 37
Schematic Diagrams
AC_IN, Charger
CHARGER VA
# Charge Current 3.0A
# Charge Volta ge 1 2.6V
P Q2 4
4
V IN P 20 0 3E V G # Total Pow er 60W
1 5
2 6
JA C K 1 3 7
50 9 3 2-0 0 3 01 -0 0 1 PL 1 VA P Q 17 8
H C B 45 3 2 K F -8 00 T 6 0 P 2 0 03 E V G P Q2 5 A
8 P R 1 14 A P 6 90 1 GS M PL 2 P R1 4 6 V _B A T
1 7 3 2
0 . 0 2 _1 % _ 32 4 . 7 U H _6 . 8 *7 . 3 *3 . 5 0 . 02 _ 1 %_ 3 2
2 6 2 1 7
G ND 1 5 1
PC 7 4 P C1 PC 2 PR1 1 8
G ND 2
0 _0 4
0 _ 04
4 . 7 u_ 2 5 V _X 5R _0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
5
6
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7u _ 2 5V _ X 5 R _ 0 8
4. 7u _ 25 V _ X 5 R _ 0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
PR 1 1 30 K _ 1 %_ 0 4
0 . 1 u _5 0 V _ Y 5 V _0 6
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
*0 . 3 3 u_ 5 0 V _0 8
0 . 1u _ 5 0V _ Y 5 V _ 0 6
0. 1u _ 50 V _ Y 5 V _ 06
0 . 1u _ 5 0V _ Y 5 V _ 06
4
8
20 0 K _ 1% _ 0 4
0 . 1u _ 5 0V _Y 5 V _ 0 6
P R 11 6
1 0K _ 0 4 P R1 5 7 3
PR1 1 7 0_ 0 4 P Q2 5 B
4
PR1 6 2
P R 16 1
A P 6 90 1 GS M
PC7 7
1 0K _ 1 % _0 4
P C 11
PC1 2
PC1 7
PC1 6
P C 11 1
P C1 2 0
P C1 1 8
P C1 1 9
P C1 1 0
P C1 1 5
P C 11 4
10 0 K _ 1% _ 0 4
P C1 5 0 . 1u _ 5 0V _ Y 5V _ 0 6
P C 10 7 P R 1 44
* 0_ 0 4
PD 3
V_ BAT 1 u _2 5 V _ 08 *1 0m i l _s h or t _0 4
C A PIN 25th
PR1 1 5
FOR 2S CONNECT TO GND
P C 10 3 P C 1 04 PC1 1 3 R B 0 54 0 S 2 FOR 3S CONNECT N.C.
Sheet 37 of 42 0 . 1 u_ 5 0V _Y 5V _0 6 0 . 1 u _5 0 V _ Y 5 V _ 06 0 . 1 u _5 0 V _ Y 5 V _ 06
FOR 4S CONNECT TO VREF PIN
P R 12
P R1 1 *0 _ 0 4
AC_IN, Charger V A
32
30
29
28
27
26
25
VA
31
V IN PU 6
P GN D
C B
LX
VB
C E LL S
CT L 2
OU T -1
O U T -2
1 24 PC 9 9 0. 1 u _ 50 V _ Y 5 V _ 0 6
2 VC C V IN 23 CT L 1 V DD 3
3 -I N C 1 C TL 1 22
P C 12 4 P C 1 23 P C1 2 2 P C 1 21
4 + INC 1 G ND 21 R1 7 1 0K _0 4
5 A C IN VR EF 20
0. 1 u _ 50 V _ Y 5 V _ 0 6 0 . 1 u _5 0 V _ Y 5 V _ 06 0. 1 u _ 50 V _ Y 5 V _ 0 6 0 . 1 u _5 0 V _ Y 5 V _ 06 TRERMAL PAD
6 A C OK RT 19 C
7 -I N E 3 C S 18 V OL T _S E L S MC _ B A T AC
0 . 1 u_ 5 0 V _Y 5V _ 0 6
P R1 4 7
O UT C 1
OU T C 2
C O MP 2
C OM P 3
8 AD J 1 A DJ 3 17 A
+ INC 2
AD J 2
S G ND6
-I N C 2
-I N E 1
0. 1 u _ 50 V _ Y 5 V _ 06
C O MP 1 BATT 33
39 . 2 K _ 1% _ 0 4
4 9. 9 K _ 1 %_ 0 4 D9
S G ND B A V 9 9 R E CT IF IE R
P R1 6 4 M B 3 9A 1 3 2 C
11
12
13
14
15
16
AC
9
10
S GN D 6 S MD _ B A T
1 0 K _1 % _ 04
A
PR1 6 6
V D D3 T OTAL 1 0K _ 1 % _0 4 P C9 4 CHARGE
1 0 0p _ 5 0V _ N P O_ 0 4 P R 1 40 P R1 4 9 D8
POWER CURRENT
1 K _1 % _ 04 B A V 9 9 R E CT IF IE R
ADJ P C1 2 6 1 K _1 % _ 04 ADJ C
P R 15 8 B A T_ D E T AC
0 . 01 u _ 50 V _ X 7R _ 04 P C1 0 0 *2 2 p _5 0 V _ N P O _0 4 A
PC1 0
P C 13
P R1 3 6
1 0 K _0 4 P C9 6 D7
1 0 00 p _ 50 V _ X 7R _ 04 P R 1 45 P R1 5 2 B A V 9 9 R E CT IF IE R
S G ND 6
2 0 K _1 % _ 04
A C _I N # 28 C
2 2K _ 1 % _0 4 S GN D 6 S GN D 6 S GN D 6 2 2K _ 1 % _0 4
PR1 6 3
C
P C1 0 2 AC
C A B P Q 30 1 0 00 p _ 50 V _ X 7R _ 04 P R 1 50 28 B A T _ V OL T A
VA D6
S G ND 6
P D1 1 P C 1 17 D TC 11 4 E U A 1 0 K _ 1% _ 0 4 S GN D 6 B A V 9 9 R E CT IF IE R
U D Z 1 6B
E
* 0. 1 u _ 50 V _ Y 5 V _ 0 6
V_ BAT
0.5V/1A TO T A L_ C U R
PIN 17th CONNECT
0.5V/1A CU R_ S E NS E TO BAT CONN.
E4120
P R1 3 8
5
1 02 K _ 1 %_ 0 4
PR 2 3 28 S MC _ B A T 4
28 S MD _ B A T 3
V OL T _ S E L
S YS5 V SYS5 V 28 B A T_ D E T 2
P Q2 1 P R 15 3 1
D
A O3 4 0 9 3 0 0K _1 % _ 04 2 M_ 1 % _0 4 J B A T TA 2
V _B A T S D B A T _ V OL T _ R P R1 3 9 * B T D -0 5 TI 1 G
P R 14 8 P R 1 41 G
7 6. 8 K _ 1 % _0 4
V C H G_ S E L 2 8 E5120Q
P R2 1 1 0 0K _ 1 % _0 4 1 0 0 K _1 % _ 04 P Q2
S
G
2 0 0 K _ 1% _ 0 4 P Q1 9 A MT N 7 0 02 Z H S 3 5
PR1 5 1 P C1 0 9 CT L 1
MT D N 7 00 2 Z H S 6 R 6 3 4
60 . 4 K _ 1% _ 0 4 0 . 1u _ 5 0V _ Y 5V _ 0 6 D D 3
2
P R2 2 P Q 1 9B
G 2 G 5 M TD N 7 0 0 2Z H S 6 R 1
* 1 0m i _l s h ort _0 4 28 C H G_ E N
S S
6-21-D34B0-105 J B A T TA 1
1 4
1
B TD -0 5T C 1 B
P J 17
D
PQ 1 O P E N - 1m m P R 13 5 *1 5m i l _s h o rt _0 6
2
G
S Y S 5V
M T N 7 00 2 Z H S 3 S G ND6
S
SY S5 V 3 1, 3 2
V D D3 1 4 , 2 3, 25 , 2 8, 29 , 3 1 , 32
VA 31
VIN 1 2 , 3 0, 31 , 3 2, 33 , 3 4 , 35 , 3 6
B - 38 AC_IN, Charger
Schematic Diagrams
Click Board
CLICK BOARD
CVDD3 CVDD3 CVDD3 CVDD3
CR360 CR359 CR361 CR358

CC2 CC1 CC3
0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *0.1u_16V_Y5V_04 220_04 220_04 POW ER O N 220_04 220_04
C5VS C5VS CVDD3 BAT LED
3
1 LED
CD27 CD26
2
SG
CGND CGND CGND
Y
SG
Y
CJ_TP1 CJ_TP2 CJ_TP3 RY- SP155HYYG4 RY-SP155HYYG4
1 1 1
4
CTP_DATA CTP_CLK CLED_PWR#
2 CTP_CLK 2 CTP_DATA 2 CLED_ACI N#
3 3 3
4 4 CTPBUTTON_L 4 CLED_BAT_FULL#
5 CTPBUTTON_R 5 CLED_BAT_CHG#
85201-04051 CLED_PWR# CLED_BAT_FULL#
CGND
6
85201-06051
6
85201-06051 CLED_ACIN# CLED_BAT_CHG# Sheet 38 of 42
6-20-94A50-104
6-20-94AA0-104
CGND CGND 6-52-55002-04B
6-52-55001-040
6-52-55002-04B
6-52-55001-040
Click Board
6-20-94A70-104 6-21-91A00-106 6-21-91A00-106 6-52-55002-042 6-52-55002-042
6-21-91A10-106 6-21-91A10-106
6-20-94A70-104 6-20-94A70-104
E5120Q
CSW1~ 4
2 4
1 3
LI FT RI GHT LI FT RI GHT
KE Y K EY KE Y K EY
CSW1 CSW2 CSW3 CSW4
TJG-533-S-T/R TJG-533-S-T/R *TJG-533-S-T/R *TJG-533-S-T/R
1 2 1 2 1 2 1 2
3 4 CTPBUTTON_L 3 4 CTPBUTTON_R 3 4 CTPBUTTON_L 3 4 CTPBUTTON_R
5
6
5
6
5
6
5
6
CGND CGND CGND CGND
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 6-53-3150B-245

6-53-3050B-240 6-53-3050B-240 6-53-3050B-240 6-53-3050B-240
6-53-3050B-241 6-53-3050B-241 6-53-3050B-241 6-53-3050B-241
CH3 CH1 CH4 CH2

2 9 2 9 2 9 2 9
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH237D91 MTH237D91 MTH237D91 MTH237D91

CGND CGND CGND CGND CGND CGND CGND CGND
Click Board B - 39
Schematic Diagrams
Audio Board/USB
USB PORT
A _U S B V C C AL 5 A _ US B VC C2
H C B 1 6 0 8K F -12 1 T 25 60 mil
A _ U S B V CC A _U S B V C C
AU 1 AC 1 A C7
A _5 V 5 6 50 mil s +
F L G# V OU T 1 1 0 0u _ 6 . 3V _ B _ A 0 . 1u _ 1 6V _ Y 5V _ 0 4
5 0mi ls 2 7
V I N 1 V OU T 2 A C5 A C6 A J_ U S B 1
A C9 3 8 A R1 0 *1 0 mi l _ sh o rt _ 04 1
V I N 2 V OU T 3 0. 1u _ 16 V _ Y 5 V _ 0 4 0 . 1u _ 16 V _ Y 5 V _ 0 4 L61 A G ND V+
1 0u _ 1 0V _ Y 5V _ 0 8 4 1 A US B _ P N 2 4 3 A US B _ P N2 _ R 2
EN # GN D D A TA _ L
R T 97 1 5B GS A US B _ P P 2 1 2 A US B _ P P 2 _ R 3
A GN D A G ND A G N D A GND A GN D *A W C M2 0 1 2F 2 S -1 6 1T 0 3 D A TA _ H
G ND 1
G ND 3
4
6-02-09715-920
GN D2
GN D4
A R1 1 *1 0 mi l _ sh o rt _ 04 G ND
U S 0 4 03 6 B C A 0 8 1
PIN SWAP
GND 1
GN D2
GND 3
GN D4
6-21-B49C0-104
6-21-B49B0-104
A G ND
TO M/B AUDIO JACK

Sheet 39 of 42
5 A J _ MI C 1
Audio Board/USB A MI C 1-R
A MI C _ S E NS E
AL 4 F C M1 0 0 5K F -12 1 T 03
4
3 R
A MI C 1-L AL 6 F C M1 0 0 5K F -12 1 T 03 2
6 L
1
A C1 0 AC 4 2S J -T 3 51 -S 2 3
A_ 5 V A J_ A U D I O1
10 0 p _5 0 V _ N P O_ 0 4 1 0 0p _ 5 0V _ N P O_ 0 4
MIC IN 6-20-B2800-106
A MI C 1 -R 1
A MI C 1 -L 2
3
BLACK
A HE A D P HON E -R 4 A HP_ S E N SE A _ A UD G
A HE A D P HON E -L 5
A MI C _ S E N S E 6 A S PK _ HP # 5 A J _ HP 1
A S P K _H P # 7 4
A HP _ S E N S E 8 A H E A D P H O N E -R A R3 6 8_ 0 4 AL 2 F C M 10 0 5K F -12 1 T 03 3 R
A US B _ P N 2 9
A US B _ P P 2 10 A H E A D P H O N E -L A R5 6 8_ 0 4 AL 3 F C M 10 0 5K F -12 1 T 03 2
11 6 L
A S P K OU TR + 12 1
A S P K OU TR - 13
AR 9 AR 8 A C3 AC2 2S J -T 3 51 -S 2 3
14
8 7 21 3 -14 0 0 G *1 K _ 1 %_ 0 4 * 1K _ 1 % _0 4 1 00 p _ 50 V _ N P O _ 04 1 00 p _ 50 V _ N P O _0 4
A _A U D G A G N D HEADPHONE
6-20-53A00-114 BLACK 6-20-B2800-106
A _ A UD G
AL 7
A C1 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 F C M1 0 05 K F -1 2 1T 0 3
A SP K O UT R+ 1 2
A C1 5 0 . 1 u_ 1 6 V _Y 5 V _0 4
A C1 3 0 . 1 u_ 1 6 V _Y 5 V _0 4 A L8 A C 11 A J _ S P K R 1 J_SPK1
F C M1 0 05 K F -1 2 1T 0 3 1 0 0 0p _ 50 V _ X 7R _ 04 A S P K O UT R+ _ R
A C1 6 0 . 1 u_ 1 6 V _Y 5 V _0 4 A SP K O UT R- 1 2 A S P K O U T R -_ R 1 2 1
2
85 2 0 4-0 2 00 1
A C8 C4 5 5 P C B F o ot p ri n t = 8 5 2 04 -0 2 R
A GN D A _ A UD G 1 80 p _ 50 V _ N P O _0 4 1 80 p _ 50 V _ N P O _ 04
A R1 *1 0 mi l _s h o rt _0 4
A _ A UD G 6-20-43150-102
6-20-43110-102
A H1 A H3
C 5 9D 59 C5 9 D5 9 AH 2 AH4
2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
M T H 2 76 D 11 1 MT H 2 7 6 D 1 1 1
A GN D A GN D A G N D A G ND
B - 40 Audio Board/USB
Schematic Diagrams
Power Switch & LED Board

POWER SW & LED & HOT KEY
S _ 3 .3V S S _3 .3 V
POWER
SWITCH LID SWITCH IC S D2
S _ 3 .3V S S_ 3 .3 V LED
C
S R2 *B A V 99 R E CT IF I E R
S _ 3.3 V S S _ 3 . 3V S _ 3 .3 V
SJ _ SW 1 22 0 _ 04
2 0mi l S R1 1 0 0 K _1 % _ 04 AC
1 SJ _ SW 2
2 S M _B TN # 20 mi l 20 mi l 2 0m il Z4301 S U1
3 S W E B _W W W # 1 1 2 S LI D_ S W #
4 S W E B _E M A IL # 2 S M _B T N # S C6 VC C OU T
5 3
GND
A
S L ID_ S W # SW EB_ W W W #
6 4
A
SW EB_ EM AIL # *0 .1 u _1 0 V _ X7 R_ 0 4 SC 2 S C1
7 S M GN D 5
SAP_ O N S L I D_ S W # M H2 4 8- A LF A - E S O
8 6
3
S D3 SD 1 0 .1 u _1 6 V _ Y 5 V _0 4 *1 00 p _ 50 V _ NP O _ 04
9 S M GN D 7 SAP_ O N S MG ND
S _ V IN * HT -1 5 0N B -DT S MG ND S M GND
10 8 H T-1 5 0N B -DT
S M GN D S MG ND
* 5 05 0 0-0 1 0 41 -0 0 1L 8 8 48 6 -0 80 1
C
6-52-56001-023
6-20-94K10-108
6-52-56001-028
6-52-56000-020
6-52-56001-023
6-52-56001-028
S MGN D
Sheet 40 of 42
1 0 pin & 8 pi n co- la y 6-52-56001-022 6-52-56000-020 6-02-00248-LC2 SU1, SU2
S MG ND S M GN D
6-52-56001-022 6-02-00268-LC1 3 Power Switch &
1 2
LED Board
FOR E5128Q FOR E4120Q/E5120Q
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 S_ VIN 6-53-3150B-245

HOT KEY 6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
POWER BUTTON WEB_WWW# WEB_EMAIL# SR 3
AP_KEY#
SPW R _ SW 1 S W W W _S W 1 S MA IL _ S W 1 * 10 0 K _ 1% _ 0 4 S A P _S W 1
T J G-5 3 3-S -T / R T J G-5 3 3-S -T /R TJ G-5 3 3 -S -T /R T J G-5 3 3 -S -T/R
1 2 S M_ B T N# 1 2 S W EB_ W W W # 1 2 S W E B _E MA IL # 1 2 S A P _O N
3 4 3 4 3 4 3 4
SC 4 S C3 S C5 SR 5
5
6
5
6
5
6
5
6
PSW1~8 S R4 *4 7K _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4 0.1 u _ 16 V _ Y 5 V _ 0 4 0 _ 04 0.1 u _1 6 V _ Y 5 V _ 04
3 1
4 2
S MGN D S M GN D S M GN D S MG ND S MG ND S MG ND S MG ND
S M GND
S MG ND
FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2 S M H1 S MH3 S MH 4
* TJ G- 53 3 -S -T / R S M H2 S MH5 2 9 2 9 2 9
1 2 S M_ B T N# H 7_ 0 D2 _ 3 H 7 _0 D 2_ 3 3 8 3 8 3 8
3 4 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
5
6
PSW1~8 M T H2 37 D 87 MT H2 3 7D 87 MT H2 3 7D 1 18
3 1 S MG ND S M GND S M GND S M GN D
4 2
S MGN D
6-53-3150B-245 S M GN D S MGN D
6-53-3050B-240
6-53-3050B-241
FOR E5128Q
Power Switch & LED Board B - 41

Schematic Diagrams
External ODD Board

ODD BOARD FOR E5120Q
QJ _ OD D 2 Q J_ O DD 1
S1 S1
S2 QJ _S ATA_ TXP1 S2
S3 QJ _S ATA_ TXN 1 S3
S4 S4
S5 QJ _S ATA_ R XN 1 S5
S6 QJ _S ATA_ R XP1 S6
S7 S7
Q GN D Q G ND
P1 QJ _O D D_ D ETE CT# P1
Sheet 41 of 42 P2
P3 Q _ 5VS Q_ 5VS
P2
P3
P4 QJ _S ATA_ O DD _ DA# P4
External ODD P5
P6
P5
P6
Board PI N
1- 1 62 -1 0 05 62 2 42 00 1 -1
P IN
G N D1 ~2 =WG ND Q GN D Q G ND G N D 1 ~3 =Q G N D
6-21-1 4010-0 13
6-21-1 3A00-0 13 6-21-1 4020-0 13
6-21-1 4030-0 13
Q_ 5V S
Q C2 Q C1
0. 1 u_ 16 V_ Y5 V_ 04 *0 .1 u_ 1 6V_ Y 5V_ 0 4
Q G ND
Q H1 QH 4 Q H3 Q H2
C 23 7 D9 1 C 2 37 D 91 C 67 D 67 C 67 D 67
QG N D Q GN D
B - 42 External ODD Board

Schematic Diagrams
Sequence
E 5 1 2 0 Q D 0 2 P O W E R S E Q U E N C E
VCCRTC
3 8 . 8 m s V C C R T C t o R T C R S T #
RTCRST# SPEC MIN 9mS
DD_ON#
8 7 0 u s ( D D _ O N # t o 5 V )
5V
1 . 5 m s ( D D _ O N # t o 3 . 3 V )
3.3V
PWRBTN# 8 5 m s 1 5 0 m s
RSMRST# 2 0 m s ( P W R B T N # t o R S M R S T # )
SUS_PWR_ACK 1 u s ( R S M R S T # t o S U S _ P W R _ A C K )
9 8 m s ( R S M R S T # t o S U S C # )
SUSC#
1.5V (VDDQ) 2 . 1 7 m s ( S U S C # t o 1 . 5 V ( V D D Q ) )
5 7 u s ( S U S C # t o S U S B # ) )
SUSB#
DDR1.5V_PWRGD 4 . 4 m s ( 1 . 5 V ( V D D Q ) t o D D R 1 . 5 V _ P W R G D )
5VS
9 2 0 u s ( S U S B # t o 5 V S )
Sheet 42 of 42
3.3VS 1 . 5 2 m s ( S U S B # t o 3 . 3 V S ) Sequence
4 . 7 5 m s ( S U S B # t o V T T _ M E M ( 0 . 7 5 V ) )
VTT_MEM(0.75V)
5 . 7 5 m s ( S U S B # t o 1 . 8 V S )
1.8VS
1 . 2 7 m s ( 1 . 8 V S t o 1 . 8 V S _ P W G D )
1.8VS_PWRGD
1.1VS_VTT_EN 1 . 2 7 m s ( 1 . 1 V S _ V T T _ E N t o 1 . 1 V S _ V T T )
1.1VS_VTT 8 . 4 m s ( S U S B # t o 1 . 1 V S _ V T T )
1.1VS_PWRGD 0 m s ( 1 . 1 V S _ V T T t o 1 . 1 V S _ P W R G D )
ALL_SYS_PWRGD 0 m s ( 1 . 1 V S _ V T T t o A L L _ S Y S _ P W R G D )
H_VTTPWRGD 2 m s ( A L L _ S Y S _ P W R G D t o H _ V T T P W R G D )
VGFX_VCORE_EN (DFGT_VR_EN) 8 . 4 7 m s ( S U S B # t o V G F X _ V C O R E _ E N )
VGFX_VID 0 m s ( V G F X _ V C O R E _ E N t o V G F X _ V I D )
VGFX_CORE
9 . 2 9 m s ( S U S B # t o V G F X _ C O R E )
VGFX_VORE_PG 0 m s ( V G F X _ V C O R E t o V G F X _ V O R E _ P G )
2 8 0 m s ( A L L _ S Y S _ P W R G D t o P M _ M P W R O K )
MEPWROK
SPEC 0.0001mS ~ 500mS
VCORE_ON 2 8 0 m s ( A L L _ S Y S _ P W R G D t o V C O R E _ O N )
SPEC MIN 99mS
VCORE
2 . 8 4 m s ( V C O R E _ _ O N t o V C O R E )
SPEC MAX 3mS
CLKEN# 1 2 0 u s ( V C O R E t o C L K E N # )
CLKIN_BCLK
1 . 2 m s ( C L K E N # t o C L K I N _ B C L K )
VCORE PG (DELAY_PWRGD) 6 . 4 8 m s ( V C O R E t o D E L A Y _ P W R G D )
SYS_PWRGD/SB_PWROK 2 9 7 . 7 2 m s
( S U S B # t o S Y S _ P W R G D / S B _ P W R O K )
SM_DRAMPWROK 3 7 . 7 m s ( V C O R E t o S M _ D R A M P W R O K )
6 8 m s
H_CPUPWRGD
( V C O R E t o H _ C P U P W R G D )
SPEC 0.05mS ~ 650mS
SUS_STATE# 1 . 6 4 m s
( H _ C P U P W R G D t o S U S _ S T A T E # )
SPEC 0.03mS ~ 2mS
PLT_RST# 2 3 0 u s
( S U S _ S T A T E # t o P L T _ R S T # )
SPEC MIN 60us
Sequence B - 43
Schematic Diagrams
B - 44
BIOS Update
Appendix C:Updating the FLASH ROM BIOS

BIOS Version
To update the FLASH ROM BIOS you must: Make sure you down-
Download the BIOS update from the web site. load the latest correct
Unzip the files onto a bootable CD/DVD/USB Flash Drive. version of the BIOS ap-
propriate for the com-
Reboot your computer from an external CD/DVD/USB Flash Drive. puter model you are
Use the flash tools to update the flash BIOS using the commands indicated below. working on.
Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
You should only
Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
download BIOS ver-
After rebooting the computer you may restart the computer again and make any required changes to the default BIOS sions that are
settings.
C:BIOS Update
V1.01.XX or higher as
appropriate for your
Download the BIOS computer model.
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel. Note that BIOS versions
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files are not backward com-
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model patible and therefore
(see sidebar for important information on BIOS versions). you may not down-
grade your BIOS to an
older version after up-
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive grading to a later ver-
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the sion (e.g if you upgrade
a BIOS to ver 1.01.05,
downloaded files.
you MAY NOT then go
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB back and flash the BIOS
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software). to ver 1.01.04).
Set the computer to boot from the external drive

1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the + and - keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1
BIOS Update
Use the flash tools to update the BIOS

1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message Starting MS-DOS. You will then be prompted to give Y or N responses to the programs
being loaded by DOS. Choose N for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
C:BIOS Update
restarts.
Restart the computer (booting from the HDD)

1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F9) and select Yes to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with the updated BIOS

You may now enter the BIOS and make any changes you require to the default settings.
C-2

Itautec w7535 - Clevo 6-71-W24h0-D02a GP

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Itautec w7535 - Clevo 6-71-W24h0-D02a GP

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Droits d'auteur :

Formats disponibles

E5120Q/E5120Q-C, E5125/E5125-C, E5128Q, E5128Q-C

About this Manual

The following information is included:

Appendix A, Part Lists

IMPORTANT SAFETY INSTRUCTIONS

This Computers Optical Device is a Laser Class 1 Product

Instructions for Care and Operation

Use only approved brands of Unplug the power cord before

The computer has specific power requirements:

Users Manual on CD/DVD

Note that you should al-

Card Reader/LAN JMB251C ....................................................... B-26

Audio Board/USB ........................................................................ B-40

Specifications Processor Options BIOS

Intel Core i7 Processor One 32Mb SPI Flash ROM

4MB L3 Cache & 1066MHz FSB

3MB L3 Cache & 1066MHz FSB Keyboard

Memory Security (Kensington Type) Lock Slot

Card Reader Environmental Spec

Embedded Multi-In-1 Card Reader Temperature

Built-In Gigabit Ethernet LAN Dimensions & Weight

6 Cell Smart Lithium-Ion Battery Pack, 48.84WH

Full Range AC/DC Adapter

Energy Star 5.0 Compliant

1 - 4 External Locator - Top View with LCD Panel Open

External Locator - Front & Right Side Views Figure 2

External Locator - Front & Right Side Views 1 - 5

External Locator - Left Side & Rear View

Figure 5 REAR VIEW

1 - 6 External Locator - Left Side & Rear View

External Locator - Bottom View

External Locator - Bottom View 1 - 7

Figure 7 Mainboard Overview - Top (Key Parts)

1 - 8 Mainboard Overview - Top (Key Parts)

Mainboard Overview - Bottom (Key Parts) Figure 8

Mainboard Overview - Bottom (Key Parts) 1 - 9

Figure 9 Mainboard Overview - Top (Connectors)

1 - 10 Mainboard Overview - Top (Connectors)

Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Overview - Bottom (Connectors) 1 - 11

An example of these types of boxes are shown in the sidebar.

To remove the Battery: To remove the Bluetooth Module:

1. Remove the battery page 2 - 5

To remove the Wireless LAN Module:

Removing the Battery Figure 1

Removing the Battery 2 - 5

Removing the Hard Disk Drive

a. Locate the HDD bay cover Hard Disk Upgrade Process

New HDDs are blank. Before you

You have backed up any data

You have all the CD-ROMs and

If you have access to the internet,

2 - 6 Removing the Hard Disk Drive

3. Remove the hard disk bay cover 63 (Figure 3b).

Removing the Hard Disk Drive 2 - 7

Figure 4 Removing the Optical (CD/DVD) Device

2 - 8 Removing the Optical (CD/DVD) Device

Removing the System Memory (RAM) Figure 5

Removing the System Memory (RAM) 2 - 9

5. Pull the latches to release the second module if necessary.

2 - 10 Removing the System Memory (RAM)

Removing and Installing a Processor Figure 6

Removing and Installing a Processor 2 - 11

3 . 3V S R5 6 4. 7K _ 04 OE # V C C [ 1] 3 . 3V S TMD S D A TA 1 + H DMI 2 01 2F 2S F -90 0T 04-s ho rt