Department of Electrical and Computer Engineering

CMOS Comparator Design

Extra Slides

Vishal Saxena, Boise State University

(vishalsaxena@boisestate.edu)

Vishal Saxena -1-

Comparator Design Considerations
Comparator =
Preamp (optional)
+ Reference Subtraction (optional for single-bit case)
+ Regenerative Latch
+Static Latch to hold outputs (optional)
Design Considerations
Accuracy (dynamic and static offset, noise, resolution)
Settling time (tracking BW, regeneration speed)
Sensitivity/resolution (gain)
Metastability (ability to make correct decisions)
Overdrive recovery (memory)
Power consumption

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 An Example CMOS Comparator
Vos orginiates from:
VDD
Preamp input pair
M3 M4 M5 M6 mismatch (Vth,W/L)
PMOS loads and

Vos + current mirror
Vo V o-
M1 M2
Latch offset
Vi M9
Charge-Injection
M7 M8
clock-feedthru imbalance
of the reset switch (M9)
VSS
Clock routing
Preamp Latch
Parasitics

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Latch Regeneration

VDD
PA tracking Latch
Latch reseting regenrating
M5 M6

VDD
+ -
Vo Vo
Vo+
CL M9 CL
Vo
M7 M8
Vo-
VSS VSS

Exponential regeneration due to positive feedback of M7 and M8

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Regeneration Speed Linear Model

Vo+ Vo- Vo+

-1
CL CL
CL gmVo-
M7 M8 Vo-

Vo Vo

1 1 Vo
0


o
V gm Vo /sCL 1 gm /sCL Vo

s gm /sCL 1 0 sp gm /CL , singleRHP pole

Vo t 0 Vo t 0 expt gm /CL

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Reg. Speed Linear Model

Vo+ Vo-

CL CL
Vo(t=0)
t Vo = 1V
M7 M8

Vo Vo(t=0) t/(CL/gm)
1V 100mV 2.3
CL Vo t
1V 10mV 4.6 t ln
gm Vo t 0
1V 1mV 6.9
1V 100V 9.2

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Reg. Speed Linear Model
Reg. Speed Linear Model
M3 M4 Vm+ M5 M6 Vm- gm5Vm+ gm5Vm-

Vm+ V m- =1 R9 R9
M1 M2 x Vo +
Vo-
Vo+ 2 2 Vo-
Vi M9 X
-1 -1
M7 M8
gm7 gm7

gm1 gm5R9 R9 1
A V1 A V2 , to be amplifier.
gm3 2 gm7R9 2 gm7

Vo 0 Vi 0 A V Vi 0 A V1A V2

Vo t Vi 0 A V1A V2 expt gm /CL

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Comparator Metastability
T/2 Linear Model
Reg. Speed
Vo t Vi 0 A V1A V2 expt gm /CL

Curve AV1AV2 Vi(t=0)

10 10 mV
1 2 3 4
Vo+ 10 1 mV

-
10 100 V
Vo
10 10 V

Comparator fails to produce valid logic outputs within T/2 when input falls
into a region that is sufficiently close to the comparator threshold

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Comparator Metastability
Reg. Speed Linear Model
Do
Assuming that the input is uniformly
j+1
distributed over VFS, then

Vi BER
1LSB

j
Vo t Vi 0 A V1A V2 expt gm /CL
Vos

Cascade preamp stages (typical flash comparator has 2-3 pre-amp stages)
Use pipelined multi-stage latches; pre-amp can be pipelined too

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Charge-Injection and Clock-Feedthrough in Latch

Reg. Speed Linear Model

M5 M6

Vo+ Vo-
Cgs Cgd
CM
M9 jump
CL CL Vo+
M7 M8
Vo-

Charge injection (CI) and clock-feedthrough (CF) introduce CM jump

in Vo+ and Vo-
Dynamic latches are more susceptible to CI and CF errors

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Dynamic Offset of a Latch
Reg. Speed Linear Model
Dynamic offset derives from:

Imbalanced CI and CF
Imbalanced load capacitance
Mismatch b/t M7 and M8
Mismatch b/t M5 and M6
+
Vo Clock routing

Vo- 0.5V CM jump

50mV offset
10% imbalance

Dynamic offset is usually the dominant offset error in latches

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Typical CMOS Comparator
Reg. Speed Linear Model
VDD
Input-referred latch
M3 M4 M5 M6 offset gets divided by
the gain of PA

Vos
Vo +
V o- Preamp introduces
M1 M2
Vi its own offset (mostly
M9
static due to Vth, W,
M7 M8 and L mismatches)
PA also reduces
VSS
kickback noise
Preamp Latch

Kickback noise disturbs reference voltages, must settle before next sample

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Comparator Offset
Reg. Speed Linear Model
VDD

M3 M4 M5 M6
Differential pair mismatch:
2
W


Vos 1
Vos Vth Vov L
Vo+ V o- 2 2 2
W
M1 M2
Vi M9
4
L
M7 M8
g gm5R9
A V1 m1 A V2
VSS gm3 2 gm7R9
Preamp Latch

Vos,34 Vos,56
2 2 2 2
Total input-referred Vos,78 Vos,dyn
Vos Vos,12
2 2
comparator offset: A
2
A
2
A V2
2 2
A V1 A V2
2
V1 V1

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Recall: Matching Properties
Reg. Speed Linear Model
Suppose parameter P of two rectangular devices has a mismatch error of P. The
variance of parameter P b/t the two devices is

2
A
P P SP D2 ,
2 2 1st term dominates
WL for small devices

where, W and L are the effective width and length, D is the distance

A Vth2
Threshold : Vth =
2
+ S Vth2D2
WL
2 A 2
Current factor : S 2D2
2
WL

Ref: M. J. M. Pelgrom, et al., Matching properties of MOS transistors, IEEE Journal

of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.

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Recall: Device Sizing for Mismatch
Reg. Speed
R
Linear Model
R
1 2

W X X X X X X X X

L
10 identical resistors

L L
R1 RS with std R1 R2 RS 10 10R1 with std R2 ,
W W
10
R2 R j 2 10R12 R2 10R1
2

j1

R2 10R1 1 R1 R 1 1 Spatial
averaging
R2 10R1 10 R1 R A WL

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Pre-amp Design
A fully-differential gain-stage
Avoid or use simple CMFB
Pre-amp gain reduces input referred offset due to the latch
Autozeroing techniques for offset storage and reduction

Pre-amp open-loop gain vs tracking bandwidth trade-off

Multiple stages of pre-amp limit bandwidth
Optimum value of stages 2-4

N stages:
N
N
A0 A0
AN
1 j / 0 1 / 2
0
1
A 0N
A N 3dB , 3dB 0 2 1
N

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Pre-amp (PA) Autozeroing
2'
M3 M4

1 C Vos Vo+ Vo-

Vi 2'
Vo
M5 M6
2 A
Vi+ M1 M2 Vi-

Finite preamp gain :

VOS , preamp
VOS ,in
A

For the overall comparator :

2V 2V
2V 2
OS , pre
2
OS ,latch

OS ,in
A pre A pre

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Pre-amp Design: Pull-up load

NMOS diode pull up :

gm1 W L 1
Pull-up AV
gmL W L L
Vo+ Vo-
PMOS diode pull up :
Vi+ M1 M2 Vi- gm1 W L 1
AV n
gmL p W L L

Resistorpull up :
A V gm1 RL

NMOS pull-up suffers from body effect, affecting gain accuracy

PMOS pull-up is free from body effect, but subject to P/N mismatch
Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion, well,
etc.) dont track transistors; but it is fast!

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 Pre-amp Design: More Gain

M3 Ip Ip M4
Vo + Vo-
gm1 I 2 W L 1
AV n
gm3 p I 2 Ip W L 3
Vi+ M1 M2 Vi-

Ip diverts current away from PMOS diodes (M3 & M4), reducing (W/L)3
Higher gain without CMFB
Needs biasing for Ip
M3 & M4 may cut off for large Vin, resulting in a slow recovery

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 Faster Settling Pre-amp

M3 M5 M6 M4 1
ro3
-1
ro5
gm3 gm5
Vo + Vo-
Vid gm1Vid ro1 Vod

Vi+ M1 M2 Vi-
1 1 g r
gm1 // //ro1//ro3 //ro5 m1 o1
dm
DM gain : A V
M7 gm3 gm5 3

NMOS diff-pair loaded with PMOS diodes and a PMOS cross-coupled latch
High DM gain, low CM gain, good CMRR
Simple, no CMFB required
(W/L)34 > (W/L)56 needs to be ensured for stability
Ref: K. Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2,
JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.

Vishal Saxena -20-

 Pre-amp Example

M3 M4

RL RL
+
Vo Vo-
X

Vi+ M1 M2 Vi-

M5

NMOS diff. pair loaded with PMOS diodes and resistors

High DM gain, low CM gain, good CMRR
Simple, no CMFB required
Gain not well-defined
Ref: B.-S. Song et al., A 1 V 6 b 50 MHz current-interpolating CMOS ADC, in Symp. VLSI
Circuits, 1999, pp. 79-80.

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 Pre-amp Example

NMOS diff. pair loaded with PMOS Current mirror

Simple CMFB circuit
Gain is well-defined

Ref: V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, A Distortion Compensating Flash

Analog-to-Digital Conversion Technique," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep.
2006.

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 Latch Design
Regenerative latches for faster settling
See lecture notes
At least one cross-coupled regenerative core
Local positive feedback
Numerous methods for applying the input initial signal to
regenerate upon
Latches can have large static and dynamic offsets
Large Regenerative gain for resolving small inputs
Metastability (wrong or incomplete decisions) when latch cant
make decision
Pre-amp can be used for amplifying the inputs (slower tracking
BW)
One size doesnt fit all applications
Speed vs power consumption trade-off

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Static Latch

Active pull-up and pull-down full

CMOS logic levels
M3 M4
Vi+ Vi- Very fast!
M1 M2
Q+ and Q- are not well defined in reset

mode ( = 1)
Q+ Q- Large short-circuit current in reset mode
M7
Zero DC current after full regeneration
M5 M6 Supply is very noisy

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Semi-Dynamic Latch
Diode divider disabled in reset mode
less short-circuit current
M8 Pull-up not as fast
Q+ and Q- are still not well defined in
M3 M4 reset mode ( = 1)
Vi+ Vi-
M1 M2
Zero DC current after full

regeneration
Q+ Q- Supply still very noisy
M7

M5 M6

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Dynamic Latch

Zero DC current in reset mode

Q+ and Q- are both reset to 0
M7 M5 M6 M8
Full logic level after
regeneration
Q+ Q-
Slow
M9 M10

Vi+ M1 M3 M4 M2 Vi-

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Dynamic Latch 2

M7 M5 M6 M8 Zero DC current in reset

mode
+ -
Q+ and Q- are both reset to
Q Q
0
M9 M10 Full logic level after
regeneration
M3 M4 Slow

Vi+ M1 M2 Vi-

Ref: T. B. Cho and P. R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,

JSSC, vol. 30, pp. 166-172, issue 3, 1995.

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 Current-Steering/CML Latch

RL RL
Q+ Q-
M7
Current mode logic (CML) latch
Vi+ M1 M2 Vi- M3 M4 Constant current supply very quite
Higher gain in tracking mode
M5 M6
Cannot produce full logic levels
M8
Fast
Popular for high-speed designs
Trip point of the inverters

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PA Autozeroing Example

I. Mehr and L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC, IEEE
JSSC March 2000, pp. 318-25.

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Reference Subtraction

S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, "A Power Optimized Continuous-time

Delta-Sigma Modulator for Audio Applications," IEEE JSSC, vol. 43, no. 2, pp. 351-360, Feb.
2008.

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Autozeroing and Reference Subtraction

Pre-amp

V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, A Distortion Compensating Flash

Analog-to-Digital Conversion Technique," IEEE JSSC, vol. 41, no. 9, pp. 1959-1969, Sep.
2006.

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CML based Comparator

CML-Latch

V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and N. Nigania, A 16MHz BW 75

dB DR CT ADC Compensated for More Than One Cycle Excess Loop Delay," IEEE JSSC,
vol. 47, no. 8, Aug. 2012.

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Comparators for Pipelined ADCs

Pipelined ADCs employ at least 0.5 bit/stage redundancy

Can tolerate large offsets and large noise with appropriate redundancy

Should consume negligible power in a good design

50-100 mW or less per comparator

Lots of implementation options

Resistive/capacitive reference generation
Different pre-amp/latch topologies

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Comparators for Pipelined ADCs

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Comparator Example

A 6-b 1.3-Gsample/s A/D Converter in 0.35-m CMOS

IEEE JSSC, vol. 36, no. 12, Dec 2001.

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Latch Example

A 0.9-V 60-W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range
IEEE JSSC, vol. 43, no. 2, Feb. 2008

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Comparator Example

A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time

Cascaded Modulator, IEEE JSSC, vol. 43, no. 4, Apr 2008

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Comparator Example

I. Galdi, 40 MHz IF 1 MHz Bandwidth Two-Path Bandpass Modulator With 72 dB

DR Consuming 16 mW, IEEE JSSC, vol. 39, no. 8, pp. 13411346, Aug. 2004.

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Comparator Example

Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over
100-dB SFDR," IEEE JSSC, vol. 39, pp. 2139 - 2151, December 2004.

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Comparator Example

B. Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, "A 69-mW 10-bit

80-MSample/s pipelined CMOS ADC," IEEE JSSC, vol. 38, pp. 2031 - 2039,
Dec. 2003.

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Comparator Example

J. Lin and B. Haroun, "An embedded 0.8 V/480 W 6B/22 MHz flash ADC in 0.13
m digital CMOS Process using a nonlinear double interpolation technique," IEEE
JSSC, vol. 37, pp. 1610 - 1617, Dec. 2002.

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Comparator Example

S . Limotyrakis, S. D. Kulchycki, D. Su, and B. A. Wooley, "A 150MS/s 8b 71mW

time-interleaved ADC in 0.18m CMOS," proc. IEEE ISSCC, pp. 258 - 259, Feb 2004.

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Exercise
Compare the latches with respect to
Static power dissipation
Dynamic and static Offsets
Kickback noise at the input
Number of clock phases
Maximum achievable clock speed

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References
1. Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters, 2nd Ed., Springer, 2005.
2. N. Krishnapura, Analog IC Design, IIT Madras, 2008.
3. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
4. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.

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