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MIS-502

Reflection 2

Chapter 4: - Processor Technology and Architecture.


In this chapter we come across topics like CPU instructions, execution cycles, general
purpose and special purpose registers and how to enhance processor performance and many
more.

We know that CPU is the main component of a computer which is also called as the brain of
the computer. It directs all the computer system actions including processing, storage, input
and output and the movement of data. We know that CPU consists of three components

1. Arithmetic Logic Unit (ALU)


2. Control Unit and
3. Memory Registers

The ALU performs all the computation and comparison instructions like mathematical
operations like addition, subtraction, multiplication and division. The Control Unit moves
data and instructions between main memory and registers. The Registers are the storage
locations that holds the inputs and the outputs for the ALU.

We know that when a program is being executed by the CPU there occurs complex chains of
events. To start this the control unit reads the first instruction from the primary storage and
then stores the instructions in a register and, if its necessary it also reads the data inputs from
primary storage and stores them in registers. If the instruction is a computation or comparison
instruction, the control unit signals the ALU what function to perform, where the input data is
located, and where to store the output data. The control unit handles executing instructions to
move data to memory, I/O devices, or secondary storage. When the first instruction has been
executed, the next instruction is read and executed. This process continues until the programs
final instruction has been executed. The actions the CPU performs can be divided into two
groups the instruction cycle and the execution cycle.

The instruction cycle is also called as the fetch cycle in which the control unit reads the
instructions from the primary storage, it also addresses next instruction to be read. The
instructions stored by the control unit are stored in the instruction cycle and if there are any
data inputs embedded in the instructions then they are loaded in the registers as inputs for the
ALU. In the Execution cycle the control unit itself executes the data movement instructions.
The instructions which are being executed by the ALU in response to a signal from the
control unit and also data inputs flow from registers through processing circuit and the
outputs flow to one or more registers and also stores the result in a register. The instruction
format also plays a major role, like an instruction is a command to the CPU to perform a
single process or a multi process for achieving specific data. The instruction format consists
of instruction components, they are the Opcode and the Operands. Opcode is a unique binary
number and Operands are one or more group of bits after the opcode that contain data to be
processed. There are different operations like the MOVE operation in which the load
operation is a memory address to a register and the vice versa register to memory address is a
store operation. This operation consists of Boolean logics like NOT, AND, OR and EXOR
operations and the instruction format consists of operations like the ADD, SHIFT, BRANCH
and HALT etc. Whereas coming to the RISC versus CISC. RISC is the Reduced Instruction
Set Computing and CISC is the Complex Instruction Set Computing. RISC is to avoid
unnecessary complex instructions and CISC is completely opposite to RISC. In the Clock rate
the modern cpus are much too complex in the performance standards.

Memory caches
Multiple core processors
Multiple ALU per core and
Pipelining

The instruction oriented performance includes MIPS (Millions of Instructions per Second)
and the MFLOPS (Millions of Floating Point operations per Second). Registers can be
defined as temporary storage locations. These are useful to store temporary data which are
often used during program execution. Registers are placed in CPU. There are two types of
registers:

1. General Purpose registers: - General purpose registers are usually only used to currently
execute programs

2. Special Purpose registers: -The special purpose registers are the one which are defined for
some specific task only. They perform particular task or data handling task. They can be
used to store the program state. There are three types of special purpose registers:
Instruction Register
Instruction Pointer and
Program Status Word

There are many different processor technologies being implemented and also Future Trends
like the Optical processing, Electro optical processing and Quantum processing are being
implemented.

Chapter 5: - Data Storage Technology.


This chapter deals with primary and secondary storage, how devices use to implement
primary storage etc.

Primary Storage: - The Primary storage memory is the main memory like the (RAM) where
the operating system mainly resides. Our computers CPU directly communicates with the
primary storage devices to get inputs required to execute the required processes. The memory
storages are volatile(Temporary) memory referred to as random access memory. In the
primary storage the memory is smaller and expensive and also the storages are accurate and
faster. Large amounts of data cannot be stored in primary storage as it cleans the data when
its full. The files we use most frequently use the temporary memory which are lost when the
system is turned off like the cache. This is the reason the primary storage is used for
processing the data. The primary storage is connected through data buses to CPU.

Secondary Storage: - These are the external storages where the CPU does not have a direct
access to it and it is used as a secondary communication. It can be external devices like Hard
Disks, floppy disks, CDs, pen drives and external HDDs. The secondary storage can
permanently store the data on the disks which can be retained even when the computer is
turned off, which is why the secondary storage is used for storing data and also they are
larger in size and cheaper. But when compared to the accuracy and speed the secondary
storages are slower. The secondary storage is connected through data cables to CPU.

There are two different types of RAM:

1. Static RAM and


2. Dynamic RAM.

Static RAM does now not encompass capacitors for switching moves and accordingly, they're
rather rapid however costly. Probably the most ROM applied sciences are ROM, prom
(Programmable ROM), Erasable prom (EPROM) and EEPROM (Electronically erasable
promenade). New applied sciences made solution to non-volatile RAM (NV-RAM)
equivalent to MRAM (magneto resistive RAM) and PRAM or PCRAM (section alternate
RAM). Memory packaging types incorporate DIP (dual inline package), SIMM (Single in-
line reminiscence module) and DIMM (dual inline memory module) which is the recent or
currently used packaging.

Magnetic storage procedures are used in rough drives which are rather slow compared to the
semiconductor reminiscence contraptions. The magnetic storage devices must control or
compensate for some undesirable characteristics of magnetism and magnetic storage media,
which includes the following.

Magnetic Decay
Magnetic Leakage
Minimum Threshold current for read operations
Long term storage medium integrity.

The magnetic disk performance depends on head-to-head switching time, track-to-track seek
time, rotational delay, natural access lengthens, common entry time, sequential access time,
defragmentation, data switch rate and many others.

CD-ROMS, DVDs, Blu-ray make use of optical storage methods. The bodily structure finds
similarities with those of magnetic storage to an extent, nevertheless, the differences do exist
corresponding to- data recording based on editions in reflectivity, learn/write utilising lasers
and photodetectors, single and detachable platter, scale down RPMs, low writing speeds etc.
They follow bit encoding tactics such as Pits and lands, dye-based and section-exchange
approaches. Contemporary progress in cloud technological know-how includes high
information storage, larger speeds, protection, integrity, and so forth.

Chapter 6: - System Integration and Performance.


This chapter deals with subsidiary buses and bus protocol, how the CPU and BUS interact
with peripheral devices, purpose and function of device controllers and how buffer and
caches improves computer system performance.

In this chapter basically the Framework rate and execution not just relies upon the clock
velocity of the CPU and RAM additionally on framework transport. Framework transport is a
channel that associates two or more gadgets by means of shared electrical or optical medium.
Contingent upon the gadgets the transports associate with, they are separated into address
transport, information transport, control transport and power transport. The framework
transport has its clock rate and is of two sorts: parallel transport clock rate and serial transport
clock rate, the last being more than the previous. The serial transport clock rate is about the
pace of the CPU. The clock rate fluctuates conversely with the length of the transport. Higher
transport speeds give better framework execution yet are mistake inclined. Transport Data
exchange rate.

DTR is given by: (BUS DTR = Data Transfer Unit Size * Clock Rate).

Transport takes after specific principles which are known as the transport conventions. There
are two approaches to control the transport access: Master-slave and distributed. For
enhanced execution, information exchanges to/from the CPU use DMA (Direct memory
access). This makes the CPU the transport ace just when the CPU is required.

The CPU makes use of linear address space and device controllers for logical access and for
also accessing physical devices. When the CPU state is busy, the devices need the CPU for
further functioning, and then the devices enter the wait state. The wait state is governed by
the interrupt and its priority. Each device is associated to unique interrupt request priorities.

Stack is a primary storage that functions as LIFO (Last in first out). It holds the context of the
execution. The two major operations on stack are PUSH and POP. Stack is a special purpose
register which points to the memory address called the Top of stack which helps in handling
the interrupts. When an interrupt is to be serviced, the current context is pushed to the stack,
and the interrupt is serviced and finally, the context is popped from the stack to continue the
execution. Buffers and cache are memories which are included in the modern CPU
architecture in order to achieve enhanced speed, accuracy and efficiency.

Buffers act as memory medium for data exchange. If the data in the buffer is not utilized, then
it results in buffer overflow. This can be managed using the hand-shaking signals. Increased
buffer size renders the CPU cycles redundant. Hence, small buffer sizes are preferable. For
storage devices, a relatively larger bi-directional, intelligent memory is reserved. I also came
across Stack which is a primary storage that functions as LIFO basis. It holds the context of
the execution. PUSH and POP are the two major operations on stack. Stack is a special
purpose register. It points to the memory address called the Top of stack. This helps in
handling the interrupts. When an interrupt is to be serviced, the current context is pushed to
the stack, the interrupt is serviced and finally, the context is popped from the stack to
continue the execution. Buffers and cache are memories included in the modern CPU
architecture in order to achieve enhanced speed and efficiency. Buffers act as memory
medium for data exchange. If the data in the buffer is not utilized, then it results in buffer
overflow. This can be managed using the hand-shaking signals. Increased buffer size renders
the CPU cycles redundant. Hence, small buffer sizes are preferable. For storage devices, a
relatively larger bi-directional, intelligent memory is reserved. A multicore processor is a
single microchip containing two or more fully functional CPUs. The main advantage of
multicore architecture compared with multi- CPU architecture with CPUs of equivalent
number and power is more efficient inter-CPU communication, which increases total
computational power when multiple CPUs cooperate on the same task. And also the CPU
uses the system bus and device controllers to communicate with secondary storage devices as
well as the input/output devices.

Regards,

Sreedharrao Puligilla.

References: -
Burd, Stephen E., Systems Architecture, Sixth Edition.