1 .On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1.

On the
sixth clock pulse, the sequence is ________.
A
Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
.

B
Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 0
.

C
Q0 = 0, Q1 = 0, Q2 = 1, Q3 = 1
.

D
Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 1
.
2. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift
register that is initially clear. What are the Q outputs after two clock pulses?
A
0000
.

B
0010
.

C
1000
.

D
1111
.
3. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal
shift features, called?
A
tristate
.

B
end around
.

C
universal
.

D
conversion
.
4. On the third clock pulse, a 4-bit Johnson sequence is Q0 = 1, Q1 = 1, Q2 = 1, and Q3 = 0. On the
fourth clock pulse, the sequence is ________.
A
Q0 = 1, Q1 = 1, Q2 = 1, Q3 = 1
.

B
Q0 = 1, Q1 = 1, Q2 = 0, Q3 = 0
.

C
Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 0
.

D Q0 = 0, Q1 = 0, Q2 = 0, Q3 = 0
 .

5. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The
nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the
shift register is storing ________.
A
1101
.

B
0111
.

C
0001
.

D
1110
.

6. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The
nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift
register is storing ________.
A
1110
.

B
0111
.

C
1000
.

D
1001
.
7. What type of register would have a complete binary number shifted in one bit at a time and have
all the stored bits shifted out one at a time?
A
parallel-in, parallel-out
.

B
parallel-in, serial-out
.

C
serial-in, parallel-out
.

D
serial-in, serial-out
.
8. By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a
________, ________, and ________-out register.
A
parallel-in, serial, parallel
.

B serial-in, parallel, serial

 .

C
series-parallel-in, series, parallel
.

D
bidirectional in, parallel, series
.
9. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift
register with an initial state 11110000. After two clock pulses, the register contains ________.
A
10111000
.

B
10110111
.

C
11110000
.

D
11111100
.
10. From the following list of input conditions, determine the state of the five output leads on a
74148 octal-to-binary encoder.
I0 = 1 I3 = 1 I6 = 1
I1 = 1 I4 = 0 I7 = 1
I2 = 1 I5 = 1 EI = 0
A
GS = L, A0 = L, A1 = L, A2 = H, EO = H
.

B
GS = L, A0 = H, A1 = L, A2 = L, EO = H
.

C
GS = L, A0 = L, A1 = H, A2 = L, EO = H
.

D
GS = L, A0 = H, A1 = H, A2 = L, EO = H
.

11.Which digital system translates coded characters into a more useful form?
A
encoder
.

B
display
.

C
counter
.

D decoder
 .
. 12.Why can a CMOS IC be used as both a multiplexer and a demultiplexer?
A
It cannot be used as both.
.

B
13. CMOS uses bidirectional switches.
.
. The inputs/outputs of an analog multiplexer/demultiplexer are:
A
bidirectional
.

B
unidirectional
.

C
even parity
.

D binary-coded decimal
.
14. Most demultiplexers facilitate which type of conversion?
A
decimal-to-hexadecimal
.

B
single input, multiple outputs
.

C
ac to dc
.

D
odd parity to even parity
.

15.How many possible outputs would a decoder have with a 6-bit binary input?
 A
16
.

B
32
.

C
64
.

D
128
.

16. A binary code that progresses such that only one bit changes between two successive codes is:
A
nine's-complement code
.

B
8421 code
.

C
excess-3 code
.

D
Gray code
.

17.Implementing the expression AB + CDE using NAND logic, we get:

A
(A)
.

B
(B)
.

C
(C)
.