Digital Lab

R.M.K. college of Engg. & Technology Dept.
of CSE & IT
~1~ CS6211-DIGITAL LABORATORY

R.M.K. college of Engg. & Technology Dept. of CSE & IT
PIN DIAGRAM OF BASIC LOGIC GATES:
IC 7400
IC 7408
IC 7432 IC 7486
14 13 12 11 10 9 8
Vcc
IC 7411
Gnd
1 2 3 4 5 6 7
Logic Diagram:
Verification of DeMorgans Theorem:

(AB)=A+B:
(A+B) = AB:
Truth Table for (AB)=A+B:

A B (AB) A+B
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
Truth Table for (A+B)=AB:

A B (A+B) AB
0 0 1 0
0 1 0 0
1 0 0 0
1 1 0 0

EX: NO: VERIFICATION OF BOOLEAN THEOREMS

DATE: USING DIGITAL LOGIC GATES:
AIM:
To verify the following Boolean theorems using digital logic gates.
a) DeMorgans theorem.
b) Consensus theorem.
c) Duality theorem.
Apparatus Required:
SI. No. COMPONENT SPECIFICATION QTY
1. NOT GATE IC 7404 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NAND GATE IC 7400 1
5. NOR GATE IC 7402 1
6. DIGITAL IC TRAINER KIT - 1
7. PATCH CORD - -
Theory:
DeMorgans Theorem:
a) AB = A + B:
The complement of a product of the variables is equal to the sum of complements of the
variables.
b) (A+B) = AB:
The complement of a sum of the variables is equal to the product of complements of the
variables.
Consensus Theorem:
In the simplification of Boolean expression, an expression of the form AB+AC+BC the term
BC is redundant and can be eliminated to form the equivalent expression AB+AC. By consensus
theorem,
AB+AC+BC = AB+AC
Logic Diagram:
Consensus Theorem - (AB + AC + BC) = (AB+AC):
(AB + AC + BC):
(AB+AC):
Truth Table for (AB + AC + BC) = (AB+AC):

A B C (AB+AC+BC) (AB+AC)
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1
The key to recognize the consensus term is to first find a pair of terms, one of which contains a
variable and the other contains its complement. Now we have to find the third term which should
contain the remaining variables from pair of terms eliminating selected variable and its
complement.
Duality Theorem:
The duality theorem says that, starting with a Boolean relation, you can derive another Boolean
relation by,
a) Changing each OR sign to an AND sign.
b) Changing each AND sign to an OR sign.
c) Complementing any 0 (or) 1 appearing in the expression.
For example, A + 0 = A, applying duality theorem, A.1 = A. This duality property is obtained
by changing the OR sign to an AND sign, and by complementing the 0 to get a 1. Considering
the following distributive law,
A(B+C) = AB+AC
Applying duality theorem on the above equation,
A+BC = (A+B)(A+C)
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.

Logic Diagram:
Duality Theorem:
A+BC:
(A+B)(A+C):
Truth Table for A+BC = (A+B)(A+C):

A B C (A+B)(A+C) A+BC
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

Result:
Thus the Boolean theorems are verified using logic gates.

Logic Diagram:
Function (Y = ABD+BCD+ACD+ABC):
Truth Table:
The Logic circuit has 4 inputs, output will only be high when majority of the
inputs are high.
INPUTS OUTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0

1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
EX: NO: DESIGN AND IMPLEMENTAION OF ARBITARY

DATE: FUNCTIONS USING BASIC GATES:
AIM:
To design and implement combinational circuits using basic gates for arbitrary functions.
Apparatus Required:
5. PATCH CORD - -
Theory:
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables, with no storage involved, the resulting circuit is called a
combinational logic. In combinational logic, the output variables are at all times dependent on the
combination of input variables.
A combinational circuit consists of input variables, logic gates, and output variables. The logic
gate accepts signals from the input and generates output signals. This process transforms binary
information from given input data to the required output data.
For n input variables, there are 2 n possible binary input combinations. For each possible input
combination, there is one possible output value. Thus, a combinational circuit can be specified
with a truth table that lists the output values for each combination of input variables. A
combinational circuit also can be described by m Boolean functions, one for each output variable.
Each output function is expressed in terms of the n input variables.
~ 10 ~ CS6211-DIGITAL LABORATORY
Procedure:
K-Map for majority checker:
Y= ABD + BCD + ACD + ABC

Logic Diagram:
Function (Y = P + QR):
Truth Table:
The Logic circuit has 3 inputs P, Q and R, output will be high when P is zero or
whenever Q=R=1.
K-Map:
INPUTS OUTPUT
P Q R S
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0 Y = P + QR
1 1 1 1
Result:
Thus digital logic function for combinational circuit was designed and implemented using basic
gates.
Logic Diagram:
BCD to Excess-3 Code Converter:
Excess-3 to BCD Code Converter:
EX: NO: DESIGN AND IMPLEMENTATION OF COMBINATIONAL

DATE: CIRCUITS FOR CODE CONVERTERS:
Aim:
To design, implement and verify combinational circuits using basic gates for the following code
converters,
a) BCD to Excess-3 code converter
b) Excess-3 to BCD code converter
Apparatus Required:
4. X-OR GATE IC 7486 1
5. 3 INPUT AND GATE IC 7411 1
7. PATCH CORD - -
Theory:
Code Converters:
The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between
the two systems if each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses different binary code.
Binary Coded Decimal:

Binary Coded Decimal is a method of using binary digits to represent the decimal digits 0
through 9. It is possible to assign weights to the binary bits according to their positions. The
weights in the BCD code are 8, 4, 2 and 1. Ex: (127)10 - BCD equivalent (0001 0010 0111)2.
Truth Table for BCD to Excess-3 code and Vice Versa:

BCD input Excess 3 output
B3 B2 B1 B0 X3 X2 X1 X0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
K-Map for BCD to Excess-3 Code Converter:
K-Map for X0: K-Map for X1:
X0 = B0
Excess-3 Code:
This is an un-weighted code. Its code assignment is obtained from the corresponding value of
BCD after the addition of (0011)2.
BCD to Excess-3 (or) Excess-3 to BCD:

Since each code uses four bits to represent a decimal digit, there must be four inputs and four
output variables. Four binary variables have sixteen different input combinations, only ten of the
input combinations are listed in the truth table. The six bit combinations not listed for the input
variables are dont care combination. For BCD to Excess-3, the input variable are designated as
B3, B2, B1, B0 and the output variables are designated as X3, X2, X1, X0 in the truth table. The
Boolean functions are obtained from K-Map for each output variable. The combinational logic
for the code converters are designed according the Boolean expressions from K-Map
simplification. The Boolean expressions from the K-Map are shown below.
Boolean Expression for BCD to Excess-3 Code Conversion:

X3 = B0B2 + B1B2 + B3
_ _ _ _
X2 = B0B2 + B1B2 + B0B1B2
_______
X1 = B0 B1
_
X0 = B0
Boolean Expression for Excess-3 to BCD Code Conversion:

B3 = X0X1X3 + X2X3
_ _ _
B2 = X0X2 + X0X1X2 + X1X2
B 1 = X0 X1
_
B 0 = X0
Procedure:
K-Map for X2: K-Map for X3:
X2 = B2(B0+B1) + B2B1B0 X3 = B3 + B2(B0+B1)
K-Map for Excess-3 to BCD Code Converter:

K-Map for B0: K-Map for B1:
B0 = X0 B1 = X1 X0
K-Map for B2: K-Map for B3:
B2 = X2X0+X2X1+X2X1X0 B3= X3X1X0 + X3X2
Result:
Thus BCD to Excess-3 and Excess-3 to BCD converters are designed and implemented using
basic gates and their truth table was verified.
Logic Diagram:
4 Bit Adder/Subtractor Circuit Diagram:
Internal Circuit Diagram for Full Adder FA0:
EX: NO: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY

DATE: ADDER/ SUBTRACTOR USING BASIC GATES:
Aim:
To design and implement 4 bit binary adder and 4 bit binary subtractor using basic gates.
Apparatus Required:
4. DIGITAL IC TRAINER KIT - -
5. PATCH CORD - -
Theory:
The full adder/sub tractors are capable of adding/subtracting only two single digit
binary numbers along with a carry input. But in practice we need to add/subtract binary numbers,
which are much longer than just one bit. To add/subtract two n-bit binary numbers we need to use
the n-bit parallel subtractor/adder.
Binary adder:
The two 4-bit input binary numbers are A0 through A3 and B0 through B3. The sum is
obtained from S0 through S3. Cin0 is the input carry and Cout3 the output carry. The circuit
consists of four full adders connected in cascade with the inputs to full adders A0 through A3 and
B0 through B3. The output carry of the previous stage is the input carry to current stage. Here the
carry ripples through the 4 full adders.
Binary Subtractor:
The subtraction of two binary numbers can be done by taking the 2s complement of the
subtrahend and adding it to the minuend. The 2s complement can be obtained by taking the 1s
complement and adding. To perform A-B, we complement the four bits of B, add them to the four
bits of A, and add 1 through the input carry. The four XOR gates complement the bits of B when
the input add/sum is 1(because Z xor 1 = Z) and leaves the bits of B unchanged when
add/sub=0 (because Z xor 0 = Z). Thus , when the add/sum is equal to 1, the input carry Cin0
is equal 1 and the sum output is A plus the 2s complement of B. when add/sum is equal to 0,
the input carry is equal to 0 and the sum generates A+B.
Procedure:
3. Switch on VCC and apply and verify various combinations of input according to the truth
table for 4 bit binary adder/subtractor,
a) By keeping add/sub as low, binary addition takes place.
b) By keeping add/sub as high, binary subtraction takes place.
Result:
Thus the 4 bit binary adder, 4 bit binary subtractor was designed and implement basic gates
with their truth table verified.
Pin Diagram:
4 Bit Adder/Subtractor circuit diagram:
EX: NO: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY

DATE: ADDER/ SUBTRACTOR USING MSI DEVICES:
Aim:
To design and implement 4 bit binary adder and 4 bit binary subtractor using IC 7483 MSI
device.
Apparatus Required:
3. PATCH CORD - -
Theory:
Four bit binary adder:

A 4 bit binary adder can be constructed using four full adders. Here the full adders are
connected in cascade, with the output carry from each full adder connected to the input carry of
next full adder in chain. The input carry to the adder is C1 and it ripples through the full adder to
the output carry C4.
Four bit binary subtractor:

Binary subtraction is done using 2s complement subtraction method. For subtracting B from A
using adders, S = A + B + 1. A 4 bit binary subtractor using 4 bit binary adder consists of
inverted B inputs and the carry input C1 set to 1.
Four bit binary adder/subtractor:

A4 bit binary adder/subtractor is used to perform both addition and sub-traction using a control
line add/sub. If add/sub =0 binary addition takes place and if add/sub = 1 binary subtraction
takes place, i.e. 2s complement subtraction of B from A.
Truth table - 4 Bit Binary Adder/Sub-tractor:

Adder: Add/sum = 0, Sub-tractor: Add/Sum = 1
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1 Bout D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
Procedure:
6. Switch on VCC and apply and verify various combinations of input according to the truth
table for 4 bit binary adder/subtractor,
c) By keeping add/sub as low, binary addition takes place.
d) By keeping add/sub as high, binary subtraction takes place.
Result:
Thus the 4 bit binary adder, 4 bit binary subtractor was designed and implement using IC 7483
MSI devices with their truth table verified.
PIN DIAGRAM FOR IC 74180: PIN DESCRIPTION:

I0 I7 = Data Inputs
PO = Odd Input
PE = Even Input
O = Odd Parity Output
E = Even Parity Output
Logic Diagram:
16 Bit Odd/Even Parity Generator:
Truth Table:
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 115 Active E O
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
EX: NO: DESIGN AND IMPLEMENTATION OF 16 BIT ODD/EVEN

DATE: PARITY GENERATOR USING MSI DEVICES:
Aim:
To design and implement 16 bit odd/even parity generator using IC 74180 MSI device.
Apparatus Required:
1. NOT Gate IC 7404 1
2. 8-bit parity generator/ checker IC 74180 2
3. Digital IC trainer kit - 1
4. Patch cord - -
Theory:
When digital data is transmitted from one location to another, it is necessary to know at
the receiving end, whether data received is free from errors. To help make the transmission
accurate, special error detection methods are used. To detect errors there must be constant check
on the data being transmitted. To check accuracy of the data an extra bit can be generated and
transmitted along with the data. This bit is called the parity bit. A parity bit is used for detecting
errors during transmission of binary information.
Parity generators are circuits that accept an n-1 bit data stream and generate an extra bit
that is transmitted with the bit stream. This extra bit is referred to as parity bit. In an even parity
bit scheme, the parity bit is 1 if there are odd number of 1s in the data stream and the parity bit
is 0 if there are even number of 1s in the data stream. In the case of odd parity bit scheme, the
reverse happens, that is the parity bit is 0 for odd number of 1s and 1 for even number of 1s
in the bit stream.
Procedure:
Result:
Thus a 16-bit parity generator was designed and implemented using IC74180 MSI devices with
its truth table verified.
PIN DIAGRAM FOR IC 74180: PIN DESCRIPTION:

I0 I7 = Data Inputs
PO = Odd Input
PE = Even Input
O = Odd Parity Output
E = Even Parity Output
Logic Diagram:
16 Bit Odd/Even Parity Checker:
Truth Table:
I7 I6 I5 I4 I3 I2 I1 I0 I7I6I5I4I3I211 I0 Active E O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
EX: NO: DESIGN AND IMPLEMENTATION OF 16 BIT ODD/EVEN

DATE: PARITY CHECKER USING MSI DEVICES:
Aim:
To design and implement 16 bit odd/even parity checker using IC 74180 MSI device.
Apparatus Required:
1. NOT Gate IC 7404 1
2. 8-bit parity generator/ checker IC 74180 2
4. Patch cord - -
Theory:
A parity bit is used for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number as either even or
odd. The message including the parity bit is transmitted and then checked at the receiver end for
errors. An error is detected if the checked parity bit doesnt correspond to the transmitted parity
bit. The circuit that generates the parity bit in the transmitter is called a parity generator and the
circuit that checks the parity in the receiver is called a parity checker.
In even parity, the added parity bit will make the total number of 1s as even. In odd
parity, the added parity bit will make the total number of 1s as odd. The parity checker circuit
checks for possible errors in the transmission. If the information is passed in even parity, then the
bits required must have an even number of 1s. An error occur during transmission, if the
received bits have an odd number of 1s indicating that one bit has changed in value during
transmission.
Procedure:
Result:
Thus a 16-bit parity checker was designed and implemented using IC74180 MSI device with its
truth table verified.
Logic Diagram:
Parity Generator:
Truth Table Odd/Even Parity Generator:
INPUT OUTPUT
A B C OP EP
0 0 0 1 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
k-Map for Odd Parity Generator:
OP = ABC + ABC + ABC + ABC

= B(AC+AC) + B(AC + AC)
= B(AC + AC)+ B(AC + AC)
OP = (A B C)
Note: From the truth table it is clear that both even parity and odd parity generator are
complementary logic. Therefore the Boolean expression for even generator,
EP = (A B C)
EX: NO: DESIGN AND IMPLEMENTATION OF PARITY

DATE: GENERATOR USING BSAIC GATES:
Aim:
To design and implement parity generator using basic gate.
Apparatus Required:
2. XOR GATE IC 7486 1
4. Patch cord - -
Theory:
When digital data is transmitted from one location to another, it is necessary to know at
the receiving end, whether data received is free from errors. To help make the transmission
accurate, special error detection methods are used. To detect errors there must be constant check
on the data being transmitted. To check accuracy of the data an extra bit can be generated and
transmitted along with the data. This bit is called the parity bit. A parity bit is used for detecting
errors during transmission of binary information.
Parity generators are circuits that accept an n-1 bit data stream and generate an extra bit
that is transmitted with the bit stream. This extra bit is referred to as parity bit. In an even parity
bit scheme, the parity bit is 1 if there are odd number of 1s in the data stream and the parity bit
is 0 if there are even number of 1s in the data stream. In the case of odd parity bit scheme, the
reverse happens, that is the parity bit is 0 for odd number of 1s and 1 for even number of 1s
in the bit stream.
Procedure:
Result:
Thus parity generator was designed and implemented using basic gates with its truth table
verified.
Logic Diagram:
Parity Checker:
Truth Table Odd/Even Parity Checker:
Input Input Parity Output

A B C Odd/Even(P) OPout EPout
0 0 0 0 1 0
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 1 0
EX: NO: DESIGN AND IMPLEMENTATION OF PARITY

DATE: CHECKER USING BSAIC GATES:
Aim:
To design and implement parity checker using basic gate.
Apparatus Required:
2. XOR GATE IC 7486 1
4. Patch cord - -
Theory:
A parity bit is used for detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number as either even or
odd. The message including the parity bit is transmitted and then checked at the receiver end for
errors. An error is detected if the checked parity bit doesnt correspond to the transmitted parity
bit. The circuit that generates the parity bit in the transmitter is called a parity generator and the
circuit that checks the parity in the receiver is called a parity checker.
In even parity, the added parity bit will make the total number of 1s as even. In odd
parity, the added parity bit will make the total number of 1s as odd. The parity checker circuit
checks for possible errors in the transmission. If the information is passed in even parity, then the
bits required must have an even number of 1s. An error occur during transmission, if the
received bits have an odd number of 1s indicating that one bit has changed in value during
transmission.
K-Map for Odd Parity Checker:
OPout = ABCP + ABCP+ ABCP + ABC P + ABCP + ABCP + ABCP + ABCP

= AB(CP + CP) + AB(CP + CP) + AB(CP + CP) + AB(CP + CP)
= AB(C P) + AB(C P) + AB(C P) + AB(C P)
= (C P)(AB + AB) + (C P)(AB+AB)
= (C P)(A B) + (C P)(A B)
OPout = (A B C P)
Note: From the truth table it is clear that both even parity and odd parity checker are
complementary logic. Therefore the Boolean expression for even checker,
EPout = (A B C P)
Procedure:
Result:
Thus the parity checker was designed and implemented using basic gates with its truth table
verified.
Logic Diagram:
Two Bit Magnitude Comparator:
EX: NO: DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE

DATE: COMPARATOR:
Aim:
To design and implement of 2 bit Magnitude Comparator using logic gates
Apparatus Required:
5. 3-Input AND Gate IC 7411 2
7. PATCH CORD - -
Theory:
The comparison of two numbers is an operation that determines one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B to determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.
Consider two numbers A and B with two digits each. Here A = A1 A0 and B = B1 B0.
Now the Boolean equation for the two numbers to be equal to, greater than and lesser than are as
follows,
(A=B) = (A0 B0) (A1 B1)

(A>B) = A0B0B1 + A1B1 + A1A0B0
(A<B) = A1A0B0 + A0B0B1 + A1B1
Truth Table for Two Bit Magnitude Comparator:

Inputs Outputs
A1 A0 B1 B0 A> B A= B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K-Map for Two Bit Magnitude Comparator:

K-Map for (A>B): K-Map for (A<B):
[A>B] = A0B0B1 + A1B1 + A1A0B0 [A<B] = A1A0B0 + A0B0B1 + A1B1
K-Map for (A=B):
[A=B] = (A0 B0) (A1 B1)
Procedure:
Result:
D0was
Thus the 2 bit Magnitude Comparator to D7 Data Inputs.
designed and implemented using logic gates with
their truth table verified.
A, B, C Data Select Lines.
Pin Diagram - IC74151: Pin Description:
Vcc, Gnd Power and Ground Inputs.
Y Data Output.
W Complementary Data Output.

Strobe Active low Strobe Input.
Logic Diagram:
Implementation of Boolean Function Using 8:1 Multiplexer:
EX: NO: DESIGN AND IMPLEMENTATION OF APPLICATION

DATE: USING MULTIPLEXER:
Aim:
To design and implement application using multiplexer.
Apparatus Required:
2. 8:1 MULTPLEXER IC 74151 1
4. PATCH CORD - -
Theory:
Multiplexer:
Multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. Selection of input lines controlled by a set of selection
lines 2n input lines and n selection lines. Multiplexers are used to form a selected path between
multiple sources and single destination.
IC74151 8 to 1 Multiplexer:
IC74151 is a data selector/multiplexer IC that selects one of the eight data sources D0 to D7.
The STROBE input of the IC must be at a low logic level to enable these devices. A high level at
the STROBE forces the W output high and Y output low. Both W and Y are complement to each
other. Inputs A, B, C are the selector inputs. IC 74150 is used in parallel to serial conversion. In
digital communication, a number of input lines are connected to a single output channel using
multiplexer, so that information transmitted one by one in a time shared basis.
Multiplexer for Boolean Function Implementation:
Let the function to be implemented be as given below,

F(A,B,C,D) = m(0,1, 3,4,8,9,15)
= m0+m1+m3+m4+m8+m9+m15.
It is possible to implement any Boolean function of n variables with 2 n-1 to 1 multiplexer. In this
case, out of n variables n-1 variables are connected to the selection lines and the remaining single
variable is used for the multiplexer input. A truth table will be formed according to the given
function F(A,B,C,D).
Implementation Table:
D0 D1 D2 D3 D4 D5 D6 D7
A 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 A A 0 0 A
An implementation table is formed to decide the connections to the input and select line in
order to implement the given function. The implementation table contains list of inputs to the
multiplexer and under them listed all the min-terms. The first row lists all the min-terms where A
is complemented. Second row lists all the min-terms with A un-complemented.
The min-term given in the function are circled the column is inspected separately as follows,
If two min-term in a column are not circled, 0 is applied to the corresponding

multiplexer input.
If two min-terms in a column are circled, 1 is applied to the corresponding multiplexer

input.
If the min-terms in the second row are circled and min-term in the first row is not circled,
A is applied to the corresponding multiplexer input.
If the min-term in the first row is circled and min-term in second row is not circled, A is
applied to the corresponding multiplexer input.
Procedure:
Result:
Thus the given Boolean function was implemented using multiplexer with its truth table
verified.
Pin Diagram - IC74138: Pin Description:
Y0 to Y7 Active Low Data Outputs.
A, B, C Data Select Lines.
Vcc, Gnd Power and Ground Inputs.
G1 Enable Input.
G2A,G2B Active Low Enable Input.
Logic Diagram:
Implementation of Full Subtractor Using 1:8 De-Multiplexer:
EX: NO: DESIGN AND IMPLEMENTATION OF APPLICATION

DATE: USING DE-MULTIPLEXER:
Aim:
To design and implement application using de-multiplexer.
Apparatus Required:
2. 1:8 De-Multiplexer IC 74138 1
4. PATCH CORD - -
Theory:
De-Multiplexer:
De-multiplexer is a circuit that receives information on single line and transmits the
information on one of 2n possible output lines. Selection of specific output lines is controlled by n
selection lines.
IC74154 1 to 8 De-Multiplexer:
IC74153 will act as a 1 to 8 De-Multiplexer by using the 3 address lines A, B and C to address
the active low output lines Y0 to Y7, passing data from one of the enable input G1 with the other
enable inputs low. When either G1 is low or G2A, G2B inputs are high all the outputs are high.
IC 74153 is ideally suited for implementing high-performance memory decoders. In

telecommunication IC 74153 accepts a single input signal that carries many channels and
separates those over multiple output signals.
Implementation of Full Subtractor using 1:8 De-Multiplexer:

With Din input to 1, the de-multiplexer gives min-terms at the output so by applying logical
OR to the required min-terms, full subtractor function can be realized using de-multiplexer.
Truth Table:
S.No. A B Bin D Bout

0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1
D = F(A,B,C) = m(1, 2, 4, 7) .
Bout = F(A,B,C) = m(1, 2, 3, 7).
Procedure:
Result:
Thus full subtractor function was implemented using de-multiplexer with its truth table
verified.
Pin Diagram: Pin Description:

1CLR, 2CLR Low level clear inputs.
1PRE, 2PRE Low level pre-set inputs.
Vcc, Gnd Power and Ground pins.
1CLK, 2CLK Positive edge triggered clock inputs.
1D, 2D Data inputs.
1Q, 2Q Data outputs.
1Q, 2Q Complemented Data outputs.
Logic Diagram:
Serial In Serial Out:
Truth Table for SISO Shift Register :

Clk Serial input QA QB QC QD Serial Output
0 1 0 0 0 0 0
1 1 1 0 0 0 0
2 0 1 1 0 0 0
3 1 0 1 1 0 0
4 0 1 0 1 1 1
5 0 0 1 0 1 1
6 0 0 0 1 0 0
7 0 0 0 0 1 1
8 0 0 0 0 0 0
EX: NO: DESIGN AND IMPLEMENTATION OF

DATE: SHIFT REGISTERS:
Aim:
To implement SISO and SIPO shift registers using flip flop with its truth table verified.
Apparatus Required:
1. D FLIP FLOP IC 7474 2
3. PATCH CORD - -
Theory:
A register capable of shifting its binary information either to the right or to the left is called a
shift register. The logic types of shift registers in terms of data movement are,
Serial In Serial Out:

SISO shift register accepts data serially (i.e.) one bit at a time on a single line and produces the
stored data on its output also in serial form.
Serial In Parallel Out:
SIPO shift register accepts data serially and produces the stored information on its output in
parallel form.
Procedure:
1. Verify the flip flop.
4. By applying the clock pulse, all input combinations are given and the outputs are verified
with the truth table.
Logic Diagram:
Serial In Parallel Out:
Truth Table for SIPO Shift Register :

Clk Serial input QA QB QC QD Parallel Output
[QA QD]
0 1 0 0 0 0 0000
1 1 1 0 0 0 1000
2 0 1 1 0 0 1100
3 1 0 1 1 0 0110
4 0 1 0 1 1 1011
Result:
Thus SISO and SIPO shift registers was designed and implemented using flip flop with its truth
table verified.
Pin Diagram IC 7473: Pin Description:

1CP, 2CP = neg-edge clock input for JK Flip Flop 1 and 2
1R, 2R = Negative Clear Input for JK Flip Flop 1 and 2
1J, 2J = J Input
1k, 2k = K Input
1Q, 2Q = Q Output
1Q, 2Q = Q Output
Logic Diagram:
Four Bit Ripple Counter:
Truth Table for Four Bit Ripple Counter:

Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
EX: NO: DESING AND IMPLEMENTAION ASYNCHRONOUS
DATE: COUNTER:
Aim:
To design and implement 4 bit Ripple Counter.
Apparatus Required:
1. JK FLIP FLOP IC 7473 2
2. NAND GATE IC 7400 1
4. PATCH CORD - -
Theory:
Counters are a group of flip flops connected together to perform counting operation. According
to the way the flip flops are clocked, there are two types of flip flops,
a) Asynchronous Counter
b) Synchronous Counter
In asynchronous counter, the first flip flop is clocked by the external clock pulse. Then each
successive flip flops are clocked by Q (or) Q output of the previous flip flop. In 4-bit ripple
counter, the total number of states is 16 (24) and this varies from 00002 to 11112
Procedure:
4. By applying clock pulse, all the input combinations are given and the outputs are verified
Result:
Thus 4 bit Ripple Counter was designed and implemented with their truth table verified.
Pin Diagram IC 7473: Pin Description:

1CP, 2CP = neg-edge clock input for JK Flip Flop 1 and 2
1R, 2R = Negative Clear Input for JK Flip Flop 1 and 2
1J, 2J = J Input
1k, 2k = K Input
1Q, 2Q = Q Output
1Q, 2Q = Q Output
Logic Diagram:
3-bit synchronous up/down counter:
Truth Table - JK Flip Flop: Excitation Table - JK Flip Flop:

J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
DATE:
EX: NO: DESIGN AND IMPLEMENTATION OF

DATE: SYNCHRONOUS COUNTER:
Aim:
To design, implement 3 bit synchronous up/ down counter and verify its truth table.
Apparatus Required:
1. JK FLIP FLOP IC 7473 2
4. AND Gate IC 7408 1
6. PATCH CORD - -
Theory:
A counter that advances upward through its sequence (0, 1, 2, 3...0, 1.) is called up counter. A
counter that decrement downward through its sequence (3, 2, 1, 0, 3, 2 ..) is called down
counter. A up/down counter is a counter used to perform both up counting and down counting
operation using up/down control signal.
Procedure:
4. By applying the clock pulse, all input combinations are given and the outputs are verified
Truth Table:
Input
Up/Down Present State Next State Flip Flop Input
X QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA

1 0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
1 1 0 1 0 1 X 0 X 1 1 X
1 0 1 1 0 0 X 0 0 X X 1
1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 1 1 1 X 1 X 1 X
1 1 1 1 1 0 X 0 X 0 X 1
K-Map Simplification:
K-Map for JA: K-Map for JB:
JA = 1 JB = XQA+ XQA
K-Map for JC: K-Map for

KA:
JC = XQB QA + XQBQA KA = 1
K-Map for KB: K-Map for KC:
KB = XQA + XQA KC = XQB QA + XQBQA
Result:
Thus 3 bit synchronous up/ down counter was designed and implemented with its truth table
verified.
Logic Diagram:
Full Adder:
Truth Table:
A B Cin CARRY(Cout) SUM(S)
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
EX: NO: FULL ADDER AND FULL SUBTRACTOR USING

DATE: VERILOG:
Aim:
To develop and simulate the verilog code for full adder and full subtractor.
Software Required:
Mentor Graphics ModelSim simulator.
Verliog Code:
Full Adder:
module full_adder
(
a,
b,
cin,
sum,
carry
);
input a,b,cin;
output sum,carry;
assign sum = a ^ b ^ cin;

assign carry = (a & b)|(b & cin)|(a & cin);
endmodule
Logic Diagram:
Full Subtractor:
Truth Table:
A B Bin BORROW DIFFERENCE
(Bout) (Diff)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Full Subtrator:
module full_subtractor
(
a,
b,
bin,
diff,
borrow
);
input a,b,bin;
output diff,borrow;
assign diff = a ^ b ^ bin;

assign borrow = (~a & b)|(b & bin)|(~a & bin);
endmodule
Result:
Thus the verliog code for full adder and full subtractor circuit was developed and functionally
verified using the simulation outputs.
Logic Diagram:
4:1 Multiplexer:
Truth Table:
S0 S1 Output
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Output = D0S0S1+D1S0S1+D2S0S1+D3S0S1
EX: NO: MULTIPLEXER AND DE-MULTIPLEXER USING

DATE: VERILOG:
Aim:
To develop and simulate the verilog code for multiplexer and de-multipleser.
Software Required:
Verliog Code:
4:1 Multiplexer:
module mux_4to1
(
s1,
s2,
s3,
s4,
sel,
mux_out
);
input s1,s2,s3,s4;
input [1:0] sel;
output reg mux_out;
always @*
begin
case (sel)
2'b00:
mux_out=s1;
2'b01:
mux_out=s2;
2'b10:
mux_out=s3;
2'b11:
mux_out=s4;
endcase
end
endmodule
Logic Diagram:
1:4 De-Multiplexer:
Truth Table:
Input Output
D S0 S1 D0 D1 D2 D3
1 0 0 D 0 0 0
1 0 1 0 D 0 0
1 1 0 0 0 D 0
1 1 1 0 0 0 D
D0 = DS0S1
D1 = DS0S1
D2 = DS0S1
D3 = DS0S1
1:4 De-Multiplexer:
module demux_1to4
(
s1,
s2,
s3,
s4,
sel,
mux_in
);
output reg s1,s2,s3,s4;

input [1:0] sel;
input mux_in;
always @*
begin
case (sel)
2'b00:
s1=mux_in;
2'b01:
s2=mux_in;
2'b10:
s3=mux_in;
2'b11:
s4=mux_in;
endcase
end
endmodule
Result:
Thus the verliog code for multiplexer and de-multiplexer was developed and functionally
verified using the simulation results.
Logic Diagram:
Mod-10 Ripple Counter:

Truth Table for Mod 10 Counter:

Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
EX.NO: MOD-10 AND MOD-12 RIPPLE COUNTERS USING

DATE: VERILOG:
Aim:
To develop and simulate the verilog code for mod-10 and mod-12 ripple counters.
Software Required:
Verliog Code:

module mod10
(
rst,
clk,
count_out
);
input rst,clk;
output reg [3:0] count_out;
always @(posedge clk,posedge rst)

begin
if(rst)
count_out<=0;
else
begin
count_out<=count_out+1;
if(count_out==9)
count_out<=0;
end
end
endmodule
Logic Diagram:
Truth Table for Mod 12 Counter:

Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0

module mod12
(
rst,
clk,
count_out
);
input rst,clk;
output reg [3:0] count_out;
always @(posedge clk,posedge rst)

begin
if(rst)
count_out<=0;
else
begin
count_out<=count_out+1;
if(count_out==11)
count_out<=0;
end
end
endmodule
Result:
Thus the verliog code for mod-10 and mod-12 ripple counter was developed and functionally
verified using the simulation outputs.
Logic Diagram:
SISO Shift Registers:
Truth Table for SISO Shift Register :

Clk Serial input QA QB QC QD Serial Output
0 1 0 0 0 0 0
1 1 1 0 0 0 0
2 0 1 1 0 0 0
3 1 0 1 1 0 0
4 0 1 0 1 1 1
5 0 0 1 0 1 1
6 0 0 0 1 0 0
7 0 0 0 0 1 1
8 0 0 0 0 0 0
EX: NO: SISO AND SIPO SHIFT REGISTERS USING VERILOG:

DATE:
Aim:
To develop and simulate the verilog code for SISO and SIPO shift registers.
Software Required:
Verliog Code:
SISO Shift Registers:

module siso (
rst,
clk,
serial_in,
serial_out
);
input rst, clk,serial_in;

output serial_out;
reg [3:0] tmp;
always @(posedge clk, posedge rst)

begin
if(rst)
tmp=0;
else
begin
tmp = tmp<<1;
tmp[0] = serial_in;
end
end
assign serial_out = tmp[3];
endmodule
Logic Diagram:
SIPO Shift Registers:
Truth Table for SIPO Shift Register :

Clk Serial input QA QB QC QD Parallel Output
[QA QD]
0 1 0 0 0 0 0000
1 1 1 0 0 0 1000
2 0 1 1 0 0 1100
3 1 0 1 1 0 0110
4 0 1 0 1 1 1011
SIPO Shift Registers:

module sipo (clk,
rst,
serial_in,
parallel_out
);
input clk,rst,serial_in;
output [3:0] parallel_out;
reg [3:0] tmp;
always @(posedge clk, posedge rst)

begin
if(rst)
tmp=0;
else
begin
tmp = tmp<<1;
tmp = {tmp[2:0], serial_in};
end
end
assign parallel_out=tmp;
endmodule
Result:
Thus the verliog code for SISO and SIPO shift registers was developed and functionally
verified using the simulation results.

Digital Lab

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R.M.K. college of Engg. & Technology Dept.

~1~ CS6211-DIGITAL LABORATORY

PIN DIAGRAM OF BASIC LOGIC GATES:

Verification of DeMorgans Theorem:

Truth Table for (AB)=A+B:

Truth Table for (A+B)=AB:

~3~ CS6211-DIGITAL LABORATORY

EX: NO: VERIFICATION OF BOOLEAN THEOREMS

SI. No. COMPONENT SPECIFICATION QTY

1. NOT GATE IC 7404 1

2. AND GATE IC 7408 1

4. NAND GATE IC 7400 1

5. NOR GATE IC 7402 1

6. DIGITAL IC TRAINER KIT - 1

Truth Table for (AB + AC + BC) = (AB+AC):

~6~ CS6211-DIGITAL LABORATORY

Truth Table for A+BC = (A+B)(A+C):

~7~ CS6211-DIGITAL LABORATORY

~8~ CS6211-DIGITAL LABORATORY

~9~ CS6211-DIGITAL LABORATORY

EX: NO: DESIGN AND IMPLEMENTAION OF ARBITARY

SI. No. COMPONENT SPECIFICATION QTY

1. NOT GATE IC 7404 1

2. AND GATE IC 7408 1

4. DIGITAL IC TRAINER KIT - 1

K-Map for majority checker:

Y= ABD + BCD + ACD + ABC

Excess-3 to BCD Code Converter:

EX: NO: DESIGN AND IMPLEMENTATION OF COMBINATIONAL

SI. No. COMPONENT SPECIFICATION QTY

1. NOT GATE IC 7404 1

2. AND GATE IC 7408 2

4. X-OR GATE IC 7486 1

5. 3 INPUT AND GATE IC 7411 1

6. DIGITAL IC TRAINER KIT - 1

Binary Coded Decimal:

Truth Table for BCD to Excess-3 code and Vice Versa:

K-Map for BCD to Excess-3 Code Converter:

K-Map for X0: K-Map for X1:

BCD to Excess-3 (or) Excess-3 to BCD:

Boolean Expression for BCD to Excess-3 Code Conversion:

Boolean Expression for Excess-3 to BCD Code Conversion:

K-Map for X2: K-Map for X3:

X2 = B2(B0+B1) + B2B1B0 X3 = B3 + B2(B0+B1)

K-Map for Excess-3 to BCD Code Converter:

K-Map for B2: K-Map for B3:

B2 = X2X0+X2X1+X2X1X0 B3= X3X1X0 + X3X2

4 Bit Adder/Subtractor Circuit Diagram:

Internal Circuit Diagram for Full Adder FA0:

EX: NO: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY

SI. No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 2

3. X-OR GATE IC 7486 3

4. DIGITAL IC TRAINER KIT - -

Internal Circuit Diagram for Full Adder FA1:

Internal Circuit Diagram for Full Adder FA2:

Internal Circuit Diagram for Full Adder FA3:

4 Bit Adder/Subtractor circuit diagram:

EX: NO: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY

SI. No. COMPONENT SPECIFICATION QTY

1. X-OR GATE IC 7486 1

2. DIGITAL IC TRAINER KIT - 1

Four bit binary adder:

Four bit binary subtractor: