Vous êtes sur la page 1sur 2

"UVM for VHDL" - UVVM: Universal VHDL Verication

Methodology
bitvis.no/resources/presentations/uvvm/

UVM (and SystemVerilog) are new buzzwords within advanced ASIC verication, but are often mentioned also for
FPGA verication. There is no doubt that verication is a major and increasing challenge for FPGA development,
but for most FPGA projects UVM is denitely not the answer to this challenge. For almost all companies using VHDL
for their FPGA development it doesnt make sense to change to UVM/SystemVerilog for verication. In fact, in most
cases changing to UVM/SystemVerilog will result in lower eciency and a higher cost. UVM/SystemVerilog is a
huge step in complexity, a totally dierent way of thinking, a new language and methodology very dierent from
VHDL and component orientation, and also a very expensive path with respect to tool cost.

However, UVM and SystemVerilog (and SystemC) have introduced (or standardised) some very interesting
concepts which in themselves denitely may improve lots of verication scenarios. Most of these concepts are
language independent and possible to implement in VHDL. Thus it would make very much sense to introduce these
concepts into our VHDL based testbenches, - as evolutionary and logical steps for the designers, allowing them to
continue with their current language and component orientation and then take a small step further whenever
needed.

The main problem with this approach so far has been that designers have built ad-hoc solutions, not suciently
structured, with insucient focus on understandability, maintenance and re-use. Over the last few years this has
been changing.

VHDL 2008 is a major improvement on the language itself.


OSVVM (free, open source library) is available as an excellent support for advanced random generation and
functional coverage.
This library will be updated with more functionality for advanced verication like scoreboards and more
support for coverage driven verication.
Bitvis Utility Library (free, open source library) was released last year with great support for logging/reporting,
verbosity control, alert handling and predened value and event checkers. This library should be used for any
testbench - from simplest to most complex.

With these improvements VHDL has already taken signicant steps as a verication language and methodology.
Now Bitvis introduces UVVM (Universal VHDL Verication Methodology) to take another major step. In the rst
release of UVVM we have focused on the main and most important missing methodology aspect - VHDL Verication
Components (VVC).

Most FPGAs and modules have two or more interfaces that need to operate simultaneously, and lots of corner cases
arise from the access to these interfaces at arbitrary times. Even a simple module like a UART has lots of corner
cases - for instance due to the possibility of CPU reads of the RX-register being executed at random times with
respect to data actually entering the RX register/FIFO/buer from the RX interface. To verify that all these corner
cases are OK requires simultaneous stimuli (and monitoring) of all interfaces and the ability to skew these accesses
with respect to each other. In most TBs this is handled in a very unstructured, ad-hoc manner.

UVVM provides a simple, structured and reusable approach to this problem. In UVVM we have taken care of all the
complexity of distributing commands to VVCs, queuing them inside the VVCs and executing them towards the DUT.
The VVCs may also have local sequencers, controlled by the main/central TB sequencer, and of course a system to
1/2
synchronize the various VVCs so that the central sequencer is easy to understand, extend and maintain. UVVM also
provides an excellent reporting system using the verbosity control of Bitvis Utility Library, allowing the user to follow
a command on its way from the sequencer to actual execution. Most of all, UVVM oers a methodology and usage
that is easy to understand for anyone with a VHDL or software background. UVVM also allows random stimuli in a
controlled manner.

UVVM will be released in Q2 2015, but with beta-release for selected customers Q1 (2015).
This is only the rst stage. We have several enhancements in mind for future releases. These will all be published
on our website.

An introduction to UVVM will be presented at FPGA-forum in Trondheim, February 12, 2015. The presentation will
be made available on our web-site in February.

Complete list of Presentations and Articles

inShare

2/2