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+ Des ign' Semester I
I

(2% Hours) [Total Marks: 75]

N.B. 1) All questions are compulsory.

2) Figures to the right indicate marks.
3) lllustrations, in-depth answers and diagrams will be appreciated.
4) Mixing of sub-questions is not allowed.

Q. 1 Attempt All(Each of SMarks) (1sM

)
(a) Select appropriate choice from the following:
i. The number of bits in ASCII code is _ _ d
ii. Which of the following system is digital. d
iii. The program written in our own alphanumeric characters is
called_c
iv. The duplicate registers are sometimes called as _b_
v. The numer of data registers in coldfire processor is -- c

(b) Fill in the blanks

1. Ludwig Wittgenstein Mathematician developed rules for manipulating binary
variables.
2. lf one of the inputs to an OR gate is high its output will be High
3. The term used for converting alphabets, numbers into binary is Encrypting
4. A K-map of n variables contains _2"_ cells.
5. CISC stands for Complex Instruction Set Gomputers
(c) Short Answers

i. What is BCD? Binary coded decimal

ii. What is the binary equivalent of decimal 22?
iii. Sate any 2 mnemonic names used in assembly language &their role.
LOAD, STO, ADD MULT EtC
iv. State the types of machine instructions.: Move, arithmetic, Jump & loop
etc
v. Define exception.
the term exception is used generally to describe any hardware-initiated or software-
initiated deviation from normal execution.

Q.2 Attempt the following (Any THREE)(Each of SMarks) (15M

)
(a) Write a note on computer number system.
General definition-> 1M base, no of digits ,msd ,lsd ->2 M
Types - binary octal hexadecimal ->3M
(b) State the basic logic gates. Explain any one.
AND, OR & NOT -> 1M
Explanation with dig. ->4M
 What is the role of shift re
An individual flip-flop can be used to store one bit.
Howeier, in machines in which
data are handled in words consisting of many bits (perhaps
as many as 54), it is
convenient to arrange a number of flip-flops
into a common structure called a
register. The operation of all flip-flops in a register is
synchronized by a common clock.
Thus, data are written(roaded) into or read from
ail frip-frops at the same time.
Processing of digitar data often requires the capabirity
to shift and rotate the data, so
it is necessary to provide the hardware with this facility. A simple
mechanism for
realizing both operations is a register whose contents
may be shifted to the right or
left one bit position ->3M
Example DiglExplanatin->2M

What is ripple counter? Explain witn exanrple.

A simple three-stage (or 3-bit) counter can be constructed
with T flip-flops. when the
T input is equal to 1, the frip-frop acts as a toggre, that is,
its state changes with each
successive clock pulse. Thus, two clock pulses will cause
e0 to change from the 1 state
to the 0 state and back to the 1 state or from 0 to r. to o. This
meinsthat the output
waveform of Q0 has half the frequency of the clock. similarly, because
the second flip-
flop is driven by e0, the waveform at e1 has half the frequency
oi eo, or one_fourth
the frequency of the clock. Note that we have assumed that
the positive edge of the
clock input to each flip-flop triggers the change of its state.
Such a counter is often
called a ripple counter because the effect of an input clock pulse
ripples through the
counter' For example, the positive edge of purse 4 wiil change the state
of e0 from 1
to 0. This change in e0 will then force e1 from 1 to 0, which in turn
forces e2 from o
to 1. lf each flip-flop introduces some deray , then the deray in setting
e2 is 3. such
delays can be a problem when very fast operation of counter
circuits is required.

Explain the steps to synttrffi

1. Develop an appropriate state diagram or state table.
2. Determine the number of flip-flops needed, and choose a suitable
type of flip_
flop.
3. Determine the values to be stored in these flip-flops for each state
in the state
diagram. This is referred to as state assignment.
522 AP P E N D I X A .Logic Circuits
4. Develop the state-assigned state table.
5. Derive the next-state logic expressions needed to control the
inputs of the flip-
flops.
Also, derive the expressions for the outputs of the circuit.
5. Use the derived to implement the circuit.
Write a note on multiplexer.
we know that decoders select one output line on the basis of input signals. The
selected output line has logic value 1, while the other outputs have
the value 0.
Another class of very useful selector circuits exists in which any one
of n data inputs
can be selected to appear as the output. The choice is governed by
a set of ,,select,,
inputs. Such circuits are called multiplexers.
Suppose two select inputs, w1 and w2. Their four possible valuations are used to
select one of four inputs, xr, x2, x3, or x4, to appear as the output z. A simple
logic
 circuit that can implement the require
realize larger multiplexers, in which k
data inputs to the output.
The obvious application of multiplexers is in the gating of data
that may come from a
number of different sources. For example, loading a 16-bit data register
from one of
four distinct sources can be accomplished with sixteen 4-input multiplexers.

Q.3 Aftempt the fottowing (Any T@ (1sM

)
(a) Describe memory organisatio
The memory consists of many millions of storage cells, each of which can store
a bit of information having the value 0 or 1. Because a single bit represents a
very small amount of information, the usuat approach is to deal with them in
groups of fixed size. For this purpose, the memory is organized so that group
a
of n bits can be stored or retrieved in a single, basic operation. Each group of n
bits is referred to as a word of information, and n is called the word length. The
memory of a computer can be schematically represented as a collection of
words.
Accessing the memory to store or retrieve a single item of information, either a
word or a byte, requires distinct names or addresses for each location. lt is
customary to use numbers from 0 to 2k - 1, for some suitable value of k, as the
addresses of successive locations in the memory. Thus, the memory can have
up to 2k addressable locations.
(b) Write in brief about CISC instruction set.
Complex Instruction Set Computers (CISC).
CISC instruction sets are not constrained to the load/store architecture, in which
arithmetic and logic operations can be performed only on operands that are in
processor registers.
instructions do not necessarily have to fit into a single word. Some instructions may
occupy a single word, but others may span multiple words.
lnstructions in modern CISC processors typically do not use a three-address format.
Most arithmetic and logic instructions use the two-address format Operation
destination, source-
exampleAn Add instruction of this type is Add B, A
which performs the operation B + tAl + [B] on memory operands. when the sum is
calculated, the result is sent to the memory and stored in location B, replacing the
original contents of this location. This means that memory location B is both a source
and a destination.
Consider again the task of adding two numbers
C=A+B
where allthree operands may be in memory locations. Obviously, this cannot be done
with a single two-address instruction. The task can be performed by using another
two-address instruction that copies the contents of one memory location into
another. Such an instruction is Move C, B
which performs the operation Ce[B], leaving the contents of location B unchanged.
The operation c[A] + [B] can now be performed by the two-instruction sequence
 Move C, B Add C, A
that by using this sequence of instructions the contents
9!::ry.
locations
of neither A nor B
are overwritten.
Which type of addressing mode is
Index mode-The effective address of the operand is generated
by adding a constant
value to the contents of a register,
For convenience, we will refer to the register used in
this mode as the index register.
Typically, this is just
a general-purpose register. we indicate the Index mode
symbolically as X(Ri)
where X denotes a constant signed integer value contained in the
instruction and Ri is
the name of the register involved. The effective address of the operand given
is by
EA=X+[Ri]
The contents ofthe register are not changed in the process ofgenerating the effective
address.
State & explain the ways of byte address assignment.

machines, ln both cases, byte addresses o, 4, 9,. . . are taken as the

, addresses of
successive words in the memory of a computer with a 32-bit word length.
These are
the addresses used when accessing the memory to store or retrieve a word.
Even lf dig. ls there give marks
For following instruction which address m
operation.
The Absolute mode is used in the instruction
LOAD R1 N1 loads value from mem lc N1 to regi Rl
LOAD R2 N2
ADD R2 R2 R1 adds cont f R1 R2 into R2
Write a note on assembly language.
Machine instructions are represented by patterns of 0s and 1s. such patterns
are difficult to deal with when preparing programs. Therefore, we use symbolic
names to represent the patterns. so far, we have used normal words, iuch as
Load, store, Add, and Branch, for the instruction operations to represent the
corresponding binary code patterns.
when writing programs for a specific computer, such words are normally
replaced by acronyms called mnemonics, such as LD, sr, ADD, and BR. A
shorthand notation is also useful when identifying registers, such as R3 for
register 3. Finally, symbols such as Loc may be defined as needed to
represent particular memory locations. A complete set of such symbolic names
and rules for their use constitutes a programming language, generally referred
to as an assembly language. The set of rules for using the mnemoniCs and for
specification of complete instructions and programs is called the syntax of the
language. Programs written in an assembly language can be automatically
 translated into a seque
assembler.

3ft:mptlh: lolowin
Write in brief abouGtorelnsiffin
The five-step sequence used for the Load and Add
instructions is also suitable
for store instructions, except that the final step of loading
the result into a
destination register is not required. The hardware stage
rlsponsibre for this
step takes no action. For example, the instruction
Store R6, X(R8)
stores the contents of register R6 into memory location 1 +
1Rgl. lt can be
implemented as follows:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read registers R6 and Rg.
3. Compute the effective address X +
[RS].
4' store the contents of register R6 into memory rocation x +
[Rg].
5. No action.
Explain 5 stage organisatlon of Datapath.

Explain hardwired control approach of generating control signal.

The processor generates the control signals that cause actions to take place in the
correct sequence and at the right time. There are two basic approaches: hardwired
 control and microprogrammed control. Hardwired control is discussed in this section.
An instruction is executed in a sequence of steps, where each step requires one clock
cycle. Hence, a step counter may be used to keep track of the progress of execution.
Several actions are performed in each step, depending on the instruction being
executed. In some cases, such as for branch instructions, the actions taken depend on
tests applied to the result of a computation or a comparison operation. External
signals, such as interrupt requests, may also influence the actions to be performed.
Thus, the setting ofthe control signals depends on:
. Contents ofthe step counter
. Contents ofthe instruction register
o The result of a computation or a comparison operation
. External input signals, such as interrupt requests
The instruction decoder interprets the OP-code and addressing mode information
in the lR and sets to 1 the corresponding lNSi output. During each clock cycle, one of
the outputs T1 to T5 of the step counter is set to 1 to indicate which of the five steps
involvedin fetching and executing instructions is being carried out. Since all
instructions are completed in five steps, a modulo-S counter may be used. The control
signal generator is a combinational circuit that produces the necessary control signals
based on all its inputs.
The required settings of the control signals can be determined from the action
sequences that implement each of the instructions represented by the signals lNSl to
lNSm.
(d) What is the concept of interrupts?
There are many situations where other tasks can be performed while waiting for an
l/O device to become ready. To allow this to happen, we can arrange for the l/O
device to alert the processor when it becomes ready. lt can do so by sending a
hardware signal called an interrupt request to the processor. Since the processor is no
longer required to continuously poll the status of l/O devices, it can use the waiting
period to perform other usefultasks. Indeed, by using interrupts, such waiting periods
can ideally be eliminated.
Consider a task that requires continuous extensive computations to be performed and
the results to be displayed on a display device' The displayed results must be updated
every ten seconds. The ten-second intervals can be determined by a simple timer
circuit, which generates an appropriate signal. The processor treats the timer circuit
as an input device that produces a signal that can be interrogated. lf this is done by
means of polling, the processor will waste considerable time checking the state of the
signal. A better solution is to have the timer circuit raise an interrupt request once
every ten seconds. In response, the processor displays the latest results.

(e) State & explain sequence of actions during branch instruction.

given
The sequence of steps for implementing an unconditional branch instruction is
as follows
The instruction is fetched and the PC is incremented as usual in step 1. After
the instruction has been decoded in step 2, multiplexer MuxlNC selects the branch
offset in
Step Action
1 Memory address [PC], Read memory, lR Memory data, PC [PC] + 4
2 Decode instruction
 3 PC [PC] + Branch offset
4 No action
5 No action
This is Sequence of actions needed to fetch and execute an unconditional branch
instruction.
the lR to be added to the PC in step 3. This is the address that will be used to fetch the
next
instruction. Execution of a Branch instruction is completed in step 3. No action is
taken in
steps 4 and 5.
This sequence can be readily modified to implement conditional branch instructions.
In processors that do not use condition-code flags, the branch instruction specifies a
compare-and-test operation that determines the branch condition. For example, the
instruction Branch-if-[R5]=[R6] LOOP
results in a branch if the contents of registers R5 and R5 are identical. When this
instruction is executed, the register contents are compared, and if they are equal, a
branch is made to location LOOP.
Step Action
1 Memory address [PC], Read memory, lR Memory data, PC [PC] + 4
2 Decode instruction, RA [R5], RB [R5]
3 Compare [RA] to [RB], lf [RA] = [RB], then PC [PC] + Branch offset
4 No action
5 No action
Sequence of actions needed to fetch and execute the instruction:
Branch if IR5l=[RGl LOOP.
(0 Explain program controlled l/O.
The two essential l/O devices for human-computer interaction-keyboard and display'
Consider a task that reads characters typed on a keyboard, stores these data in the
memory, and displays the same characters on a display screen. A simple way of
implementing this task is to write a program that performs all functions needed to
realize the desired action. This method is known as program-controlled l/O.
In addition to transferring each character from the keyboard into the memory, and
then to the display, it is necessary to ensure that this happens at the right time. An
input character must be read in response to a key being pressed. For output, a
character must be sent to the display only when the display device is able to accept it.
The rate of data transfer from the keyboard to a computer is limited by the typing
speed of the user, which is unlikely to exceed a few characters per second' The rate of
output transfers from the computer to the display is much higher. lt is determined by
the rate at which characters can be transmitted to and displayed on the display
device, typically several thousand characters per second.
However, this is still much slower than the speed of a processor that can execute
billions of instructions per second. The difference in speed between the processor and
l/O devices creates the need for mechanisms to synchronize the transfer of data
between them.
Example:
READWAIT Read the KIN flag
Branch to READWAIT if KIN = 0
Transfer data from KBD DATA to R5
 which reads the character into processor register R5.
WRITEWAIT Read the DOUT flag
Branch to WRITEWAIT if DOUT = 0
Transfer data from R5 to DISP_DATA
, data can be transferred between these registers and the processor
using instructions such as Load, Store, and Move. For example, the contents of the
keyboard
character buffer KBD DATA can be transferred to register R5 in the processor by the
instruction
LoadByte R5, KBD_DATA
Similarly, the contents of register R5 can be transferred to DISP-DATA by the
instruction
storeByte R5, DISP_DATA
The LoadByte and StoreByte operation codes signify that the operand size is a b$e, to
distinguish them from the Load and Store operation codes that we have used for word
operands.

Q.5 Attempt the following (Any THREE) (Each of SMarks) (15)

(a) Write note on full adder.

(b) With example explain indexed addressing.

See Q.3 c

(c) What are the components of processor?

(d) Convert decimal number 356 to binary & octalform.

(e)
 Discuss addressing modes supported by NIOS ll processor.

**** NOTE: