PowerManagement Part3

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S A M D AV I S
POWER
SUPPLIES
SYSTEMS
APPLICATIONS
COMPONENTS
SEMICONDUCTORS
Copyright 2016 by Penton Media,Inc. All rights reserved.

POWER ELECTRONICS LIBRARY
TABLE OF CONTENTS
ID
VGS
VD
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
MANAGEMENT
0V
-1V
-1.5V
-2V
-2.5V
-3.3V
BY SAM DAVIS
VDD BP6 BP3 BOOT
VIN 100.0
Linear VGS
Regulators HSFET 80.0
Driver 5V
Control 60.0 4V
Anti-Cross- SW 3V
BP6
20.0
Conduction
RT 2V
Oscillator Pre-Bias LSFET 40.0 1V
SYNC/RESET_B ID 00.0 0V
Ramp
PWM
S Q GND
OC Event -20.0
RESET_VOUT + Current
R Q Average IOUT Sense, -40.0
COMP
OC
Error Amplifier Detection CLK -60.0
FB Fault
+ VREF for -80.0
Soft-Start and OC Threshold DATA
Reference VOUT_COMMAND -100.0
DAC -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0
SMBALERT
PMBus Engine VD
VSET Courtesy of Efficient Power Conversion
ADC, PMBus Commands, CNTL
VOUT Sense
IC Interface, EEPROM
OV/UV Detection
ADDR0
INTRODUCTION........................................................ 2 PART 4: POWER APPLICATIONS

ADDR1
DIFFO
Temperature 750 k
Sensing PGOOD
AGND PART 1: THE POWER SUPPLY CHAPTER 12: WIRELESS POWER TRANSFER................ 98
PGND
CHAPTER 1: POWER SUPPLY FUNDAMENTALS............ 3 CHAPTER 13: ENERGY HARVESTING........................ 104

VOUTS+ VOUTS TSNS/SS
CHAPTER 2: POWER SUPPLY CHARACTERISTICS.......... 6 CHAPTER 14: CIRCUIT PROTECTION DEVICES........... 108
CHAPTER 3: POWER SUPPLIES MAKE OR BUY?....... 14 CHAPTER 15: PHOTOVOLTAIC SYSTEMS................... 115
CHAPTER 4: POWER SUPPLY PACKAGES................... 17 CHAPTER 16: WIND POWER SYSTEMS..................... 124
CHAPTER 5:
POWER MANAGEMENT CHAPTER 17: ENERGY STORAGE............................. 129
REGULATORY STANDARDS.................... 24 CHAPTER 18: ELECTRONIC LIGHTING SYSTEMS........ 134
CHAPTER 6: POWER SUPPLY SYSTEM CHAPTER 19: MOTION SYSTEM POWER
CONSIDERATIONS............................... 27 MANAGEMENT................................. 141
CHAPTER 20: COMPONENTS AND METHODS
PART 2: SEMICONDUCTORS FOR CURRENT MEASUREMENT........... 146
CHAPTER 7: VOLTAGE REGULATOR ICS.................... 31 CHAPTER 21: THERMOELECTRIC GENERATORS......... 151
CHAPTER 8: POWER MANAGEMENT ICS................. 51 CHAPTER 22: FUEL CELLS......................................... 156
CHAPTER 9: BATTERY POWER MANAGEMENT ICS.... 68 CHAPTER 23:
POWER MANAGEMENT OF
TRANSPORTATION SYSTEMS............... 162
CHAPTER 24: POWER MANAGEMENT TEST
PART 3: SEMICONDUCTOR SWITCHES
AND MEASUREMENT......................... 172
SILICON POWER MANAGEMENT
CHAPTER 10:
CHAPTER 25: DATACENTER POWER......................... 184
POWER SEMICONDUCTORS................. 77
CHAPTER 11: WIDE BANDGAP SEMICONDUCTORS... 91
LEARN MORE @ electronicdesign.com/powermanagement | 1

PART 3. SEMICONDUCTOR SWITCHES
CHAPTER 10:
SILICON POWER-MANAGEMENT
POWER
SEMICONDUCTORS
S
ilicon power semiconductors +v 10-1. Power management power
are employed in power man- semiconductors duplicate the action of
agement systems. They are a mechanical switch in which a control
found in two different forms: Load operation turns the power semiconductor
Discrete Power Semi- switch on and off to control power applied
conductors (single type to a load.
housed in a package.)
Integrated Power Semiconductors Control Power turned off so zero current flows to the load.
MOSFETs and BJTs (bipolar junction Signal Switch It should also have zero impedance when
transistors) can be integrated with other turned on so that the on-state voltage drop is
circuits in a single package. In addition, zero. Another idealistic characteristic would
various types of power semiconductors be that the switch input consumes zero pow-
may housed in a hybrid (multi-chip mod- er when the control signal is applied. Howev-
ule, or MCM) package, that is, interconnected with other er, these idealistic characteristics are unachievable with
monolithic discrete devices in the same package. the present state of the art.
Power switches are actually the electronic equivalent In the real world, actual power semiconductor switch-
of a mechanical switch, except for much faster switching es do not meet the ideal switching characteristics. For
speed. Fig. 10-1 is the representation of a mechanical
switch. The individual power semiconductor switch
applies power to a load when a control signal tells it to
do so. The control signal also tells it to turn off. Ideally, (a) Control Signal
the power semiconductor switch should turn on and off
+V
in zero time. It should have an infinite impedance when
10-2. Actual power semiconductors do not meet the ideal

switching characteristics. 0V
(b) Ideal Output
(a) Control signal applied to an ideal power semiconductor
switch whose +V
(b) Ideal output exhibits zero transition time when turning on
and off.
(c) Actual power switch exhibits some delay when turning on 0V
and off. (c) Actual Output

POWER ELECTRONICS LIBRARY CHAPTER 10: SILICON POWER-MANAGEMENT POWER SEMICONDUCTORS
Drain voltage and also p-channel devices

+V Source
that require a negative gate voltage
+V
to turn on. Their current conduction
capabilities are up to several tens of
amperes, with breakdown voltage
Gate ratings (BVDSS) of 10V to 1000V.
Body MOSFETs used in integrated
Body
Diode circuits are lateral devices with gate,
Diode
Gate source and drain all on the top of the
device, with current flow taking place
in a path parallel to the surface. The
Vertical Double diffused MOSFET
-V -V (VDMOS) uses the device substrate
Source Drain as the drain terminal. MOSFETs used
N-Channel P-Channel
in integrated circuits exhibit a higher
10-3. N-Channel and P-Channel Power MOSFETs showing the voltage on-resistance than those of discrete
polarity of the Drain and the gate pulse polarity to turn the device on. MOSFETs.
The fabrication processes used to
example, Fig. 10-2(a) shows a control signal applied manufacture power MOSFETs are the
to an ideal power semiconductor switch whose output same as those used in todays VLSI circuits, although the
exhibits zero transition time when turning on and off device geometry, voltage and current levels are signifi-
(Fig. 10-2(b)). When the transistor is off (not conducting cantly different. Discrete monolithic MOSFETs have tens
current) power dissipation is very low because current is or hundreds of thousands of individual cells paralleled
very low. When the transistor is on (conducting maximum together in order to reduce their on-resistance.
current) power dissipation is low because the conduct- The gate turns the MOSFET on when its gate-to-
ing resistance is low. In contrast, an actual power switch source voltage is above a specific threshold. Typical gate
exhibits some delay when turning on and off, as shown thresholds range from 1 to 4 V. For an n-channel MOSFET
in Fig. 10-2(c). Therefore, some power dissipation occurs a positive bias greater than the gate-to-source threshold
when the switch goes through the linear region between voltage (VGS(th) ) is applied to the gate, a current flows
on and off. This means that the most power dissipa- between source and drain. For gate voltages less than
tion depends on the time spent going from the off to on VGS(th) the device remains in the off-state. P-channel
and vice versa, that is, going MOSFETs use a negative
through the linear region. Thus, gate drive signal to turn on.
500
the faster the device goes When power semicon-
through the linear region, the ID ductor switches first found
TOP 3.9A
EAS, Single Pulse Avalanche Energy (mJ)
lower the power dissipation 400 7.0A

wide use, discrete transistors,
and losses. BOTTOM 8.8A pulse transformers, opto-cou-
plers, among other compo-
Power MOSFETs 300 nents were used to drive the
Power MOSFETS (Met- power MOSFET on and off.
al-Oxide Semiconductor Field Now, specially designed gate
Effect Transistors) are among 200 driver ICs are used in many
the most widely used power applications. This minimizes
switch semiconductors. Power the drive requirements from
100
MOSFETs are three-terminal a low power circuit, such as
silicon devices that function by a microprocessor, and also
applying a signal to the gate 0
acts as a buffer between the
that controls current conduc- 25 50 75 100 125 150 controlling signal and the
tion between source and drain Start TJ, Junction Temperature (C) power semiconductor switch.
(Fig. 10-3). They are available 10-4. Avalanche occurs if the maximum drain-to- The gate driver supplies
in n-channel versions that source voltage is exceeded and current rushes enough drive to ensure that
require a positive gate turn-on through the device. the power switch turns on

2.0 12
RDS(ON), Drain-to-Source On Resistance (Normalized)
ID = 11A
VGS = 4.5V
1.5 9
ID, Drain Current (A)

1.0 6
0.5 3
0.0 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 25 50 75 100 125 150
TJ, Junction Temperature (C) TC, Case Temperature (C)
10-5. Normalized Variation of on-resistance vs. junction 10-6. Maximum Drain Current for a typical N-Channel
temperature for an N-Channel MOSFET. Power MOSFET.
properly. Some gate drivers also have protection circuits vices are rated in terms of EAR, the repetitive avalanche
to prevent failure of the power semiconductor switch and energy.
also its load. Trench technology provides the desirable charac-
MOSFET characteristics include several parameters teristics of low on-resistance sometimes at the expense
critical to their performance: of high avalanche energy. Trench power MOSFET tech-
Blocking voltage (BVDSS) is the maximum voltage nology provides 15% lower device on-resistance per
that can be applied to the MOSFET. When driving an unit area than existing benchmark planar technologies
inductive load, this includes the applied voltage plus any but usually at the cost of higher charge. And, the trench
inductively induced voltage. With inductive loads, the technology allows 10% lower on-resistance temperature
voltage across the MOSFET can actually be twice the coefficient. Fig. 10-4 is plot of single pulse avalanche
applied voltage. energy for a MOSFET.
Maximum single pulse avalanche energy (EAS) deter- On-resistance (RDS(ON)) for both planar and Trench
mines how much energy the MOSFET can withstand un- MOSFETs is important because it determines the power
der avalanche conditions. Avalanche occurs if the max- loss and heating of the power semiconductor. The lower
imum drain-to-source voltage is exceeded and current the on-resistance the lower the device power loss and
rushes through the device. The higher the avalanche val- the cooler it will operate. Low on-resistance drastically
ue the more rugged the device. The avalanche condition reduces heat-sinking requirements in many applications,
can cause two possible failure modes that can destroy which lowers parts count and assembly costs. In many
a MOSFET. The most destructive is bipolar latching applications, the low on-resistance also eliminates the
that occurs if the device current causes a voltage drop need to parallel MOSFETs for low on-resistance, which
across its internal device resistance, resulting in transis- leads to improved reliability and lower overall system
tor action and latching of the parasitic bipolar structure cost than previous MOSFET generations. In virtually all
of the MOSFET. A second failure mode is thermal, which MOSFETS, the n-channel versions have lower on-resis-
occurs if the avalanche condition raises the device tem- tance than p-channel devices with the same operating
perature above its maximum junction temperature. voltages.
Trench technology offers an avalanche capability ap- RDS(ON) decreases with increasing cell density. The
proaching industry-leading planar technology. To ensure cell density has increased over the years from around
satisfactory performance, devices in this technology can half a million per square inch in 1980 to around eight
be fully characterized for single pulse avalanche ener- million for planar MOSFETs and around 12 million and
gy (EAS) up to their maximum junction temperature. The higher for trench technology.
higher the EAS, the more rugged the device. Some de- Maximum junction temperature, TJ(max), is a function of

1000 6
ID = 7.0A
Operation in This Area Limited
by Rds(On)
5
VDS = 6.0V
100
VGS, Gate-to-Source Voltage (V)

ID, Drain-to-Source Current (A)
4
10sec VDS = 12V
10 1 msec 3
10 msec
2
1
TC = 25C 1
TJ = 150C
Single Pulse
0.1 0
0.1 1 10 100 0 5 10 15 20
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)
10-7. Typical Maximum Safe Operating for an N-Channel 10-8. Total Gate Charge (Qg) of an N-Channel Power
Power MOSFET MOSFET Varies With the Drain-Source Voltage
the electrical characteristics of the device itself, as well mechanism called secondary breakdown that significant-
as the package employed. Package thermal properties ly reduces the SOA.
determine its ability to extract heat from the die. The junc- Total Gate charge (QG) The charge on the gate termi-
tion-to-ambient and junction-to-case thermal resistance nal of the MOSFET as determined by its gate-to-source
is a measure of the MOSFETs ability to extract heat. Data capacitance. The lower the gate charge, the easier it is
sheets rate thermal resistance in terms of either C/W or to drive the MOSFET. Total gate charge, QG, affects the
K/W. The lower the thermal resistance, the more efficient highest reliable switching frequency of the MOSFET. The
the package is in eliminating heat. In some cases, a heat lower the gate charge, the higher the frequency. Oper-
sink may be required to maintain the device junction ation at higher frequencies allows use of lower value,
temperature below its maximum rating. Fig. 10-5 shows smaller size capacitors and inductors, which can be
the variation of RDS(ON) with junction temperature for VGS = significant factors in system cost. A low gate charge also
4.5 V and 10 V. VGS is gate-to-source voltage. makes it easier to drive the MOSFET, however, designers
Drain current (ID) establishes the ability of the MOS- sometimes need to trade-off switching frequency with
FET to drive a specific load. This value can be limited by EMI considerations. Some New trench devices exhibit
the MOSFETs package. When operated in the pulsed lower gate charge than some existing planar technolo-
mode, the MOSFETs drain current can be several times gies by replacing larger die with new smaller die devices
its continuous rating. In the pulsed mode the pulse width that have been optimized to offer a lower charge version
and duty cycle determine safe drain current and device of the trench devices. Fig. 10-8 shows the gate charge
power dissipation. Fig. 10-6 shows the maximum drain for a typical power MOSFET, which is specified in nC,
current vs. case temperature. nano-coulombs.
Safe operating area (SOA) for a MOSFET is a function Although input capacitance values are useful, they
of the voltage and current applied to the device. Power do not lend themselves to calculation of the gate current
semiconductor manufacturers include a curve in their required to switch the device in a given time and they do
power transistor data sheets (Fig. 10-7) that defines the not provide accurate results when comparing the switch-
allowable combination of voltage and current, which ing performance of two devices. A more useful parame-
is called the devices safe operating area (SOA). The ter from the circuit design point of view is the total gate
product of the voltage and current represents the watts charge. Most manufacturers include both parameters on
dissipated in the chip. If you exceed the SOA, the chip their data sheets. Using gate charge, QG, the designer
will get too hot and fail. MOSFET devices are limited can calculate the amount of current required from the
by the SOA; bipolar devices have an additional failure drive circuit to switch the device on in a desired length of

1.6 100
1.4
VGS(th), Gate Threshold Voltage (V)
TJ = 150C
ISD, Reverse Drain Current (A)

10
ID = 250A
1.2
TJ = 25C
1
1.0
VGS = 0V
0.8 0.1
-75 -50 -25 0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0
TJ, Temperature (C) VSD, Source-to-Drain Voltage (V)
10-9. The Gate Threshold Voltage of this N-Channel 10-10. Body-Diode Forward Voltage for an N-Channel
Power MOSFET Is About 1.28 V for ID = 250A at 25C. Power MOSFET.
time because QG = current time. For example, a device MOSFETs have typical values of about 2V to 3V, whereas
with a gate charge of 20nC can be turned on in 20msec other devices can have higher values. In Fig. 10-9 is the
if a current of 1mA is supplied to the gate, or it can turn threshold voltage plotted against junction temperature.
on in 20nsec if the gate current is increased to 1A. These Power Loss MOSFETs are expected to have low
simple calculations would not have been possible with conduction and switching losses. For power manage-
input capacitance values. ment applications, conduction losses, ruggedness and
Gate charge and on-resistance are inter-related. That avalanche capability are important features. Conduction
is, the lower the gate charge, the higher the on-resis- losses are determined by the product of operating cur-
tance and vice versa. Historically, MOSFET manufac- rent and on-resistance (I2R) of the power MOSFET.
turers have focused on reducing RDS(on) without paying Maximum Allowable Power Dissipation (PD) is the max-
much attention to gate charge. This has changed in the imum allowable power dissipation that raises the MOS-
last several years, with new designs and processes be- FETs die temperature to the maximum allowable junction
coming available that offer reduced gate charge devices. temperature, Tjmax, when the case temperature is held
Figure of Merit (FOM) relates to the tradeoff between at 25C. Tj max is normally 150C or 175C.
RDS(ON) and gate charge. The product of RDS(ON) QG Body-Diode Forward Voltage (VSD) is the guaran-
is a figure of merit (FOM) that compares different power teed maximum forward drop of the body-drain diode at
MOSFETs for use in high frequency applications. a specified value of source current. The value of VSD
Threshold Voltage (VGS(TH)) is the minimum gate- is significant and must be low in applications where
source electrode bias required to form a conducting the source-drain voltage may extend into the negative
channel between the source and the drain regions. It is range, causing forward biasing the body-drain diode. If
usually measured at a drain-source current of 250A. A this happens, the source-drain current flows from drain
value of 2-4V for high voltage devices with thicker gate straight to the source contacts, across the forward bi-
oxides, and logic-compatible values of 1-2V for lower ased body-diode p-n junction.
voltage devices with thinner gate oxides are common. In A second and more dominant current conduction path
battery-based applications where power is a premium, will exist through the channel if the gate-source voltage,
the trend is towards lower values of RDS(on) and Vgsth. VGS >Vgsth. Low voltage and low RDS(on) power MOSFETs
Gate oxide quality and integrity become major issues as are used in such synchronous rectifier modes since their
gate oxide thickness is reduced to achieve lower Vgsth, forward voltage drop can be as low as 0.1V versus the
the minimum voltage is required between the gate and typical Schottky diode forward voltage drops of 0.4-
source that enables the MOSFET to turn on. Logic level 0.5V. Maximum values of 1.6V for high voltage devices

(>100V) and values of 1.2V for 10-11. Typical N-Channel

low voltage devices (<100V) Drain MOSFETs Parasitic
are common for VSD. A typical Capacitances Includes CGD
source-drain diode forward volt- Power MOSFET (Gate-to-Drain), CDS (Drain-
LD
age is shown in Fig. 10-10. to-Source), and CGS (Gate-to-
Thermal Resistance, Junc- CGD Source)
tion-to-Case (RJC) is the junc- CDS
tion-to-case thermal imped- Controller Gate RG surfaces to prevent static
ance of the MOSFET, a typical Input charge problems.
surface mount package can CGS Switching and Transient
Gate Driver
have a thermal resistance of Response is determined by
30-50 C/W, whereas a typical LS the time required to estab-
TO-220 device can be 2C/W lish voltage changes across
or less. Data sheets may also capacitances and current
Source
provide a value for RJA for the changes in inductances. RG
junction-to-ambient thermal re- is the distributed resistance of
sistance of the power MOSFET the gate and is approximately
Maximum dV/dt is the maximum rate of rise of source- inversely proportional to active area. Values of around
drain voltage allowed if the MOSFETs dV/dt. If this rate is 20 -mm2 are common for the product of RG and active
exceeded, the voltage across the gate-source terminals area for polysilicon gates. Fig. 10-11 shows the parasit-
may become higher than the threshold voltage of the ics in the MOSFET input. Ls and LD are source and drain
device, forcing the device into current conducting mode lead inductances and are around a few tens of nH. There
and under certain conditions a catastrophic failure may are also several parasitic capacitances associated with
occur. the power MOSFET. Gate-source capacitance, CGS, is
There are two possible mechanisms by which a dV/ the capacitance due to the overlap of polysilicon gate
dt induced turn-on may take place. One becomes active with the source and the channel regions and is not a
through the feedback action of the gate-drain capaci- strong function of applied voltage. Fig. 10-12 illustrates
tance CGD together with CGS forming a capacitive divid- the variation of the parasitic capacitances vs. the drain-
er that can generate a pulse sufficient to exceed the Vth source voltage.
and turn the device on during fast voltage transitions on CRSS is the reverse transfer capacitance, which is the
the drain. When a voltage ramp appears across the drain capacitance between the drain and gate with the source
and source terminals of the device. Usually the driver will connected to ground. This capacitance is equal to the
sink a current flowing through the gate resistance, RG, to
10000
clamp the gate low during the off state, if Rg is too large, VGS = 0V
it is sometimes possible that the driver is isolated from CISS =CGS+CGD CDS Shorted
the gate allowing the device to turn on. RG is the total CRSS=CGDS
COSS=CDS+CGD
gate resistance in the circuit.
The second mechanism for the dV/dt turn-on in
MOSFETs is through the parasitic BJT. The capacitance
C, Capacitance (pF)
CISS
associated with the depletion region of the body diode,
extending into the drift region is denoted as CDB and 1000 COSS
appears between the base of the BJT and the drain of
the MOSFET. This capacitance gives rise to a current that
flows through the base resistance, RB, when a voltage
ramp appears across the drain-source terminals.
Static Electricity (ESD) Effects is another way to kill
CRSS
semiconductors. The static charge accumulated by a
person handling an MOSFET semiconductor is often 100
enough to destroy the part. Therefore, manufacturers of 1 10 100
semiconductors have instituted static discharge ratings VDS, Drain-to-Source Voltage (V)
that range from 3000V to 5000V. Handlers of MOSFET 10-12. Typical Plot of N-Channel MOSFETs Parasitic
semiconductors use grounding straps and conductive Capacitances vs. Drain-to-Source Voltage.

gate-to-drain capacitance. CRSS, often referred to as uration of the older planar MOSFETs. And, new Trench
the Miller capacitance, is one of the major parameters MOSFETs offer significant advantages over the older
affecting rise and fall times of the output voltage during generation Trench MOSFETs and also some improve-
switching. Plus, it also affects turn-off delay time. The ments over the older planar MOSFET technology.
capacitances decrease over a range of increasing drain- Among the other technologies are MDMesh . ST-
source voltage, especially the output and reverse trans- Microelectronics says that the improvement in RDS(ON)
fer capacitances. achieved with MDmesh V will significantly reduce losses
Important parameters for MOSFETs are listed in Table in line-voltage PFC circuits and power supplies, which
10-1. will in turn enable new generations of electronic products
offering better energy ratings and smaller dimensions.
Power MOSFET Fabrication Technologies This new technology should help designers with high
The trench MOSFET has replaced the planar device efficiency targets and also save power.
in many applications because it extends the cell density MDmesh V achieves its RDS(ON) per area performance
limit. Trench technology allows a higher cell density but by improving the transistor drain structure to lower the
is more difficult to manufacture than the planar device. drain-source voltage drop. This reduces the devices on-
Process refinements have yielded devices with steadily state losses while also maintaining low gate charge (Qg),
increasing density and lower on-resistance. TrenchFET enabling energy-efficient switching at high speeds and
devices have achieved on-resistance less than 1mW for delivering a low RDS(ON) x Qg Figure of Merit (FOM). ST
a 25mm2 silicon die, exclusive of lead resistance. claims that the breakdown voltage of 650V is also high-
Trench MOSFETs employ the same schematic config- er than competing 600V devices, delivering a valuable
safety margin for designers. A
TABLE 10-1. MOSFET PARAMETERS further advantage of STs MD-
Symbol Parameter Description mesh V MOSFETs is a cleaner
V(BR)DSS Breakdown voltage The MOSFETs maximum operating voltage, where the turn-off waveform, enabling
reverse-biased body-drift diode breaks down and current easier gate control and simpler
flows between the source and drain. filtering due to reduced EMI.
VGS(TH) Threshold voltage Minimum gate electrode voltage required to cause the STMicroelectronics STrip-
MOSFET to conduct. FET technology uses an
RDS(ON) On-resistance RDS(ON) = RSOURCE +RCH+RA+RJ+RD+RSUB+RWCML optimized layout and updat-
RSOURCE = Source diffusion resistance ed manufacturing process to
RCH = Channel resistance
improve the gate charge, gate
RA = Accumulation resistance
RJ = JFET component-resistance of the region between resistance and input capaci-
the two body regions tance characteristics. The low
RD = Drift region resistance gate charge enables excellent
RSUB = Substrate resistance switching behavior and the
RWCML= Sum of Bond Wire resistance, contact resistance
low gate resistance means fast
between the source and drain metallization and silicon,
metallization and leadframe transient response. The tech-
contributions. nology also offers an extremely
IDS(MAX) Maximum drain Maximum drain-to-source output current. low figure-of-merit, meaning re-
current duced conduction and switch-
QG Total gate charge Gate charge allows calculation of the amount of current ing losses.
required from the drive circuit to switch the device on in a Among STMicroelectron-
desired length of time. ics introductions is a series
PD The maximum Maximum allowable power dissipation that raises the die of 30V surface-mount power
allowable power temperature to the maximum allowable when the case transistors, achieving on-resis-
dissipation temperature is held at 25oC. tance as low as 2 m (max) to
TJ ( MAX) 25 increase the energy efficiency
PD = of products such as comput-
R JC
where: ers, telecom and networking
TJ(MAX) = Maximum allowable temperature of the p-n junc- equipment. The latest-gener-
tion (normally 150oC or 175oC) ation STripFET VI DeepGATE
RJC = Junction-to-case thermal impedance of the MOSFET. family process has high equiv-

alent cell density and said 10-13. DirectFET is a surface mount

Die Can
to be best RDS(ON) in relation semiconductor for board-mounted power
to active chip size. This is applications. It eliminates unnecessary elements
around 20 per cent better of packaging that contribute to higher inductance
than the previous genera- and resistance, both thermal and electrical,
tion and allows the use of so that its power capabilities exceed those of
Drain Gate Source Substrate
small surface-mount power comparably sized packages.
packages in switching reg-
ulators and DC-to-DC converters, the Top View
company said. Encapsulation Exposed Lead Frame 10-14. The PolarPAK package
Infineon has developed CoolMOS increases the power handling capability
technology for high voltage Power of power MOSFETs while keeping a PCB
MOSFETs that reduces the RDS(ON) area landing pattern no bigger in area than
product by a factor of five for 600V tran- that of a standard SO-8 orPowerPAK
sistors. It has redefined the dependence SO-8.
of RDS(ON) on the breakdown voltage.
The more than square-law dependence chip scale and ball grid array packages
in the case of a standard MOSFET has Side View for low voltage power MOSFETs.
Lead Frame Silicon
been broken and a linear voltage de- The International Rectifier DirectFET
pendence achieved. It is said that this power package is surface-mount power
opens the way to new fields of applica- MOSFET packaging technology de-
tion even without avalanche operation. signed for efficient topside cooling in a
Lead Frame
System miniaturization, higher switching SO-8 footprint (Fig. 10-13). In combina-
frequencies, lower circuit parasitics, tion with improved bottom-side cooling,
higher efficiency, reduced system costs are pointing the the new package can be cooled on both sides to cut part
way towards future developments. It has also set new count by up to 60%, and board space by as much as
benchmarks for device capacitances. Due to chip shrink 50% compared to devices in standard or enhanced SO-8
and novel internal structure, the technology shows a very packages. This effectively doubles current density (A/
small input capacitance as well as a strongly nonlinear in2) at a lower total system cost. The DirectFET MOSFET
output capacitance. The drastically lower gate charge family offerings match 20V and 30V synchronous buck
facilitates and reduces the cost of controllability, and the converter MOSFET chipsets, followed by the addition at
smaller feedback capacitance reduces dynamic losses. 30V targeted for high frequency operation. The DirectFET
This technology, improves the minimum RDS(ON) values in MOSFET family is also available in three different can
the 600 to 1000 V operating range.
12V VCC
MOSFET Packages
MOSFETs are available in Small Outline IC (SOIC)
packages for applications where space is at a premium.
Larger through-hole TO-220, TO-247 and the surface
mountable D2PAK or SMD-220 are also available. Newer
High-Side
package styles include chip scale devices and also the Driver
DirectFET and PolarPak packages.
Devices with breakdown voltage ratings of 55V-60V VOUT
PWM VCC
and gate-threshold voltages of 2 to 3V are used mainly in Low-Side
through-hole packages such as TO-220, TO-247 or the Driver
surface mounted D2PAK (SMD220). These through-hole
packages have very low thermal resistance. Despite their
higher thermal resistances, more surface-mount SOIC
packages are finding their way into applications due to
the continuous reduction in on-resistance of power MOS-
FETs. SOIC packages save space and simplify system 10-15. DrMOS Is a Multi-Chip Module That Contains Two
assembly. The newest generation of power MOSFETs use MOSFETs and the Associated Drive Circuits.

THWn BOOT V IN 10-16. Vishay

Intertechnologys SiC632CD
V DRV
Thermal monitor integrated DrMOS power
& warning stage for multiphase POL
regulator applications
V CIN UVLO combines power MOSFETs,
advanced MOSFET gate
DISB# driver IC, and a bootstrap
V CIN
- 20K Schottky diode.
+ PHASE
PWM logic Anti-cross Vref = 1 V
control & conduction GL
PWM state control VSWH
- is that the individual MOS-
machine logic +
Vref = 1 V FETs performance charac-
V DRV teristics can be optimized,
C GND whereas monolithic MOSFETs
produce higher on-resis-
tance. Although the com-
VSWH
P GND
ponent cost of a multi-chip
module may be higher than a
monolithic part. The designer
ZCD_EN# GL P GND must view the cost from a
system viewpoint.
sizes. That is, space is saved,
Vishays PolarPAK (Fig. 10-14) is a thermally en- potential noise problems are minimized, and fewer
hanced package that facilitates MOSFET heat removal components reduce production time and cost. Here, the
from an exposed top metal lead-frame connected to a multi-chip approach is superior to use of a monolithic
drain surface in addition to a source lead-frame con- part.
nected to a PCB. PolarPAK was specifically designed for Unlike discrete solutions whose parasitic elements
easy handling and mounting onto the PCB with high- combined with board layout significantly reduce sys-
speed assembly equipment and thus to enable high tem efficiency, the DrMOS module is designed to both
assembly yields in mass-volume production. PolarPAK thermally and electrically minimize parasitic effects
power MOSFETs have the same footprint dimensions and improve overall system efficiency. In operation, the
of the standard SO-8, dissipate 1 C/W from their top high-side MOSFET is optimized for fast switching while
surface and 1 C/W from their bottom surface. This pro- the low-side device is optimized for low RDS(ON). This
vides a dual heat dissipation path that gives the devices arrangement ideally accommodates the low-duty-cycle
twice the current density of the standard SO-8. With its switching requirements needed to convert the 12V bus to
improved junction-to-ambient thermal impedance, a Po- supply the processor core with 1.0V to 1.2V at up to 40A.
larPAK power MOSFET can either handle more power or
operate with a lower junction tempera- SiC632CD
ture. A lower junction temperature VCC Vishay Intertechnologys SiC-
means a lower RDS(ON), which in turn MOSFET 2 632CD integrated DrMOS power
means higher efficiency. A reduction stage for multiphase POL regulator
L VOUT
in junction temperature of just 20 C Gate applications combines power MOS-
can also result in a 2.5 times increase Drive FETs, advanced MOSFET gate driver
COUT
in lifetime reliability. IC, and a bootstrap Schottky diode
MOSFET 1 (Fig. 10-16). Housed in thermally
DrMOS enhanced 5 mm by 5 mm Power-
Intels November 2004 DrMOS 10-17. A Synchronous Rectifier PAK MLP55-31L package, it offers
specification identified a multi-chip Employs Two N-Channel MOSFETs, a 45 % smaller footprint compared
module consisting of a gate driver Which Provides More Efficient with discrete solutions. The devices
and power MOSFET. A major advan- Rectification than Conventional are suitable for industrial PC and
tage of using this module (Fig. 10-15) Diodes. high-current multiphase modules

used in networking and industrial applications. packaging and handling precautions for semiconductors
This integrated device offers continuous current up to and is an electronic standard for the time the device can
40 A in the 5 mm by 5 mm PowerPAK MLP55-31L pack- be exposed to ambient room conditions of approximately
age. Besides its high-current capabilities and footprint 30C/60%RH. The reason this is important is that thin
savings, the power stage also lowers package parasitics fine-pitch devices could be damaged during surface
to enable switching frequencies up to 2 MHz further mount technology (SMT) reflow when moisture trapped
shrinking the overall solution size and profile by reducing inside the component expands. Trapped moisture can
the size of the output filter. Its high- and low-side MOS- damage a semiconductor. In extreme cases, cracks will
FETs utilize Gen IV TrenchFET technology to reduce extend to the component surface.
switching and conduction losses. The integrated power According to IPC/JEDECs J-STD-20: Moisture/Reflow
driver IC is compatible with a wide range of PWM control- Sensitivity Classification for Plastic Integrated Circuit (IC)
lers and supports tri-state PWM logic of 5 V. SMTs, there are eight levels of moisture sensitivity. Orig-
The SiC632CD is optimized for synchronous buck inally MOSFETs was rated at MSL 3, which allowed 168
converters, DC/DC voltage regulation modules, and hours of moisture testing. MSL 1 allows an unlimited time
multiphase VRDs for CPUs, GPUs, and memory. To for the moisture test.
increase light-load efficiency in these applications, the Today, there are new applications and power MOS-
driver IC incorporates diode emulation mode circuitry FETs continue to grab them. . This includes Electric
and zero-current detect. An adaptive dead time control Power Steering (EPS) and Micro Hybrid Vehicles, and
helps to further improve efficiency at all load points. To chassis, drive train and power train systems. Besides
support PS4 mode light-load requirements for IMVP8, meeting the AEC Q101 standard, they must meet the
the power stages reduce current consumption to 5 A cost constraints imposed by automotive manufacturers.
when systems are operating in standby mode, and they For EPS, an electric motor driven by a power MOS-
can awake from this state within 5 s. Protection features FET provides steering assist to the driver of a vehicle. A
for the RoHS-compliant, halogen-free devices include typical system employs sensors detect the motion and
undervoltage lockout (UVLO). torque of the steering column, and a computer module
controls system performance. Software allows varying
Power MOSFETs for Synchronous Rectifiers amounts of assistance to be applied depending on driv-
Fig. 10-17 shows a simplified synchronous rectifier ing conditions.
circuit. Typical synchronous rectifiers consist of high-side Electric systems have a fuel efficiency advantage
and low-side MOSFETs, which require different charac- over conventional hydraulic power steering. The electri-
teristics for an optimum design. Generally, the best high cal approach eliminates the belt-driven hydraulic pump
side MOSFET is one with the lowest Qswitch RDS(ON) constantly running, whether assistance is required or not.
figure-of-merit. Qswitch is defined as the post gate thresh- Another major advantage is the elimination of a belt-driv-
old portion of the gate-to-source charge plus the gate-to- en engine accessory, and several high-pressure hydrau-
drain charge (Qgs2 + Qgd). In contrast, the best high side lic hoses between the hydraulic pump, mounted on the
MOSFET must exhibit very low RDS(ON) coupled with good engine, and the steering gear, mounted on the chassis.
Cdv/dt immunity. This simplifies manufacturing and maintenance.
A micro-hybrid system performs a stop-start function
Power MOSFETs for Automotive Applications completely transparent to the driver, during idling, like
Over the last two decades Power MOSFETs have waiting for a traffic light, a starter-alternator turns off the
evolved as a necessary power handling component is engine. Then, the engine restarts very quickly and silently
virtually all automobiles. To be eligible for use in automo- when the drive steps on the accelerator. This technique
tive electronic systems these power MOSFETs must meet cuts fuel consumption and gas emissions at standstill.
the AEC Q101 standard. Some new power MOSFETs are Tests have shown that this can cut fuel consumption
AEC Q101 qualified and will fit in the growing use of elec- about 6%.
tric motors, solenoids and fuel injectors. Power MOSFETs Power MOSFETs have played a major role make
have low on-resistance, 40 V and 100 V maximum oper- automotive systems more reliable. Among the traditional
ating voltage and the ability to tolerate the high-voltage mechanical components that have been eliminated are
transients such as load dump that can occur in automo- shafts, pumps, hoses, fluids, coolers, etc., which reduces
tive electrical systems. the weight of the vehicle and improves fuel efficiency.
An important feature of these new MOSFETs is their Safety improvement is another feature of electronic con-
Moisture Sensitivity Level, or MSL. This relates to the trols that provide more automated functions that cannot

be achieved by mechanical techniques. Compared with junction. Breakdown voltage is primarily determined by
mechanical systems, the electronics trend also allows the resistivity of the epitaxial layer.
easier modification or upgrade of automotive systems. All applications of power MOSFET switches require
MSL-1 preconditioning is required for surface mount some guardbanding when specifying BVDSS rating. It is
capable devices that are put on Temperature Cycling, important to remember that there is a price to be paid for
H3TRB, IOL, and Autoclave tests. If straight leaded this in the form of either higher RDS(on) or larger die. There
devices (such as I-PAK or TO-262) are used, then the de- may be applications where a reduction of conservative
vices are required to undergo the preconditioning with a guardbanding on BVDSS can be justified by an improved
third reflow exposure in lieu of the surface mounting step RDS(on) specification or lower cost without jeopardizing
performance or reliability.
MOSFETs and BJT Comparison Bipolar transistors have ratings for maximum current
Power MOSFETs are capable of operating at very high under continuous and pulsed conditions. Exceeding
frequencies compared with Bipolar Junction Transistors these ratings usually result in device failure. Current rat-
(BJTs) whose switching speed is much slower than for a ings on MOSFET transistors have a different meaning be-
power MOSFET of similar size and voltage rating. Typical cause they behave as a resistor when they turn on. This
rise and fall times of power MOSFETs are of the order of means that the maximum voltage drop or heat generated
several nanoseconds which is two orders of magnitude determines the maximum current. Turning the current on
faster than bipolar devices of similar voltage rating and and off at high speeds reduces the average power or
active area. BJTs are limited to frequencies of less than heat generated, thereby increasing the maximum allow-
100kHz whereas power MOSFETs can operate up to able current.
1MHz before switching losses become unacceptably
high. Recent advances in the design and processing of Power semiconductor Reliability
MOSFETs are pushing this frequency limit higher. Excessive operating voltage can cause power
Power MOSFETs are voltage controlled devices with semiconductor failures because the devices may have
simple drive circuitry requirements. Power BJTs on the small spacing between their internal elements. An even
other hand are current controlled devices requiring large worse condition for a power semiconductor is to have
base drive currents to keep the device in the ON state. high voltage and high current present simultaneously. A
Power MOSFETs have been replacing power BJTs in few nanoseconds at an excessive voltage or excessive
power application due to faster switching capability and current can cause a failure. Most power semiconductor
ease of drive, despite the very advanced state of manu- data sheets specify the maximum voltage that can be
facturability and lower costs of BJTs. applied under all conditions. The military has shown very
BJTs suffer from thermal runaway. The forward volt- clearly that operating semiconductors at 20% below their
age drop of a BJT decreases with increasing tempera- voltage rating provides a substantial improvement in their
ture potentially leading to destruction. This is of special reliability.
significance when several devices are paralleled in order Another common killer of power semiconductors is
to reduce forward voltage drop. Power MOSFETs can be heat. Not only does high temperature destroy devices,
paralleled easily because the forward voltage increases but even operation at elevated, non-destructive tempera-
with temperature, ensuring an even distribution of current tures can degrade useful life. Data sheets specify a max-
among all components. They can withstand simultane- imum junction temperature, which is typically between
ous application of high current and high voltage without 100C and 200oC for silicon. Most power transistors
undergoing destructive failure due to second breakdown. have a maximum junction rating of 125C to 150C, the
However, at high breakdown voltages (>~200V) the safe operating temperature is much lower.
on-state voltage drop of the power MOSFET becomes
higher than that of a similar size bipolar device with Transient Effects
similar voltage rating, making it more attractive to use the Power semiconductors can be destroyed by very
bipolar power transistor at the expense of worse high-fre- short pulses of energy. A major source of destructive
quency performance. transients is caused by turning on or off an inductive
Breakdown voltage (BVDSS) is the drain-to-source volt- load. Protection against these problems involves a care-
age at which a current of 250A starts to flow between ful combination of operating voltage and current margins
source and drain while the gate and the source are short- and protective devices.
ed together. With no bias on the gate, the drain voltage is
entirely supported by the reverse-biased body-drain p-n Power dv/dt and di/dt

The terms dv/dt and di/dt reflect a E silicon wafer, usually called yield. Not
time rate of change of voltage (dv/dt) only does a larger die size mean a
or current (di/dt) describe their reac- PNP disproportionately larger cost, but key
tion to turning on or off a reactive load. parameters may not be the same for
These problems can occur in power JFET all functions of each device on the die.
G
semiconductor switches because all
sections of the device do not behave MOSFET NPN
RB IGBT
in an identical manner when subjected An insulated-gate bipolar transistor
to very high rates of change. It is not C (IGBT) is a three-terminal power semi-
only important to look at the dv/dt and 10-18 Simplified IGBT equivalent conductor device primarily used as an
di/dt values generated within a circuit, circuit electronic switch that combines high
but also turn on and turn off times as C efficiency and relatively fast switch-
well. ing. The IGBT provides the simple
gate-drive characteristics of MOSFETs
G
EMI with the high-current and low-satura-
Switching power on and off at a rapid rate can cause tion-voltage capability of bipolar tran-
E
electromagnetic interference (EMI) that can affect nearby sistors. It combines an isolated-gate
electronic systems. Domestic and international standards 10-19. IGBT FET for the control input and a bipolar
define the amount of EMI that can be emitted. circuit symbol power transistor as a switch in a single
Unclamped Inductive Switching (UIS) device.
Whenever current through an inductance is turned off The IGBT is used in medium- to
quickly, the resulting magnetic field induces a counter high-power applications like switch-mode power sup-
electromagnetic force (CEMF) that can build up surpris- plies, traction motor control and induction heating. Large
ingly high potentials across the switch. With transistor IGBT modules typically consist of many devices in paral-
switches, the full buildup of this induced potential may lel and can have very high current-handling capabilities
far exceed the rated voltage breakdown of the transistor, in the order of hundreds of amperes with blocking volt-
resulting in catastrophic failure. ages of 6000 V. These IGBTs can control loads of hun-
There are two failure modes when subjecting a MOS- dreds of kilowatts. It is equally suitable in resonant-mode
FET to UIS. These failure mechanisms are considered as converter circuits.
either active or passive. The active mode results when The main advantages of IGBT over a Power MOSFET
the avalanche current forces the MOSFETs parasitic bi- and a BJT are:
polar transistor into conduction. In the passive mode the 1. Low on-state voltage drop due to conductivity mod-
instantaneous device temperature reaches a critical val- ulation and on-state current density. So smaller chip size
ue. At this elevated temperature the MOSFETs parasitic is possible, reducing cost.
bipolar transistor causes catastrophic thermal runaway. 2. Low driving power and a simple drive circuit due
In both cases the MOSFET is destroyed. to the input MOS gate structure, which allows relatively
easy control compared with current controlled devices in
Cost Considerations high voltage and high current applications.
As a semiconductor chip gets larger its cost grows 3. Compared with a bipolar transistor, it has better
exponentially. And, there is the cost of the package that current conduction capability as well as forward and
houses the integrated power device and the cost of in- reverse blocking capabilities.
terconnections. In deciding whether to integrate a power Main disadvantages are:
semiconductor into an integrated circuit or use two sepa- 1. Slower switching speed compared with a power
rate devices, look at the die size of each. If an integrated MOSFET, but better than a BJT.
power semiconductor and a discrete power semicon- 2. Possibility of latchup due to the internal PNPN thy-
ductor have large die, the die cost dominates the overall ristor structure.
cost, it would be cheaper to use two parts. A simple equivalent circuit model of an IGBT is shown
Integrated power semiconductors make sense when in Fig. 10-18. It contains MOSFET, JFET, NPN and PNP
the die sizes are moderate, or there are multiple outputs. transistors. The collector of the PNP is connected to the
This is so because the package and handling costs base of the NPN and the collector of the NPN is connect-
offset the increased silicon cost. A major impact on cost ed to the base of the PNP through the JFET. The NPN
is the number of good devices that can be obtained from and PNP transistors represent the parasitic thyristor that

60
voltage and current ratings similar to that of the bipolar
TJ = 25C
transistor. However, the presence of an isolated gate in
50 VGE = 17 V to 13 V
an IGBT makes it a lot simpler to drive than the BJT as it
requires much less drive power.
IC, COLLECTOR CURRENT (A)
40 An IGBT is turned ON or OFF by activating and

deactivating its Gate terminal. Applying a positive input
30 11 V
voltage signal across the Gate and the Emitter will keep
the device in its ON state, while making the input gate
20 signal zero or slightly negative will cause it to turn OFF
in much the same way as a bipolar transistor or MOSFET.
9V
10 Another advantage of the IGBT is that it has a much low-
er on-state channel resistance than a standard MOSFET.
7V
0 The IGBT is a voltage-controlled device, so it only
0 1 2 3 4 5 6 7 8
requires a small voltage on the gate to maintain con-
VCF, COLLECTOR-EMITTER VOLTAGE (V)
duction through the device unlike BJTs that require that
10-20. Output characteristics of the 15A, 600V the Base current is continuously supplied in a sufficient
NGTB15N60EG at 25C enough quantity to maintain saturation.
Also, it is a unidirectional device, meaning it can only
constitutes a regenerative feedback loop. The resistor RB switch current in the forward direction, that is from col-
represents the shorting of the base-emitter of the NPN lector to emitter unlike MOSFETs that have bi-directional
transistor to ensure that the thyristor does not latch up, current switching capabilities (controlled in the forward
which will lead to the IGBT latchup. The JFET represents direction and uncontrolled in the reverse direction).
the constriction of current between any two neighboring The principal of operation and gate drive circuits for
IGBT cells. It supports most of the voltage and allows the the IGBT are similar to that of the N-channel power MOS-
MOSFET to be a low voltage type and consequently have FET. The basic difference is that the resistance offered by
a low RDS(ON) value. A circuit symbol for the IGBT is the main conducting channel when current flows through
shown in Fig. 10-19. It has three terminals called Collec- the device in its ON state is very much smaller in the
tor (C), Gate (G) and Emitter (E). IGBT. Because of this, the current ratings are much high-
In general, high voltage, high current and low switch- er than an equivalent power MOSFET.
ing frequencies favor the IGBT while low voltage, low The main advantages of using the IGBT over other
current and high switching frequencies are the domain of types of transistors are its high voltage capability, low
the MOSFET. ON-resistance, ease of drive, relatively fast switching
There two types of IGBTs: Non-punch-through (NPT) speeds and combined with zero gate drive current
and punch-through (PT). The PT type has an extra buffer makes it a good choice for moderate speed, high voltage
layer that performs two functions: applications such as in pulse-width modulated (PWM),
Avoids failure by punch-through action because the variable speed control, switch-mode power supplies or
depletion region expansion at applied high voltage is solar powered DC-AC inverter and frequency converter
restricted by this layer. applications operating in the hundreds of kilohertz range.
Reduces the tail current during turn-off and shortens One of the main advantages of the IGBT transistor is
the fall time of the IGBT. the simplicity by which it can be driven ON by applying
NPT IGBTs have equal forward and reverse break- a positive gate voltage, or switched OFF by making the
down voltage, so they are suitable for ac applications. gate signal zero or slightly negative allowing it to be used
PT IGBTs have less reverse breakdown voltage than the in a variety of switching applications.
forward breakdown voltage, so they are applicable for With its lower on-state resistance and conduction
dc circuits where devices are not required to support losses as well as its ability to switch high voltages at high
voltage in the reverse direction. frequencies without damage makes the IGBT ideal for
The IGBT has a much lower on-state resistance, RON driving inductive loads such as coil windings, electro-
than an equivalent MOSFET. This means that the I2R drop magnets and dc motors.
across the bipolar output structure for a given switching ON Semiconductors NGTB15N60EG IGBT features
current is much lower. The forward blocking operation of a robust and cost effective NonPunch Through (NPT)
the IGBT transistor is identical to a power MOSFET. Trench construction. It is intended for switching applica-
When used as static controlled switch, the IGBT has tions and offers both low on state voltage and minimal

switching loss. Therefore the IGBT is well suited for motor 5. Jeff Perry, MOSFET Selection For Switching Power Supply
drive control and other hard switching applications. Incor- Systems, PET, April, 2012.
porated into the device is a rugged copackaged re- 6. Avery Lu, PowerStage MOSFETs - More Power in Less
verse recovery diode with a low forward voltage. Figure Space, PET, March, 2012.
10-20 is this IGBTs output characteristics at 25C. 7. Shah, Hemal, Demystifying Power MOSFETs Avalanche
Features Ruggedness, PET, August, 2011.
Low Saturation Voltage Resulting in Low Conduction 8. Havanur, Sanjay, Designing with DrMOS Part 1: Concept and
Loss Features, PET, February, 2011.
Low Switching Loss in Higher Frequency Applications 9. Havanur, Sanjay, Designing with DrMOS, Part II: Application
Soft Fast Reverse Recovery Diode Guidelines, PET, March, 2011.
10 _s Short Circuit Capability 10. Satyavrat Laud, IGBT FAQs, PET, May, 2014.
Excellent Current versus Package Size Performance 11. Klaus Vogel, Impact of IGBT and Diode Evolution on Design
Density of High Power Density Inverter Modules, PET, November, 2013.
This is a PbFree Device 12. Benjamin Jackson, High Speed IGBTs Take on the Super
Junction MOSFET, PET, October, 2012.
Related Articles 13. Clemente, Steve, Webtools Speed Up IGBT Selection and
1. Sam Davis, Unique MOSFETs Automatically Regulate and Design, PET, February, 2011.
Balance Series-Connected Supercaps, PET, December, 2013. 14. Sam Davis, LT4320 Ideal Diode Bridge Controller, PET,
2. Kim Gauen, Intelligent Power Switches for 24V Vehicular August, 2013.
Systems, PET, January, 2013. 3. 15. Davis, Sam, Schottky Diodes: the Old Ones Are Good, the
3. Chris Swartz, Hot-Swap Controller and Circuit Breaker New Ones Are Better, PET, March, 2011.
Protects External MOSFETs, PET, September, 2012.
4. Sam Davis, Semiconductor Back-to-Basics: Power MOSFETs, BACK TO TABLE OF CONTENTS
PET, September, 2012.
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APP NOTE

PART 3. SEMICONDUCTOR SWITCHES
CHAPTER 11:
WIDE BANDGAP
SEMICONDUCTORS
W
ide bandgap (WBG) semiconductor making possible more compact, less costly product
materials allow smaller, faster, more designs.
reliable power electronic components As manufacturing capabilities improve and market ap-
and with higher efficiency than their plications expand, costs are expected to decrease, mak-
silicon-based counterparts. These ing WBG-based devices competitive with less expensive
capabilities make it possible to re- Si-based devices. Several manufacturing challenges
duce weight, volume, and life-cycle costs in a wide range must be addressed to make WBG materials more cost
of power applications. Harnessing these capabilities can effective, including:
lead to dramatic energy savings in industrial processing Cost of producing larger-diameter wafers needs to be
and consumer appliances, accelerate widespread use of reduced.
electric vehicles and fuel cells, and help integrate renew- Novel device designs that effectively exploit the prop-
able energy onto the electric grid. erties of WBG materials are needed to achieve the volt-
WBG semiconductors permit devices to operate at age and current ratings required in certain applications.
much higher temperatures, voltages, and frequencies Alternative packaging materials or designs are also
making the power electronic modules using these mate- needed to withstand the high temperatures in WBG
rials significantly more powerful and energy-efficient than devices.
those made from conventional semiconductor materials. Existing systems may have to be redesigned to inte-
Figure 11-1 compares the breakdown voltages of silicon grate the WBG devices in ways that deliver their unique
and WBG semiconductors SiC and GaN. capabilities.
WBG semiconductors are expected to pave the way
for exciting innovations in power electronics, solid-state TABLE 11-1. WBG MATERIAL COMPARISON
lighting, and other diverse applications across multiple Material Chemical Symbol Bandgap Energy
industrial and clean energy devices with vastly superior (eV)
performance compared to current technology. Projected Germanium Ge 0.7
WBG benefits are: Silicon Si 1.1
Elimination of up to 90% of the power losses that
Gallium Arsenide GaAs 1.4
currently occur during ac-to-dc and dc-to-ac power
Silicon Carbide SiC 3.3
conversion.
Gallium Nitride GaN 3.4
Operation up to 10 times higher than Si-based devices,
which will enhance high-power performance. Diamond C 5.5
Operation up to higher maximum temperature of Si-
based devices, which will provide better overall system SiC
reliability. Using SiC (silicon carbide) can reduce on-resistance
Enabling of smaller and lighter systems with reduced to two orders of magnitude in compared with existing
lifecycle energy use, along with opportunities for new Si devices. Use of SiC devices can reduce power loss
applications. extensively, when applied to power conversion systems.
Operation at higher frequencies than Si-based devices, These SiC devices such as power MOSFET or IGBT

POWER ELECTRONICS LIBRARY CHAPTER 11: WIDE BANDGAP SEMICONDUCTORS
3. GaN-on-silicon offers the advantage of self-isolation

101 and therefore efficient monolithic power integrated cir-
SI Limit
cuits can be fabricated economically.
100 4. Enhancement-mode (normally off) and depletion mode
SIC Limit
RON (mm2)
(normally on) GaN devices are available.

10-1
GaN Limit SiC Power MOSFET
10-2
Cree is the first to come up with a viable MOSFET. The
ability to make these parts rests on the gate structure,
10-3
which requires a physics and chemistry solution. The
company still has some tweaking to do with the pro-
10-4
101 102 103 104 cess, but it appears to be well ahead of the other compa-
Breakdown Voltage (V) nies that have ventured into this technology.
Courtesy of Efficient Power Conversion The commercial production of 1200 V SiC power
MOSFETs is now feasible because of recent advances
11-1. Comparison of breakdown voltage for Si, SiC, and in substrate quality, improvements in epitaxy, optimized
GaN. device design, advances made in increasing channel
mobility with nitridation annealing, and optimization of
are used in combination with rectifier devices such as device fabrication processes. SiC is a better power
Schottky barrier diode (SBD). SiC-SBD has been intro- semiconductor than silicon (Si) because SiC has a much
duced. Within the last few years, SiC power MOSFETs higher electric field breakdown capability (almost 10x),
have been manufactured after being able to produce higher thermal conductivity, and higher temperature op-
usable SiC material. eration capability (wide electronic band gap).
SiC excels over Si as a semiconductor material in
GaN 600V and higher-rated breakdown voltage devices. SiC
Silicon power MOSFETs have not been able to keep Schottky diodes at 600V and 1200V ratings are commer-
pace with evolutionary changes in the power electronics cially available today and are already accepted as the
systems industry. The power electronics industry reached best solution for efficiency improvement in boost-convert-
the theoretical limit of silicon MOSFETs and now must go er topologies as well as in solar inverters by substituting
to another semiconductor material whose performance them for the previously used Si PiN free-wheeling diodes
matches todays newer systems. The new material is that have significant switching losses
gallium nitride (GaN), a high electron mobility (HEMT) The SiC MOSFET being discussed here is a 1200V,
semiconductor, which is poised to usher in new power 20A device from Cree that has a 100m RDS(on) at a +15V
devices that are superior to the present state of the art. gate-source voltage. Besides the inherent reduction in
Although GaN is young in its life cycle, it will certainly see on-resistance, SiC also offers a substantially reduced
significant improvements in the years to come. on-resistance variation over operating temperature. From
Gallium nitride (GaN) is grown on top of a silicon sub- 25C to 150C, SiC variations are in the range of 20%
strate. The end result is a fundamentally simple, elegant, versus 200% to 300% for Si. The SiC MOSFET die is ca-
cost-effective solution for power switching. This device pable of operation at junction temperatures greater than
behaves similarly to Silicon MOSFETs with some excep- 200C, but for this particular example it is limited by its
tions. TO-247 plastic package to 150C.
GaN transistors behave in a similar manner to silicon The technology also benefits from inherently low gate
power MOSFETs. A positive bias on the gate relative charge, which allows designers to use high switching
to the source causes the device to turn on. When the frequencies and thereby specify smaller passive compo-
bias is removed from the gate, the electrons under it are nents such as inductors and capacitors.
dispersed into the GaN, recreating the depletion region,
and once it the capability to block voltage. Among GaNs GaN Power Transistors
features: Performance of silicon-based MOSFETs is reaching
1. GaN offers superior performance compared with both its upper performance limit. One company developing a
silicon and silicon carbide. higher performance alternative is Efficient Power Con-
2. Device-grade gallium nitride can be grown on top of version (EPC). EPC produces gallium nitride (GaN) on
silicon wafers. silicon wafers using standard MOS processing equip-

ment. EPC produces gallium nitride 11-2. Enhancement the power devices or a short circuit
on silicon wafers using standard D mode GaN has a will result. Enhancement mode
MOS processing equipment. GaNs circuit schematic devices do not have this problem:
exceptionally high electron mobility similar to silicon with zero bias on the gate, an en-
and low temperature coefficient al- G MOSFETs with gate hancement mode device is off and
lows very low RDS(ON), while its later- (G), drain (D), and will not conduct current.
al device structure and majority car- source (S). The threshold of enhancement
rier diode provide exceptionally low mode GaN FETs is lower than that
QG (total gate charge) and zero QRR of silicon MOSFETs. This is made
(source-drain recovery charge). As
S possible by the almost flat rela-
a result, GaN devices can handle tionship between threshold and
tasks benefitted by very high switching speeds. temperature along with the very low gate-to-drain capac-
Initially, GaN-on-silicon transistors were depletion itance (CGD). The device starts to conduct significant
mode types. That is, they operated like a normally on current at 1.6V, so care must be taken to ensure a low
power switch that required a negative voltage to turn impedance path from gate-to-source when the device
them off. The ideal mode for designers is an enhance- needs to be held off during high speed switching in a
ment mode transistor that is normally non-conducting rectifier function.
and requires a positive voltage to turn it on, like the pres- The threshold of depletion mode GaN HEMTs ranges
ent silicon-only N-channel MOSFETs. EPC produces an from -5 V to -20 V.
enhancement mode GaN transistor using a proprietary Besides its low RDS(ON), the lateral structure of the
process with a GaN-on-silicon structure. In operation, a enhanced GaN FET also makes it a very low-capacitance
positive gate voltage turns the enhancement mode GaN device. It can switch hundreds of volts in nanoseconds,
transistor on. giving it multi-megahertz capability. With a lateral struc-
An advantage of the GaN transistor is that its block- ture, CGD comes only from a small corner of the gate and
ing voltage rating depends on the distance between the is much lower than the same capacitance in a vertical
drain and gate; the longer the distance, the higher the MOSFET.
voltage rating. Another GaN advantage is its very low Gate-to-source capacitance (CGS) consists of the
on-resistance. junction from the gate in channel, and the capacitance of
GaN transistors borrowed the same nomenclature as the dielectric between the gate and the field plate. CGS
their silicon brethren: gate, drain, and source, as shown is large compared with CGD, giving GaN FETs good dv/dt
Fig. 11-2. In addition, on-resistance and breakdown immunity, but still small compared with silicon MOSFETs.
voltage of a GaN device have a similar meaning as their The drain-to-source capacitance (CDS) is also small,
silicon counterparts. On-resistance (RDS(ON)) versus gate- being limited to the capacitance across the dielectric
source voltage curves are similar to silicon MOSFETs. from the field plate to the drain. Capacitance versus volt-
The temperature coefficient of GaN FETs on-resistance age curves for GaN FETs are similar to those for silicon,
is similar to the silicon MOSFET as it is positive, but the except that for a similar resistance, its capacitance is
magnitude is somewhat less. significantly lower.
GaN has a higher critical electric field strength than The GaN transistor structure is a purely lateral device,
silicon. Its higher electron mobility enables a GaN de- without the parasitic bipolar junction common to silcon
vice to have a smaller size for a given on-resistance and MOSFETs. Therefore, the enhancement GaN reverse bias
breakdown voltage than a silicon semiconductor. Com- or diode operation has a different mechanism, but a
pared to silicon devices, this also allows devices to be similar function. With zero bias gate-to-source there is an
physically smaller and their electrical terminals closer absence of electrons under the gate region. As the drain
together for a given breakdown voltage requirement. voltage decreases, a positive bias on the gate is created
The two types are the depletion mode and enhance- relative to the drift region, injecting electrons under the
ment mode. The depletion mode transistor is normally on gate. Thus, there are no minority carriers involved in con-
and is turned off with a negative voltage relative to the duction, and therefore no reverse recovery losses.
drain and source electrodes. In contrast, the enhance- Although QRR is zero, output capacitance (COSS)
ment mode transistor is normally off and is turned on has to be charged and discharged with every switch-
by positive voltage applied to the gate. Depletion mode ing cycle. For devices of similar RDS(ON), enhancement
transistors are inconvenient because at start-up of a GaN FETs have significantly lower COSS than silicon
power converter, a negative bias must first be applied to MOSFETs. It takes a bias on the gate greater than the

0.1 F The maximum allowable gate-source voltage for an

VIN enhanced GaN FET of 6V is low compared with tradi-
tional silicon. The gate voltage is also low compared to
HB
HOH most power MOSFETs, but does not suffer from as strong
VDD a negative temperature coefficient. And, the body diode
HOL
1 F forward drop can be a volt higher than comparable sili-
HS Load con MOSFETs.
HI LM5113 Because the total Miller charge (QGD) is much lower
for an eGaN FET than for a similar on-resistance pow-
LILOH er MOSFET, it is possible to turn on the device much
LOL faster. Too high a dv/dt can reduce efficiency by creating
EP VSS shoot-through during the hard switching transition. It
would therefore be an advantage to adjust the gate drive
pull-up resistance to minimize transition time without
inducing other unwanted loss mechanisms. This also
allows adjustment of the switch node voltage overshoot
11-3. EPC GaN transistors employ the Texas and ringing for improved EMI. For eGaN FETs, where the
Instruments LM5113 half-bridge gate driver IC. threshold voltage is low, the simplest general solution
is to split the gate pull-up and pull-down connections in
threshold voltage to turn on the enhancement FET in the the driver and allow the insertion of a discrete resistor as
reverse direction; the forward voltage of the diode is needed.
higher than silicon transistors. The LM5113, from Texas Instruments, is an example
In the cascode configuration for depletion mode de- of an eGaN FET optimized half-bridge driver that imple-
vices, the low-voltage silicon MOSFET has very low QRR ments bootstrap regulation (Fig. 11-3). Integrated in the
due to its body diode, which is orders of magnitude lower undervoltage lockout is an overvoltage clamp that limits
than a high-voltage silicon device with similar ratings to bootstrap voltage to 5.2 V ensuring sufficient reliable
the high-voltage HEMT. operation under all circuit conditions. In addition to the
The three most important GaN FET parameters are: clamp, there are separate source and sink pins, >50 V/
Maximum allowable gate voltage ns dv/dt capability, matched propagation time, 0.5 pull
Gate threshold voltage down, and separate high-side and low-side inputs to
Body diode voltage drop unlock the efficiencies the eGaN FETs enable.
D
VDD
HV GaN HEMT
HSB
UVLO HSGPU
Level Output
Shifter Driver
HSGPD
Dead HSS LV Si MOSFET
IN Time Logic
Controller
LSB G
EN LSGPU
Level Output K S
RDTL Shifter Driver 11-5. Transphorm employs a
LSGPD
cascode circuit to drive the GaN
RDTH LSS device. Drain, gate, and source
are similar to a silicon MOSFETs
GND LSO D, G, and S, and K is the Kelvin
11-4. PE29100 functional diagram. contact for the gate return.

0.0
1.0
2.0
POWER ELECTRONICS LIBRARY 3.0 WIDE BANDGAP SEMICONDUCTORS
CHAPTER 11:
0V
PE29100 -1V
To allow normally off operation of a depletion mode
The PE29100 from Peregrine Semiconductor (Fig. 11- -1.5V
GaN HEMT, it is often packaged in cascode with a
4) is an integrated high-speed driver intended to control low-voltage silicon MOSFET-2V to allow normally off opera-
-2.5V
the gates of external power devices, such as enhance- tion. The cascode configuration provides the ruggedness
-3.3V
ment mode gallium nitride (e.g. eGaN) transistors. The of a silicon gate, coupled with the improved voltage
outputs of the PE29100 are capable of providing switch- blocking characteristics of a high-voltage GaN HEMT.
ing transition speeds in the sub-nanosecond range for Figure 11-5 shows the cascode configuration with a
hard switching applications up to 33 MHz. The PE29100 depletion mode HEMT employed
ID by Transphorm. There
is available in a flip chip package. VGS for the gate driver since the
are no special requirements
The PE29100 is manufactured on Peregrines UltraC- VD
gate is connected to a standard silicon gate rated at 20
MOS process, a patented variation of silicon-on-insulator V with threshold around 2 V.
(SOI) technology on a sapphire substrate, offering the The layout is most critical regardless if the device is
-3.0
performance of GaAs with the economy and integration e-mode, d-mode, or cascode configuration. All of these
-2.0
of conventional CMOS. devices switch extremely fast and therefore the parasit-
-1.0
ic inductance
0.0 of the layout must be as
100.0 small as1.0
possible; in the range of 0.4 nH
VGS to 2.0 nH
2.0is desirable.
80.0
0V There
3.0are two types of GaN transis-
60.0 -1V tors, enhancement
0V mode and depletion
-1.5V -1V
mode. Enhancement mode is normally
20.0
-2V -1.5V
off and is turned on by a positive pulse.
40.0 -2.5V -2Vmode is normally on and is
Depletion
ID 00.0 -3.3V -2.5V
turned off by a negative pulse. Output
-3.3V
characteristics of a depletion mode GaN
-20.0
transistor are in Fig. 11-6. Figure 11-7
-40.0 shows the output characteristics of an
-60.0 enhancement mode GaN transistor.
-80.0 LMG5200
-100.0 Figure 11-8 shows the LMG5200 from
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0
Texas Instruments, a half-bridge, GaN
VD Courtesy of Efficient Power Conversion power stage with a highly integrated
11-6. Output characteristics of a depletion mode GaN transistor. high-side and low-side gate drivers that
includes built-in UVLO protection circuit-
100.0 ry and an overvoltage clamp circuitry.
VGS The clamp circuitry limits the bootstrap
80.0
5V refresh operation to ensure that the
60.0 4V high-side gate driver overdrive does
20.0 3V not exceed 5.4 V. The device integrates
2V two 19-m GaN FETs in a half-bridge
40.0 1V configuration. The device can be used
ID 00.0 0V in many isolated and non-isolated topol-
ogies, allowing very simple integration.
-20.0
The package is designed to minimize
-40.0 the loop inductance while keeping the
-60.0 PCB design simple. The drive strengths
for turn-on and turn-off are optimized to
-80.0 ensure high-voltage slew rates without
-100.0 causing any excessive ringing on the
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 gate or power loop.
VD Courtesy of Efficient Power Conversion Propagation delays between the
11-7. Output characteristics of an enhancement mode GaN transistor. high-side gate driver and low-side gate

driver are matched to allow very tight control of dead 11-10. The all-SiC
time. Controlling the dead time is critical in GaN-based 300A, 1.2kV half-
applications to maintain high efficiency. HI and LI can bridge module
be independently controlled to minimize the third quad- is packaged in
rant conduction of the low-side FET for hard switched industry-standard
buck converters. A very small propagation mismatch 62mm housing.
between the HI and LI to the drivers for both the falling
and rising thresholds ensures dead times of <10 ns.
Co-packaging the GaN FET half-bridge with the driver
ensures minimized common source inductance.
This minimized inductance has a significant perfor- UVLO, if there is sufficient voltage (VCC > 2.5 V), the driv-
mance impact on hard-switched topologies. er actively pulls the high-side and low-side gate driver
The built-in bootstrap circuit with clamp prevents the output low. The UVLO threshold hysteresis of 200 mV
high-side gate drive from exceeding the GaN FETs maxi- prevents chattering and unwanted turn-on due to voltage
mum gate-to-source voltage (VGS) without any additional spikes. Use an external VCC bypass capacitor with a
external circuitry. The built-in driver has an undervoltage value of 0.1 F or higher. A size of 0402 is recommended
lockout (UVLO) on the VDD and bootstrap (HB-HS) rails. to minimize trace length to the pin. You should place the
When the voltage is below the UVLO threshold voltage, bypass and bootstrap capacitors as close to the device
the device ignores both the HI and LI signals to prevent as possible to minimize parasitic inductance.
the GaN FETs from being partially turned on. Below
All-SiC 300A
LMG5200 Crees all-SiC 300A, 1.2kV half-
UVLO and 2 HB bridge module circuit (Fig. 11-9)
Clamp
1 VIN is packaged in industry-standard
62mm housing (Fig. 11-10). The
Level
VCC 6 Shifter module reduces energy loss due to
switching by more than five times
HI 4 compared to the equivalent silicon
3 HS
solution. This efficiency enables an
all-SiC high power converter rated up
to the megawatt level.
UVLO 8 SW
The all-SiC 62mm half-bridge
module allows designers to reduce
the amount of magnetic and cooling
LI 5 9 PGND
elements, delivering double the pow-
7 AGND er density and a lower system cost
while also reducing end user cost
of ownership. Offering a simplified
11-8. LMG5200 half-bridge with GaN output transistors and internal gate two-level topology that is feasible at
drivers. higher frequencies, the new module
can also eliminate the need to invest
1 in multi-level silicon-based solutions.
This Cree SiC power module is available with multiple
gate driver options and is pin-compatible to standard
62mm half-bridge modules, including IGBT modules rat-
3 2 ed at 450A or more. This allows designers to quickly and
easily evaluate the modules unparalleled capabilities.
The all-SiC 300A, 1.2kV half-bridge module is avail-
able as part number CAS300M12BM2. Companion gate
drivers are also available.
4 5 6 7 A newer module design also configured as in Fig.
11-9. Configuration of the Cree half-bridge. 11-9 is said to be the industrys most optimized to

achieve the unique benefits of SiC technologywith a 5. Sam Davis, Gallium Nitride Transistors Switch in the Sub-
66% reduction in module inductance to 5.5nH, compared Nanosecond Timeframe, powerelectronics.com, October 2013.
to competitive power products at 15nH. This reduction 6. Sam Davis, GaN Basics: FAQs, powerelectronics.com,
in module inductance enables faster switching speeds, October 2013.
higher frequency operation, and ultra-low losses. 7. Michael A Briere, Characterizing Performance of Mid-voltage
Available as part number CAS325M12HM2, the GaN-on-Si Devices, powerelectronics.com, July 2013.
high-performance power module is configured in a 8. Michael de Rooij, eGaN FET - Silicon Power Shoot Out: A
half-bridge topology comprised of seven 1.2kV 25m Retrospective, powerelectronics.com, July 2013.
C2M SiC MOSFETs and six 1.2kV 50A Z-Rec Schottky 9. Robinson Law, SiC MOSFET Gate Drive Optocouplers,
diodes. The companion gate driver (CGD15HB62LP) is powerelectronics.com, June 2014.
specifically designed for integration with the module to fit 10. Sam Davis, SiC Transistor Basics: FAQs, powerelectronics.
within the 62mm mounting footprint. An engineering com, October 2013.
evaluation kit that includes both the module and the gate 11. Mark Loboda, Design Considerations for SiC-based Power
driver is also available so design engineers can quickly Electronics, powerelectronics.com, November 2012.
and easily test the performance of the new device in their 12. Roger Allan, SiC: A Rugged Power Semiconductor
systems. Compound To Be Reckoned With, powerelectronics.com,
February 2012.
Related Articles 13. Deepak Veereddy, SiC Super Junction Transistors Offer
1. Eric Faraci, Enabling Industrial and Automotive Breakthrough High Temp Performance, powerelectronics.com,
Multimegahertz Buck Converters with GaN, powerelectronics. November 2011.
com, September 2015. 14. Sam Davis, 1200V SiC MOSFET Poised to Replace Si
2. Sam Davis, Half-Bridge GaN FET Module Comes In QFN, MOSFETs and IGBTs, powerelectronics.com, February 2011.
powerelectronics.com, March 2015. 15. Sam Davis, SiC and GaN Vie for Slice of the Electric Vehicle
3. Sam Davis, Fourth Generation Boosts eGaN FET Pie, powerelectronics.com, November 2009.
Performance, powerelectronics.com, July 2014.
4. Sam Davis, Wide Bandgap Semiconductors, BACK TO TABLE OF CONTENTS
powerelectronics.com, June 2014.
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VDD BP6 BP3 BOOT

INTRODUCTION........................................................ 2 PART 4: POWER APPLICATIONS

CHAPTER 1: POWER SUPPLY FUNDAMENTALS............ 3 CHAPTER 13: ENERGY HARVESTING........................ 104

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PART 3. SEMICONDUCTOR SWITCHES

10-2. Actual power semiconductors do not meet the ideal

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Drain voltage and also p-channel devices

lower the power dissipation 400 7.0A

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ID, Drain Current (A)

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VGS, Gate-to-Source Voltage (V)

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ISD, Reverse Drain Current (A)

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(>100V) and values of 1.2V for 10-11. Typical N-Channel

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alent cell density and said 10-13. DirectFET is a surface mount

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THWn BOOT V IN 10-16. Vishay

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40 An IGBT is turned ON or OFF by activating and

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Featured Semiconductor Assets

Automotive LED Driver Secondary-Side

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PART 3. SEMICONDUCTOR SWITCHES

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3. GaN-on-silicon offers the advantage of self-isolation

(normally on) GaN devices are available.

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0.1 F The maximum allowable gate-source voltage for an

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For more power management solutions,

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