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However, backplane bandwidth us how to study a switch is enough? Obviously, the estimation method
is of no use, I think it should be from two aspects to consider:
1, the number of port capacity) all the X ports and 2 times should be less than the backplane
bandwidth, can realize full duplex nonblocking switching, proof switch has the condition of maximum
data exchange performance of the play.
2,) full configuration throughput (Mpps) = full configuration of the GE port number 1.488Mpps 1
Gigabit ports in the packet length as the theoretical throughput of 64 bytes for 1.488Mpps. For
example, one can provide a maximum of 64 Gigabit ports on the switch, the full configuration
throughput should reach 64 1.488Mpps = 95.2Mpps, can ensure that all port average speed, non
blocking packet switching. If a switch up to 176 Gigabit ports, and claimed that the throughput is less
than 261.8Mpps (176 x 1.488Mpps = 261.8), then the user has reason to believe that the switch is
used to structure design of obstruction. The general is both meet the switch is qualified switches.
For example:
2950G-48
4506
64G backplane
4306 x + (engine) = 32
Throughput = 32 1.488=47.616
The backboard is relatively large, relatively small switch throughput, in addition to retain the upgrade
ability is the software efficiency or special chip circuit design problems; the backboard is relatively
small. The throughput is relatively large switches, overall performance is relatively high. But the
backplane bandwidth can be believed that the manufacturers of publicity, but the throughput is unable
to believe that manufacturers of publicity, because the latter is a design value, the test is difficult and
not very meaningful. (this sentence seems to say the anti)
Switch back version rate is generally: Mbps, refers to the second layer,
The internal structure and the exchange rate is closely related to the backplane bandwidth resources.
At present, the internal structure of the switch are mainly the following: one is the shared memory
structure, this structure dependent center to provide high performance full port connection exchange
engine, the core engine checks each input packet to determine routing. This method requires a lot of
memory bandwidth, high management cost, especially with the increase of the switch port, the central
memory prices will be very high, so the switch becomes the bottleneck of performance of the
realization of the kernel; two is the cross bus structure, it can be a direct point to point connection in
the port, the single point transmission the performance is very good, but not suitable for the multi point
transmission; three is a hybrid cross bus structure, this is a way to achieve mixed cross bus, its design
is the development, will cross bus matrix into a matrix of small, intermediate through a bus connected
with the high performance. Its advantages are reducing the cross bus number, reduce cost, reduce
bus contention; but the bus connection matrix becomes a performance bottleneck new.
Exchange capacity switch is also known as the backplane bandwidth or exchange of bandwidth, is the
largest amount of data exchange interface processor or interface card and the data bus can huff and
puff. Exchange capacity that exchanges data exchange capability, the unit Gbps, general switch
exchange capacity from a few Gbps to hundreds of Gbps inequality. The exchange capacity of a
switch is high, the data processing ability is stronger, but at the same time the design cost will be
higher.
1) all the number multiplied by the port of port capacity and 2 times should be less than the exchange
capacity, which can realize full duplex nonblocking switching, proof switch has the condition of
maximum data exchange performance of the play.
2) full configuration throughput (Mpps) = full configuration port number * 1.488Mpps, of which 1
Gigabit ports in the packet length as the theoretical throughput of 64 bytes for 1.488Mpps.
Exchange capacity utilization rate is closely related with the internal structure of the switch. At present,
the internal structure of the switch are mainly the following: one is the shared memory structure, this
kind of structure dependent center to provide high performance full port connection exchange engine,
the core engine checks each input packet to determine routing. This method requires a lot of memory
bandwidth, high management cost, especially with the increase of the switch port, the central memory
prices will be very high, so the switch becomes the bottleneck of performance of the realization of the
kernel; two is the cross bus structure, it can be a direct point to point connection in the port, the single
point transmission performance very good, but not suitable for the multi point transmission; three is a
hybrid cross bus structure, this is a way to achieve mixed cross bus, its design is the development, will
cross bus matrix into a matrix of small, intermediate through a high performance bus connection. Its
advantages are reducing the cross bus number, reduce cost, reduce bus contention; but the bus
connection matrix becomes a performance bottleneck new.
What is the relation between exchange rate and capacity of forwarding packets
Forwarding bandwidth = packet forwarding rate *8* (64812) =1344* packet forwarding rate
But when I saw the parameter CISCO Catalyst 3560G-24TS--24, is unable to verify that the formula.
Cisco Catalyst 3560G-24TS--24 10/100/1000 Ethernet ports, 4 SFP Gigabit Ethernet port; 1RU
I judge the switch is not the line speed switch. If the line speed, forwarding rate = (24+4)
*1.48809=41.66652M,
Is it right? Wrong parameter formula, but many products have proved this formula.
1, our company low-end LSW exchange using store and forward mode, exchange capacity by the size
of the cache (BUFFER) bus and bus frequency.
That is, exchange capacity = buffer width * cache bus frequency =96*133=12.8Gbps
Division I low-end LSW ports support full duplex, so the switch port capacity is its ability to provide two
times the port of. That is,
Port capacity = 2* (n*100Mbps+m*1000Mbps) (n: switches are n 100M ports, M: switch has m 1000M
port),
Our company LSW is the line speed forwarding forwarding ability test, to deal with the minimum
packet length to measure, for Ethernet minimum packages for 64BYTE, plus the frame overhead of
20BYTE, therefore the minimum package for the 84BYTE.
For 1 full duplex 1000Mbps interface to achieve the line speed forwarding capacity: = 1000Mbps/
((64+20) *8bit) = 1.488Mpps
For 1 full duplex 100Mbps interface to achieve the line speed forwarding capacity: = 100Mbps/
((64+20) *8bit) = 0.149Mpps
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