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Well-rounded technical, hands-on, and problem-solving skills in system/software/firmware

for full product life cycle MRD, budgeting, scheduling, hiring, mentoring, design,
implementation, QA/SQA, release, document. and training.
Gradually increased leadership responsibilities 1 directly reported engineer in
Ministor/Seagate, 2 intern students in IBM, 3 mixed level engineers in GlobaspanVirata, and a
total of 2 directly/indirectly reported/FAEs in Exar/Hifn.
Strong experience in firmware development, PCIe kernel driver model, QA, system
level validation, hardware/ software benchmark (fio, iperf, siege), API/Library/SDK,
SoC/ASIC bringup, architecture design, and lab equipments
Good knowledge in X86_64, QPI, PCIe TLB, BIOS, AER, NUMA issues, SMP Linux kernel
drivers, RPM, IPMI, Server Management, and SQA test plan/metrics (Acceptance, Error
Injection, Stress, Performance, & Compatibility Tests).
Familiar with Data Compression (LZS/LZJB/GZIP/ZLIB), Storage Protocol (iSCSI, NAS,
IB, and FC), HDD (ATA/SATA/ SAS/FCAL) firmware (read/write caching, defect
management, spindle control, etc), SSD/Flash/NVRAM firmware (wear leveling, defect
management, etc), MO/Blu-ray DVD, and Storage System (RAID, HBA, NAS, VTL, Dedup,
Familiar with Network Security/Firewall/VPN/UTM (IPSec/SSL/TLS/IKE/DH/RSA), Layer
2/3/4/5 protocol stacks (TCP/IP/HTTP/SSH/SNMP/VLAN/xDSL/ATM/3GPP/LTE), Wi-Fi
(802.11n/11ac), WiMax (802.16), Ethernet (CSMACD).
Good knowledge in MySQL, Hadoop MapReduce/HDFS, data center technologies,
large-scale distributed systems, Cloud/Network Security (Threat
Detection/Prevention), Cryptography, SDN/OpenFlow, OpenStack Swift, & Agile.
Open Source Community (OpenSSL/OpenSWAN) software contributor.
Proven track record of delivering quality software/firmware cross multiple sites in a timely
Familiar with Asian ODM/OEM culture, fluent in Mandarin and basic Japanese, and willing to
travel to Asia (50%).

Programming Languages: C/C++ (10+ yr), Linux Shell (10+ yr), Python (4 yr), Java (2
yr), PHP & JS (1 yr), & Assembly
Operating Systems: Linux/SMP, Openwrt, RTOS, UNIX, Mac OS X, VMware, FreeBSD,
OpenBSD, VxWorks, Windows.
Microprocessor/Microcontroller/SoC: ARM Cortex/7/9/11, Intel Puma 6MG, MIPS 5231, 8051,
80x86, 68K, PPC 403.
Performance Tools: fio, iPerf, OProfile, gprof, Terasort, SPEC2000, OpenSSL Speed
Test, Siege Util, IXIA, Smartbit.
Version Control/Tools/IDE: GIT, GNU tools (GDB), CVS, SVN, PVCS, SourceSafe, Visual Studio,
and Eclipse
Web Servers/Applications: Apache and Nginx.
Lab Equipment: Logic/bus/spectrum analyzers, PCIe protocol/signal analyzer (LeCroy), and
digital/analog scopes.

Sustained Linux PCIe kernel driver, provided SoC/ASIC bringup thru JTAG, and resolved
PCIe Gen 2, BIOS spread spectrum, PCIe AER, DMA, PCIe BARx, SanbyBridge Server
warm boot, IPMI config. and other compatibility issues.
Focal point for supporting 8- 10 Asia SOHO/SMB accounts, interfaced with 10+ Asian
FAE/ODM/OEM, conducted FAE/distributor/customer trainings, assisted FAEs, visited 8 10
customers, and secured more than 5M design wins.
Lead Hifns security PCIe board qualification and cryptographic SDK release software testing,
designed and executed SQA test plan/metrics using Linux Shell and Python scripts, and
interfaced with China design teams.
Accomplished definitions of VTL LZS PCIe-based compression card software API requirements,
participated in design (in GNU C/C++)/architecture/documentation review, and all post-sales
technical support.
Supported hardware CCMP offload engine on Intels WiMax (802.16) base stations and FPGA
board test/validation.
Provided PCIe board schematic reviews, data sheets, software release documents,
technical bulletin, and FAQs.

Hifn Inc. Jun. 2002 Sep. 2005

Staff Software Applications Engineer
Provided 2nd level customer support thru e-mail, Saleforce.com, or conference call, resolved
PCIe BARx register compatibility, PCIe cache line size, PCIe TLB/DMA, and other
performance issues on PCI v2.0/PCIX/PCIe 1 platforms.
Integrated and optimized IPSec/SSL/IKE/TCP/IPv4/IPv6 VPN protocol stack, Linux PCIe
kernel driver, cryptographic APIs, and Windows/Linux/VxWorks/OpenBSD driver into
customers ARM 7/9/11 SOHO/SMB/VPN appliances.
Worked with hardware team to bringup/validate/debug SoC/ASIC functionalities on Xilinx
FPGA board.
Accomplished definitions of PKI API requirements, architecture design, and documentations.
Jointly developed Korea SEED algorithm in GNU C/C++ on Hifns HSP platform and
cryptographic software driver.
Worked with technical writer to provide design guide, users guide, and Application Notes as
well as review PCIe board schematic, errata, and, data sheets.

GlobespanVirata Inc. Apr. 2000 Jun. 2002

Staff Firmware/Lead Engineer
Supervised 3 engineers (1 GUI, 1 senior principal, and 1 middle level engineers) on GUI
software, xDSL firmware, UART device driver, and TCP/IP/SNMP MIB integration projects on
Viratas ARM7TDMI platforms.
Lead engineer responsible for specifying HDSL2/G.SHDSL PHY SoCs/ASICs/Chipsets,
defining device driver, APIs, and DSP interface architecture, interfacing with cross-functional
teams, bringing up ASIC thru JTAG/ICE, GNU C/C++ tools, firmware, and DSP code on Linux,
code review, training FAEs and mentoring junior engineers.
Architected, developed, integrated, and documented HDSL2 PHY device drive into Viratas
Layer 2/3 protocol stack (TCP/IPv4, SNMP, DNS, DHCP, Bridge/Router, VPN, etc) to become a
total turn-key SOHO/SMB router solutions.
Created the whole software development system (Keil 8052 C compiler, GUI menus, GNU
tools, GEENI/ SIGNUM emulators, Microsoft SourceSafe, RCS, lab stations, Release notes, and
a Linux sub network.
Siros Technologies, Inc. Mar. 1999 - Apr. 2000
Senior Firmware Engineer/Software Manager
Managed interaction with the hardware vendors (TI) and cross-functional teams, e.g., servo
and PCB design teams.
Participated in SCSI SoC/ASIC bringup, hardware testing, disc error rate measurement,
and software tool support.
Firmware/software lead for specification, architecture design, implementation, Magneto
Optical drive hardware validation, software tool support, firmware integration and
Lead engineer responsible for architecting and developing SCSI II firmware, IPC servo code,
UART device driver using TI C/C++ compiler, TMS320C27 DSP assembly, TI RTOS,
SourceSafe, and Windows NT environment for the next generation Magneto Optical drives
(pre-Blu-ray DVD drives).
IBM Corporation, Storage System Division Feb. 1998 - Feb. 1999
Group Lead/Staff Firmware Engineer
Supervised, mentored, and trained 2 intern students on setting SCSI/FCAL firmware testing
Group lead engineer responsible for developing SAS/SCSI II/III, UART, and Fibre Channel
(FCAL) HDD firmware in command handler, caching algorithm, read/write code, channel, and
servo DSP IPC interface using C, 80188 assembly, Windows NT for 3.5" drives.
Project lead for capital budget, recruiting, scheduling, coordinating firmware/hardware issues,
managing code/test scripts bring-up, debugging SoCs/ASICs, interfacing with cross-
functional teams, and supervising testing activity.

Seagate Technology, San Jose Apr. 1995 - Feb. 1998

Lead/Principal Firmware Engineer
Supervised, mentored, and trained 1 middle level firmware engineer on ATA/IDE/HDD
firmware testing.
Managed DVT/DMT failure analysis, cross-functional team interactions, supervising functional
testing (Acceptance, compatibility, and performance), firmware integration, resolving design
issues, and supporting automated test tool.
Lead engineer for debugging ATA/IDE/HDD SoCs/ASICs, IDE drive hardware validation/bring-
up, and developing 8052 interface (command handling, caching, defect management in 8052
assembly) and DSP firmware in Windows.
Coordinated with servo DSP IPC group, read/write channel, drive integration, PCB design,
DVT, FA, and test process groups for various reliability issues, signal integrity, hardware
testing, and error rate measurements.
Helped transferred 3 2.5 hard drive products to Seagates Singapore factories/production

MiniStor Peripheral Corp. Jan.

1993 - Apr. 1995 Principal Firmware Engineer
Mentored and trained 1 junior level firmware engineer on ATA/IDE/HDD firmware debug and
Principal engineer responsible for developing 2.5" ATA/IDE/HDD drive firmware in Zilog C95
Assembly, ATA/IDE SoC/ASIC validation, read channel error rate measurement on
Windows 3.1 environment, and training an engineer.
Developed IDE/PCMCIA controller firmware in Zilog C95 assembly, PVCS, and Windows 3.1
for 1.8" drives including read/write engine, look ahead caching read, SELFTEST, download thru
interface, OTP code, and DSP/servo IPC code.
Successfully transferred SELFTEST firmware to MiniStor's Singapore factory/production lines in
6 months.
Quantum Corporation Jul. 1990 -
Jan. 1993
Senior Firmware Engineer
Developed ATA/SCSI/HDD firmware in NEC K7 assembly languages, hardware
validation/bringing up SoCs/ASICs, PVCS, including read/write multiple commands, self-
diagnostic, write caching, and segmented caching code.
Integrated defect management, DSP/servo IPC error recovery, and vendor unique
commands and released firmware to Quantum's pilot production lines.
Performed functional tests and monitored compatibility test issues.
Developed AUTO TRANSFER function for Quantum's IDE SoC/ASIC chips.

Chips & Technologies, Inc. May.

1989 - Jul. 1990 Design Engineer

MSEE : May 1989, GPA 3.7/4.00, May 1989, Marquette University, Milwaukee, WI
BSEE: Jun. 1981, class rank : 2nd of 55, National Taipei University of Technology, Taipei,
Taiwan, R.O.C.
Completed Hadoop and VMware Player training classes, Aug. 2014 Exar Corporation.
Completed extensive management and professional training classes, Sep. 1997 Seagate
UCSC Extension instructor for "Real-Time Software Design" class, San Jose, May '91 - Jun. '93.
Completed VLSI design classes (Verilog and VHDL) from UC/Berkeley course and SITN network
course, Sep. 1990. Quantum Corporation.