1522 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.

7, JULY 2008

A 65 nm CMOS Multistandard, Multiband TV Tuner

for Mobile and Multimedia Applications
Iason Vassiliou, Member, IEEE, Kostis Vavelidis, Member, IEEE, Nikos Haralabidis, Senior Member, IEEE,
Aris Kyranas, Member, IEEE, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos,
Charalambos Kapnistis, Member, IEEE, Spyros Kavadias, Member, IEEE, Nikos Kanakaris,
Emmanouil Metaxakis, Christos Kokozidis, and Hamed Peyravi

AbstractThis paper presents a direct conversion, multistan-
dard TV tuner implemented on a 65 nm digital CMOS process
occupying less than 7 mm2 . The tuner is compliant with several
digital terrestrial, fixed and mobile TV standards, including
DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB
noise figure at VHF, UHF, and L-band, respectively, while the
measured sensitivity at UHF for the QPSK-1/2 DVB-T mode is
98 dBm at the PCB connector. The implemented RF front-ends
support both single-ended and differential inputs. An integrated
61 fractional-N synthesizer operating from 1.2 to 1.8 GHz
achieves less than 1 integrated phase error, thus enabling a max-
imum SNR in excess of 37 dB for VHF and UHF. Multistandard
capability is also enabled by programmable channel-select filters.
Power consumption is less than 140 mW in DVB-T mode for all
three bands.
Index TermsDirect conversion, DVB-H, DVB-T, fractional-N
synthesizer, ISDB-T, mobile TV, OFDM, RF CMOS, RF receiver,
system-on-a-chip (SOC), T-DMB, TV tuner, wireless.
I. INTRODUCTION
S DIGITAL mobile TV is being deployed in several
A countries using a variety of standards, video reception
becomes the latest feature of multimedia-enriched handheld
devices. To allow for user flexibility and enable economies
of scale for handset and multimedia terminal manufacturers,
multistandard digital video receivers, supporting both mobile
and broadcast TV, are desirable.
In broadcast TV, the most dominant standards expected to
co-exist are DVB-T in Europe, ISDB-T in Japan/Brazil, both
based on OFDM modulation (orthogonal frequency-division
multiplexing), and ATSC in USA based on 8-VSB (vestigial
sideband modulation). In mobile TV, the frontrunner appears
to be DVB-H [1], which is an extension of DVB-T. Its main
features are 1) low-power reception, enabled by operation in
bursts (time-slicing) with a typical 1:10 on/off ratio at the
expense of lower resolution and 2) additional error-coding
(FEC) for more robust Doppler performance, needed for mo-
bile operation. DVB-H is defined mainly for a portion of the
UHF band, 470750 MHz, to allow interoperability with the
Manuscript received November 28, 2007; revised January 28, 2008.
I. Vassiliou, K. Vavelidis, N. Haralabidis, A. Kyranas, Y. Kokolakis,
S. Bouras, C. Kapnistis, S. Kavadias, N. Kanakaris, C. Kokozidis, and
H. Peyravi are with Broadcom Hellas S.A., 17455 Alimos, Greece (e-mail:
iason@broadcom.com).
G. Kamoulakos and E. Metaxakis are with Elxys Innovations, Marousi,
Athens, Greece.
Digital Object Identifier 10.1109/JSSC.2008.923721
0018-9200/$25.00 2008 IEEE
900 MHz GSM band in Europe. Deployment in the VHF III
band (170240 MHz) and L-band (14501490 MHz for Europe
and 16701675 MHz for USA) is also discussed. T-DMB
(Terrestrial Digital Multimedia Broadcasting) [2], defined in
the VHF III, L-bands and already deployed in Korea, is also
OFDM-based and uses the DAB (Digital Audio Broadcasting)
physical layer [3] for mobile TV operation. In Japan, a lower
bandwidth, mobile version of ISDB-T has been deployed using
430 kHz channels in UHF. Finally, several more mobile TV
standards, both terrestrial and satellite, are emerging world-
wide, such as MediaFLO [4] and ATSC-mobile in the USA,
DMB-T and satellite-based CMMB in China. Taking into
account the above requirements, a multistandard tuner needs
to support multiple RF bands, arbitrary channel spacing and
channel bandwidths from 0.43 to 8 MHz. Furthermore, all
sensitivity, blocking and intermodulation specifications of the
different standards should be met, ideally without sacrificing
the optimality of the solution.
In addition to multistandard operation, low-cost, low-power
and small physical size required by cellular phones and other
mobile terminals necessitates moving into smaller geometries
and integrating more functionality into a single piece of silicon.
High performance radios in nanometer digital CMOS processes,
is a critical step towards single-die implementations of complex
communication and broadcast standards.
This paper presents the implementation such a radio tuner
using a 65 nm digital CMOS process, supporting most popular
mobile and fixed broadcast TV standards, such as DVB-T/H,
T-DMB and ISDB-T (including one- and three-segment mobile
versions). Section II describes challenges related to mobile TV
specifications, while Section III gives an overview of the se-
lected architecture. The circuit implementation is presented in
detail in Section IV, while Section V discusses in depth chal-
lenges related to the 65 nm process. Finally, detailed measure-
ment results, including system-level testing with a digital de-
modulator in a field programmable gate array (FPGA), are pre-
sented in Section VI.
II. MULTISTANDARD TUNER DESIGN CHALLENGES
AND SPECIFICATIONS
To support the terrestrial broadcast TV range of 48900 MHz,
typical broadcast TV tuners need to address issues related to
covering several octaves, such as rejection of interference at in-
teger multiples of the wanted signal and in-band image rejec-
tion. These issues have been extensively addressed in the tech-
nical literature[5], [6], and typical techniques include using ex-
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS
ternal RF tracking filters with limited bandwidth that track
the signal carrier [7], or the up-down conversion super-hetero-
dyne architecture [8]. Such tuners tend to be power-hungry and
bulky, which makes them unsuitable for mobile TV. In addition,
covering a range of several octaves with a single RF front-end
requires wideband low-noise amplifiers (LNAs), which usually
have poor noise figure (NF) performance. Since most mobile
TV standards use only a portion of the 48900 MHz broadcast
TV band, namely the VHF III and UHF bands with the addi-
tion of L-band, harmonic rejection requirements are not as se-
vere, thus making direct conversion with multiple RF front-ends
a viable, low-cost, low-power alternative [9][11]. Multiple RF
front-ends also support flexibility in the final implementation,
since depending on the application, it is desirable to support one
or more of the above bands at a time using different antennae
configurations. For example, in cellular phones it may be desir-
able to have two different antennas that support the UHF and
L-band or one antenna supporting UHF only.
Among the radio standards that this implementation is in-
tended to support, DVB-T and DVB-H pose the most stringent
sensitivity and blocking requirements. In the MBRAI 2.0 spec-
ification [12] for DVB-T/H, a noise figure (NF) below 4 dB is
required. In addition to the low NF, the 64-QAM modulation
used requires a signal-to-noise ratio (SNR) in excess of 25 dB
in mobile reception conditions (Portable and Doppler channels).
In OFDM systems, when a high SNR is required, other impair-
ments such as I/Q mismatch and phase noise may affect the
overall bit-error rate (BER) [13]. To avoid degrading an SNR of
25 dB due to additive white Gaussian noise (AWGN), additional
circuit noise should be at least 10 dB below the AWGN noise
level, which translates into an equivalent SNR of 35 dB when
input signal is not limited by AWGN. To achieve this SNR, an-
alytical calculations [14] and simulations show that to an rms
in-band integrated phase noise error of less than 1 ( 37 dBc)
and I/Q phase and gain mismatch of less than 1 and 0.1 dB,
respectively, are needed. Since the tuner is continuously tuned
to a channel, I/Q mismatch can be corrected by blind adaptive
calibration in the demodulator [15].
Both T-DMB and DVB-T/H standards define several recep-
tion conditions in the presence of other interfering TV channels,
some of which have significant impact on the tuner specifica-
tions. Some of the most significant are the following [2], [12]:
1) S2 pattern in DVB-T/H: digital TV interference 2 channels
away and higher, up to 40 dB stronger than the 64-QAM,
( ) wanted signal. In addition to sharp channel-
select filters, in direct conversion or low-IF architectures,
this implies high second-order linearity. Analysis shows
that in order to meet this specification with a 3 dB imple-
mentation margin, an IIP2 in excess of 30 dBm is needed,
while the NF should be less 10 dB. In T-DMB/DAB, the
40 dB far-away blocking specification for digital interfer-
ence results into a lower IIP2 requirement.
2) S1 pattern in DVB-T/H: analog TV (PAL/SECAM) adja-
cent channel interference, up to 35 dB stronger than the
wanted 64-QAM ( ) signal (43 dB stronger for
interference at other channels than adjacent). As the carrier
of the analog TV picture carrier (where the signal power is
concentrated) is only 5.25 MHz away from the center of the
1523
Fig. 1. L1 DVB-T/H specification, 1f = 16 MHz for 8 MHz channel spacing.
wanted channel, this specification poses stringent analog
filtering requirements. For an 8-MHz channel raster, to
avoid saturation of the ADC, at least 25 dB attenuation is
needed at 5.25 MHz from the baseband analog filters. In
addition, reciprocal mixing of the LO phase noise with the
picture carrier will also result into in-band interference. To
meet this specification with at least 3 dB margin, the inte-
grated phase noise from 1.25 to 9.25 MHz offset from the
LO should less than 60 dBc.
3) L1 pattern in DVB-T/H: interference from digital and
analog TV, two and four channels away from the wanted
channel, as depicted in Fig. 1. Since the interferers are
defined to be 40 and 45 dB stronger than the wanted
16-QAM signal, taking into account other sources of SNR
degradation, such as NF, and allowing for 3 dB margin,
this translates into an IIP3 requirement of 5 dBm and an
NF of less than 8 dB.
Additional challenges include the presence of GSM interfer-
ence from a cell-phone up-link in DVB-H, which calls for high
LNA linearity and filtering. Given the requirements for low cost
and low power, the above specifications call for careful design
and innovative techniques.
III. ARCHITECTURE
Fig. 2 shows the tuner in the context of a digital TV system
that could support a single or multiple antennas. Depending on
the application any combination of RF bands could be used.
The block diagram of the direct-conversion multistandard TV
tuner is shown in Fig. 3 [16]. By using three RF front ends cov-
ering the 174240 MHz (VHF III), 470862 MHz (UHF IV/V)
and 1.41.7 GHz (L-band for T-DMB in Europe and DVB-H
in US) bands, respectively, most mobile TV standards deployed
worldwide are supported. Since each RF front-end is separate,
interference at harmonics of the local oscillator frequency is al-
ways out of band; thus it can be rejected by an external RF filter,
which is typically required in cellphone applications to reject
1524
Fig. 2. Multistandard tuner IC in digital TV system implementation.
Fig. 3. Multistandard TV tuner block diagram.
GSM interference, or the tuning of matching circuits and in-
ternal low-noise amplifiers (LNAs). Even though most applica-
tions use one or two of the three RF bands and typically separate
antennas are used to optimize performance and antenna area for
each band, connection to a single antenna is still possible by
the appropriate combination of external switches and RF filters
(Fig. 2).
All three RF front-ends employ variable-gain LNAs and pas-
sive mixers as in [10]. At the LNA outputs, a logarithmic am-
plifier is connected to provide an RSSI, used to detect wideband
interference. The RSSI is digitized by the companion baseband
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
demodulator, which implements the RF AGC algorithm: when
interference is large, RF gain is reduced thus helping to achieve
the high linearity required in meeting the blocking and inter-
modulation specifications for DVB-H/T and T-DMB.
The analog baseband path consists of two digitally pro-
grammable gain amplifiers (PGAs) before and after the
channel-select filters. An on-chip analog-to-digital converter
(ADC) is included for analog gain control of the PGAs,
allowing versatility in the system implementation. A pro-
grammable look-up table is used for the optimization of the
gain distribution between the PGAs and filter for optimal NF
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS
Fig. 4. (a) LNA simplified schematic. (b) Passive mixers.
and linearity, depending on the standard. Similarly, an on-chip
digital-to-analog converter (DAC) can be used to digitally
control the LNA gain.
As in [10], a fractional-N synthesizer is used for LO
generation. This allows a wide range in selecting the external
crystal reference, which ultimately can be shared with other ap-
plications to save cost, while maintaining a fine frequency step
which is necessary for multistandard operation. A high com-
parison frequency makes the phase-locked loop (PLL) division
ratio small and allows the use of a high loop bandwidth,
which reduces the overall integrated phase noise. To minimize
the required VCO frequency range of operation, the PLL covers
a range from 1.2 to 1.8 GHz. Quadrature LO for the UHF and
VHF mixers is generated by division of the VCO frequency by
2/3 or 6/8, respectively, while a first-order polyphase filter is
used for the L-band. Since the receiver operates continuously re-
ceiving signal from the same transmitter, adaptive I/Q mismatch
calibration at the baseband modem can be used to eliminate the
1525
potentially high I/Q mismatch due to the polyphase filters and
the divide-by-three circuits.
The tuner also provides options to take advantage of the
digital processing power of the companion demodulator. As
discussed in detail in Section IV, the LO signal can be used to
calibrate both the baseband filters and the resonance frequency
of the LNAs load. Finally, to allow for optimization depending
on the standard requirements, all circuit blocks have pro-
grammable bias. This feature can also be used by the baseband
modem to dynamically adapt power consumption depending
on the channel conditions, as detected by the wideband RSSI
and the ADC input signal.
IV. CIRCUIT DESIGN
A. RF Front-End
The LNAs for all three bands use a common-source, cas-
code topology with degeneration, as shown in Fig. 4(a). For the
1526
Fig. 5. Fractional-N synthesizer and VCO.
UHF band, wideband input matching is achieved by using ex-
ternal series inductors and an on-chip switched capacitor bank
, which is adjusted according to the desired tuning frequency.
Typically in a system-on-a-chip (SoC) environment, it is prefer-
able to use fully differential RF input stages to minimize digital
noise coupling. However, some performance degradation from
single-ended operation could be acceptable in applications sen-
sitive to cost/area, where eliminating external baluns is impor-
tant. For this reason, all three LNAs can support both differen-
tial and single-ended inputs by adjusting the external matching
and appropriately programming internal switches. For the UHF
and L-band LNAs, in the single-ended mode, device M1B is
switched off by S1 and RF switch S2 is turned on to adjust the
primary coil inductance of the output transformer. The VHF
LNA uses external output load inductors and can operate as
single-ended using only one of the two input branches. Switched
capacitor banks ( ) are also used at the outputs of the LNAs
to maintain optimal gain across the desired frequency ranges.
Continuous analog gain control is achieved by current steering,
controlled by a replica circuit that regulates the current of de-
vices M3C, M3D. A feedback loop generates voltage from
an externally applied voltage , so that the current through
devices M3Rn, M3Rp is proportional to variable transconduc-
tance . By programming , different slopes of the gain
versus control voltage can be set. Typical LNA gain and NF in
all bands is estimated at 25 dB and 2 dB, respectively, while IIP3
at maximum gain is 2 dBm.
To implement the wideband RSSI function, a logarithmic
amplifier is used, tapping the signal at the LNA outputs. The
pseudo-logarithmic, piecewise linear function is implemented
as a cascade of limiters with their outputs rectified and summed
together.
The RSSI is also used at power-up to fine-tune the LNA
output resonance at different carrier frequencies. By using an
RF switch, the LO signal is injected at the LNA output and an
algorithm which runs at the companion digital demodulator,
finds the optimal combination of the switched capacitor bank
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
that maximizes the RSSI indication. This is especially useful
for the VHF LNA where narrow tuning is used to filter out
potential interference at the third harmonic of the LO that
can be down-converted by the third harmonic of the mixer.
With this tuning the RF front-end is stabilized versus process
tolerances, power supply variations and temperature.
To achieve high linearity and low flicker noise, all RF
paths employ double-balanced current mode passive mixers
[Fig. 4(b)], which are commonly used in applications de-
manding high linearity. The mixers are followed by low-noise,
high linearity baseband programmable-gain transimpedance
amplifiers to convert the output current into voltage.
B. Phase-Locked Loop
The fractional-N synthesizer used for LO generation is
shown in Fig. 5. The 19-bit fractional part of the division ratio
is modulated by a third-order MASH modulator achieving
a frequency resolution of better than 50 Hz. The VCO covers
a range from 1.2 to 1.8 GHz using complementary cross-cou-
pled pairs and a MOS varactor for tuning. A switched varactor
bank provides the necessary tuning range. The loop filter used
is passive, third-order with programmable resistor values. The
charge-pump current is programmable and is automatically ad-
justed to keep the loop bandwidth constant despite the VCO gain
variation and process, temperature and power supply tolerances.
At channel-selection, a coarse tuning scheme is activated to
find the optimum varactor combination for the desired VCO
oscillating frequency. This is achieved by initially charging
the LPF at a DC voltage and allowing the PLL to operate in
closed-loop. By tracking the VCO control voltage with an ADC,
the tuning algorithm changes the varactor bank accordingly: if
the control voltage goes higher than a programmed threshold
a higher varactor setting is selected, if it goes lower a lower
varactor setting is selected. Each time the LPF is re-charged,
while the PLL is in open-loop state. The total lock time, in-
cluding coarse tuning, ranges from 90 to 120 s, depending on
the number of steps required during the binary varactor search.
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS
Fig. 6. Analog baseband path (single-ended equivalent, actual path is differential).
A number of on-chip low dropout (LDO) regulators are used
to isolate the PLL supply from noise coupling that can prove
detrimental to LO spectral purity. Hard switching blocks like,
i.e., the PFD and the prescaler, are treated by the quiet-the-
speaker technique, using a separate power line and are physi-
cally isolated in the layout implementation.
C. Analog Baseband
The detailed block diagram of the analog baseband section
is shown in Fig. 6. Following the current-mode passive I/Q
mixers, low-noise/high gain-bandwidth, current-to-voltage am-
plifiers are used (PGA1). Gain programmability is achieved by
using switched feedback resistors. The second programmable
gain block (PGA2) consists of three stages of resistive feedback
amplifiers. All gain stages use DC-servo loops. The output is
integrated on a sampling capacitor using an active RC filter
with a programmable pole. By using a transconductor that con-
verts the integrated output voltage to a current, a correction is
injected at the input of the gain stage that compensates for DC
offset. To enable fast initial acquisition of DC offset, a higher
frequency pole can be programmed during a training phase,
while during normal reception the pole can be programmed to a
lower frequency to avoid corrupting the data. If required by the
demodulator, a hold/servo switch enables the DC servo loop to
also operate in an open-loop mode after initial acquisition of
the DC offset.
The order and attenuation of the filters needed was deter-
mined by the S1, S2 blocking specifications for DVB-T/H.
These specifications call for a 3.8 MHz passband and 25/70 dB
attenuation at 5.25/13.25 MHz, respectively. To support dif-
ferent channel bandwidths required for multistandard operation,
from 8 MHz for DVB-T/H to 430 kHz for one-segment ISDB-T,
sixth-order Chebyschev low-pass filters are used with a pro-
grammable corner frequency from 100 kHz to 7 MHz.
1527
Fig. 7. Gate rupture after an ESD HBM 2 kV zap.
The filters are implemented using opamp-RC integrators in
leapfrog configuration with switched passive components.
An auto-calibration loop is enabled at power-up to tune the
filters to the desired , within 0.5% accuracy. The frac-
tional-N synthesizer provides the appropriate clock for an 8-bit
direct digital synthesis frequency generator that produces a tone
at the desired 3 dB, which is then applied to the inputs of
the filters and is compared with the filter output using an rms
detector. A digitally controlled loop adjusts the filter bandwidth
until the input attenuated by 3 dB equals the output. Even though
calibration is done at power-up, the variation of due to the
resistors temperature coefficient for the 30 C to 85 C range
was measured to be less than 2%, which does not affect system
measurements.
V. 65 NM PROCESS CONSIDERATIONS
Continuously shrinking CMOS geometries have a direct
benefit in silicon area and allow more complex systems to be
integrated on a single die. However, this comes at the cost
of increased design cycle and a multitude of issues involving
1528
Fig. 8. ESD scheme.
complex device models, accurate interconnect impedance
estimation/extraction, manufacturability and aging concerns.
Analog and RF functions may suffer as standard circuit
topologies are not directly transferable to nanometer scale
digitally oriented processes. The combination of reduced power
supply, high channel conductance, and low gate oxide break-
down voltage, along with the relatively high device threshold
to mitigate leakage current in off state, lead to small output
dynamic range in stacked-device topologies and difficulties in
meeting linearity requirements. To alleviate those concerns,
accurate device modelling, detailed RF tuning, and high quality
factor ( ) inductors and capacitors were used. In the analog
baseband path, the 2.5 nominal I/O supply was used along
with a mix of both thin and thick oxide devices. A well-ob-
served principle was to employ self-calibration techniques that
fine-tune the receiver blocks upon start-up, i.e., channel select
filters, thus eliminating any process parameter spread affecting
the system performance.
To avoid performance degradation due to gate leakage,
which is also significant in nanometer processes, standard
design practices were used: currents and not voltages were used
for biasing circuitry, bias currents were kept above a certain
threshold, and modest mirror ratios were used. Thin-oxide MOS
capacitors were avoided and fringe metal capacitors were ex-
tensively used. Induced lattice stress and nonuniformity issues
[e.g., relative size of active area (LOD), well proximity effect
(WPE)] that affect matched-device performance requirements
have been treated by proper device sizing, dummy insertion,
accurate layout geometry modelling, and optimization of local
floorplanning. More intense aging phenomena [e.g., hot carrier
injection (HCI), punchthrough, and negative bias temperature
instability (NBTI)] are detrimental to analog circuits and should
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
be taken into account during design and layout iterations. These
phenomena were handled by optimizing the per-device oper-
ating conditions in order not to stress it out of the combined
safe operating limits.
Efficient ESD protection, especially for RF devices, should
handle both the requirements for low input capacitance in order
not to degrade the receiver noise figure and protecting sensitive
thin-oxide devices with small oxide breakdown voltage [17],
[18]. The snapback effect in nanometer CMOS processes is
not effective enough to be used for ESD protection since the
snapback voltage of the MOS device is quite high and oxide
breakdown risk is prominent. This is due to the low resistivity
substrate that does not present enough voltage drop at the base
region of the parasitic BJT to forward bias the baseemitter
junction. The result of this behavior is seen in the failure
analysis microphotograph of Fig. 7, where the gate of an LNA
input device is severely ruptured after an HBM zap at 2 kV
due to inefficient capability of the ESD structure to discharge
fast enough, producing a high-voltage spike. Therefore, snap-
back-based protection circuits cannot carry enough current and
are limited only to secondary ESD protection. All critical ESD
paths were treated to present minimum impedance by using
multiple metal layer routing, provide fast clamping action with
adequate current capacity by careful design of the clamps, and
ensure uniform turn-on of the protecting devices by properly
symmetrical layout. Especially for the L-band LNA input, the
ESD protection network was measured to degrade the NF by
an affordable 0.10.2 dB, while for the VHF and UHF LNAs,
no degradation was observed.
Some of the measures taken are shown in Fig. 8 and include
the following. i) Universal low resistance ESD ground path for
fast return of the pulse charge. This way the voltage built-up
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS 1529

TABLE I
MEASURED PERFORMANCE SUMMARY, TYPICAL CONDITIONS

is kept low enough to protect the gate oxide. ii) Power supply
decoupling capacitors have been extensively used to also keep
the voltage build-up low. iii) A series poly resistance has been
placed in non-RF I/Os in order to provide isolation of the ac-
tive circuits during an ESD event. iv) Secondary protection has
been used when signals are crossing between power domains
and it is physically placed close to the sensitive devices. v) It
is important to guarantee a low-resistance discharge path for
cross-coupled power domain ESD events that will not require
a voltage level higher than the oxide breakdown for the power
clamps and the in-series diodes to conduct. vi) When a sepa-
rate digital GND is used, this is connected to global ESD GND
via a pair of back-to-back diodes for switching noise isolation
purposes. Finally, vii) the specific package model was used to
evaluate the ESD discharge characteristics and locate any weak
points in the implemented scheme.
VI. MEASUREMENTS
The chip is implemented in a standard digital 65 nm CMOS
and occupies a total area of less than 7 mm . A die micropho-
tograph is shown in Fig. 9 and typical measurement results are
summarized in Table I. Performance has been characterized in
all bands and modes, verifying multistandard, multiband capa-
bility. In addition to analog/RF measurements, the tuner has
also been extensively characterized for the full MBRAI 2.0 spec
using a DVB-T/H demodulator implemented in FPGA. Both
single-ended and differential operation was verified, showing
essentially the same performance in NF, linearity and related
system-level measurements.
Plots of NF and gain at all three bands in differential mode
are shown in Fig. 10. In all bands, NF is less than 3.5 dB,
which includes external balun and PCB losses. A slight in-
crease of NF of 0.5/0.2 dB at maximum gain was observed
in ISDB-T/T-DMB modes respectively, where the baseband
opamp-RC filters use larger resistors and the lower signal band-
width increases the contribution of flicker noise to the overall
SNR. Measurements over a temperature range of 30 C to
85 C and power supply corners show NF degradation of
less than 1 dB, while a gain degradation of 4 dB is tolerated
due to the excess gain budgeted. No significant degradation of
the NF was observed due to stringent ESD requirements and
initial tests proved no damage to the sensitive RF ports up to
2 kV HBM stress. NF performance was also verified by system
sensitivity measurements. In Fig. 11, sensitivity for QPSK-1/2
and 64-QAM-3/4 DVB-T modes is plotted over the full UHF
range, indicating compliance with MBRAI2.0 with at least
1.5 dB margin. Sensitivity at VHF and L-band also exceeds
98 dBm in the QPSK-1/2 DVB-T mode.
IIP2 and IIP3 requirements are met with significant margin,
as indicated by system measurements. At a 5 dB backoff
1530
Fig. 9. Die photo.
Fig. 10. Gain, NF versus frequency.
from maximum RF gain in UHF, where the RSSI-AGC loop
converges with typical RSSI target voltage for the DVB-T L1
blocking spec, IIP3 is 2 dBm while NF is 4.5 dB. Similarly,
at a 10 dB RF backoff, IIP2 and NF at UHF are 40 dBm and
5.5 dB, respectively. Linearity is also confirmed by DVB-T
blocking (S1S2) and intermodulation (L1L3) system mea-
surements, shown in Table I. In all bands, the stringent L1 spec
is met with more than 3 dB margin, while for S2, the margin is
at least 4 dB.
A typical synthesizer phase noise plot is shown in Fig. 12,
while Fig. 13 shows the integrated phase error (after LO di-
vider) and spot phase noise at 100 kHz (before LO divider) for
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
Fig. 11. Sensitivity in DVB-T mode, UHF, 2 210 Vitterbi BER.
the 474858 MHz UHF range. The PLL locking range has been
measured under all process, temperature, and supply variation
and exceeds the required 1.21.8 GHz range. Low integrated
phase noise error and accurate filter matching help achieve an
SNDR1 in excess of 35 dB, which is needed for robust mo-
bile operation. In Fig. 14, the SNDR is measured by calcula-
tion of the constellation error by the digital demodulator for dif-
ferent input powers and with AGC loops running in real-time.
In both plots (channel UHF 45 and channel VHF 8), the peak
SNR exceeds 37 dB, while for a significant input power range
SNR exceeds 30 dB. Initially SNDR in increases linearly, as it
is dominated by AWGN and then it reaches a maximum value
as it is limited by phase noise, linearity and frequency-depen-
dent I/Q mismatch. As signal increases further and LNA gain
is decreased, due to the steering technique used, the current
in the LNA main branch is reduced, which causes linearity to
drop thus dominating the overall SNDR. Fig. 15 shows a plot
of a 64-QAM 3/4 constellation achieving a 35 dB SNR at UHF
channel 45.
In continuous DVB-T mode, the tuner consumes less than
140 mW in all bands, split between the 1.2 and 2.5 V nominal
supplies, while lower channel bandwidth and linearity require-
ments help reduce power consumption in 1-segment ISDB-T
and T-DMB modes.
VII. CONCLUSION
As a first step towards a multistandard mobile TV SoC,
a multiband, multistandard direct-conversion tuner has been
implemented on a standard digital 65 nm CMOS process.
Nanometer CMOS implementation posed several hurdles,
1To be precise, the SNDR measured here is actually error vector magnitude
(EVM), which is the overall constellation error as measured by the demodulator
and includes all imperfections such as AWGN, phase noise, ADC quantization
noise, sampling jitter, etc.
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS 1531

Fig. 12. Typical phase noise plot at synthesizer output.

Fig. 15. 64-QAM constellation with 35 dB SNR.

ACKNOWLEDGMENT
The authors acknowledge M. Margaras, P. Merakos, and
K. Tsilipanos for their support in board design and testing.

Fig. 13. Integrated phase error versus frequency.
Fig. 14. SNR versus input power at UHF (Ch. 45), VHF (Ch. 9).
including severe ESD requirements, which were overcome
by careful implementation and by using the ample digital
processing power that the process provides. As indicated by
sensitivity, blocking and intermodulation measurements for
DVB-T/H, the tuner performs better than state-of-the-art imple-
mentations at less than half the power consumption [10][12].
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Iason Vassiliou (S94M99) received the Diploma
in electrical engineering from the National Technical
University of Athens, Greece, in 1991, and the M.Sc.
and Ph.D. degrees in electrical engineering from
the University of California at Berkeley in 1995 and
1999, respectively.
He currently holds the position of Project Man-
agerSenior Principal Engineer at Broadcom,
Athens, Greece. From 2001 to 2005, he was Chief
Technologist with Athena Semiconductors, a startup
specializing in wireless solutions. He has authored
several papers on wireless transceivers and analog CAD.
Kostis Vavelidis (M99) received the Diploma and
Ph.D. degree in electrical engineering from the
National Technical University of Athens, Greece, in
1991 and 1996, respectively.
From 1997 to 2001, he worked as an RF and
Mixed-Signal IC Design Consultant for several
semiconductor companies. In 2001, he co-founded
Hellenic Semiconductor Applications and in 2002,
Athena Semiconductors, which was acquired by
Broadcom in 2005. He is currently Senior Manager
of Engineering at Broadcom, working on wireless
radio development and products for mobile digital TV and cellular.
Nikos Haralabidis (M97SM07) received the
Physics degree from the University of Thessaloniki,
Greece, and the Ph.D. degree from the National
Technical University of Athens, Greece.
From 1997 to 2001, he was with the Institute of
Microelectronics, NCSR Demokritos, Athens,
Greece, as a Postdoctoral Scientist and Lecturer.
In 2001, he co-founded Hellenic Semiconductor
Applications, which became part of Athena Semi-
conductors and was acquired by Broadcom in 2005,
where he now holds the position of Senior Principal
Scientist. He has contributed 45 papers in journals and conference proceedings.
Aristeidis Kyranas (S95M03) was born in 1972
in Athens, Greece. He received the Diploma and the
Ph.D. degree, both in electrical engineering, from the
National Technical University of Athens, Greece, in
1995 and 2002, respectively.
Since 1995, he has been working in the area of
analog IC design. He currently holds the position
of Senior Staff Design Scientist with Broadcom,
Greece. His research interests are in the area of
low-power RF IC design.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
Ioannis Kokolakis received the Diploma degree
from the Department of Electrical and Computer En-
gineering, Democritus University, Thrace, Greece,
in 1993, where he is currently pursuing the Ph.D.
degree.
Since 2002, he has been with Athena Semiconduc-
tors, which is now Broadcom, in Greece. In his cur-
rent position, he is a Senior IC Design Engineer re-
sponsible for the design of CMOS frequency synthe-
sizers for WLAN, cellular, and digital TV standards.
Stamatis Bouras received the Diploma and Ph.D.
degrees in electrical engineering from the National
Technical University of Athens, Athens, Greece, in
1990 and 1996, respectively.
He was a cofounder of Helic S.A and Hellenic
Semiconductor Applications S.A. He worked as a
Technical Consultant at Theta S.A. and as Technical
Manager at Athena Semiconductor S.A. Since
2005, he has been an Engineering Manager with
Broadcom, Athens, Greece.
George Kamoulakos received the B.S. degree
from the National Technical University of Athens
(NTUA), Athens, Greece, and the Ph.D. degree from
the the Kapodistrian University of Athens, in 1996
and 2003, respectively.
Previously, he has been a Senior Staff Design Sci-
entist with Broadcom, a Senior RFIC Engineer with
AthenaSemi, an IC Designer with Helic, and a Ju-
nior Engineer with ISD. He is an author or co-au-
thor of many papers in scientific periodicals and con-
ferences. He is a co-founder of Elxys Innovations,
Marousi, Athens, Greece.
Charalampos Kapnistis (M01) received the Ph.D.
degree from the National Technical University of
Athens, Athens, Greece, in 2002.
From 1996 to 1999, he was an R&D Engineer
with the NCSR Demokritos, Athens, designing
low-power CMOS analog circuits for radiation
detectors. Since 2001, he has been with Athena
Semiconductors, which is now Broadcom, in
Greece. He is currently a Principal IC Design En-
gineer responsible for several RF circuits including
transmit modulators, power amplifiers, and high-fre-
quency RSSI.
Spyros Kavadias (S91M97) received the B.Sc.
and Ph.D. degrees from the Physics Department,
University of Athens, Athens, Greece, in 1990 and
1995, respectively.
From 1997 to 2001, he was with IMEC, Leuven,
Belgium. In 2001, he joined Athena Semiconductor,
which was acquired by Broadcom in 2005. His inter-
ests include the design of CMOS analog circuits for
wireless transceivers.
VASSILIOU et al.: A 65 NM CMOS MULTISTANDARD, MULTIBAND TV TUNER FOR MOBILE AND MULTIMEDIA APPLICATIONS
Nikos Kanakaris received the M.Sc. degree from
the Department of Electrical and Electronic Engi-
neering, Imperial College London, London, U.K.,
and the Diploma degree from the National Technical
University of Athens (NTUA).
He was an RF Design Engineer with Oxtek,
Atmel, and Helic S.A. He joined Athena Semicon-
ductors (later acquired by Broadcom Corp.) in 2004.
He is currently with Broadcom, Athens, Greece, as
a Senior Staff Design Engineer.
wireless telecommunication systems.
Emmanouil Metaxakis received the Dipl. Eng. and
Ph.D. degrees in electrical engineering from the Uni-
versity of Patras, Greece, in 1994 and 2003, respec-
tively.
He worked as a Consultant with Renaissance
Wireless, Senior Staff Design Scientist with
Broadcom, Senior RFIC Engineer WITH Athena
Semiconductors, and RFIC and Systems Engineer
with Theta Microelectronics. He currently holds
the position of CEO at Elxys Innovations, Marousi,
Athens, Greece.
1533
Christos Kokozidis received the Diploma in
Computer Engineering and Informatics from the
University of Patras, Greece, in 1998, and the M.Sc.
degree in micrelectronics from the Informatics and
Telecommunications Department, University of
Athens, Greece, in 2000.
In 2002, he joined Athena Semiconductor, which
was acquired by Broadcom in 2005. He currently
holds the position of Staff IC Design Engineer
with Broadcom Hellas, where his interests include
the design of analog and mixed-signal circuits for
Hamed Peyravi received the B.S. degree from Shiraz
University, Shiraz, Iran, in 1995, and the M.S. degree
from Urmia University, Urmia, Iran, in 1998, both in
electrical engineering.
He was with Urmia Semiconductors as an IC De-
sign Engineer, for two years. In 2002, he joined Helic
S.A., where he designed various circuits for BiCMOS
transceivers. In 2005, he joined Athena Semiconduc-
tors which was acquired by Broadcom, where he has
been responsible for analog and RF circuit design.