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Proteo Digital
DESCRIO BSICA:
Hardware:
Circuitos de Entrada (TCs e Filtros)
Aquisio de Dados (Converso A/D)
Configurao (Ajustes)
Unidade Central de Processamento
(Microprocessador, Memrias e Perifricos)
Circuitos de Sada (Atuaes e Indicadores)
Software
CONTROLES MICROPROCESSADOS
(Religadores)
RELS MICROPROCESSADOS
(Disjuntores, painis e fiaes)
CONTROLES MICROPROCESSADOS
(Religadores)
FXB - Cooper
Form4C - Cooper
POLARR - Whipp & Bourne - Relig. GVR
PANACEA - Whipp & Bourne
CAPM4 - NU-LEC
Ajustes de Fase:
Mnimo trip
Curva de fase: normal ou modificada
Ajustes de Neutro:
Mnimo trip
Curva de Neutro: normal ou modificada
Prof Jlio Xavier 7
PROTEO E COORDENAO DE REDES AREAS DE DISTRIBUIO
Religadores e Rels Microprocessados
CURVAS DE PROTEO
Inseridas na memria no voltil dos controles
Original ( IEC, ANSI, curvas clssicas)
Modificada
Mtodos de modificao da curva
Multiplicador de tempo
Retardo adicional
MRT - minimum response time
High current trip (instantneo)
Retardo do instantneo
Prof Jlio Xavier 8
CONTROLES MICROPROCESSADOS
(Religadores)
Ajustes Suplementares:
1-SHOT
CONTROLES MICROPROCESSADOS
(Graduaes exemplos)
FXB - Cooper
Form4C - Cooper
POLARR - Whipp & Bourne - Relig. GVR
PANACEA - Whipp & Bourne (software de ajuda)
CAPM4 - NU-LEC
RELS MICROPROCESSADOS
Proteo
RELS MICROPROCESSADOS
PROTEO DE ALIMENTADORES
Multiplicidade de ajustes
funo 50: IOC de fase: pickup e retardo
funo 51: TOC de fase: mnimo trip e curva
funo 50N: IOC de neutro: pickup e retardo
funo 51N: TOC de neutro: min. trip e curva
RELS MICROPROCESSADOS
PROTEO DE ALIMENTADORES
RELS MICROPROCESSADOS
PROTEO DE ALIMENTADORES
Funo religamento - 79:
nmero de religamentos
rearme de fase
rearme de neutro
tempo de bloqueio religamento para fechamento
manual
superviso da tenso de referncia
RELS MICROPROCESSADOS
PROTEO DE ALIMENTADORES
Funo break-failure - 62BF: YES/NO
Funes adicionais:
Medio
Registro de eventos
Oscilografia
Relao de TC: ampres primrios
RELS MICROPROCESSADOS
PROTEO DE ALIMENTADORES
RELS UTILIZADOS COELBA:
SPAC - ABB (SE CANDEAL)
SPAJ - 140 C - ABB
PL150 - TEAM-ARTECHE
IRD - ZIV
SEL - 351A - SCHWEITZER
Residual Ground Inst./Def.-Time Overcurrent Elements (See Figures 3.10 and 3.11)
(Number of residual ground element pickup settings dependent on preceding enable setting E50G = 1 - 6)
Pickup (OFF, 0.25 - 100.00 A {5 A nom.}, 0.05 - 20.00 A {1 A nom.}) 50G1P = 18 (2160)
Pickup (OFF, 0.25 - 100.00 A {5 A nom.}, 0.05 - 20.00 A {1 A nom.}) 50G2P = 34 (4080)
(Number of residual ground element time delay settings dependent on preceding enable setting E50G = 1 - 6; all four time delay settings are enabled if
E50G 4)
Time delay (0.00 - 16000.00 cycles in 0.25-cycle steps) 67G1D = 3
Time delay (0.00 - 16000.00 cycles in 0.25-cycle steps) 67G2D = 0
Time delay (0.00 - 16000.00 cycles in 0.25-cycle steps) 67G3D =
Time delay (0.00 - 16000.00 cycles in 0.25-cycle steps) 67G4D =
Curve (U1 - U5, C1 - C5; see Figures 9.1 through 9.10) 51PC = C3
Time-Dial (0.50 - 15.00 for curves U1-U5, 0.05 - 1.00 for curves C1-C5) 51PTD = 0.1
Pickup (OFF, 0.50 - 16.00 A {5 A nom.}, 0.10 - 3.20 A {1 A nom.}) 51GP = 0.5
Curve (U1 - U5, C1 - C5; see Figures 9.1 through 9.10) 51GC = C3
Time-Dial (0.50 - 15.00 for curves U1-U5, 0.05 - 1.00 for curves C1-C5) 51GTD = 0.6
Open interval 2 time (0.00 - 999999.00 cycles in 0.25-cycle steps) 79OI2 = 900 cycles
Open interval 3 time (0.00 - 999999.00 cycles in 0.25-cycle steps) 79OI3 = 0.00
Open interval 4 time (0.00 - 999999.00 cycles in 0.25-cycle steps) 79OI4 = 0.00
Reset time from reclose cycle (0.00 - 999999.00 cycles in 0.25-cycle steps) 79RSD = 1800 cycles
Reset time from lockout (0.00 - 999999.00 cycles in 0.25-cycle steps) 79RSLD = 300 cycles
Reclose supervision time limit (OFF, 0.00 - 999999.00 cycles in 0.25-cycle steps) (set 79CLSD = 0.00 for most 79CLSD = 0.00
applications; see Figure 6.2)
Other Settings
Minimum trip duration time (4.00 - 16000.00 cycles in 0.25-cycle steps) TDURD = 9 cycles
(see Figure 5.1)
Close failure time delay (OFF, 0.00-16000.00 cycles in 0.25-cycle steps) CFD = 60 cycles
(see Figure 6.1)
Three-pole open time delay (0.00 - 60.00 cycles in 0.25-cycle steps) 3POD = 1,5 cycle
(usually set for no more than a cycle; see Figure 5.3)
Load detection phase pickup (OFF, 0.25 - 100.00A{5 A nom.}, 50LP = 0,25A
0.05 - 20.00 A {1 A nom.}) (see Figure 5.3)
Trip Logic Equations (See Figure 5.1) TR = 51PT+51GT+67P1T + 67G1T + 67P2T+ 67G2T
Drive-to-lockout 79DTL =
Fault indication [used in INST, A, B, and C target logic (see Table 5.1); used also to FAULT = 51P + 51G
suspend demand metering updating and peak recording and block max./min. metering
(see Demand Metering and Maximum/Minimum Metering in Section 8)]
Power System Configuration and Date Format (See Settings Explanations in Section 9)
REGISTRO DE EVENTOS:
OSCILOGRAFIA (exemplo):
REGISTRO: 12 A 60 CICLOS
PREFAULT : 4 CICLOS
FAULT: DISTURBANCE PERIOD
TRIGGER:
TRIP
SIGNAL INTERNAL
EXTERNAL CONTACT