RFG50N06, RFP50N06, RF1S50N06SM

Data Sheet January 2002

50A, 60V, 0.022 Ohm, N-Channel Power Features

MOSFETs 50A, 60V
These N-Channel power MOSFETs are manufactured using
rDS(ON) = 0.022
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives Temperature Compensating PSPICE Model
optimum utilization of silicon, resulting in outstanding Peak Current vs Pulse Width Curve
performance. They were designed for use in applications
such as switching regulators, switching converters, motor UIS Rating Curve
drivers, and relay drivers. These transistors can be operated 175oC Operating Temperature
directly from integrated circuits.
Symbol
Formerly developmental type TA49018.
D

Ordering Information
PART NUMBER PACKAGE BRAND G
RFG50N06 TO-247 RFG50N06
S
RFP50N06 TO-220AB RFP50N06

RF1S50N06SM TO-263AB F1S50N06

NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06SM9A.

Packaging
JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE
DRAIN SOURCE
GATE DRAIN
DRAIN GATE
DRAIN
(BOTTOM (FLANGE)
SIDE METAL)

JEDEC TO-263AB

GATE DRAIN
(FLANGE)
SOURCE

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

RFG50N06, RFP50N06
RF1S50N06SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS 20 V
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID 50 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM (Figure 5)
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS (Figure 6)
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 131 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.877 W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 260 oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 150oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V (Figure 11) 60 - - V
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V
Zero Gate Voltage Drain Current IDSS VDS = 60V, TC = 25oC - - 1 A
VGS = 0V
TC = 150oC - - 50 A
Gate to Source Leakage Current IGSS VGS = 20V - - 100 nA
Drain to Source On Resistance rDS(ON) ID = 50A, VGS = 10V (Figures 9) - - 0.022
Turn-On Time tON VDD = 30V, ID = 50A - - 95 ns
RL = 0.6, VGS = 10V
Turn-On Delay Time td(ON) - 12 - ns
RGS = 3.6
Rise Time tr (Figure 13) - 55 - ns
Turn-Off Delay Time td(OFF) - 37 - ns
Fall Time tf - 13 - ns
Turn-Off Time tOFF - - 75 ns
Total Gate Charge Qg(TOT) VGS = 0 to 20V VDD = 48V, ID = 50A, - 125 150 nC
RL = 0.96
Gate Charge at 10V Qg(10) VGS = 0 to 10V - 67 80 nC
Ig(REF) = 1.45mA
Threshold Gate Charge Qg(TH) VGS = 0 to 2V (Figure 13) - 3.7 4.5 nC
Input Capacitance CISS VDS = 25V, VGS = 0V - 2020 - pF
f = 1MHz
Output Capacitance COSS - 600 - pF
(Figure 12)
Reverse Transfer Capacitance CRSS - 200 - pF
Thermal Resistance Junction to Case RJC (Figure 3) - - 1.14 oC/W

Thermal Resistance Junction to Ambient RJA TO-247 - - 30 oC/W

TO-220, TO-263 - - 62 oC/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 50A - - 1.5 V

Reverse Recovery Time trr ISD = 50A, dISD/dt = 100A/s - - 125 ns

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves Unless Otherwise Specified

1.2 60
POWER DISSIPATION MULTIPLIER

1.0 50

ID , DRAIN CURRENT (A)

0.8 40

0.6 30

0.4 20

0.2 10

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

0.5
THERMAL IMPEDANCE
ZJC, NORMALIZED

0.2

0.1 0.1 PDM

0.05
t1
0.02 t2
0.01 NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZJC x RJC + TC
0.01 -5
10 10-4 10-3 10-2 10-1 100 101
t1 , RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

400 103
TJ = MAX RATED
FOR TEMPERATURES ABOVE 25oC
SINGLE PULSE
TC = 25oC DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
IDM , PEAK CURRENT (A)

100
ID , DRAIN CURRENT (A)

VGS = 20V 175 T C

100s I = I 25 ------------------------
150

1ms
VGS = 10V
10
OPERATION IN THIS TC = 25oC
AREA MAY BE
10ms 102
LIMITED BY rDS(ON) TRANSCONDUCTANCE
100ms MAY LIMIT CURRENT
DC IN THIS REGION
VDSS(MAX) = 60V
1 40
1 10 100 10-3 10-2 10-1 100 101 102 103 104
VDS , DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (ms)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves Unless Otherwise Specified (Continued)

300 125
PULSE DURATION = 80s
VGS = 10V DUTY CYCLE = 0.5% MAX
TC = 25oC
IAS, AVALANCHE CURRENT (A)

100 100 VGS = 8V

ID , DRAIN CURRENT (A)

STARTING TJ = 25oC
VGS = 7V
75

10 STARTING TJ = 150oC 50
VGS = 6V

If R = 0 VGS = 5V
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) 25

If R 0 VGS = 4V
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
1 0
0.01 0.1 1 10 0 1.5 3.0 4.5 6.0 7.5
tAV, TIME IN AVALANCHE (ms) VDS , DRAIN TO SOURCE VOLTAGE (V)

NOTE: Refer to Fairchild Application Notes 9321 and 9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

125 2.5
PULSE DURATION = 80s -55oC 25oC PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDD = 15V NORMALIZED DRAIN TO SOURCE VGS = 10V, ID = 50A
ID, DRAIN CURRENT (A)

100 2.0
175oC
ON RESISTANCE

75 1.5

50 1.0

25 0.5

0 0
0 1 2 3 4 5 6 7 8 9 10 -80 -40 0 40 80 120 160 200
VGS , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

2.0 2.0
VGS = VDS, ID = 250A ID = 250A
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE

1.5 1.5
THRESHOLD VOLTAGE
NORMALIZED GATE

1.0 1.0

0.5 0.5

0 0
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

Typical Performance Curves Unless Otherwise Specified (Continued)

4000 60 10
VGS = 0V, f = 1MHz

VDS , DRAIN TO SOURCE VOLTAGE (V)

VGS , GATE TO SOURCE VOLTAGE (V)

CISS = CGS + CGD VDD = BVDSS VDD = BVDSS
CRSS = CGD
COSS = CDS + CGD 45 7.5
C, CAPACITANCE (pF)

3000

CISS

2000 30 5.0
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
COSS 0.25 BVDSS 0.25 BVDSS
1000 15 2.5
RL = 1.2
CRSS Ig(REF) = 1.45mA
VGS = 10V
0 0 0
Ig(REF) Ig(REF)
0 5 10 15 20 25 t, TIME (s)
20 80
VDS , DRAIN TO SOURCE VOLTAGE (V) Ig(ACT) Ig(ACT)

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01
tAV

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)
VDS
tr tf
VDS
90% 90%
RL
VGS

+ 10% 10%
VDD 0
-
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

Test Circuits and Waveforms (Continued)

VDS
RL VDD Qg(TOT)

VDS
VGS = 20V

VGS Qg(10)
+
VDD
VGS VGS = 10V
-

DUT VGS = 2V
Ig(REF) 0
Qg(TH)

Ig(REF)
0

FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

 RFG50N06, RFP50N06, RF1S50N06SM

PSPICE Electrical Model

.SUBCKT RFP50N06 2 1 3

REV 2/22/93

*NOM TEMP = 25oC

CA 12 8 3.68e-9
CB 15 14 3.625e-9
CIN 6 8 1.98e-9
5 DRAIN
DBODY 7 5 DBDMOD 10 2
DBREAK 5 11DBKMOD DPLCAP LDRAIN
- RDRAIN
DPLCAP 10 5 DPLCAPMOD 6 DBREAK
ESG
8 16
+ VTO
EBREAK 11 7 17 18 64.59 - DBODY

+
EVTO MOS2
EDS 14 8 5 8 1 GATE 21
-

+
EGS 13 8 6 8 1 9 20 18 6 11 +
1 MOS1
ESG 6 10 6 8 1 8 17
LGATE RGATE EBREAK
18
EVTO 20 6 18 8 1 RIN CIN -
RSOURCE 7 LSOURCE
IT 8 17 1 8
3
S1A S2A SOURCE
LDRAIN 2 5 1e-9 12 15 RBREAK
13 14 17 18
LGATE 1 9 5.65e-9 8 13
LSOURCE 3 7 4.13e-9
S1B S2B RVTO
13
MOS1 16 6 8 8 MOSMOD M=0.99 CA CB IT 19
MOS2 16 21 8 8 MOSMOD M=0.01 + + 14 -
5
EGS 6 EDS 8 VBAT
- 8 - +
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 0.690
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 12e-3
RVTO 18 19 RVTOMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 8 19 DC 1
VTO 21 6 0.678

.MODEL DBDMOD D (IS=9.85e-13 RS=4.91e-3 TRS1=2.07e-3 TRS2=2.51e-7 CJO=2.05e-9 TT=4.33e-8)

.MODEL DBKMOD D (RS=1.98e-1 TRS1=2.35E-4 TRS2=-3.83e-6)
.MODEL DPLCAPMOD D (CJO=1.42e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.65 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.23e-3 TC2=-2.34e-7)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.49e-5)
.MODEL RVTOMOD RES (TC1=-5.03e-3 TC2=-5.16e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.75 VOFF=-2.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-6.75)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.7 VOFF=2.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.3 VOFF=-2.7)

.ENDS

NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authors, William J. Hepp and C. Frank Wheatley.

2002 Fairchild Semiconductor Corporation RFG50N06, RFP50N06, RF1S50N06SM Rev. B

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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4