J Electron Test (2015) 31:207215
DOI 10.1007/s10836-015-5515-7
A Shift-Register Based BIST Architecture for FPGA Global
Interconnect Testing and Diagnosis
Igor Gadelha Pereira Leonardo Alves Dias
Cleonilson Protasio de Souza
Received: 8 April 2014 / Accepted: 11 February 2015 / Published online: 13 March 2015
Springer Science+Business Media New York 2015
Abstract This paper describes the implementation of a
shift-register based Built-In Self-Test (BIST) architecture
for FPGA global interconnection resources testing. Through
this, it is possible to configure FPGA resources that need
to be tested in order to obtain high reliability FPGA-based
systems. The proposed BIST approach takes advantage of
FPGA low-level resources in order to generate cyclic test
patterns, analyse testing response and store test results
in a simple way. Additionally, the same BIST configura-
tion set is capable of diagnosing the tested interconnection
resources with no additional configurations thereby reduc-
ing time requirements. This paper presents the proposed
BIST architecture and its diagnosis scheme, its implemen-
tation on a Xilinx FPGA, and experimental results.
Keywords Built-in self-test Field-programmable gate
array Global interconnection resource testing FPGA
testing and diagnosis
1 Introduction
Field-Programmable Gate Arrays (FPGAs) are silicon
devices that can be (re)programmed in the field to imple-
ment any user-defined functions and are mainly applied
Responsible Editor: V. D. Agrawal
I. G. Pereira L. A. Dias C. P. de Souza ()
Departement of Electrical Engineering, Federal University
of Paraba - UFPB, Joao Pessoa, Paraba, Brazil
e-mail: protasio@cear.ufpb.br
I. G. Pereira
e-mail: igor.pereira@cear.ufpb.br
L. A. Dias
e-mail: leonardo.dias@cear.ufpb.br
to ASIC prototyping and for the designing of high relia-
bility systems. A typical FPGA architecture is composed
of repeated and regular configurable logic blocks (CLBs),
input/output blocks (IOBs), and programmable interconnec-
tion resources (IRs) interconnecting all its internal elements
[7, 10, 12], as shown in Fig. 1.
In order to guarantee proper and reliable operation,
FPGAs need to be tested, that is, its internal elements
should be verified to find out if they are fault-free before
programming the final application.
It is known that the main feature of FPGAs, namely
their reprogrammability, makes them more difficult to test
than non-reprogrammable devices [2, 9]. However, it also
makes it feasible for them to be configured with built-in
self-test (BIST) logic in order to test their internal resources.
A basic BIST scheme is composed mainly of a test pat-
tern generator (TPG), an output response analyser (ORA)
and a block under test (BUT) for CLB/IOB testing or inter-
connection under test (so called IUT) for programmable
interconnection testing [8, 11, 12]. It is important to note
that using the BIST approach testability is achieved without
any overhead, since the BIST configurations are removed
when the FPGA is reconfigured to its normal operation
[8, 12].
A complete FPGA test is composed of logic testing
(CLBs, IOBs and other embedded logics) and testing of
interconnection resources (IRs). The FPGA IRs consist
of wire segments and switch matrices (SMs) made up of
programmable interconnect points (PIPs) [10] that are con-
trolled by configuration memory bits, which are the set of
all programming bits that establishes a configuration which
determines the function of the device [12].
Testing of FPGA IR is very important because the inter-
connection resources of FPGAs comprises almost 90 % of
the total area of FPGAs [1, 5, 6, 10, 15]. Indeed, IR has a
208
Fig. 1 A typical FPGA
architecture
higher fault probability since they require an area larger than
other FPGA resources [15]. In this way, IR testing becomes
one of the most important procedures of FPGA testing. This
paper focuses on IR testing.
IR testing involves studying the FPGA IR architecture
in order to propose a specific test scheme. Next, test con-
figurations based on the test scheme are derived and the
set of all test configurations must meet the requirements of
both high IR coverage and reasonable small number of test
configurations since the total test time is dominated by this
[10].
Dixon [4] describes the most common strategies for
BIST-based interconnection testing, simulation results and
the way these strategies apply test vectors to IUTs. Of these
strategies, the most relevant one is the cross-coupled par-
ity dual counter. Based on this strategy, the cross-coupled
parity routing BIST architecture proposed in [15] is capable
of testing 6 IUTs per configuration and a total of 51 test
configurations are needed to test all of the global routing
resources in a case study considering Xilinx Virtex-4 series
FPGAs where its main limitation is the use of feedback lines
for response analysing that limits the number of IUTs per
configuration (details in next section).
Since, in general, the main goal of any interconnection
testing is to minimize the number of test configurations by
maximizing the number of IUTs for any given test configu-
ration, this paper presents a BIST approach in order to test
global routing resources in FPGA using the total capability
of the look-up tables (LUTs), that is, using all their inputs
with no feedback lines.
The CLBs of most of the FPGA families can be config-
ured as shift-register chain either in a direct way, which is
the case of all the families from Xilinx, or in an indirect
J Electron Test (2015) 31:207215
way, which is the case of some families from Altera. An
interesting feature which is specific to Xilinx FPGAs is that
the LUTs of some groups of CLBs (called SLICEM) can
be configured as an n-bit shift register, where n could be
16 or 32. For Altera FPGAs, it is supported to configure
shift-register chains using logic elements (LEs) combina-
tion. This is the case of high-end FPGAs like Stratix IV,
Stratix III, Stratix II, Stratix GX, Stratix; mid-end FPGAs
like Arria II, Arria GX; and low-end FPGAs like Max10,
Cyclone IV, Cyclone III, Cylone II, Cyclone. Other FPGA
manufactures also support this characteristic.
The BIST scheme proposed in this paper is implemented
as a CLB-based TPG/ORA combination where some CLBs
are configured as combinational ORA and others in the
same group are configured as shift-register based TPG using
the shift-register chain featured in the FPGA. Taking this
into consideration, up to 8 IUTs per configuration can be
tested at once, resulting in the reduction of the number of
test configurations.
This paper describes the proposed BIST architecture in
Section 2. Section 3 shows an implementation of the pro-
posed BIST in a Spartan 3E FPGA. Section 4 describes a
BIST based diagnosis to locate the faulty wire based on test
results. The tools used are shown in Section 5 followed by
experimental results in Section 6. Conclusions are given in
Section 7.
2 Proposed BIST Architecture
In this paper, both stuck-at fault model and bridge fault
model for fault modelling in FPGA interconnections have
been used. The stuck-at fault model considers that faulty
J Electron Test (2015) 31:207215
b
Fig. 2 a The cross-coupled parity routing BIST. b Compact view
interconnections are stuck at logical 1 or 0 and bridge fault
model assumes that shorted wires and open wires may occur
between interconnections. PIP faults, such as PIP stuck-
close (stuck-on) and stuck-open (stuck-off), are considered
in interconnect testing as they are equivalent to stuck-at
faults in the configuration memory bits [15]. This paper
addresses the aforementioned fault models and does not
consider delay faults.
As described in the last section, the most relevant BIST
for FPGA interconnection testing is the cross-coupled parity
Fig. 3 Proposed general BIST architecture
209
a b
Fig. 4 a Altera shift register chain. b Xilinx SLICEM LUT as 16-bit
shift register
dual counter proposed in [15] where the BIST architecture
is implemented in each CLB of the FPGA which, in turn,
consists of four slices where each slice contains two flip-
flops and two 4-input LUTs. Each slice is configured either
as an odd parity TPG (Odd TPG), an even parity TPG (Even
TPG), an odd parity ORA (Odd ORA) or an even parity
ORA (Even ORA), as shown in Fig. 2a or in Fig. 2b in
a compact view. The reason for testing only 6 IUTs per
Fig. 5 Arrangement of slices within the Xilinx CLB
210
Fig. 6 Spartan 3E global
routing lines [13]
configuration is that each ORA uses a feedback line which
limits the input number of the corresponding LUT to 3.
In this paper, a BIST architecture for interconnection
testing is proposed which is composed of a TPG based
on shift register chain (featured in most FPGA families)
and of a combinational-logic based ORA, as shown in
Fig. 3. The proposed BIST is able to test up to 8 IUTs at
once, since there is no feedback line in the ORA scheme
as shown in [15]. Additionally, a cyclic test pattern (for
instance, 0xAAAA... = 101010101010...) has been cho-
sen as shift-register TPG seed in conjunction with a specific
combination logic for ORA (based only on XOR operation)
in order to maintain the cyclical sequence generation when
Fig. 7 Proposed BIST
architecture
J Electron Test (2015) 31:207215
the ORA output is feedback to shift-register TPG provided
that no interconnection faults have occurred. As explained
later, this proposal is capable of testing and diagnosing
faulty interconnections.
As described, the main ideas of the proposed BIST are
the uses of a combinational ORA and a shift-register chain
based TPG. With respect to the shift-register chain based
TPG, advantage is taken of a feature which uses special
routing resources in order to chain registers together in
a CLB to act as a shift register [3]. Figure 4a shows a
configuration of shift-register chain used in many FPGA
families from Altera. Figure 4b shows a configuration of
shift-register chain used in all FPGA families from Xilinx.
J Electron Test (2015) 31:207215
Fig. 8 The CLB-based TPG/ORA combination
Section 3 is focused on implementing the proposed BIST
on the interconnect resources testing of Xilinx FPGAs.
3 An Implementation of the Proposed BIST
Considering Xilinx FPGAs, hardware resources are indi-
cated by the number of slices that an FPGA has, where a
slice is comprised of LUTs and flip-flops (FFs). In turn,
each CLB comprises a number of interconnected slices, as
shown in Fig. 5, where the slices that support both logic and
memory functions are called SLICEM and the slices that
support logic only, are called SLICEL. In general, half the
LUTs support both logic and memory (including shift regis-
ters chain feature) while half support logic only, and the two
types alternate throughout the array columns. The amount of
LUTs and FFs in a slice depends on the specific family. For
example: Virtex-II (2 LUTs and 2 FFs), Spartan-3 (2 LUTs
and 2 FFs), Virtex-6 (4 LUTs and 8 FFs), Artix-7 (4 LUTs
and 8 FFs).
Focusing on testing the interconnection resources of Xil-
inx Spartan 3E FPGA family, which has been chosen as
an example, its programmable interconnection network con-
sists of horizontal and vertical wire segments with different
length that operate in conjunction with PIPs. Global rout-
ing resources are used to interconnect programmable logic
Fig. 9 Test set formed by three
CLB (CLBi , CLBi + 1p and
CLBi + 2p)
211
resources, such as CLBs, IOBs, and dedicated embedded
resources (RAMs, DSPs). Each logic resource has a switch-
box (SB) which provides a connection between the logic
resources and global routing network [14].
There are three types of global interconnection wire seg-
ments on Spartan 3E and they are classified according to the
number of CLBs they span [13], namely Double Lines (span
two CLBs); Hex Lines (span six CLBs, three-by-three); and
Long Lines (span the whole die in both directions and span
six-by-six CLBs), as shown in Fig. 6. Additionally, double
and hex lines are directional and propagate in all directions
(north, south, east and west) being present in an 8-line bus,
and long lines are bidirectional and can be sourced from any
point of the line, being present in a 24-line bus [13].
For double and hex lines, the wire segment terminals are
named BEG (begin), MID (middle) and END (end). These
names are used to distinguish a given SB terminal with
respect to its relationship to the source or destinations of the
wire segment [13]. So, in each SB there are 32 BEG termi-
nals, 32 MID terminals and 32 END terminals connected to
double lines and hex lines in all directions.
Since each CLB of Spartan-3E FPGA is composed of
four slices (namely, 2 SLICEMs and 2 SLICELs) and each
slice has 2 LUTs, the proposed BIST architecture is imple-
mented as follows: the two SLICEL are configured as ORA
(where the LUTs are configured as 4-input combinational
logic) and the two SLICEM are configured as shift-register
based TPGs (where the LUTs are configured as 16-bit shift-
register, called SRL16), as shown in Fig. 7. Figure 8 shows
a view of the BIST architecture where it is possible to see
the internal connections from the PASS/FAIL signals to the
inputs of the shift-register based TPG with the result that
the ORA responses are fedback into the shift-register based
TPG.
The basic operational testing block set of the proposed
BIST architecture, called Test Set (TS), is shown in Fig. 9
which consists of three CLB (CLBi , CLBi + 1p and
CLBi +2p), each configured as the TPG/ORA combination
(as shown in Fig. 8), where i is the relative position of the
CLB with respect to a FPGA row or a FPGA column and
p is the span of the wire segment. For example, in Spartan
3E FPGA, p is equal to 1, 3, or 6 meaning that a given wire
212
Fig. 10 Complete FPGA test scheme
segment spans one-by-one CLBs (Double Lines), three-by-
three CLBs (Hex Lines), or six-by-six CLBs (Long Lines),
respectively.
As shown in Fig. 9, the TPG of CLBi applies test vectors
into the ORA of CLBi + 1p (through MID inputs) and into
the ORA of CLBi + 2p (through END inputs) in order to
test FPGA wire segments labelled as A, B and C.
Figure 10 shows the complete configuration of the pro-
posed BIST architecture considering only the horizontal
segment channels of the FPGA (the same configuration can
be applied to the vertical segment channels. For simplicity, it
is not shown) where T Si is the i-th test block. It is important
to note that CLB0 + 1p and CLB0 + 2p of T S0 comprise
the CLB1 and CLB1 + 1p of T S1 and so on.
The FPGA test response is obtained by reading back the
status of all SRL16s (this process is called readback) that
form the TPGs after a specified clock cycle running. As the
TPG seed is a cyclic sequence, the test response of a good
Fig. 11 Proposed shift-register
based BIST
J Electron Test (2015) 31:207215
FPGA maintains the same cyclic sequence. If not, the FPGA
is fault. Additionally, FPGA diagnosis is possible, as shown
in Section 4, by analysing the obtained test response.
3.1 Shift-register Based TPG
As shown in Fig. 4b, each one of the four available SLICEM
LUTs can be configured as a SRL16-based TPG. In this
way, each TPG can source two signals, one from any of its
FFs (addressable by MUX A[3:0]) and the other from the
Q15 output (the last FF). As a result, by using four TPGs
(that is, a CLB), it is possible to source 8 signals from each
CLB. A cyclic test pattern seed is preloaded in SRL16 as
an initial condition and test patterns are generated in every
clock cycle. This approach does not depend on any feedback
network for TPG proper operation, eliminating faults that
occur in the local network of each CLB. The chosen cyclic
test pattern seed is 0xAAAA which is a periodic vector with
period 2.
To be able to detect interconnection faults, these 8 sig-
nals, which are output from BEG terminals, are jointly
applied in the MID input terminals and in the END input
terminals of two subsequent CLBs. In this way, the proposed
ORA is implemented in two SLICELs of each CLB where
two 4-input LUTs of one SLICEL analyse the MID input
signal and the other two 4-input LUTs of the other SLICEL
analyse the END input signal. The obtained LUT results are
shifted back to each one of the SRL16 register TPGs, as seen
in Fig. 11.
It is important to observe that by applying more than
16 clock cycles, test responses are outputted from the
SRL16 register and then reapplied to the IUTs. Also, by
applying less than 16 clock cycles, the test results are
incomplete.
J Electron Test (2015) 31:207215 213

Fig. 13 XDL example

TPG. Configuring SRL16 registers to work with 16-bit posi-

tions, it is possible to apply 16 clock cycles and store 16
test results in each SRL16 register. The strategy of storing
test results in SRL16 registers allows the use of readback in
order to obtain the test result of the entire FPGA.
To guarantee that the feedback of the ORA output to
the SRL16-based TPG input does not change the cyclic
test pattern sequence, each LUT-based ORA is programmed
with XOR SUM of IUTs values in such a way that the
LUT-based ORA responses are also cyclic, that is,
10101010.., provided that there is no faulty IUT.

4 Proposed Diagnosis Scheme

The proposed BIST approach is capable of diagnosing and

locating a faulty wire segment in double or hex lines, due
to the ORA results on MID and END terminals. Double
and hex lines can be divided in three wire segments, as
seen in Fig. 12, namely A, B and C. It is important to note
that ORA1 checks for errors in the END terminals and
ORA0 checks for errors in the MID terminals. In this way,

Fig. 12 Diagnosis scheme

3.2 ORA

In the proposed BIST strategy, the ORA scheme is emulated

by SLICEL LUTs. In this way, during every clock cycle,
signals are applied to IUTs by the SRL16-based TPG, anal-
ysed by the proposed ORAs of the two subsequent CLBs,
and then the results are shifted back to the SRL16-based

Table 1 Interconnection diagnosis

ORAMI D ORAEN D Fault

Location
Ok Faulty C
Faulty Ok B
Faulty Faulty A
Ok Ok None
Fig. 14 Overall procedure of the proposed method
214 J Electron Test (2015) 31:207215

Fig. 15 Example: data file piece

with SRL16 registers values

if any ORA detects a fault, the fault can be located through
indications that are summarized in Table 1.
The prominent feature of the proposed BIST scheme is
that test and diagnosis are performed with the same set of
configurations reducing time requirements.
5 Tools
This section describes the tools used to obtain experimen-
tal results considering the proposed BIST approach. Results
have been obtained from implementations based on XDL
(Xilinx Design Language) that provides access to
every logical resource of the FPGA. In general, as XDL
is used by Xilinxs internal work and it is not well docu-
mented, a trial-and-error process has be done to obtain some
information about how XDL works. An example of an XDL
piece, specifying nets and activating PIPs, can be seen in
Fig. 13.
Due to the low level XDL implementations that create
extensive and complex files with thousands of lines, a C-
based program has been developed in order to generate
.XDL files automatically.
Figure 14 shows the complete procedure in order to
implement the proposed BIST strategy for FPGA intercon-
nect testing.
After the procedures shown in Fig. 14, the readback data
in .bin files are then submitted to a developed C-based
program that reads this logic allocation file (.ll) and looks
for specific bit positions in the readback bitstream. The pro-
gram generates a .data file that contains the test results
from SRL16 registers. These test results can be used to show
if the device is OK or faulty. An example of a piece of an
obtained .data file is shown in Fig. 15. Note that these
lines are followed by another in byte intervals, so two lines
contain SRL16 internal register states.
Experimental results were obtained on a PCB platform
developed in this research that comprises a Spartan 3E
xc3s100e device and the communication between the FPGA
and the host computer is carried out by a JTAG interface.
6 Experimental Results
The proposed BIST strategy has been simulated using ASL
(Auburn Simulator Language) and AUSIM (Auburn Simu-
lator) using the defined SRL16 initial states and the defined
LUT functions. Simulation results are presented in Fig. 16
and compared with the state-of-the-art [15]. The simulation
results were obtained with only one SRL16 in single fault
condition, 7 IUTs and generating 16 test vectors at 16 clock
cycles.
As can be seen in Fig. 16, both BIST strategies achieve
100 % fault coverage for stuck-at and bridge faults (Dom-
inant and Dominant AND/OR). The main difference is
related to the amount of IUTs that they can source and

Table 2 Number of BIST configurations

Routing Resource Directions Config.

North South East West

Double Lines 2 2 2 2 8
Hex Lines 2 2 2 2 8
Non-CLB Double Lines 2 2 0 0 4
Non-CLB Hex Lines 2 2 0 0 4
Total Configurations in our work 24
Total Configurations in [15] 41
Fig. 16 Fault coverage
J Electron Test (2015) 31:207215
analyse. SRL16 BIST based strategy can analyse 7 IUTs
(since not all of the 8 TPG signals sources could be routed to
global network for Spartan 3E xc3s100e) per test configura-
tion while cross coupled parity strategy can analyse 6 IUTs
per test configuration. Table 2 summarizes the total number
of configurations to test the FPGA double and hex lines.
7 Conclusion
This paper has described a shift-register based BIST archi-
tecture that takes advantage of FPGA hardware resources
in order to emulate TPGs and ORAs for testing global
interconnection resources of FPGA. It was shown that the
BIST approach is capable of generating cyclic test patterns,
analysing testing response and storing test results. It was
also shown that the BIST approach tests more interconnec-
tions per configuration with a reduced set of configurations.
A prominent feature of the approach is that testing and diag-
nosis are performed with the same set of configurations
reducing time requirements.
Acknowledgments This project was financially supported by the
CNPq-Brazil (PNM-GM, Grant Procs. 550123/2013-0), and CNPq-
Brazil (Grant Procs. 573738/2008-4 INCT NAMITEC).
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Igor Gadelha Pereira graduated in Electrical Engineering in 2011
from Federal Institute of Paraba, Brazil and received the M.Sc. degree
in Electrical Engineering in 2014 from Federal University of Paraba,
Brazil. His research interests include VLSI testing, FPGA, sip-core,
medical images, biological signals and data compression.
Leonardo Alves Dias graduated in Industrial Technologist in 2014
from Federal Institute of Paraba, Brazil and is studying for Mas-
ters degree in Electrical Engineering at Federal University of Paraba,
Brazil. His research interests include VLSI testing and FPGA testing.
Cleonilson Protasio de Souza is currently a professor at Federal Uni-
versity of Paraba - Brazil. He graduated in Electrical Engineering in
1989 and received the M.Sc. degree in Electrical Engineering in 2001
from Federal University of Maranhao, Brazil. He received the doc-
torate degree in 2005 from Federal University of Campina Grande -
Brazil. His research interests include VLSI testing, Energy Harvesting
and Wireless Sensor Network.