Defining Computer Architecture

Old view of computer architecture:

Instruction Set Architecture (ISA) design

Introduction
i.e. decisions regarding:
registers, memory addressing, addressing modes,
instruction operands, available operations, control flow
instructions, instruction encoding

Real computer architecture:

ECE466/CS466

Specific requirements of the target machine
Advanced Computer Design to maximize performance within
constraints: cost, power, and availability
Architecture Includes ISA, microarchitecture, hardware
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Computer Architecture Why Study Computer Architecture

ISA As a hardware designer/researcher know how to

Instruction format, addressing modes,
e.g. Intel IA32, IA64
Organization (Microarchitecture)
Pipeline design, cache memories,
e.g. Intel i486, P6
Hardware
Clock frequency, fabrication technology,
e.g. Intel Pentium 4 1.3 GHz, 2.4 GHz,
design processor, cache, storage, graphics,
interconnect, and so on
As a system designer know how to build a computer
system using the best components available
As a software designer know how to get the best
performance from the hardware

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 Single Processor Performance
Computer Technology Move to multi-processor

Performance improvements:
Improvements in semiconductor technology
Feature size, clock speed
Improvements in computer architectures
Enabled by HLL compilers, UNIX
Lead to RISC architectures

Together have enabled: RISC

Lightweight computers
Productivity-based managed/interpreted
programming languages

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Current Trends in Architecture Classes of Computers

Personal Mobile Device (PMD)
e.g. smart phones, tablet computers
Cannot continue to leverage Instruction-Level

Emphasis on energy efficiency and real-time
parallelism (ILP)

Single processor performance improvement ended in Desktop Computing

2003 Emphasis on price-performance
Servers
New models for performance: Emphasis on availability, scalability, throughput
Data-level parallelism (DLP) Clusters / Warehouse Scale Computers
Thread-level parallelism (TLP) Used for Software as a Service (SaaS)
Request-level parallelism (RLP) Emphasis on availability and price-performance
Sub-class: Supercomputers, emphasis: floating-point
performance and fast internal networks
These require explicit restructuring of the Embedded Computers
application

Emphasis: price

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Parallelism Trends in Technology
Classes of parallelism in applications: Integrated circuit technology
Transistor density: 35%/year
Data-Level Parallelism (DLP) Die size: 10-20%/year
Task-Level Parallelism (TLP) Integration overall: 40-55%/year

DRAM capacity: 25-40%/year (slowing)

Classes of architectural parallelism:

Instruction-Level Parallelism (ILP) Flash capacity: 50-60%/year

Vector architectures/Graphic Processor Units 15-20X cheaper/bit than DRAM
(GPUs)
Thread-Level Parallelism Magnetic disk technology: 40%/year
Request-Level Parallelism 15-25X cheaper/bit then Flash
300-500X cheaper/bit than DRAM

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Bandwidth and Latency Latency vs. Bandwidth

Bandwidth or throughput Latency Throughput ?
Total work done in a given time
10,000-25,000X improvement for processors
300-1200X improvement for memory and disks
Bandwidth grows by
at least the square
Latency or response time of the improvement
Time between start and completion of an event in latency
30-80X improvement for processors
6-8X improvement for memory and disks

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Energy and Power Power
Intel 80386
Dynamic power consumed ~ 2 W
Transistor switch from 0 -> 1 or 1 -> 0 3.3 GHz Intel
x Capacitive load x Voltage2 x Frequency Core i7 consumes
switched 130 W
Reducing clock rate reduces power, not Heat must be
energy dissipated from
1.5 x 1.5 cm chip
Static power This is the limit
Currentstatic x Voltage of what can be
Scales with number of transistors cooled by air

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Reducing Power Trends in Cost

Techniques for reducing power:
Dynamic Voltage-Frequency Scaling
Low power state for DRAM, disks
Power gating
Turning off cores
Cost driven down by learning curve
Yield
DRAM: price closely tracks cost
Microprocessors: price depends on
volume
10% less for each doubling of volume

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 Principles of Computer Design Textbooks
Take Advantage of Parallelism Computer
e.g. multiple processors, disks, memory banks,
Architecture: A

pipelining, multiple functional units
Quantitative
Principle of Locality Approach 5th
Reuse of data and instructions Edition, John
Focus on the Common Case
Hennessy and David
Amdahls Law Patterson, Morgan
Kaufmann

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Course Contents
1. Fundamentals (Chapter 1)
Course Contents
Technology trends
Performance evaluation 4. Architectural simulator: SimpleScalar
5. Memory hierarchy (Chapter 2 and Appendix B)
2. Instruction set principles (Appendix A) Cache designs
3. Instruction-level parallelism (Chapter 3 and Hardware, software cache optimizations
Appendix C) Main memory optimization
Pipelining
Virtual memory
Multiple-issue and dynamically scheduling
6. Beyond ILP (Chapters 3 and 4)
Support of speculative execution and precise
SMT and Multi-core
interrupt GPU
Instruction fetch and branch prediction
Limits on ILP

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Prerequisite Grading
ECE/CS 366 or equivalent Homework 20%
Basic logic design Projects (2) 10%
Assembly language Midterm 30%
Single-cycle and pipelined processor
Final 35%
designs
Class participation 5%

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Class Website Contact

Instructor: Zhichun Zhu
Check blackboard.uic.edu regularly for Office hours: T 1:00 2:30pm
Announcements Office: 1015 SEO
Slides zzhu@uic.edu, 355-0441
Assignments

TA: TBA
Submit homework and project report via Office hours: TBA
Blackboard Office: TBA

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