Analog Integr Circ Sig Process manuscript No.

(will be inserted by the editor)

Low power Ring Oscillator for IoT Applications

Rajendra Nayak 1 Iman Kianpoor 2

Pydi Bahubalindruni 1 .

the date of receipt and acceptance should be inserted later

Abstract This paper proposes a low power ring oscillator by combining cur-
rent starving technique with negative skewed delay approach. This design has
shown an improvement of more than 50% in the power delay product com-
pared to the state of the art techniques. Circuit simulations are carried out in
standard 65 nm technology. The proposed circuit has shown a robust perfor-
mance against temperature and voltage variation within 10%. Therefore this
circuit can find potential applications in IoT devices and RFID tags operating
from 10 MHz to 1 GHz.
Keywords low power ring oscillator, current starving, power delay product,
Negative skewed delay.

1 Introduction

Low power circuits are essential realizers of IoT systems. Oscillators are one
of the main blocks that act as the heart of the system. Among different ar-
chitectures of on-chip oscillators, ring oscillators (ROs) are preferred because
of their simplicity and less area. They are important blocks in many appli-
cations, such as, RFID tags, wireless sensor networks (WSN) and biomedical
circuits and systems. With the advancement of technology scaling, low power
RO with power consumption in the order of nano-watt is required for above
applications.
Significant work has been done in addressing the low power requirements
of RO. The most common low-power technique is current starving (CS) Wen
et al. (2013),Panyai and Thanachayanont (2012),Tabesh and Hamedi-Hagh
1 IIIT Delhi, Okhla Phase-3, Near Govindpuri Metro Station, Delhi-110020
E-mail: bpganga@iiitd.ac.in, rajendra15106@iiitd.ac.in
2 INESC TEC and Faculty of Engineering, University of Porto,

Campus FEUP, Rua Dr. Roberto Frias, 378, 4200-465 Porto, Portugal
E-mail: iman.kianpoor@gmail.com
2 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .

(2013), in which current supplied to each inverter is restricted so that the

transistors are starved of current and the circuit promises a low power con-
sumption. Differential low power ring voltage controlled oscillators (VCOs) are
reported in Ghafari et al. (2012, 2013). Other low-power ROs employed either
transistors operating in subthreshold region Sun and Jiang (2016) or digitally
controllable switch Li et al. (2015). Addition based CS RO is presented in
Zhang and Apsel (2011), which shows better performance as compared to con-
ventional CS. Modified CS technique has been reported in Azarmehr et al.
(2012), in which low dynamic power is achieved by reducing the voltage swing
at internal nodes. This is achieved by providing two extra switching transistors
in the signal path to minimize the swing. However, in all these techniques as
the current decreases, the output signal frequency also decreases, which in turn
is not showing significant improvement in the power delay product (PDP).
On the other hand, to improve frequency of oscillation, several techniques
can be applied. By adding a sub-feedback inverter with opposite phase into a
node of the main loop inverter, delay is reduced and hence frequency is im-
proved Nugroho et al. (2012). Other techniques include frequency multiplica-
tion using current sub harmonic injection locking Borjkhani et al. (2014). By
using negative skewed delay approach Lee et al. (1997), the frequency of the
RO can be improved by increasing number of high-to-low and low-to-high tran-
sitions. Nevertheless, this approach compromises with the power consumption
as this metric is directly proportional to the frequency of oscillation, again not
showing significant improvement in the PDP.
In order to address the above mentioned challenge, this paper proposes
a novel RO by combining current starving Wen et al. (2013) with negative
skewed delay approach Lee et al. (1997) to preserves advantages of both the
techniques i.e. high-frequency of operation without compromising the power
consumption. Hence PDP or figure of merit (FOM) can be improved. Circuit
simulations are carried out in standard 65 nm technology. These results have
shown a robust performance against temperature and voltage variations.
The rest of the paper is organized as follows. Section II demonstrates the
proposed circuit design and its operating principle. Section III presents sim-
ulation results and discussions and finally conclusions are drawn in Section
IV.

2 Circuit Design

A typical RO Razavi (2001) consists of odd number of inverter cells connected

in a feedback loop. A 7-stage RO circuit schematic is presented in Fig. 1.
In this circuit, the output parasitic capacitance (which are contributed from
the transistors gate capacitance in the very next stage) of single inverter is
charged through the PMOS transistor towards Vdd in one half cycle. In the next
half cycle this capacitor is discharged through the NMOS transistor towards
ground. Therefore, there is continuous charging and discharging of capacitor
in each cycle, which leads to oscillations and the frequency of ring oscillator
Low power Ring Oscillator for IoT Applications 3

is given by,
1
f= (1)
2 n td
where n is the number of stages, td is the delay of each stage. By varying the
current( I) through the inverter, td can be varied and hence the frequency. I is
dictated by the aspect ratios of both PMOS and NMOS in the inverter stage.
To obtain high speed opertion while maintaining low power consumption, the
aspect ratio of PMOS to NMOS should be maintained between 1.4 - 1.7 HE
et al. (2006). In order to obtain optimum power and frequency, this ratio is
maintained throughout the paper for all the RO techniques to ensure similar
operating condition for a fair comparison of performance.
The dynamic power dissipation of RO is given by,
2
P ower = CL Vdd f (2)

where is the activity factor, CL is the sum of output load capacitance of each
inverter stage, Vdd is the supply voltage and f is the frequency of oscillation.
is 1 for general circuits. Power consumption is directly proportional to the
frequency as per (2). Therefore, this architecture needs to be further modified
to guarantee low power consumption, while operating at higher frequencies.

Vdd

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout

Min1 Min2 Min3 Min4 Min5 Min6 Min7

Fig. 1: Schematic of 7-stage ring oscillator.

2.1 Current starving techniques

Schematic of a CS RO is shown in Fig. 2. In this circuit, MOSFETs Mip and

Min operate as an inverter, while MOSFETs Mbp and Mbn operate as current
sources. Mbp and Mbn provide biasing current through mirroring operation
(by keeping aspect ratios of all biasing PMOS as well as NMOS transistors
4 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .

same). In this configuration, as the bias current is low, in the order of nano-
ampere range, the transistors operate near sub-threshold region and hence low
power consumption can be achieved Harrison and Charles (2003). By varying
Ib , the time to charge and discharge the gate capacitance of the very next
stage can be varied and consequently the frequency. As expected from (2),
lower frequency means lesser is the power consumption and vice versa. In
order to achieve further low power consumption, Ib should be kept as low as
possible. However, it imposes limitation on the frequency of operation. This
design can not guarantee optimum PDP as it trades off between frequency of
operation and the power consumption. To improve the PDP, frequency has to
be improved without compromising power consumption by employing novel
circuit design techniques.

Vdd Vdd

Mbp8 Mbp1 Mbp2 Mbp3 Mbp4 Mbp5 Mbp6 Mbp7

Ib

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7

Mbn8 Mbn1 Mbn2 Mbn3 Mbn4 Mbn5 Mbn6 Mbn7

Mbn9

Fig. 2: Schematic of 7-stage current starved ring oscillator.

2.2 Skewed topology

Schematic of a 7-stage negative PMOS skewed delay RO (PMOS skewed) is

shown in Fig. 3. In this circuit, the input of the PMOS is connected to the
negative delay elements. Hence, the input signal to the PMOS comes earlier
than that of the NMOS. Unlike the conventional inverter cell, the skewed delay
cell turns the PMOS prematurely on when the low-to-high output transition
occurs. This compensates for the performance of the PMOS, which is usually
slower than the NMOS. Similarly, when the high-to-low output transition oc-
curs, the PMOS of the skewed delay cell turns off prematurely before the
NMOS turns on, thereby speeding up the transition. Hence, the cell delay is
minimized and results in improved frequency of operation. However, since the
Low power Ring Oscillator for IoT Applications 5

number of transitions are higher, this topology shows higher power consump-
tion as compared to conventional RO (Fig.1).

Vdd

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout

Min1 Min2 Min3 Min4 Min5 Min6 Min7

Fig. 3: Schematic of 7-stage Negative PMOS skewed delay ring oscillator.

Similarly by connecting negative delay elements to the NMOS transistor

instead of PMOS, negative NMOS skewed delay RO (NMOS skewed) can be
obtained and its schematic is shown in Fig. 4. In this circuit, the operation is
exactly similar to that of PMOS skewed shown in Fig. 3. Here NMOS transis-
tor gets prematurely on and off when high-to-low and low-to-high transition
occurs respectively. Hence the transitions are faster compared to conventional
RO (Fig.1), which results in higher frequency of operation. Similar conse-
quences can be noticed for power consumption and it is in agreement with (2).

Vdd

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7

Fig. 4: Schematic of 7-stage Negative NMOS skewed delay ring oscillator.

6 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .

Since NMOS is faster than PMOS (n > p ), frequency is more in case

of NMOS skewed as compared to PMOS skewed with same configuration of
inverters. Similarly, the power consumption is higher in NMOS skewed as com-
pared to PMOS skewed, which is in agreement with the power and frequency
relationship as in (2). The PDP of this technique is not optimized as fre-
quency trade off with the power consumption. To improve PDP, circuit design
techniques have to be modified to get higher frequency of operation without
compromising the power consumption.
In summary, CS approach promises low power consumption but imposes
limitations on the frequency of operation. On the other hand, negative skewed
delay approach shows improvement in the frequency of oscillation, but trades
off with the power. By combining these two techniques into a single circuit,
it is possible to preserve the advantages of both the methods i.e. low power
consumption from CS approach and high frequency of operation from the
negative skewed delay approach. Such topologies are presented in Fig.5 and
Fig.6 respectively.

2.3 Current Starved Skewed topology

Vdd Vdd

Mbp8 Mbp1 Mbp2 Mbp3 Mbp4 Mbp5 Mbp6 Mbp7

Ib

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7

Mbn8 Mbn1 Mbn2 Mbn3 Mbn4 Mbn5 Mbn6 Mbn7

Mbn9

Fig. 5: Schematic of 7-stage NMOS skewed CS ring oscillator.

Schematic of proposed 7-stage current starved negative skewed NMOS de-

lay RO (NMOS skewed CS) is shown in Fig. 5. The operation of this oscillator
is the combination of both CS and NMOS skewed approaches. By CS, the
reference bias current is reduced to minimize the power consumption of the
circuit. However, this leads to reduction in frequency, which can be compen-
sated by the NMOS skewed technique. The power increased by this approach
Low power Ring Oscillator for IoT Applications 7

Vdd Vdd

Mbp8 Mbp1 Mbp2 Mbp3 Mbp4 Mbp5 Mbp6 Mbp7

Ib

Mip1 Mip2 Mip3 Mip4 Mip5 Mip6 Mip7

Vout
Min1 Min2 Min3 Min4 Min5 Min6 Min7

Mbn8 Mbn1 Mbn2 Mbn3 Mbn4 Mbn5 Mbn6 Mbn7

Mbn9

Fig. 6: Schematic of 7-stage PMOS skewed CS ring oscillator.

is less as compared to increase in the frequency. This is because both CS and

NMOS skewed approach compensates the tradeoff between the frequency and
power consumption. In this case, it is expected that the (2) has the activity
factor () less than 1 and results in improved FOM or PDP.
Similarly, schematic of a 7-stage current starved negative skewed PMOS
delay RO (PMOS skewed CS) is shown in Fig. 6. The principle of operation
is the combination of both CS and PMOS skewed approaches. Compared to
NMOS skewed cs, this circuit shows better PDP as the power consumption
is less in PMOS skewed Fig.3 as compared to NMOS skewed Fig.4 under
similar operating conditions. This is in agreement with the skewed topology
performance comparison explained above.

3 Results and Discussion

The proposed circuit configuration is implemented in standard 65 nm technol-

ogy node and simulated with cadence tools. The PDP is a measure of energy
and is defined by the product of the average power Pavg and the gate delay
(td ). In low power applications, PDP has to be minimized. For a RO, this
metric is given by,
P DP = Pavg td
and tp is given by
1
tp =
2 n f requency
where n is the number of stages.
Proposed circuits temperature dependent behavior is compared against the
state of the art work under similar conditions in Fig. 7. Here one can observe
8 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .

that over a wide range of temperature, proposed technique has shown a robust
performance. In addition, the PDP is very low compared to other techniques
thereby ensuring better FOM.

10-1
Conventional
CS
NMOS skewed
PMOS skewed
NMOS skewed CS
10-2 PMOS skewed CS
PDP ( W.s)

10-3

10-4
0 20 40 60 80 100
o
Temp. ( C)

Fig. 7: PDP variation against temperature for different topologies.

The output of NMOS skewed CS RO and PMOS skewed CS RO can be

observed in Fig. 8. The outputs are in agreement with full swing oscillations
(almost between 0 - Vdd ).

In order to have a fairer comparison, we have simulated all the circuits

under similar conditions and proposed circuits performance is compared with
state of art as in Table 1. Conventional CS RO has shown the best perfor-
mance compared to the rest of the designs in state of the art. NMOS skewed has
shown the worst performance among all simulated designs due to high number
of transitions resulted from negative skewed delay. Proposed techniques (NMOS
skewed CS and PMOS skewed CS) have shown an improvement of 30% and
70% respectively. As expected, PMOS skewed CS has shown an improved per-
formance compared to NMOS skewed CS and is in agreement with the expected
behavior as explained in section 2. Similarly the proposed designs performance
are compared with other works related to low power design in Table 2. As it
can noticed, the current work (NMOS skewed CS and PMOS skewed CS) has
shown improved performance compare to the state-of-art.
Low power Ring Oscillator for IoT Applications 9

PMOS skewed CS

Amplitude (V)
1 0.92
0.5

0
0 2 4 6 8
Time (ns)
NMOS skewed CS
Amplitude (V)

1
0.96
0.5

0
0 2 4 6 8
Time (ns)

Fig. 8: Proposed ring oscillator output from both PMOS skewed CS and NMOS
skewed CS.

Table 1: Comparison with other designs when same aspect ratio is considered.

Design No. Work Description Technology (nm) Vdd (V) PDP (W*s)
1 7-Stage Ring 65 1.0 0.00403
2 CS 65 1.0 0.00144
3 PMOS skewed 65 1.0 0.00422
4 NMOS skewed 65 1.0 0.00457
5 Proposed NMOS skewed CS 65 1.0 0.00108
6 Proposed PMOS skewed CS 65 1.0 0.00067

4 Conclusions

This paper proposed a novel ring oscillator, by combining current starved

technique with PMOS/NMOS negative skewed delay approach to improve the
PDP. High speed design techniques are incorporated to get optimum perfor-
mance by choosing aspect ratio of the inverter PMOS to NMOS transistors in
the range of 1.4 - 1.7 . Designs PMOS skewed CS RO and NMOS skewed CS
RO have shown a performance improvement of more than 50% and 30% when
compared to the CS RO approach (which has shown a better performance in
the state of art). In addition, these designs have shown a robust performance
against temperature (5%) and voltage variations (10%). Therefore, the pro-
posed circuits could find potential applications in IoT systems and other low
power applications. The design can be made further robust against process vari-
10 Rajendra Nayak 1 , Iman Kianpoor 2 Pydi Bahubalindruni 1 .

Table 2: Comparison with other works

Design Design Approach Work description Technology Vdd (V) PDP(W*s)

No. (nm)
1 Negative Skewed Lee et al. (1997) 800 5.0 2.07874
Delay
2 CS Azarmehr et al. (2012) 65 1.0 0.00483
3 Feedback Voltage Nugroho et al. (2012) 180 1.8 0.22892
Controlled
4 CS Ghafari et al. (2013) 65 1.0 0.0395
5 Digitally Control- Li et al. (2015) 350 3.0 1.2500
lable Switch
6 Subthreshold Sun and Jiang (2016) 180 1.8 0.26181
Region
7 Current sub har- Borjkhani et al. (2014) 180 1.8 0.00833
monic injection
locking
8 CS Panyai and Thanachayanont (2012) 180 1.8 0.72833
9 CS Zhang and Apsel (2011) 90 1.2 0.00806
10 CS Tabesh and Hamedi-Hagh (2013) 130 1.2 0.05316
11 CS Ghafari et al. (2012) 65 1.0 0.04900
12 Sub-threshold Bias Lee and Cho (2009) 180 1.2 1.0
13 CS Proposed NMOS skewed CS 65 1.0 0.00108
14 CS Proposed PMOS skewed CS 65 1.0 0.00065

ations by adding feedback techniques like a unique combined temperature and

process compensation circuit Lee and Cho (2009), Sundaresan et al. (2006).

Acknowledgements Authors would also like to thank prof. Joao Goes for his valuable
contributions. This work is funded by early career research grant ECR/2017/000931.

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