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GDI: Logic Gates, 2-Bit Full Adder and Process

Corner Simulation
Abstract:
A low-power digital combinatorial circuit design called GDI (gate diffusion input) is used for the implementation of
various basic functions of logic gates. The same logic gates have been implemented using CMOS (complementary
MOS) and their performance is compared. The performance (delay, power) of various logic gates implemented by
GDI are tabulated for a capacitance of 1fF. A 2-bit full adder is implemented with GDI cells of the functions
previously simulated and the performance (delay, power and energy) are tabulated. Process corner simulation is then
implemented and various cases has been discussed for optimising the circuit.
Index Terms CMOS, GDI, delay, power, 2-bit full adder, VLSI, process corner.

1.INTRODUCTION
VLSI has been playing a vital role in todays technology rule. Digital circuits have replaced Analog in almost every
application. Therefore, optimising the performance of these digital circuits for faster, more power-efficient and reliable
has become the most demanding issue in the industry. Gate Diffusion Input (GDI) is one such technique which has
proved as an alternative to Static CMOS Logic. There are two methods of implementing the logic gates using GDI which
are Twin-Well, P-Well respectively.
In this implementation, we have first implemented the basic GDI cell. Then we have implemented the same using Full-
Swing GDI cell. Then, using these basic GDI cells we have made all the required components for 2-Bit Carry Look
Ahead. They are:

pg (propogate and generate for each bit)


PG (final propogate and generate for 2-bit adder)
CLA (1-bit carry look ahead adder)
LCG (last carry generator)
lastCLA (last cell in carry look ahead adder)
2-bit full adder
After making the schematics of all these circuits, the power, delay and energy of the adder are
calculated and then process corner simulation is done on the adder.

2.LITERATURE REVIEW
In first look GDI cell similar to CMOS inverter but GDI cell consists of 3 inputs G (common gate input of PMOS and
NMOS), P (input to drain/source of PMOS) and N (input to drain/source of NMOS).Bulks of both PMOS and NMOS
are attached to their diffusion P, N to reduce bulk effect. GDI decreases both gate leakage current and sub threshold
leakage current as compared to traditional CMOS. But its performance depreciates when used in and below 90nm
technology. Fabrication of basic GDI cell is not possible in traditional p well progression. When substrate attached to
drain, threshold voltage is increased and when the substrate is attached to source, body effect is destroyed in below
equations.

Vth = Vtho + (2 + Vsb 2) - VDS


Vth stands for threshold voltage, VSB stands for source body voltage, Vth o stands for zero bias threshold voltage,
stands for substrate bias coefficient, F is fermi potential, VSB Source to substrate voltage, VDS drain to
source voltage and is drain induced barrier lowering (DIBL) coefficient .
Modified GDI is a new technique for designing low power digital circuits. This technique is adopted from GDI
technique. MGDI technique is used to reduce power dissipation, transistor count and area of digital circuits. MGDI also
consists of three input terminals - G, (input of both PMOS and NMOS) P, (input to drain/source of PMOS) and N (input
to drain /source of NMOS) except the bulks of PMOS (Sp) and NMOS (Sn) are constantly coupled to VDD and GND,
respectively.
MGDI overcomes the drawbacks of GDI cell. With technology scaling, the influence of source body voltage on transistor
threshold voltage gets exceeding abridged i.e. the linearized body coefficient in above equation. Make MGDI
pertinent in 65 nm technology and below.
CMOS it requires 6 transistors. The main advantage of MGDI technique is that it reduces transistor counts and area on
chip thats cause of low power consumptions. So it is easy to design complex circuits using MGDI technique.

3.CIRCUIT DESIGN

The Gate-Diffusion-Input (GDI) methodology relies on the employment of a straightforward cell. One could also be
think about the CMOS electrical converter within the 1st look of this circuit, however there area unit some major
variations within the two:
The GDI cell contains 3 inputs G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS),
and N (input to the source/drain of NMOS). (2) Bulks of each NMOS and PMOS area unit connected to N or P
(respectively), thus it will be haphazardly biased in distinction to CMOS electrical converter. The GDI cell with four
ports will be recognized as a replacement Multi-functional device, which may attain six functions with simply totally
different combos of inputs G, P and N. Shows that straightforward configuration changes within the inputs G, P, and N
of the fundamental GDI cell will result in terribly totally different Boolean functions at the output out. Most of those
functions area unit advanced (usually consume 6-12 transistors) in CMOS, whereas terribly straightforward (only two
transistors per function) within the GDI style methodology. Meanwhile, multiple-input gates will be enforced by
combining many GDI cells.
N P G Output Function
0 B A AB F1
B 1 A A + B F2
1 B A A+B OR
B 0 A AB AND
C B A AB + AC MUX
0 1 A A NOT

Basic GDI circuit


The CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard
CMOS NAND and NOR gates. The CLA design is compared with our previously shown GDI methodology [8], which
utilizes swing-restoring buffers with selective application of high-Vth transistors, as well as with standard CMOS
implementation. Simulation results show CLA functionality and robustness under global and local process variations.
The CLA presents 2x area reduction and 45x power reduction, compared to the conventional CMOS implementation.

OR full swing

MUX full swing


AND Full Swing

XOR Full Swing


F1 Full Swing

F2 Full Swing
2-Bit Full Adder

PG full swing circuit


LCG full swing circuit

CLA full swing circuit


LastCLA circuit

The FS GDI implementation is based on the F1 and F2 cells. The implementation did not require addition of inverters
for driving the SR transistors. All the inverted signals that were used in SR transistors appeared inherently in the
functional implementation. In MUX cell implementation, a couple of complementary SR transistors was used at the
output, making the cell similar to a PTL MUX.
4. DESIGN CONSTRAINTS

For a symmetric operation of the Inverter and all the other logic gates, we have selected Wn:Wp ratio to be 1:3 for all
the schematics of both CMOS and GDI logic gates. The same has been followed for the implementation of 2-Bit Full
Adder too. The conclusion for the same has been made in the previous lab exercises.
The body terminal of NMOS is always connected to the ground and a separate pin has to be provided because in GDI
we use both Source of NMOS and drain of PMOS are also used as inputs to realise more logic gates using only two
MOSFETs.
The body terminal of PMOS is always connected to the Voltage source for the same reason mentioned above and a pin
has been given.

5. SIMULATION PARAMETERS

Ln 180 nm
Lp 180 nm
Wn 1 um
Wp 3 um
T (time period) 10 ns
V_dd 1.8 V
6. SIMULATION RESULTS

Simulation results correspond to capacitor transient and power characteristics: [For Cap loads from 1 fF to 10 fF.]

AND capacitor
Characteristics

AND capacitor power


characteristics
AND Capacitor Swing Restorer
Characteristics

AND Capacitor Swing Restorer


Power Characteristics
F1 capacitor charctersitcs

F1 capacitor power
characteristics
F1 capacitor swing
restore
characteristics

F1 capacitor swing
restore power
characteristics
F2 capacitor swing
restore
characteristics

F2 capacitor power
characteristics
F2 capacitor swing
restore power
characteristics

F2 Capacitor
Characteristics
mux capacitor
characteristics

mux capacitor power


characteristics
mux capacitor swing restore
characteristics

mux capacitor swing restore


power characteristics
not capacitor

not capacitor power


or capacitor

or cpacitor power

or capacitor swing restore and or capacitor swing restorer power characteristics


7. SUMMARY

The power and delay of every logic gate implemented by GDI has been tabulated:
Logic Gate Power Delay
OR 2.8uw 0.39ns
AND 33.08nw 0.11ns
MUX 41.79nw 0.24ns
NOT 2.704uw 0.11ns
F1 103.2nw 0.21ns
F2 74.3nw 0.48ns
Table 1: Logic Gate Implementation using Full Swing GDI
The power, energy and delay of 2-Bit Full Adder has been tabulated:
2-Bit Full Adder
Logic Gate Power Delay
S0 19.79uw 0.22ns
S1 19.79uw 0.61ns
Cout 19.79uw 0.88ns
Table 2: 2-Bit Full Adder using Full Swing GDI

Figure: Energy of 2-bit Full Adder

8. DESIGN OPTIMIZATION

Process Corner Simulation for Circuit Design Optimisation has been done. For the process corner simulation,
temperature and wn are taken as the parameters to be varied and the rest of them are always kept constant.
We have varied temperature from 10 to 50 in steps of 5. Wn is varied from 1um to 10um. The results for the some of
the conditions are as follows:
Figure: wn=3u, t=20 degrees, Cout

Figure: wn=3u, t=20 degrees, s0

Figure: wn=3u, t=20 degrees, s1


Figure: wn=8u, t=40 degrees, Cout

Figure: wn=8u, t=40 degrees, s0

Figure: wn=8u, t=40 degrees, s1


9. CONCLUSION

The benefits of Gate Diffusion Input (GDI CELL) technique, 2-transistors implementation of advanced logic functions
and in-cell swing restoration underneath bound operative conditions are distinctive among existing low-power style
techniques. This alongside positive measuring and simulation results, give proof that Gate Diffusion Input (GDI CELL)
style would possibly enrich the tool chest of VLSI designers. We hope that the given results can encourage any analysis
activities on Gate Diffusion Input (GDI CELL) technique. The difficulty of serial logic style with Gate Diffusion Input
(GDI CELL) is presently being explored, furthermore as technology compatibility for twin-well CMOS method.
Additional work was drained automation of a logic style methodology supported Gate Diffusion Input (GDI) cells.
Simulation is done in Comparison between conventional, GDI and MGDI technique is shown in the case of area,
transistor count and static power consumptions. Using MGDI technique, implemented logic gates and digital circuits
reduced to 25% - 90% in number of transistors and due to this area on chip decreases as well as significant reduction in
power consumptions. Using MGDI technique various digital circuits can implement to increase efficiency of digital
circuits.

10. REFERENCES

1. Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits Arkadiy Morgenshtein,
Alexander Fish, and Israel A. Wagner
2. Full-Swing Gate Diffusion Input logicCase-study of low-power CLA adder design Arkadiy Morgenshtein,
Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish
3. Lab Manual, EED 401, VLSI: Design