Shiv Nadar University, Dadri

Deptt of Electrical Engineering (EE)

Course Title: Introduction to VLSI Design

Course Code: EED 401

Credits: 4

L:T:P: 3:0:1

Semester: Summer 2017

Instructor: Dr. Sonal Singhal

Office: FF D-wing, Cabin No.-15

E-mail: sonal.singhal@snu.edu.in

Extension: 114
Lecture: Two-one and half an hour sessions per week
Laboratory: 2 hrs per week,

Prerequisites: Synthesis of digital logic design. Characteristics of MOS or CMOS devices

Catalog Course Description: Introduction to VLSI Design: A course on design of Very Large
Scale Integrated (VLSI) circuits concentrating on the CMOS technology. MOS transistor theory
and the CMOS technology. Characterization and performance estimation of CMOS gates. CMOS
gate and circuit design. Simulation using CAD tools.
Laboratory experience in CMOS VLSI design

Course Topics:
Modeling of MOS Transistor: Introduction, MOS Modelling, Structure and Operation of MOS,
Current-Voltage Characteristics, Scaling and Small-Geometry Effects, MOSFET Capacitances,
LEVEL1-LEVEL2-LEVEL3 modeling technique-various model comparison,

Models for Digital Design: Miller Capacitance, The Digital MOSFET Model, Effective
Switching Resistance of Long Channel MOSFET, Short-Channel MOSFET Effective Switching
Resistance, Capacitive Effects.

CMOS Technology: Static CMOS inverter, DC Characteristics, Noise Margins, Inverter

Switching Point, Ideal Inverter VTC.

Dynamic Characteristics of CMOS inverter: Computing the capacitance-propagation delay

sizing inverter for performance optimization. Power consumption in CMOS logic gates: Static
Power consumption, Dynamic power consumption, dynamic or glitching transitions, Design
techniques to reduce switching activity. Sizing for Large Capacitive Loads, Buffer Topology,
Other Inverter Configurations. The Ring Oscillator.

Pass Transistor Logic: MOSFET Pass Gate, Delay through a Pass Gate, The Transmission Gate
(The TG) Sizing in pass transistor. Applications of the Transmission Gate as Path Selector and
Static Circuits

COMBINATIONAL MOS LOGIC CIRCUITS: DC Characteristics of the NAND and NOR

Gates, Switching Characteristics, Parallel Connection of MOSFETs, Series Connection of
MOSFETs, NAND Gate, Quick Estimate of Delays, Number of Inputs, Complex CMOS Logic
Gates, Cascode Voltage Switch Logic

Dynamic CMOS design: Fundamentals of Dynamic Logic, Charge Leakage, Simulating

Dynamic Circuits, Domino logic, Optimization of Domino logic, NPCMOS logic, Designing
logic for reduced supply voltages. Design of Latch.

LOW-POWER CMOS LOGIC CIRCUITS: Introduction, Overview of Power Consumption,

Low-Power Design Through Voltage Scaling, Estimation and Optimization of Switching
Activity, Reduction of Switched Capacitance

Memory Design: Design of 6T static memory cell, NAND and NOR Flash Memory

References: 1. CMOS Digital Integrated Circuits: Analysis

and Design, S.-M. Kang and Y. Leblebici, 2nd
Edition, McGraw-Hill, Inc., 1999
2. Circuit Design, Layout and Simulation, R.
Jacob, Baker, 3rd Edition, Willey.
3. Digital Integrated Circuits: A Design
Perspective, Jan M. Rabaey, Prentice
Hall, Inc., 1996
4. Principles of CMOS VLSI Design. A Systems
Perspective, 3rd Edition, byNeil H. E. Weste,
Karman Eshraghian, Addison-Wesley, 2004
5 Basic VLSI Design, D.A. Pucknell and K.
Eshraghian, 3rd Edition, Prentice Hall, Inc.,
1994
CAD and Computer Tools Used: Cadence CAD Tool

Assignments:
There will be several homework and reading assignments. In reading assignments students are
expected to read research papers and submit summaries. Representative papers from IEEE
Transactions (10-12 pages in length) covering different aspects of the course material will be
chosen. Students need to present the key findings of the papers in 10-15 minutes.
Grading Scheme:

Quizzes 15 %
Midterm 15%
Laboratory 25 %
Final Term 35 %
Overall Performance 10 %