Finfet

Recent Development of
FinFET Technology for CMOS

Logic and Memory
Chung-Hsun Lin
EECS Department
University of California at Berkeley
Outline
Why FinFET
FinFET process
Unique features of FinFET
Mobility, workfunction engineering, corner effect, QM,
volume inversion
Issues
Recent FinFET Develop
Triple-gate FinFET, Omega FET, Nanowire FinFET,
Independent gate, Multi-channel FinFET, Metal-gate/high-K
FinFET, Strained FinFET, Bulk FinFET
Memory
DRAM, SONOS, SRAM
Conclusion
NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 2

MOSFET Scaling
ITRS 2001 Projection

100
GATE LENGTH (nm)

10
The first transistor The Power5
1947 microprocessor LOW POWER
HIGH PERFORMANCE
Technology Scaling 1
2000 2005 2010 2015 2020
YEAR
Investment Better Performance/Cost
Same transistor
design concept
Market Growth

Scaling : Moores law
Technology Drivers
Reduced cost /
function
Improved
performance
Greater circuit
functionality
Source: Intel

Bulk-Si MOSFET Scaling Issues
Leakage current is the primary barrier to scaling
To suppress leakage, we need to employ:
Higher body doping lower carrier mobility, higher
junction capacitance, increased junction leakage

Thinner gate dielectric higher gate leakage
Ultra-shallow S/D junctions higher Rseries
G Desired characteristics: Lg
Tox
- High ON current (Idsat)
- Low OFF current Gate
S
Source Xj Drain
D Leff
courtesy of Prof. Kuroda
Keio University Substrate Nsub

Issues for Scaling Lg to <25 nm
VT variation (statistical dopant fluctuations)
Leakage
Incommensurate gains in Idsat with scaling

limited carrier mobilities
parasitic resistance

Advanced MOSFET Structures
Leakage can be suppressed by using a thin body
Ultra-Thin Body Double Gate
Gate
Gate 1 Vg
Source SOI Drain TSi
TBOX
Source SOI Drain TSi
SiO2
Tox Gate 2
Silicon Substrate

Thin-Body MOSFETs
Control short-channel effects with Tbody
No channel doping needed!
Relax gate oxide (Tox) scaling
Double-Gate is even more effective

Scalable to 10nm gate lengths
Gate Gate
Source Drain Source Drain
Buried Oxide
Gate
Substrate Tbody
Ultra-Thin Body Double-Gate
Electric Field Reduction
Reduced vertical field Gate Qinv

in DG and UTB
Qinv + Qdepl
E eff = Qdepl
Si Bulk
No doping = Qinv
Gate
No Qdepl!
Expected to benefit:
Buried Oxide
Mobility
Substrate
Gate Leakage
Thin-Body

Thin-Body MOSFETs
Control short-channel effects with Tbody
Relax gate oxide (Tox) scaling
Improved mobility
Ion Lower vertical electric field
DG
Idrain
No impurity scattering Bulk
Improved swing
Better control of SCE Vgate
Lower VT
Cload
No depletion or junction capacitance
Double-Gate is even more effective

Scalable to 10nm gate lengths
Potentially less Vt scatter (dopant fluctuation)

Circuit level benefits
Thin body devices
FO4 Inverter Delay [ps]

9 Good control of SCE 20 Bulk
UTB
9 Steep Sub-threshold DG
swing 10 Tbody,UTB
9 Higher Idsat 8 = 5nm
6
9 Lower Capacitance - No
Cjunc and Cdepl 4
Tbody,UTB
9 Better CV/I delay at < 5nm
lower power 2
50 35 25 18
Technology Lgate [nm]
Source: Leland Chang

Double-Gate MOSFETs
Gate 1 Planar DG
MOSFET
S D
Gate 2
Current flow
Current flow
S
D
Gate 2 Gate 1
Gate 1 Gate 2
D
Current flow
S
Vertical DG
FinFET MOSFET
Multi-Gate FinFET
Drain Drain
Gate
Source
Gate
Gate Gate
Gate
Gate
Source Drain
Drain Drain
Gate
Source Source
Planar 90
FinFET
DG-FET Rotation
Rotation allows for self-aligned gates
Layout similar to standard SOI FET

FinFET Process Flow
Si Fin SiO2 Resist
BOX
Poly
SOI Substrate
Fin Patterning Poly Gate Deposition/Litho
Si3N4 NiSi
Spacer
Gate Etch S/D Implant + RTA

Spacer Formation Silicidation

FinFET Device Structure
Source
Gate
Drain
All features defined by optical lithography

and aggressive trimming

10nm FinFET TEM
NiSi
Poly-Si
220
SiO2 cap
Lg=10nm
Si Fin
BOX

10nm FinFET I-V
Dual N+/P+ poly gates: Vd=-1.2V Vd=1.2V

-3 -3
- Need VT control 10 10
0.1V
Drain Current [A/m]

-0.1V
Low DIBL
NMOS: 120 mV/V -5
10
-5
10
PMOS: 71 mV/V
Good SCE despite thick -7 -7
10 PMOS 10
Tox (27 EOT) & Wfin
NMOS
S=125 S=101
(26nm) mV/dec mV/dec
- Due to large S/D -9
10
-9
10
doping gradient & -1 0 1
spacer thickness Gate Voltage [V]

Short-Channel Effects
160 160
Subthreshold Slope (mV/dec)

Acceptable DIBL and NMOS
subthreshold slope down PMOS
120 120
to below 20nm Lgate W =26nm
DIBL (mV/V)
fin
Nearly ideal (60mV/dec) 80 80

subthreshold slope at
long Lgate
40 40
NMOS better than PMOS
due to slower As 0 0
diffusion 0 20 40 60 80 100
Gate Length (nm)

Orientation
<100>
in
Dra
Gate (110) (100)
(110)
e
urc
Surface
So
~(111) (110)
<110>
Rotation by 45 changes orientation from (110) to (100)

Intermediate rotation similar to (111)

How Mobility Changes
500 500
Electron Mobility [cm /Vs]

Oxynitride Oxynitride
Hole Mobility [cm /Vs]

2 400 400
2
(100)
300 300
200 (111) 200 (110)

(111)
100 100
(110)
(100)
0 0
0.2 0.4 0.6 0.8 1.0 0.2 0.4 0.6 0.8 1.0
Effective Field [MV/cm] Effective Field [MV/cm]
By shifting away from (100):

e is degraded, h is enhanced
Can we benefit from changing the N/P ratio?

Gate Delay
20
PMOS enhancement (20%) Lgate=35nm Fanout=4
is larger than NMOS
% Delay Speedup vs. (100)

degradation (8%) 15 h, e
Net delay improvement
NOR
Trade off h and e 10
NOR: PMOS stack
Inv
h very important
5 NAND
Most improvement
NAND: NMOS stack

Oxynitride
h less important
0
(100) NMOS
Least improvement (100) (111) (110)
(110) PMOS
Orientation

Optimized FinFET
Source
Gate
Gate
Drain
Source
Source
Drain
Drain
Drain
Source
(110) PMOS (100) NMOS
Trade off layout area for performance

FinFET Layout Area
0.8 50
Layout Area [m ]
Layout Area [m ]
2
2
(100) 0.6 40
(110)
(111) 30
o o
0.4
45 N / 90 P 20
o o
90 N / 45 P 0.2
10
Inverter 0.0 0
Idsatn,p=1.1mA Idsatn,p=110mA
Non-(100) orientation saves area

Higher PMOS Idsat reduces drawn W
45 orientation is less area efficient for smaller W

These devices are small anywaydoes it matter?
Use only in critical path?

Hybrid-Orientation-Technology (HOT)
Super HOT: SOI version

DSB: bulk version

VT: What CMOS Needs
Inverter Response
Need symmetrical VTs for
proper CMOS operation
VDD
Need low VTs for speed
Output
VIN= VIN=
VTN VDD-VTP
0 VDD
Input

Gate Work Function
Single gate material

1.0 VTn VTn = -VTp = 0.4V
-VTp
Threshold Voltage [V]
0.8 N+/P+ Poly

N Poly
P Poly

VTn = -VTp = -0.2V

0.6 VT=0.4V
+
+
0.4 For low body doping,
VT=0.2V desired M values are:
0.2
~ 4.5 eV for NMOS
0.0
4.52eV 4.95eV ~ 5.0 eV for PMOS
-0.2
Need two separate work
4.2 4.4 4.6 4.8 5.0 5.2 functions for NMOS and
Gate Workfunction [eV] PMOS!

Molybdenum M Engineering
by Ion Implantation
M can be lowered by
N+ implantation and
thermal anneal
M increases with
dose
energy
(N segregates to SiO2
interface & forms Mo2N)
P. Ranade et al., IEDM 2002
Anneal time = 15m except for 900oC (15s)

TMo = 15nm

Mo-Gated FinFETs (PMOS)
Y.-K. Choi et al., IEDM 2002
-3
10 |Vt|=0.2V for lightly doped
Lg=80nm, TSi=10nm body, and is adjustable
Drain Current, Id [A/um]
-5 Vds=0.05V by N+ implantation
10
-7 Alternative technique:
10 Vt shift
Full silicidication (NiSi) of
-9 n+/p+ Si gates
10 (J. Kedzierski et al., W. Maszara et al.,
Z. Krivokapic et al., IEDM 2002)
-11
10 Mo Potential issues include:
15 -2
MoN(N2=5x10 cm ) - dopant penetration
-13
10 - thermal stability
-0.8 -0.6 -0.4 -0.2 0.0 0.2 - stress/adhesion
Gate Voltage, Vg[V] - gate dielectric reliability

Corner Effect in Triple or More Gates
Corner Effect
Different Vth at corner region
Significant subthreshold leakage current
Strong corner radius, body doping dependence
B. Doyle et al., VLSI Tech., p. 133, 2003

Corner Effect [1]
Vg=0.2 V Vg=1 V z
z
y y
D
S
2D current density distribution 2D current density distribution
6
3 4x10
DESSIS 3-D device
Current Density (A/cm )

z direction
2
2
Current Density (A/cm )
y direction
simulator
6
3x10
2
Ideal rectangular fin 6

2x10
shape 1
6
1x10
z direction
Nsub=1e15cm-3 y direction
0
0 0 5 10 15 20 25 30
0 5 10 15 20 25 30
Position (nm) Position (nm)

Corner Effect [2]
Nsub=5e18cm-3 7
2.0x10
z
)
2
Current Density (A/cm
corner y
1.5x10
7
7
1.0x10
Vg=0.2 V
flat 5.0x10
6
0.030
0.025
0.0 0.020
-0.015 0.015
-0.010
-0.005 0.010
is
Ax
0.000
X Ax 0.005 0.005
Y
is 0.010
0.000
0.015
2D current density distribution

20
z 4x10
)
-3
y 20
Electron Density (cm

3x10
Vg=1 V 20
2x10
20
1x10
0.030
0 0.025
0.020
-0.015 0.015
-0.010
-0.005 0.010
is
Ax
0.000
X Ax 0.005 0.005
Y
2D current density distribution is 0.010
0.000
0.015
3D Simulation w/ Various Shape of Corner
Lg=1m, Wsi=30nm, Hsi=30nm, Tox=1nm

R=0, 5, 10, 15m
-5
Normalized Drain Current (A/m)

8.0x10
Normalized Drain Current (A/m)
1E-5
-5 R=15nm
6.0x10
R=10nm
1E-7
R=5nm
-5
R=0nm
4.0x10
1E-9
R=15nm
-5
R=10nm 2.0x10
1E-11
R=5nm
R=0nm
1E-13 0.0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V) Gate Voltage (V)

Short Channel Behavior
MG device with sharp corner shows better

short channel behavior than the rounded
corner
100
R=0nm
80 R=15nm
DIBL (mV/V)
60
40
20
0
0 200 400 600 800 1000
Gate Length (nm)

Double-humps induced by cap transistor
30x30nm structure, Tox=3nm,

Lg=1mm, Nsub=5e18cm-3
Cap transistor induced lower Vt is
very significant.
It may attribute to thicker Tox, and
more partial depleted.
-6
4.0x10
1E-5
30x30nm
Lg=1m, Tox=3nm 1E-7
-6
3.0x10 -3
Nsub=5e18cm
Drain Current (A)
1E-9
dGm/dVg
-6
2.0x10 1E-11
1E-13
-6
1.0x10
1E-15
0.0 1E-17
0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.5 1.0 1.5 2.0

Volume Inversion [1]
Gate Gate Gate Gate
eDensity eDensity
6.1E+13 6.1E+13
5.3E+13 5.3E+13
T si 4.5E+13 T si 4.5E+13
3.6E+13 3.6E+13
2.8E+13 2.8E+13
2.0E+13 2.0E+13
15 -3 18 -3
N sub =10 cm N sub =10 cm
Oxide Oxide
The electron density distribution from the 3-D ISE

device simulator. Volume inversion is significant in
intrinsic channel SDG (left).
Volume Inversion [2]
1E-5
Inversion charge sheet density (C/cm )

2
15 -3
0.6 Nsub = 10 cm 15
Nsub = 10 cm
-3
1E-7
Electric Potential (V)
0.5
0.4
1E-9
0.3
s0, 10nm 1E-11 Tsi
0.2
s, 10nm
0.1 s0, 20nm
1E-13
s, 20nm Tsi = 10 nm
0.0 Tsi = 20 nm
0.0 0.2 0.4 0.6 0.8 1.0 1E-15

0.0 0.2 0.4 0.6 0.8 1.0
For intrinsic channel doping, volume inversion is valid and the
potential through the Si film is flat in the subthreshold region.
The inversion charge (current) in the subthreshold region is
proportional to Tsi.

QM Surface Potential Correction
Undoped case

I-V Verification
Model can predict both subthreshold and strong inversion

region well.
-5
1E-4 6.0x10
5.0x10
-5 Symbols: 2D simulation
1E-6
Drain Current (A/m)
Drain Current (A/m)

Lines: Model
4.0x10
-5 Classic
1E-8 QM
-5
3.0x10
1E-10
-5
Symbols: 2D simulation 2.0x10
Lines: Model
1E-12 Classic -5
1.0x10
QM
1E-14 0.0
0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0

S/D Series Resistance Issue
J. Kedzierski et al., IEDM 2001
S/D series resistance will degrade the performance of thin body

device
Can be improved by the selective Si epitaxy raised S/D

Outline
Why FinFET
FinFET process
volume inversion
Issues
Memory
DRAM, SONOS, SRAM
Conclusion

Triple-Gate Transistor
B. Doyle et al., VLSI Tech. 2003

Omega-Gate Transistor

5nm Nanowire FinFET

Independent Gate FinFET
Control the threshold voltage

Ideal rectangular shape of Si fin

Independent Gate FinFET

Multi-Channel FinFET

Metal Gate FinFET

Metal-Gate FinFET
Vth adjustment
K.G. Anil et al., VLSI Tech. 2005
Improvement of Ion
TiN/HfO2 FinFET
Vth adjustment
Reduce Gate leakage
N. Collaert et al., VLSI Tech. 2005

Inverted T Channel (ITFET)
L. Mathew et al., IEDM 2005

UTB + FinFET
Continuous effective width
Strained FinFET
25% drain current enhancement of PFET by introducing

recessed Si0.8Ge0.2 S/D
Compressive stress and raised S/D P. Verheyen et al., VLSI 2005

Impact of Gate-Induced Strain
MuGFETs with TiSiN gate (+3GPa stress as deposited)
500 400
(100) metal (100) metal
(110) metal (110) metal
400 (100) poly ref (100) poly ref
300
4% (110) poly ref 10% (110) poly ref
300
59% 200
200
100
100 8%
NMOS PMOS
0 0
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
Stress [MPa] Mobility Enhancement [%]

Eeff=0.4MV/cm
(100) (110) (100) (110)
xx yy zz
NMOS NMOS PMOS PMOS
z
Experiment 4 59 8 10
y
x Inverse PR Model -540 -290 -1900 4 59 -1 10

Issue of Fin Formation
K. Endo et al., IEDM 2005
Neutral beam etching can accomplish damage (defect) free fabrication

of high aspect ratio fin.
Higher mobility is obtained in NB device due to atomically-flat surface
Sidewall Spacer Transfer (SWT) Process
Both gate and fin are formed by SWT

SiN is selected as hard mask material
for Si RIE on top of fin
Can be used as the CMP stopper during
poly gate planarization (important for
gate SWT)
Suppress the agglomeration of Si fin
during selective Si epi
Prevent the leakage of the top corner
A. Kaneko et al., IEDM 2005 Used as RIE stopper in the gate RIE
process

SWT Process
The threshold voltage

uniformities for SWT
FinFETs of 15nm fin and
15nm gate length over
the wafer is better than
ArF and EB lithography

Selective Gate Sidewall Spacer Formation

FinFET on Bulk Si Substrate
Bulk FinFET has the advantages of cheaper wafer cost, ease of

combination with conventional bulk CMOS.
K. Okano et al., IEDM 2005

Characteristics of Bulk FinFET
Better subthreshold swing

Better short channel control
Negligible body effect
T. Park et al., VLSI 2003

Outline
Why FinFET
FinFET process
volume inversion
Issues
Memory
DRAM, SONOS, SRAM
Conclusion

DRAM application of Bulk FinFET

DRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT

NWL Scheme
Lower VT (doping concentration) FinFET combined

with NWL scheme can provide lower leakage and
higher performance
NWL bias is critical to refresh fail bit

SONOS Application of FinFET
J. Hwang et al., TSMC 2005
High Performance FinFET SONOS flash cells

with gate length of 20nm is demonstrated.
Program/erase window of 2V with high P/E
speed (Tp=10ms, TE=1ms)
SONOS Application of FinFET
Excellent endurance: up to
10K P/E cycles
Good retention: 1.5V after
10years retention time
J. Hwang et al., TSMC 2005

FinFETs based 6-T SRAMs
load
WL Large fraction of
V DD
the total chip area
M2 M4 will be memory1
Leakage problem
VR
M5 VL M6
access Limited by impact

M1 M3
of variations
BL pulldown BL
FinFETs offer good control of short channel effects

1Source : Ranganathan, 2000

Static Noise Margin
The minimum noise
voltage at the storage
node needed to flip the
state
Large SNM is desirable
Make pulldown device
stronger relative to
access transistor
Source: Bhavnagarwala, 2001

SNM spread with variations
Thicker Si body better
0.3 Tsi = 11nm Higher performance
0.25 Tsi = 15nm due to Rs limitations

Greater noise
Probability
0.2
0.15 immunity (SNM)

0.1 Lesser spread in
SNM
0.05
0
0.1 0.15 0.2 0.25
SNM (V)
Taurus Device Simulation

SNM spread with variations
TSi = 15nm
0.3 To improve SNM
(110) / 1fin (100 )/
a) Wpulldown - 2 fins
2 fins
Laccess
Probability
b)
0.2
(100)/ c) eff, pulldown>eff, access
1fin (100)pulldown device
0.1
(110) access device
0
0.1 0.15 0.2 0.25
SNM (V)
Taurus Device Simulation

FinFET Circuit design tradeoffs
Advantages Limitations
Excellent SCE Gate material
control Contact/Series
Scalability resistance
Double-gates are Area efficiency
self-aligned (fin pitch)
Insensitivity to Back gate routing
channel doping

Conclusion
Unique FinFET physics are introduced.
Recent developing effort on FinFET

technology are discussed
Independent gate, Multi-channel FinFET, Metal-
gate/high-K FinFET, Strained FinFET, Bulk FinFET
FinFET based CMOS and memory cells are

very promising for sub-32 technology
node.

Thank you very much
for your attention

Finfet

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Recent Development of

FinFET Technology for CMOS

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 2

ITRS 2001 Projection

GATE LENGTH (nm)

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 3

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 4

junction capacitance, increased junction leakage

Ultra-shallow S/D junctions higher Rseries

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 5

VT variation (statistical dopant fluctuations)

Incommensurate gains in Idsat with scaling

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 6

Leakage can be suppressed by using a thin body

Ultra-Thin Body Double Gate

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 7

Relax gate oxide (Tox) scaling

Double-Gate is even more effective

Source Drain Source Drain

Reduced vertical field Gate Qinv

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 9

Double-Gate is even more effective

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 10

FO4 Inverter Delay [ps]

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 11

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 13

Gate Etch S/D Implant + RTA

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 14

All features defined by optical lithography

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 15

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 16

Dual N+/P+ poly gates: Vd=-1.2V Vd=1.2V

Drain Current [A/m]

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 17

Subthreshold Slope (mV/dec)

Nearly ideal (60mV/dec) 80 80

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 18

Rotation by 45 changes orientation from (110) to (100)

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 19

Electron Mobility [cm /Vs]

Hole Mobility [cm /Vs]

200 (111) 200 (110)

By shifting away from (100):

Can we benefit from changing the N/P ratio?

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 20

% Delay Speedup vs. (100)

NAND: NMOS stack

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 21

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 22

Non-(100) orientation saves area

45 orientation is less area efficient for smaller W

Use only in critical path?

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 23

Super HOT: SOI version

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 24

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 25

Single gate material

0.8 N+/P+ Poly

VTn = -VTp = -0.2V

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 26

Anneal time = 15m except for 900oC (15s)

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 27

NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 28