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Improving fault-tolerance capability of on-chip

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Article in The Journal of Supercomputing January 2016

DOI: 10.1007/s11227-015-1513-x

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 Improving fault-tolerance capability of on-chip binary CDMA bus
Tatjana R. Nikolic, Goran S. Nikolic, Goran Lj. Djordjevic, Mile K. Stojcev

University of Nis, Faculty of Electronic Engineering, A. Medvedeva 14, 18000 Nis, Serbia

Tatjana R. Nikolic (corresponding author)

University of Nis, Faculty of Electronic Engineering, A. Medvedeva 14, 18000 Nis, Serbia
tel. +381 18 529 224
fax. +381 18 529 105
e-mail: tatjana.nikolic@elfak.ni.ac.rs

G. S. Nikolic, G. Lj. Djordjevic, M. K. Stojcev, Faculty of Electronic Engineering, University of

Nis, Nis, Serbia
G. S. Nikolic
e-mail: goran.nikolic@elfak.ni.ac.rs
G. Lj. Djordjevic
e-mail: goran.lj.djordjevic@elfak.ni.ac.rs
M. K. Stojcev
e-mail: mile.stojcev@elfak.ni.ac.rs

Abstract

Shrinking technology and growing complexity of the contemporary system on chip designs
require high performance and reliable interconnection architecture. Binary CDMA-encoded on-
chip bus permits simultaneous use of the shared communication medium by multiple data streams
and alleviates contention and queuing delays experienced by a conventional time-division
multiplexing shared bus. In this paper, we present an encoding scheme for improving reliability
of the on-chip interconnect system based on a binary CDMA bus. Without adding extra wires to
the bus, the proposed encoding method replaces the standard binary encoding with a non-
weighted code which tolerates single-bit error at any bus wire within the timing window of a
single CDMA transaction. In addition, we derive constraints for a codeword selection under
which the single-bit error tolerance is achieved, and provide a recursive algorithm for code
construction. Simulation results show that the proposed encoding scheme significantly improves
the post-decoding bit error rate performance of the binary CDMA bus under a binary symmetric
channel model.
Keywords: Fault-tolerance, multi-processing system on-chip, system on-chip interconnects,
CDMA bus, bus encoding.

1
1. Introduction

With the constant growing complexity of modern multi-processing system on chip (MPSoC)
architectures, the role played by the on-chip interconnection infrastructure becomes increasingly
important for the overall system performances and reliability. Among the various conventional
on-chip interconnection architectures a shared bus is the most simple and the most cost effective
solution for small-scale MPSoCs. The communication between the processing cores in these bus-
based systems is traditionally based on a time-division multiplexing (TDM) protocol, which is
simple but inefficient in simultaneous dealing with multiple data transactions. As only one
processing core can perform a data transaction over the bus at a time, there is a need for a
dedicated arbiter to manage the serialization of access requests. Contention and arbitration delays
associated with the bus access may prohibit the scalability of MPSoC, resulting in diminishing
performance returns as more processing cores are connected to the common TDM bus structure
[1][2][3][4].

The code-division multiple access (CDMA) technique, as a form of multiple access which
permits simultaneous use of the communication medium by multiple data streams, has recently
emerged as a promising solution to reduce the variance of bus access latency in MPSoC. With
this technique, the perfect separation of concurrently transmitted data streams is achieved by
encoding each stream prior to transmission using an orthogonal spreading code. Orthogonal
codes (e.g. Walsh code) have the property that a code sequence has a high correlation with itself,
and a zero correlation with other code sequences. This property allows receivers to retrieve any
one of the original data streams by correlating the composition of encoded streams with the
corresponding code sequence. Therefore, the CDMA technique enables an on-chip
communication paradigm where multiple transmissions can proceed, in parallel, over the shared
bus, unlike the conventional TDM bus architectures where only one processing core can transmit
at a given time [5]. Flexible dynamic reconfiguration is another advantage of on-chip CDMA, as
the receiver can retrieve an arbitrary data stream by simply changing the code sequence. Also,
because the same code sequence can be used for different receivers, multicast and broadcast
flows are easily accommodated. Moreover, the on-chip CDMA enables efficient adaptive sharing
of bandwidth among concurrent data streams by assigning more than one orthogonal code
sequences to streams [6][7].

The main design choice in the on-chip CDMA-based interconnect architecture concerns the
transport method for the composite CDMA encoded stream. In the -channel CDMA bus
system, the composite stream is a sequence of the so called sum-chips, where each sum-chip can
take one of + 1 different numerical values, and each subsequence of successive sum-chips
(so called CDMA packet) encodes parallel input bits (one bit from each data stream).
Therefore, to deliver bits of useful information, the total of (1 + 2 ) bits must be
transported over the CDMA bus. Note that this amount of information redundancy is inherent in

2
any CDMA transmission system. There are two general methods on how to cope with the
information redundancy in on-chip CDMA transport without compromising the speed of data
transfer. The first one is to use the analog multi-level transmission lines to increase the bus
bandwidth. With this scheme, the amplitude modulation is performed chip by chip on the multi-
level signal. Therefore, to transport sum-chips in -channel CDMA bus system, ( + 1)-level
signaling is required. As increases, the multiple signal levels become more closely spaced, and
consequently more susceptible to channel interference noise, clock jitter and skew [3]. The
second method is to transport the binary equivalents of sum-chip values in a parallel form over
the conventional binary bus. With this method, known as the binary CDMA bus, (1 + 2 )
two-level signal wires are required to transport one sum-chip per bus cycle [8][9].

The reliability of data transmission is another important issue in the design of the on-chip
interconnection. With the shrinking line widths and spacing, and reducing supply voltage in
modern VLSI technology, the interconnection wires become more susceptible to noise and faults
[10]. Error detection and correction coding techniques are commonly used to address these
issues. These techniques are generally targeted to single- and multiple-bit errors caused by
transient faults that are the most common type of faults in todays integrated circuits [11].
Powerful error detection and correction codes usually require introduction of redundant bits,
which increases the number of interconnection links and complexity of the encoder and decoder
logic [12][13][14][15]. Despite the fact that the binary CDMA transmission bus involves
substantial information redundancy, its fault tolerance capability is rather moderate. Indeed, as
confirmed by our simulation experiments of the 8-channel binary CDMA bus system, a single-bit
error in CDMA packet produces two erroneous bits in the decoded data on average. The poor
fault tolerance of the conventional binary CDMA bus is mostly due to the inadequate encoding of
the sum-chip values, which are transmitted over the bus as-is, i.e. as the signed binary numbers in
twos complement representation. Weighted binary encoding is not well suited to the CDMA
decoding process because a bit-error at a position of higher numerical weight can cause a large
change of the sum-chip value, which cannot be masked by the rest, correct sum-chips during the
decoding. In addition, because every sum-chip of CDMA packet participates in the decoding of
every data bit, a single erroneous sum-chip value can affect multiple decoded bits. A combination
of different types of codes with a hardware redundancy technique can effectively tolerate a high
number of faults [16]. The usage of logic CDMA mechanism and the interconnection grid
structure for the implementation of -tuple modular redundancy system is described in [17]. An
interconnection architecture that combines logic CDMA, as a coding technique, and duplication
with logic comparison, as a hardware redundancy technique, is proposed in [18]. These
approaches lead to an improved reliability, but at the cost of significant hardware overheads.

In this paper, we suggest a different approach to improving the fault-tolerance capability of an

on-chip binary CDMA bus: instead of adding costly hardware redundancy, we propose to exploit
the inbuilt information redundancy in the composite CDMA stream, and change the way the
information is encoded on the bus. Specifically, we introduce a reliable binary CDMA bus design

3
using a non-weighted bus encoding scheme with the capability of tolerating a single-bit error in
the CDMA packet without adding extra wires to the bus. With this approach, relatively simple
code converters are added on both sides of the binary CDMA bus, while the conventional CDMA
encoder and decoder logic remains unchanged. The singe-bit error tolerance is accomplished by
limiting the magnitude of change in the sum-chip value, caused by a single-bit error, to the range
which can be tolerated by the conventional CDMA decoder assuming that all the remaining sum-
chips of the same CDMA packet are error-free. We also provide a manually designed encoding
scheme for 8-channel CDMA bus, and develop an algorithm for constructing a coding scheme for
2-channel binary CDMA bus from a known -channel code. When this encoding scheme is
used to design a reliable binary CDMA bus, simulation results show that a significant drop in the
post-decoding bit-error rate is achieved.

The remainder of this paper is organized as follows. In Section 2, we review Walsh-Hadamard

transform and its usage in on-chip CDMA-based communications. In Section 3, we present the
architecture of N-channel binary CDMA bus system. Section 4 describes the proposed encoding
scheme for binary CDMA bus system. Conditions for single-bit error tolerance are first derived,
and then the code constructing algorithm is presented. Section 5 presents an evaluation of the
proposed encoded and standard binary CDMA bus in terms of post-decoding bit-error rate.
Concluding remarks are presented in Section 6.

2. Walsh-Hadamard Transform

Walsh sequences found their use in CDMA-based communications because they are perfectly
orthogonal and satisfy a desirable set of auto- and cross-correlation properties. In this section, we
will briefly review the Walsh-Hadamard transform and its elementary properties which provide
the basis for on-chip CDMA communications.

The Walsh-Hadamard matrix of order = 2 is a symmetric square matrix with elements

+1 and -1 of size satisfying the orthogonality condition:

where is a transposition sign, and is an identity matrix of order . The Walsh-Hadamard

matrix of order = 2 can be constructed recursively as follows [19][20]:

21 21
2 = [, ]2 2 = , 1 = [1], = 1,2, .
21 21

The smallest examples of Walsh-Hadamard matrices are:

1 1 1 1
1 1 1 1 1 1
2 = , 4 =
1 1 1 1 1 1
1 1 1 1

4
Every row (or column) of is a Walsh sequence of length . Due to the symmetry of Walsh-
Hadamard matrices, the th Walsh sequence of
is , = ,0 , , ,1 = 0, , , 1, , = 0, , 1. The distinct Walsh sequences of
agree in /2 places and differ in /2 places. Therefore, the Walsh sequences are mutually
orthogonal, i.e.:

0
, , =
=

where dot operator, ., denotes the inner product of two vectors.

The Walsh-Hadamard transform (WHT) is defined as the matrix-vector product: = that

converts an input 1 column vector = [0 , , 1 ] of = 2 real numbers into the
output 1 column vector = [0 , , 1 ] of Walsh coefficients. The individual Walsh
coefficients of can be computed as the inner products between the Walsh sequences and the
input vector:
1

= , = , , = 0, , 1 (1)
=0

The inverse WHT (I-WTH) is identical to the foreword one, except for the multiplication
1
factor 1/: = . Given a vector of Walsh coefficients, the individual elements of the

input vector can be computed as:
1
1 1
= , = , , = 0, , 1 (2)

=0

The WHT is an example of a generalized class of Fourier transforms, which performs orthogonal,
symmetric, and linear operation on 2 real numbers. The WHT is used in many different
applications, including power spectrum analysis, digital signal processing, communications,
numerical analysis, combinatorics, and logical design and analysis. In the area of on-chip
communications, the WHT and I-WHT are used to separate different data streams on a shared
CDMA bus. The general principle of data transfer over the on-chip CDMA bus is illustrated in
Fig. 1. In this context, the input vector of the WHT contains only elements +1 and -1, where
each element represents a bit of information (0 or 1) originating from one of separate data
sources. Also, elements of the matrix are usually called chips, and the Walsh coefficients are
called sum-chips. At the transmitting end of the CDMA bus, the WHT block converts the data
vector into a CDMA packet , comprising the sequence of sum-chip values. At the receiving
end, the I-WHT block is used to reconstruct the original data streams. Connectivity between the
sources and sinks of data streams is determined by the distribution of Walsh sequences over the
sinks. To accept a specific data stream, the sink has to be configured with the Walsh sequences

5
associated with that data stream. This allows various forms of connectivity, including unicast and
multicast.

WHT block I-WHT block

wN,0 wN,0
d0 d0
data stream 0 data stream 0
wN,1 wN,1
d1 d1
data stream 1 data stream 1
c
.. CDMA bus ..
. .
wN,N-1 wN,N-1
dN-1 dN-1
data stream N-1 data stream N-1

Fig. 1. General principle of on-chip CDMA data transfer

3. Binary CDMA bus

The architecture of a MPSoC based on the binary CDMA-bus is shown in Fig. 2. The -channel
CDMA-bus subsystem provides a simultaneous transfer of up to = 2 bit-streams from the set
of source nodes to the set of destination nodes. The system operates synchronously: the
source nodes generate data bit-streams with a bit frequency , while the entire CDMA
subsystem operates on a chip frequency, , which is times higher than the bit frequency. To
each source and destination node a Walsh sequence generator (WSG) is associated. The WSG
outputs chips of a Walsh sequence at frequency . The output sequence of the WSG
associated to a source node is fixed to , . On the other side, the WSG of each destination
node is configurable with any Walsh sequence , , = 0, , 1, to allow reception of a bit-
stream from an arbitrary source node. The bit-streams from different source nodes are applied to
the CDMA encoder bit-by-bit. During the th chip interval of a bit period, the CDMA encoder
computes the sum-chip according to (1). The computed sum-chip is transferred over the
CDMA bus to all destination nodes. Blocks denoted as Line_encoder and Line_decoder in Fig. 2
are omitted in the conventional binary CDMA bus [8], [9], and the sum-chip is transferred over
the bus without any modification or conversion, i.e., = +1 , = 0, , . At each destination
node, the received sum-chip is processed by the local CDMA decoders according to (2): the sum-
chip is multiplied with the chip currently present at the output of the local WSG and their product
is added to the sum of previous products. At the end of the bit period (i.e. after chip intervals),
each CDMA decoder decides on the final value of the data bit and then output the bit to its
destination node.

6
 CDMA encoder
@fchip = N x fbit CDMA packet

..
.
WSG xN-1 zn sn+1
Source
dN-1 sum-chip: 0 1 N-1
node

..
zn-1 sn bn
N-1

..
@fbit
0
zn-2
..
sn-1
Line
..
bn-1

. .
CDMA bus
.
encoder

.
@fchip = N x fbit
b0
@fchip = N x fbit z1 s2
WSG x0 z0 s1
Source d
0
node s0

.. ..
. .

.. ...
0 0
Line Line

.
@fbit decoder decoder
0 0
@fchip = N x fbit @fchip = N x fbit

..
.

..
.
CDMA CDMA
WSG WSG
decoder decoder

Destin. Destin.

.
..
node node
0 N-1
@fbit @fbit

Fig. 2. N-channel binary CDMA bus

3.1. CDMA Encoder/Decoder

We will consider now the operation of the CDMA encoder and CDMA decoder in more details.
The hardware implementation of the WHT block (the task of the CDMA encoder) and I-WHT
block (the task of the CDMA decoder) is complicated by the fact that the elements of Walsh-
Hadamard matrix are bipolar values +1 and -1, and the inner products in (1) and (2) involve
arithmetic multiplication and addition operations. To simplify the digital design, the bipolar
values +1 and -1 are represented with logic values 0 and 1, respectively. The mapping between
bipolar and logic representations can be expressed as:

1
=
(1 ) (3)
2
where, {1, +1} is a bipolar, and {1,0} is a logic value. This simple linear mapping
allows the usual multiplication operation in (1) to be implemented by using an exclusive or
(XOR) operation. However, the summation of product terms in (1) is more involved, and is
accomplished in two steps. As can be seen in Fig. 2, to obtain the sum-chip value, the
combinational logic block zeros counter (designated with 0) counts the number of zeros in the
vector (1 , 2 , , 0 ) present at the output of the XOR array, and then the resulting sum is
adjusted with a simple logic circuit. The sum at the output of the zeros counter block equals:
1

= (1 ) (4)
=0

Let = , be the the product term in (1), and let = = 1

=0 be the value of the sum-
chip . By substituting (3) in (4), and rearranging we obtain:

7
 = 2 (5)
Because the sum is an integer value and is within a range [0, ], where = 2 , it can be
represented as an ( + 1) - bit number ( , 1 , , 0 ). Hence, the equation (5) can be
represented in a binary form as shown in Fig. 3(a).

zn zn-1 sn+1 sn
0 0 1 1
zn zn-1 zn-2 ... z0 0 0 1 0 0
- 0 1 0 0 0 1 0 0 1 +1 =
1
sn+1 sn sn-1 s1 s0 1 1 1 0 =
1
(a) (b)
Fig. 3. Binary interpretation of the equation (5): a) subtraction scheme; b) truth table

From Fig. 3(a), it is evident that the transformation (5) changes only the two most significant bits
of according to the truth table in Fig. 3(b). It should also be noted that the least significant bit
of the sum-chip value, 0 , is always 0, and it does not have to be transmitted instead, the
constant zero bit is simply appended at the receiver end. Therefore, the width of the CDMA bus
needed to transfer a single sum-chip value is + 1 bit-wires.

The CDMA decoding scheme is depicted in Fig. 4. According to (2) the received sequence of
sum-chip values, , is decoded by computing the correlation with a specific Walsh sequence of an
individual source node. Because each element in the Walsh sequence , is interpreted as either
+1 or -1, the multiplication in (2) acts as sign change of the sum-chip value if the corresponding
bit of the Walsh sequence is -1. Consider a destination node configured with the Walsh
sequence , , and let = 1
=0 , be the value of summation term in (2). If sum-chips are
received without errors, then can take only two values: (if the value of the original bit is
0) or (if the original bit value is 1). A more general decoding rule is the one in which the
value of the decoded bit is decided by the sign of : If is positive, the bit is decoded as 0;
otherwise, the bit is decoded as 1:

0 0
= () =
1 <0 (6)

where is the signum function. Let us note that the decoding rule (6) allows tolerance of
transmission errors to some extent. Also note that, strictly speaking, the value of the decoded bit
is undermined in the case of = 0.

8
 0

CDMA
bus +-
>
Accumulator > D
E FF
Q
Decoded
data
From
E clr >
WSG
0 add; 1 - subtract @fchip @fdata @fdata

Fig. 4. CDMA decoder

Example 1. To illustrate the operation of binary CDMA bus, let us consider the following
example. Suppose that the data bit-vector = [1 0 0 0] (i.e. [1 1 1 1] in bipolar representation)
is transferred over the CDMA bus from the set of = 4 source nodes to the set of 4 destination
nodes. At the transmitting end, the data bit-vector is transformed into the CDMA packet =
4 = [2 2 2 2] . The sum-chips are transferred as 2s complement binary numbers
with the least significant bit truncated: 001, 111, 111, 111. At the receiving end, the omitted
zero bit is appended, and the I_WHT is applied on the CDMA packet. Assuming that the th
destination node is configured with the Walsh sequence 4, , = 0, ,3, the I_WHT produces
= 4 = [4 4 4 4] , where the th element in corresponds to the value present in the
accumulator of the th destination node at the end of bit period.

3.2. Sum-chip transfer

When a sum-chip is transferred from the CDMA encoder to the CDMA decoders, transient errors
on the bus wires can cause the received sum-chip value to be different than the original value
sent. Let and be the original (i.e. transmitted), and received sum-chip values, respectively.
Then, = , where symbol denotes a bitwise exclusive-or operation, and is the error
pattern, i.e. a bit-vector of length + 1 in which the th bit being set means that the th bit of the
original sum-chip is flipped during data transfer. We use 0 to denote the error vector of all zeros
(corresponds to error-free data transfer). Similarly, 1 denotes an error pattern with exactly one
1 bit. In our error model, the term single-bit error means that all sum-chips of a CDMA packet
are associated with 0 except one which is affected by 1 . Note that in the binary CDMA bus,
where every sum-chip of a CDMA packet is a specific mixture of data bits originated from
different sources, even a single-bit error may affect decoding of multiple data bits, as illustrated
in the following example.
Example 2. Consider again the transfer of the data vector = [1 0 0 0] over the binary CDMA
bus, but now with an error e1 of pattern 100 occurring on the CDMA bus during the second chip
period, so that the destination nodes will receive 011 instead of 111. This single-bit error changes
the value of the second sum-chip from -2 to 6. The result of the decoding process is: =
4 [2 6 2 2] = [4 8 12 4] . Comparing this result with the error-free scenario in
Example 1 shows that a single erroneous sum-chip changes chip summations at all destination
nodes. The magnitude of this change is 8 at each position, and it equals the weight of the flipped
sum-chip bit. The erroneous decoded data bits occur at the positions where the sign of change is

9
opposite to the sign of the correct summation value. As can be seen, only the third summation
keeps the original sign. A similar effect appears with other 1 error patterns, but with a smaller
error magnitude. The 1 error pattern of 010 at any one of sum-chips will increase or decrease
every chip summation by the value of 4. Although the error magnitude of 4 cannot alter signs of
summations, it can change some of them to zero, thus preventing decoding of the original data
bits. Note that the binary CDMA bus is resilient to the single-bit errors of pattern 001 because the
error magnitude of 2 is too low to change the original signs of the chip summation values. In
general, for any , the critical single-bit error patters are those with 1 at two leftmost bit
positions.

4. CDMA bus encoding scheme

In this section, our goal is to design a bus encoding scheme that can tolerate a single-bit error in
-channel binary CDMA bus based system. The main idea of our approach is to replace the
weighted binary code with a code in which the error magnitude of any 1 error pattern will be
smaller than . At the hardware level, introducing a bus encoding requires the insertion of: one
line_encoder block and line_decoder blocks (see Fig. 2). The line_encoder block converts the
sum-chip value at the output of the CDMA encoder into a line codeword which is distributed by
the CDMA bus. At each destination node, the line_decoder block converts the line codeword
back into the original sum-chip value for further processing by the CDMA decoder.

The minimum width of any encoded CDMA bus is determined by the number of different sum-
chip values that can appear at the output of the CDMA encoder. An important property of WHT
of an input vector of length = 2 with elements in {1, +1} is that it produces sum-chips that
can only take + 1 different values from the set of even integers within the range [, ].
Therefore, the minimum width of the binary CDMA bus is = 2 ( + 1) = + 1.
Because the bus with + 1 bit lines can actually relay any of 2+1 = 2 different bit patterns in
each cycle, there are 1 bit patterns that never appear on the CDMA bus (in the absence of
transmission errors). In the sequel of the section, we will provide a bus encoding scheme which
exploit this inherent information redundancy of the binary CDMA in order to ensure the fault
tolerance under single-bit error assumption without adding new bus lines.

The single-bit error correcting encoding scheme for -channel binary CDMA bus, named the
CDMA line encoding, , is defined by a pair of functions: the encoding function
(implemented by line_encoder block), and decoding function (implemented by each
line_decoder block). The function is a one-to-one mapping from the set of + 1 sum-chip
values to the set {0,1}+1 of binary codewords of length + 1. On the other hand, in general, the
function is a many-to-one mapping from the set of codewords to the set of sum-chip values. An
encoding scheme can be represented in a form of a bipartite graph whose vertices are
divided into the set of sum-chip values and the set of codewords such that every edge
connects a vertex in to one in . Fig. 5 shows an example of a graph representation of a

10
hypothetical 4 encoding scheme. The arrows indicate the direction of mapping: downside
arrows define the encoding function, and upside arrows define the decoding function.

sum-chips (set C)

-4 -2 0 2 4

E D

000 001 010 011 100 101 110 111

line codewords (set V)

Fig. 5. CDMA bus encoding scheme as bipartite graph

A codeword is the primary codeword if there exists a sum-chip value so that =

(). In there are + 1 primary codewords. For example, in Fig. 5, the sum-chip of value -
4 is mapped into the primary codeword 000, and the primary codeword 000 is mapped back
into the same sum-chip value. In fact, for any sum-chip value the following is true: () =
. For the remaining 1 (non-primary) codewords there are two options on how each of them
can be included into the encoding scheme: either as secondary or non-valid codeword. A non-
primary codeword is a secondary codeword if it is decoded as a sum-chip value, i.e. the
decoding function () is defined for . A codeword is the non-valid codeword if it is neither
primary nor secondary codeword. The decoding function is not defined for non-valid codewords,
and as such they are discarded before CDMA decoding. For CDMA decoding based on I-WHT,
discarding a received sum-chip has the same effect as using the value of 0 for that sum-chip. In
fact, with such CDMA decoding, non-valid codewords may be interpreted as secondary
codewords of the sum-chip of value 0, and their decoded value is 0. Therefore, in the sequel we
assume () = 0 for any non-valid codeword . In Fig. 5 the non-valid codewords are
designated with a cross sign.

Let (, ) be the Hamming distance between codewords and from the set , i.e., the number
of bit positions at which and are different. Codewords and are neighbors if (, ) = 1.
If a codeword suffers an 1 error, then it will be changed into one of its + 1 neighboring
codewords. If (, ) > 1, then cannot be changed to under any 1 error.

Example 3. Consider 4 in Fig. 5. Let the codeword = 000, which is the primary codeword
of the sum-chip value -4, suffers the single-bit error 1 = 001. With the rightmost bit flipped, the
codeword becomes = 001. Because 001 is the secondary codeword of the same sum-chip
value, this 1 error is corrected by the line decoders. Such immediate error correction is possible
only for a few combinations of sum-chip values and 1 error patterns due to the limited number
of available line codewords. For example, the single-bit error 1 = 010 changes = 000
to = 010, which is the primary codeword of some other sum-chip value. In this case, after line

11
decoding, the CDMA decoders receive the sum-chip value -2 instead of -4. For correcting such
single-bit errors we have to rely on the properties of the I-WHT.

Assume that the CDMA packet = [0 , 1 ] is affected by a single-bit error 1 at th

sum-chip position. Due to this error, the CDMA decoders of all destination nodes receive the
erroneous CDMA packet = [0 , 1 ] in which the sum-chip is replaced with the
value = (( )1 ). Let us focus on a destination node whose WSG is configured with the
th Walsh sequence , = ,0 , , ,1 , = 0, , 1. If is a result of the inner-
product between the correct CDMA packet and the Walsh sequence , , then the result of the
inner-product between the erroneous CDMA packet and , is:
1

= , = , + , = , ( )

=0

According to (6) the condition for single-bit error correction is ( ) = (), that is:

( , ( )) = ()

Because the summation can only assume two different values, and , and , is either +1
or -1, the previous condition is fulfilled if the following inequality is true:

| | < (7)
Note that the condition (7) is what we intuitively deduced in Example 2: a single-bit error in
CDMA packet is tolerated if the magnitude of error is lower than .
The condition (7) imposes the following two constraints on the encoding and decoding functions
of the .
Constraint 1. Let = ( ) be the primary codeword of the sum-chip value , and let ( ) =
{ |( , ) = 1} be the set of s neighboring codewords. Then, {( )| ( )}.
Since there are + 1 codewords in ( ), the erroneous sum-chip = 1 can assume at
most + 1 different values. The condition (7) implies that the absolute difference between the
sum-chip value and the decoded value of any neighboring codeword of must be strictly less
than .

Constraint 2. If = 0, then the inequality (7) is true for any sum-chip value except and .
This means that the set of neighbors of the primary codeword for the sum-chip value ()
must not include codewords that decode to 0. In particular, if is the primary codeword of the
sum-chip value , then each neighboring codeword of need to decode to a positive-valued
sum-chip, i.e. to one of /2 = 21 sum-chip values in the set {2, 4, , }. Similarly, if is the
primary codeword of the sum-chip value , then all its neighboring codewords must represent
negative-valued sum-chips, i.e. those in the set {, + 2, , 2}.

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A direct consequence of Constraint 2 is that the set of neighbors of the primary codeword of sum-
chip () must not contain non-valid codewords. This observation leads us to the following
property of the .
Property 1. The minimum number of secondary codewords in is:
2( 2(22 1)) (8)
Proof: In there are 21 1 positive sum-chip values different than . Consequently,
among + 1 neighbors of the primary codeword of sum-chip value , there are at most 21
1 neighbors that are primary codewords. Due to Constraint 2, the remaining 2(22 1)
neighbors must be secondary codewords that are decoded into positive sum-chip values. The
same number of secondary codewords is due to the sum-chip value . In total, the minimum
number of secondary codewords is equals the Eq. (7).

5. Construction of CDMA bus encoding scheme

In this section we will use the constraints introduced in Section 4 in order to construct the
encoding scheme . We will first prove the nonexistence of 4 . Then we will present 8 ,
and finally, provide a procedure for constructing 2 code from the known code.

For implementation of 4 9 codewords are required: 5 primary codewords and 4 secondary

codewords (due to Property 1). Since the codeword length in this case is + 1 = 3, the number
of different codewords in 4 is 8. Hence, we conclude that the construction of 4 is not
possible.

Note that according to Property 1 the minimum number of secondary codewords in 8 is 2. For
> 8 (i.e. > 3), the eq. (8) evaluates negative values. Therefore, the Property 1 does not
impose any requirements related to the number of secondary codewords that have to be included
into the for > 8.

Fig. 6 shows the 8 encoding scheme as 4-dimensional hypercube graph: a graph whose nodes
are codewords and edges connect the neighboring codewords (i.e. those at Hamming distance of
1). Dark nodes are primary, white nodes are secondary, and crossed nodes are non-valid
codewords. Each valid codeword is associated with the sum-chip value (). In 8 the
codewords are of length 4. Among 16 codewords, there are 9 primary and 2 secondary
codewords. The remaining 5 codewords are non-valid.

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 0110 0111 1110 1111
-6
0100 0101 8 1100 1101
2 8 6

-2 -8 -8
0010 0011 1010 1011
0 4 -4
0000 0001 1000 1001

Fig. 6. Hypercube representation of

The 8 is constructed by first fixing the primary codewords for sum-chip -8, 0, and 8, so that the
codewords for -8 and 8 are at the maximum Hamming distance of 4, and the codeword for sum-
chip 0 is at the distance of 2 between either of them. These codewords are: 8 = 1010, 0 =
0000, and 8 = 0101. Codewords for positive sum-chip 2, 4, and 6 are chosen from the set of
neighbors of 8 . Due to Constraint 2, the forth neighboring codeword of 8 is declared as the
secondary codeword with the decoded sum-chip value of 8. Similarly, codewords for sum-chips -
2, -4, and -6 are all neighbors of 8 , and the forth remaining neighbor of 8 is declared as the
secondary codeword of the sum-chip -8. Remaining 5 codewords are non-valid in this encoding
scheme. With such codeword selection, the Hamming distance of 1 exists only between
codewords for sum-chip values of the same polarity. Because the absolute difference between
any two sum-chips of equal polarity is smaller than , the basic requirements of CDMA bus
encoding scheme capable of correcting single-bit errors (Constraint 1) is satisfied.

Now we will present the recursive procedure for constructing the encoding scheme 2 starting
from . The contains /2 positive and /2 negative sum-chips in addition to the sum-
chip 0. By doubling , the sets of positive and negative sum-chips are doubled, too. The
codeword length of 2 is one bit longer in respect to . The basic idea of the code
construction procedure is to keep all zeroes as the primary codeword for sum-chip 0, and
append to each non-zero primary codeword of a single bit of value 0 or 1 to obtain two
primary codewords of 2 . Formally, this construction procedure is defined by the following
two rules:

Rule 1 (primary codewords): Let = () be the primary codeword of a sum-chip in , and

let the symbol & denotes an operator for concatenating two binary strings. Then, in 2 :

&0 is the primary codeword of the sum-chip ;

&1 is the primary codeword of the sum-chip + () .

Rule 2 (secondary codewords): If is the secondary codeword of the sum-chip {, }

in , then in 2 :

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 &1 is the secondary codeword of sum-chip () 2.

The correctness of the Rule 1 follows from the simple fact that by appending two equal-length bit
strings with the same number of arbitrary bits does not decrease the Hamming distance between
them. According to the Rule 1, the primary codewords of the positive sum-chips in 2 are of
the form &, where {0,1} and is the primary codeword of a positive sum-chip in .
The same holds for the primary codewords of the negative sum-chips in 2 , which are of the
form &, where {0,1} and is the primary codeword of a negative sum-chip in . Due
to Constraint 1, the condition , > 1 is satisfied. Since the condition &, &
, is valid for any and the Constraint 1 is fulfilled in 2 , too.

Due to Rule 2, the secondary codewords are always associated with the sum-chips of maximum
and minimum values, ensuring that flipping a single bit of their primary codewords will result in
generating a codeword of the same-polarity sum-chip (as required by the Constraint 2).

8 16
sum-chip primary secondary primary secondary
codeword codeword codeword codeword
16 01011 01111
14 11011
12 00011
10 01001
8 0101 0111 01010
6 1101 11010
4 0001 00010
2 0100 01000
0 0000 00000
-2 0010 00100
-4 1000 10000
-6 1110 11100
-8 1010 1011 10100
-10 00101
-12 10001
-14 11101
-16 10101 10111
Fig. 7. and

Example 4. Fig. 7 tabulates the encoding schemes 8 and 16 . It is easy to see how 16 is
constructed from 8 . For example, 0100 is the primary codeword of the sum-chip 2 in 8 .
Starting from this codeword we produce two primary codewords in 16 : 01000 is for sum-chip
2, and 01001 for sum-chip 10. Similarly, starting from the primarily codeword 0010 of the sum-
chip -2 in 8 , we obtain codewords for two negative sum-chips in 16 : 00100 is for -2, and
00101 is for -10. Also, the secondary codeword 0111 of 8 with appended bit 1 becomes the

15
secondary codeword 01111 in 16 . For example, flipping any bit of the codeword 01011
(primary codeword of sum-chip 16) results in either a primary codeword of a positive sum-chip
or in the secondary codeword of sum-chip 16, which is in accordance with the Constraint 2.
Similar observation holds for the sum-chip -16.

6. Simulation results

In this section, we will present and discus the simulation results on the effectiveness of the
proposed approach for improving the fault tolerance performance of the binary CDMA bus. We
adopt 8-, 16-, and 32-channel binary CDMA bus to simulate the proposed bus encoding scheme.
The architectural parameters varied in summations were: a) the size of the system (), and b) the
bus encoding scheme: standard (transfer of sum-chip values as 2s complement binary numbers),
and encoded (transfer of sum-chips encoded with the proposed encoding method). During each
simulation run, each source node transmitted a continuous data stream of a random content, and
each destination node received one data stream (i.e. it was configured with the unique Walsh
sequence). Transient bit errors were injected by directly flipping the individual bits of the
codewords transferred over the binary CDMA bus, according to a specific error model. Two error
models were considered: the multiple-bit error model, and the binary symmetric channel (BSC)
error model. After processing the CDMA packet at each destination node, the decoded data bits
were compared with the original values. The fault tolerance performance of different system
configurations were compared in terms of the post-decoding bit error rate (BER). In our case, the
post-decoding BER is defined as the ratio between the number of data bits received in error in
respect to the total number of data bits received.

6.1. Multiple-bit error model

In the first set of simulations, we examine the error resilience of the standard and the proposed
encoding schemes to single- and multiple-bit errors by injecting a fixed number of bit-errors at
randomly chosen bit positions of every CDMA packet transferred over the bus. Table 1 reports
the BER obtained for {1,2,3,4,5}. The BER data in this table are computed by averaging over
107 CDMA packets. Without the bus encoding, even single-bit errors produce a significant
fraction of data bits that could not be recovered. For example, in 8-channel CDMA bus system,
20.6% of all received data bits are incorrectly decoded, and the percentage increases with an
increase of the number of bit-errors injected into CDMA packet. Higher resilience to single- and
multiple-bit errors of larger CDMA bus systems is due to their wider buses. As shown in Section
3, in the standard binary CDMA bus system, a data bit is incorrectly decoded only if an error
impacts the two most significant bit positions of the sum-chip. Hence, as a bus is wider, the
probability of uncorrectable bit-error to occur is lower. However, even in the 32-channel CDMA
bus system, the post-decoding BER under single-bit error condition is still substantial.

Table 1. Reduction of post-decoding BER by using LCN under multiple-bit error model
N=8 N=16 N=32

16
 standard encoded standard encoded standard encoded
1 0.206 0 0.159 0 0.130 0
2 0.304 0.094 0.249 0.006 0.212 0.0019
3 0.342 0.152 0.297 0.031 0.263 0.0089
4 0.363 0.209 0.328 0.059 0.296 0.0207
5 0.387 0.249 0.343 0.086 0.318 0.0341

The inclusion to the proposed bus encoding scheme not only provides the single-bit error
tolerance, but also improves BER performances of the binary CDMA bus in the presence of
multiple-bit errors. For example, implementing the 8 bus encoding scheme in an 8-channel
binary CDMA bus system results in the reduction of the post-decoding BER in the presence of
double-bit transmission errors from 30.4% to 9.4%. In should be noticed that the improvement in
post-decoding BER in the presence of multiple-bit errors notably decreases with the increase of
the system size. As indicated in Table 1, with the use of 32 , the double-bit error affects only
0.19% of data bits, on average, which represents a two orders of magnitude improvement over
the standard binary CDMA bus.

6.2. BSC error model

In the second set of simulations, each wire of the -channel binary CDMA bus is modeled as an
independent binary symmetric channel with a crossover probability [21]. With BSC channel
model, the probability that a bit of an encoded sum-chip will be received incorrectly is
independent of the actual bit value itself, and the fault affecting a given bit is independent of that
affecting other bits of the sum-chip as well as bits of the preceding or succeeding sum-chips. Fig.
8 compares the post-decoding BER of the standard and encoded bus in 8-, 16- and 32-channel
binary CDMA bus systems for different crossover probabilities. A lower post-decoding BER and
a steeper slope of BER curves in the encoded in respect to the standard CDMA bus systems
clearly indicates that the proposed encoding scheme improves the fault tolerance capability of the
binary CDMA bus system, independently of its size. Consistently lower post-decoding BER of
the encoded over the standard CDMA bus is due to the ability of the proposed encoding scheme
to tolerate single-bit errors and its improved resilience to multi-bit errors. When the crossover
probability is low, the vast majority of erroneous CDMA packets are corrupted by single-bit
errors. Such bit-errors are harmless in the encoded bus, but they may produce post-decoding
errors in the standard bus. With the increase of the crossover probability, multi-bit errors start to
appear more often. Although the proposed encoding scheme does not tolerate bit-errors of
multiplicity larger than one, the probability of their correction is significantly higher than in the
standard bus.

17
 Fig. 8. Post-decoding BER versus crossover probability of BSC for standard and encoded CDMA
buses of different sizes

It can also be observed from Fig. 8 that the post-decoding BER is lower in smaller standard
binary CDMA bus systems than in larger ones, which might seem to be in contrast with the
results on multiple-bit error resilience given in Table 1. In fact, when the crossover probability is
kept constant and the system size increases, there are two opposing tendencies which determine
the post-decoding BER. On one hand, as the bus is wider, the chance for a bit-error to produce
the post-decoding error is lower. On the other hand, in larger CDMA bus systems, the length of
CDMA packet is larger, too, and consequently the larger is the chance for a CDMA packet to be
contaminated with multiple-bit errors. Because an incremental increase in system size adds only
one bus wire, but it doubles the number of sum-chips in CDMA packet, the second tendency
prevails. Fig. 8 indicates that the post-decoding BER difference between the binary CDMA buses
of different sizes is smaller in encoded than in standard systems. This observation suggests that
the gain in BER achieved by adding a wire to the encoded bus practically compensates the loss in
BER due to doubling the CDMA packet length.

7. Conclusion

With an ability to support simultaneous transmission of multiple data streams in multi-processor

systems on chip, the CDMA-based shared bus is seen as a promising solution to alleviate the
contention and queuing delay experienced by a conventional time-division multiplex (TDM) bus.
However, providing fault tolerance in the CDMA-based bus system is more difficult than in the
conventional TDM bus. In contrast to the TDM bus, where a transient error occurring on the bus
corrupts only data that is transferred during the bus cycle when the error occurs, in the CDMA

18
bus, even a single-bit error may affect the correct decoding of multiple simultaneously transferred
data streams. In this paper, we have approached the problem of improving the fault-tolerance
capability of the CDMA-based bus through involving a bus encoding scheme adapted to specific
properties of CDMA-encoded data stream. The presented technique is applicable to the on-chip
CDMA-based interconnect systems that use Walsh-Hadamard transform for orthogonal encoding,
and binary CDMA bus for data transfer. An important feature of the proposed technique is that
the improvement in fault-tolerance capability is accomplished without adding extra wires to the
bus, but only relying on the information redundancy inherently involved in CDMA transmission.
Simulation results show that this low-cost fault-tolerance scheme improves post-decoding bit
error rate performance of the binary CDMA bus. Finally, it should be pointed out that, in this
paper, we have considered the shared bus as an isolated part of the complete CDMA-based on-
chip communication subsystem. An interesting topic for future research could include the study
of alternative CDMA decoding methods, with improved fault-tolerance capability in respect to
the standard correlation CDMA decoder.

Acknowledgement

This work was supported by the Serbian Ministry of Education, Science and Technological
Development, Project No. TR-32009 Low-Power Reconfigurable Fault-Tolerant Platforms.

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