Académique Documents
Professionnel Documents
Culture Documents
MUSIC CIRCUITS
The Blacksburg Continuing Education'M Series
The Blacksburg Continuing Education SariesT " of books provide a Laboratory-or experiment.
oriented approach to electronic topics. Pr_nt and forthcoming titles in this series include:
In most cases, these books provide both text material and experiments, which permit one to
demonstrate and explore the concepts that are covered in the book. These books remain among
the very few that provide step.by-step instructions concerning how to learn basic electronic con
cepts, wire actual circuits, test microcomputer interfaces, and program computers based on popu
lor microprocessor chips. We have found that th"e books are very useful to the electronic novice
who desires to join the "electronics revolution," with minimum time and effort.
FIRST EDITION
FIRST PRINTING-1982
BARRY KLEIN
CHAPTER 1
CHAPTER 2
CHAPTER 3
CONTROL VOLTAGE GENERATORS, PROCESSORS, AND CON-
TROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Controllers-Control Voltage Generators-Control Voltage Processors
CHAPTER 4
CHAPTER 5
FILTERS III
Filter Basics-Voltage Controlled Filters-Fixed Filter Circuits
CHAPTER 6
CHAPTER 7
CHAPTER 8
APPENDIX A
APPENDIX B
IC DATA SHEETS AND PIN DIAGRAMS . . . . . . . . . . . . . . . . . . . . 234
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
SYNTHESIZER SYSTEM
DESIGN
9
Pitch
The pitch of a sound is perceived in the listener's mind-not
read on a meter. Pitch is often thought to be the same as fre-
quency. They are related but separate properties. Frequency is
the measurement of a waveform's repetition rate. Frequency is
measured in cycles per second, or hertz (Fig. 1-2). One-
thousand hertz is called one kilohertz.
- 1 Hz (FUNDAMENTAL)
- 2 Hz (SECOND HARMONIC)
- 4 Hz (FOURTH HARMONIC)
o 0.5
TIME (SECONDS)
10
HARMONIC HARMONIC
WAVEFORM DESIGNATION CONTENT AMPLITUDE RELATIONSHIPS
rv- SINE 0 0
Timbre
Finally, one of the most important characteristics (and hardest
to duplicate) of a sound is its tonal character, or timbre. This is
the character of a musical tone that distinguishes one musical
instrument from another playing the same tone. It is mostly a
sound's variation in frequency content (not pitch) with time.
The time variable is the impOltant characteristic to remember if
11
TIME
SYNTHESIS TECHNIQUES
12
user. Therefore most of these systems exist in university labs
and studios and not in music stores.
Additive Synthesis
Additive synthesis is a method of sound generation char-
acterized by the summation of pseudo-harmonically related
sound sources (usually sine wave) with slowly varying ampli-
tudes, frequencies, and/or phases.
Small additive systems can be made up of analog modules
such as those used in subtractive systems (Fig. 1-5). Several
exponential vco's (voltage controlled oscillators) would be ini-
tially set up at the desired pseudo-harmonic frequencies. In this
type of veo the frequency gencrated by the oscillator is an ex-
ponential function of the voltage input (Fig. 1-6). All vco's
share a common control voltage (CV) from the keyboard. Thus,
with a change in key position on the keyboard, the pitch would
change but the harmonic relationships (timbre) would remain
constant. Separate yoltage controlled amplifiers are placed on
the outputs of the vco's. Each voltage controlled amplifier is fed
its own control envelope. Thcn all voltage controlled amplifier
outputs are summed together. The end result simulates the
changing harmonic content of a natural sound.
Larger systems are dcsigned with digital circuitry. Before
such a system is constructed, a selected sound, such as middle
C on the piano, is first analyzed for varying frequency content.
Then digital oscillators are made to produce waveforms for each
harmonic present in the analyzed sound (Fig. 1-7). The
waveform consists of a large number of sequential amplitude
stcps. Each step is represented digitally. All of the step codes
for one complete cycle of the waveform are stored in memory.
The memory is scanned serially from start to finish and back
again for as long as the waveform is desired. The rate at which
the memory is scanned determines the frequency; the fre-
quency equals the sample rate divided by the number of steps
per cycle. Usually, though, the scanning rate is crystal con-
trolled for stability, and, instead, the digital code (the waveform
memory address) is incremented to changed frequency.
Amplitude control is achieved by multiplying the digital code
by another digital code stored in another "envelope" register.
The final digital code is fed to a digital-to-analog converter
(dae) and low-pass filtered so that all high-frequency eompo-
13
VOLTAGE VOLTAGE
CONTROLLED 1 CONTROLLED p--
OSCILLATOR AMPLIFIER
(VCO) (VCA)
rA
J
21 VCA
VCO 0---
i
B
--
.--- MIXER
OUTPUT
,--0
--
31 p..-
VCO VCA
i
41
VCO VCA P--
D A
i B A
cv C
=>--
ENVELOPE
D r--\..
KEYBOARD
GENERATOR
=>--
14
VOLTAGE IN
I, .-------, ,
,,
, ,,
-- - - - -- - - - - - - - - - - - - - - - - - - - - - --- - - - --I
AMPLITUDE
(ENVELOPEI
REGISTER
,, ,,
,
l
,
,
___________________________ --J
MIXER
OUTPUT ADDITIONAL
OSCILLATORS
15
trol over frequency content of a note with time (more natural
sounds) but has the disadvantages of complexity, high cost, and
great difficulty in programming in real time. (Real time means
"while you are playing.") To change a parameter in the sound
with a large digital additive system, a new computer program
must be initiated.
Nonlinear Synthesis
Frequency modulation (fm) is a nonlinear synthesis tech-
nique employing two oscillators, one modulating the frequency
of another. The modulated oscillator output consists of fre-
quency sidebands on either side of (and including) the original
(unmodulated) frequency. The number of partials in this
waveform depends on the modulation index, which is the ratio
of frequency deviation to the frequency of the modulating wave.
Like additive synthesis, fin can be employed using analog
synthesizer modules (Fig. 1-8). Many veo circuits now include
linear frequency control inputs for this purpose. Frequency
modulation produces sounds that are more natural sounding
with less equipment.
Frequency modulation is enjoying popularity with computer
music enthusiasts also. Digital oscillators are employed that are
similar in design to those used in additive systems, except for
the fm capability. Due to the smaller amount of circuitry
needed, the computer's speed requirement is not as great. Con-
sequently, some real-time, fin synthesis systems do exist.
Other examples of nonlinear synthesis include any methods
that distort the original waveform in a nonlinear fashion. These
may include full-wave rectification, variable clipping circuits,
CONTROL
VOLTAGE
lEXP !EXP
VOLTAGE VOLTAGE VOLTAGE
CONTROLLED CONTROLLED CONTROLLED
OSCILLATOR AMPLIFIER LIN OSCILLATOR
CONTROL
ENVELOPE
Fig. 1-8. Fm synthesis using analog modules.
16
Fig. 1-9. A digital synthesizer capable of linear fm. (Courtesy Bell
Laboratories)
17
VOLTAGE 141- VOLTAGE VOLTAGE
CONTROLLED CONTROLLED CONTROLLED -----<) OUTPUT
OSCILLATOR SAW FILTER ATTENUATOR
i i
CV /--.
GATE
KEYBOARD ENVELOPE
TRIGGER GENERATOR
18
Fig. 1-11. The Moog System 55 synthesizer. (Courtesy Moog Music, Inc.)
19
Fig. 1-12. The Sequential Circuits Prophet 5, a polyphonic synthesizer.
(Courtesy Sequential Circuits)
20
The sound is often enhanced by paralleling two tone-
generating sections that are slightly out of tune. When two notes
that are very near in frequency are mixed together, they audibly
"beat" against each other. This is called the ensemble effect. It
is a characteristic of natural instruments (ever tune a guitar?).
This type of synthesizer is often designed to imitate string sec-
tions of an orchestra. Usually the sounds available are preset
and may only be variable over a small tonal range.
21
TOP-OCTAVE GENERATOR
OCTAVE DIVIDERS
AND
SAWTOOTH CONVERTERS
CHORUS
(ANALOG DELAY LINE)
OUT
22
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
KEY POSITION
23
loOn VCo.}
EXPONENTIAL
100 n CURRENT OSCillATOR
SOURCE
TUNE VCo.2
EXPONENTIAL
>-..........- - - + 1 CURRENT OSCillATOR
SOURCE
I.",- CAPACITOR
STORAGE \ TUNE
LINEAR CONTROL
VOLTAGE
(1112 V PER NOTE-
1 V PER OCTAVE)
I CONTROL
I VOLTAGE OUT
GATE
ov11------------'-----'----------'----
Fig. 1-16. Keyboard timing signals.
TRIGGER
24
The most common timing signal is the gate. Its level is high
whenever a key is down. It is used to initiate the envelope
generator. When used with an ADSR-type envelope generator
(see Figs. 1-17 and 1-18), it will start the attack portion of the
envelope and, after the decay, will determine when the final
release portion of the envelope will occur.
I I I I
i I I I
: I
I I
I A = ATTACK
I
I D = DECAY
I S = SUSTAIN
I R = RELEASE
GATE
TRIGGER
ADSR
OUTPUT
25
The trigger can also be used to trigger sample and holds or
sequencers.
Most synthesizers use gate and trigger voltages that are at
least as large in magnitude as the signal waveforms. Typically
they are from 5 to 10 volts when high.
The module input accepting the timing signal(s) will usually
consist of a Schmitt trigger or comparator. These circuits are
level-sensitive circuits that change states when the input
crosses a determined threshold. The typical threshold in many
commercial synthesizers is 2 volts. Such an input structure
allowS slowly rising input voltages to act as trigger (or gate)
sources.
Input Structure
The most common input structure for control and signal volt-
ages is the op-amp summing node. This is the "-" input with
negative feedback. The circuit is basically an inverting sum-
ming stage.
The value of the 1 V/OCT control voltage input resistor is most
often a 100-kn low-tolerance (0.1 percent) type for gain accu-
racy and stability. This aids in reliable tracking of modules
within the synthesizer.
Output Structure
The output structure usually consists of a low-impedance
source followed by a l-kn resistor. This l-kn resistor protects
the low-impedance source from shorts to ground which may
accidentally occur when setting up a patch with patch cords.
The resistor also allows passive mixing by directly wiring two
(protected) modules' outputs together.
The only output that will not have a protection resistor will
be the control voltage output. A l-kn resistor in such a position
would create a I-percent error when fed into the 100-kn 1 V/OCT
input of a module.
Signal Levels
Most synthesizers output 10-volt peak-to-peak waveforms
from the oscillators. However, the center of the waveform swing
may be either 0 volts or 5 volts. This is because signal voltages
are usually plus and minus .5 volts, and control voltages are
usually 0 to 10 volts. Careful attention should be paid to these
26
signal levels because most module inputs are dc coupled. It will
not do any harm to wire 0-10 V to an input meant for +/-5 V,
but the result will probably not be as planned.
A level-translator module may be included in a system to
allow oscillator waveforms to function as control voltages (0-10
V) as well as sound source signals (+/-.5 V). Such a module
would employ op amps to shift +/-5-V signals to 0-1O-V
signals.
27
POWER SUPPLY CIRCUITS
28
RECTIFIER
REGULA TOR
FIL TER
V\.
Fig. 21. A basic power supply.
The Transformer
The voltage output of a transformer will vary, depending on
its load. This is due to the voltage drop created by the resis-
tance of the transformer secondary winding. With no load, very
little current is drawn through the transformer and the output
voltage is high. With a load, more current is drawn through the
transformer and the output voltage is lower. Most manufacturers
rate their transformers at full output current. These voltages are
expressed as rms (root-me an-square) voltages, which are 70.7
percent of the peak voltages. Typical no-load to full-load yoltage
29
output variation is about 20 percent. With a light load, the out-
put may be high enough to cause the regulator input voltage to
be above its maximum allowable value.
Secondary current ratings should be at least 1.2 times the load
current for the full-wave center-tap configuration and 1.8 times
the load current for the full-wave bridge configuration. For twin
i5-volt supplies a 36-volt ct (center tapped) transformer is fre-
quently used. For 5-volt supplies a i2.6-volt ct filament trans-
former is popular.
The Rectifier
The diodes in the rectifier circuit must be able to handle the
average current drawn by the load as well as any surge currents
due to turn-on transients or output shorts. In full-wave rectifier
circuits each diode passes an average of one-half of the output
load current. However, the rms ripple current into the filter is at
least twice the output current. The magnitude of the rms cur-
rent increases as the ripple voltage decreases. By increasing the
size of the filter capacitor in the power supply design, the ripple
voltage will decrease. Also, when the supply is first turned on,
the filter capacitor acts as a short circuit. During this time the
current is limited only by the secondary resistance of the trans-
former. Therefore the rectifier diodes must be able to handle
this current surge.
A good practice is to use diodes of at least twice the average
dc current drawn by the load. For the majority of circuits
i-ampere diodes are sufficient.
The peak reverse voltage (prv or piv) rating of the rectifier
diodes should be at least twice the peak output voltage of the
transformer.
For a full-wave, center-tapped transformer configuration (Fig.
2-3) the peak output voltage is
1.4i4Vrms _ V
reel
2
where
Vrms is the secondary rms voltage at full load,
Vrect is the voltage drop across the diode at full load, approx-
imately 1.25 V, not 0.6 V.
30
r - - -__
v+
v+
'-------0 v-
Fig. 2-2. Typical transformer/rectifier configurations.
31
creased. Most regulators have high ripple-rejection ratios (large
ripple in, small ripple out), allowing the ripple to be fairly large.
Such a design has a high peak voltage to make up for the cur-
rent output of the filter capacitor in between charging intervals.
The regulator has to work hard (it will generate heat) to regulate
this voltage down to the regulated output level. A circuit de-
signed with less ripple (larger filter capacitor) has the peak volt-
age (which is set by the transformer secondary voltage) closer to
the drop-out voltage of the regulator. The regulator will have to
work less since its input is closer to the desired output voltage.
A formula to determine the value of the filter capacitor (Fig.
2-3) is
C=h x106
120VriP
where
C is the capacitance in microfarads,
h is the maximum load current in amperes,
11120 second is the time interval between charging cycles at a
frequency of 120 Hz.
V riP is the ripple voltage in volts, which can be a maximum of
V pk - (Vout + 3), where V out +3 is the drop-out voltage.
Ie REGULATORS
The majority of common Ie regulators are of the series pass
design, as shown in Fig. 2-4. A voltage reference (Vrer ) is com-
pared with the regulator output voltage (Vout ). The comparator
notes any difference in voltage and adjusts the bias on the base
of the series pass transistor for more or less conduction. Usually,
a low-value resistor is placed in series with the transistor out-
put. As the load draws more current from the supply, the volt-
age across this resistor increases. As the output current ap-
proaches the specified maximum output of the regulator, this
voltage turns off the series pass transistor. Often included in the
Ie design is a temperature-sensing circuit that shuts down the
regulator if it gets too hot.
Heat Sinks
Ie regulators require heat sinking when the load current is 20
percent or more of the maximum rated output. If the heat sink is
32
] REGULATOR t--oQ
SERIES PASS
TRANSISTOR RCL
Vin 0-.......,-----------_____. r---<.........--Nlr........ Vou!
too small, the regulator will get very hot and shut itself off (if it
has that capability). For small-current applications the power
supply chassis can serve as the heat sink. For load currents
larger than 500 milliamperes, however, separate heat sinks
should be provided. These can often be obtained hom surplus
sources or can be made from aluminum extrusions.
Regulator Types
There are two types of Ie voltage regulators: fixed-voltage
and adjustable. The fixed-voltage regulator has all of the cir-
cuitry shown in Fig. 2-4 on the chip. It is available in several
33
output voltages. Fixed regulators are low in cost, easy to use,
and can be used with external components for higher-current,
adjustable, or tracking twin supply circuits. Low-power versions
are available for local, on-card regulation.
Adjustable voltage regulators are often very similar to fixed
regulators in design, with the exception that the voltage refer-
ence is adjustable and/or external. In addition, the current limit-
ing function can sometimes be controlled externally. A disad-
vantage of fixed regulators is that output voltages will often vary
2 percent or more with different production lots. Adjustable
regulators can be easily adjusted to the desired voltage. For
example, the LM317 adjustable regulator can be set for any
voltage between 1.2 and 37 volts with specifications equal to, or
better than, those of fixed regulators.
34
'IN4001
LM309K,
Vin LM3405, Voul
725 V IN OR OUT 5 V, lA
LM7805
'OPTIONAL
(A) Circuit.
o -+
TOP
VIEW
-4-
. TOP
VIEW IN -+ OUT
Fixed-Voltage Regulators
Fig. 2-5 shows a common 5-volt, I-ampere fixed-voltage
regulator circuit. Its performance is similar with the LM309K,
LM,340-5, or the LM7805. If the filter capacitor is more than 4
inches away from the regulator use a tantalum-type capacitor
(0.2 ,uF or larger). The output capacitor should be at least 1.0,uF
and tantalum. If tantalum capacitors are hard to find, you may
try a 25-,uF aluminum electrolytic in parallel with a O.I-,uF
ceramic type as suggested earlier. A protection diode may be
necessary to prevent latch-up with negative loads.
Fig. 2-6 shows a twin I5-volt, l-ampere, fixed-voltage reg-
ulator power supply. Its perfonnance is similar with either reg-
ulator listed. Take care when mounting the negative-voltage
regulators to heat sinks: the case is not ground but the input.
Fig. 2-7 shows a tracking supply using fixed-voltage reg-
ulators. The trimpot in the negative supply is adjusted fiJr a
35
+15V
LM340-15 1A
IN OR OUT
LM7815
IN4720
,] 0.22 p.F
CERAMIC
2.2 p.F
TANT
0.1 p.F
CERAMIC
10p.F+
TANT
GND
IN4720
LM32015
IN OR OUT
LM7915 -15V
lA
IN LM340-15 OUT
+
+15 v
D
10K
GND 1%
25 p.F IN4001
8 LM301 2
6 I-::- 10K
ij+ 4 ...... 3 1%
l- 50 5K
4-
IK
,; 25p.F -15V ,; 25p.F
GND TRIM J IN4001
LM320-15
IN OUT -15 v
Adjustable-Voltage Regulators
A very popular adjustable-voltage regulator Ie with superior
specifications and a low price is the 723. A functional pin dia-
36
gram of the 723 is shown in Fig. 2-8. The current limit and
output voltage (2-37 volts) are set externally. A voltage refer-
ence is provided within the chip and is brought out on pin 6.
The available output current of the IC is a maximum of 150
milliamperes. External pass transistors can be added for higher
output currents.
NC 14 NC
INV INPUT 4 11 Vc
Vrof 6 9 Vz
V- 7 8 NC
Fig. 2-9 shows a twin supply using the 72.3. When a twin
supply is made from two positive regulators, ground connec-
tions of the two circuits must be kept separate except for a
single common ground connection at the output. A center-
tapped transformer may not be used. In the circuit of Fig. 2-9
the transformer has two separate secondary windings. Another
method is to use two separate transformers. Capacitors C.3 and
C8 reduce ripple on the V rer output (pin 6 of the 723s). Resistors
Rl and R6 improve temperature stability. The components in
the voltage divider network should have low temperature
coefficients for low output voltage drift with ambient tempera-
ture variations.
The positive supply of Fig. 2-10 is similar to the one in Fig.
2-9. The negative supply is unique, however. As the positive
supply rises in amplitude due to load variations, the voltage at
the negative input to the op amp (previously 7.5 V) will also
rise. As this voltage rises, the op amp senses a difference in
potential between the "+" and "-" inputs. It then tries to cor-
rect this at its output, pin 6. This causes the op amp to draw
37
w
Ct:J
"T1
cP'
N
723
ICI +15V
4 1%
<::-
CD_
"'111
'<;. lK C5+ 1O /LF
mO
< CERMET TANT
:::!;:o 100pF
13K
OJ0 R4 1% OV
<O:l
OJ . .
N ...
-111
::J n
COli'"
ClJ 3'
6..10
0.1 /LF
to";:;
g (1) C6 723
2200/LF R6 IC2
'" ... 3.3K
C8 4 1%
t:5. TANT
ClO 4. 10/LF
lK TANT
en NOTES: CERMET
I: 1. MOUNT Ql AND Q2 ON SEPARATE HEATSINKS.
'tl 100 pF
'tl 2. FOR HIGHER CURRENT OUTPUT REDUCE R2 AND R7 BY !3K
R9 1%
PARALLELLING WITH SAME VALUE RESISTOR. 0
CHOOSE Ql AND Q2 TO HANDLE CURRENT DESIRED. -15 V
REPLACE POWER TRANSFORMER AND RECTIFIERS
WITH HIGHER CURRENT VERSIONS.
."
cpO
12
?
- ,_...- V. u! 110
l>
ST4-36
+
T 723 3.90 +15 V
S:Cf1 5. +
3.32K
o ;:;-
- 1% U- lOjtF
6' Vref TANT
'" I
:::r-n
o:;, _.
3.01K
1%
r
0::::1
COCCI
470pF
--.,0 9.09K
"'"
S; 1% 3.01K
<:: 11\
1%
C/) C -15V
6
,0' :g
3.01K
S"<"
",' 1%
'---C') 3.01K 1% j.'10jtF
o .L TANT
<::
C/)
'"
2000
C/J 3.90
Cii
(j)
1% RESISTORS MAY BE REPLACED WITH NEAREST T+' 200 jtF
w 5% TYPE WITH SOME LOSS IN TEMPERATURE STABILITY .L 40V
co
more current and the voltage drop across the 200-ohm resistor
increases. This voltage turns on the 2N4923 transistor, making
the output more negative. The 3.9-ohm resistor acts as a
current-limit sensor. As the output current increases, the voltage
drop across this resistor increases, causing the 2N3904 to turn
on and cut off the 2N4923 when the output current gets too
high.
SUGGESTIONS
9-40 V
R
+ -----,
I
I
I
I
I
I
6.95 V :
I
I
I
I
I
_____ JI
K+\
KY,
TOP VIEW
40
33K
lK SCR > 25 V. 2 A
2.7K
5V 5V,lA
4.7 V
(B) With SCR, resistors, and zener SCR 15 V. 2 A
diode.
lK
41
CONTROL VOLTAGE
GENERATORS,
PROCESSORS, AND
CONTROLLERS
42
that is a slew limited (increased rise and fall times) version of its
input. A trigger and gate extractor generates timing signals if its
input surpasses a certain dc level. An envelope follower accepts
an input signal and outputs a dc level according to the input
signal's average amplitude with time.
CONTROLLERS
Keyboards
The most common controller for a synthesizer is the
keyboard. Its circuitry is referred to as the keyboard interface.
Most inexpensive synthesizers have a one-voice, or mono-
phonic, keyboard. The output signals of this keyboard consist of
a 1 V/octave control voltage, a gate signal, and a trigger signal
(review Fig. 1-16).
The control voltage is a dc level that corresponds to the posi-
tion of a key pressed on the keyboard. The voltages for each key
occur in linear steps, 1112 volt apart, for 1 volt per octave. Some
keyboard circuits allow the ratio of volts per octave to be altered
with a "range" control. This provides the capability to play mi-
crotonal scales.
The keyboard control voltage output remains at the dc level
of the last key played even after the key is released. Often it is
desired to have notes last longer than a key is held down. The
constant key voltage causes the vco(s) to continue oscillating at
the frequency of the last note played. If the envelope generator
has been set up for a long decay time, it will cause the note to
last even longer after the key is released. Most monophonic
keyboards will output a dc control voltage for the lowest note
played if more than one key is held down. This is called low-
note priority.
Most synthesizers have a feature called portamento. Increas-
ing portamento lengthens the amount of time the control volt-
age takes to change from one key voltage to another. With no
portamento the change is instantaneous and the abrupt change
in oscillator frequency is obvious. With a moderate amount of
portamento the glide from note to note becomes apparent (see
Fig. 3-1).
When one or more keys are depressed a gate signal is gener-
ated. This is a timing signal that is interfaced to an envelope
generator. When a key is pressed the gate output goes high, ini-
43
CONTROL VOLTAGE
I
oV ------t-------I----+-------
I
I
I
I I
I ':
I I
I I
I I CONTROL VOLTAGE
I
I WITH PORTAMENTO
oV -- ----- ----------------
l FAST
l
SLOW
lFAST
NO PRESSURE
HIGH PRESSURE
(8) Pressure sensitive.
45
+5V
Cl
R9 41 pJ "
+15 V
RI 17K 4 8
>--+--jI-->----+--j2
6 555
I ICI
15 3 25ms
C6 01 pJ
GATE 1+5VI
R19
1 5K
n
1%
R21 68K
I
R22
!OK
TRIGGER
1+5 V)
1.25 ms
CV
OUT
-15 V
= IN9141lN4148
AS.A6.AI = 81FET TYPE ILF356 TLOSI)
AI.A2.A3.A4.AS = LM301 OR SIMILAR
pressed. Capacitor Cll filters out noise on the bus line. The A2
circuitry acts as a differentiator. Any change in control voltage
pulsed through C2 and R8 is amplified by A2. These pulses are
input to ICI, which is a one-shot monostable that triggers on a
negative input pulse. Once this monostable is triggered, ICI
pin 3 remains high for about 2.5 ms.
Op amp A3 acts as a comparator in this circuit. It goes high
any time the voltage on the positive input rises above the volt-
age on the negative input pin (which is set by RI2 and RI5).
The voltage on the negative input is set at about 0.35 V, half
way between ground and the -0.7-V output of A5 when no keys
46
are pressed. Possible A5 key control voltage outputs range from
o volts (R5 shorted) to several volts, depending on the keys
pressed and their octaves. The -15- to + 15-V level output of A3
is converted to a 0- to 5-V level by D2, R16, and R17. A 5-V
level into IC2 pin 4 enables IC2 and allows the pulse from ICI
to cause a 1..5-ms trigger pulse out on pin 3.
Diode Dl and resistors R14 and R15, along with capacitor C7,
delay the rising leyel of A3, causing comparator A4 to output a
delayed -1.5-V to + 15-V level. This level is converted to a 0- to
5-V level by D3, R18, and R19. This output is the gate.
The trigger output (pin 3) of IC2 is input to comparator A8.
This -15- to + 15-V level turns on the sample-and-hold FET,
Q2. This allows the keyboard control voltage to be stored by
C 10 and buffered by A6. The output of A6 is fed to the por-
tamento circuit of R26 and C12. This is buffered by A7 for the
final control voltage output.
If the gate voltage were not delayed by A4, the synthesizer's
envelope generator would be activated before the new
keyboard control voltage was set up on the sample and hold.
This would cause the old pitch to be heard for a short interval if
a fast attack setting was used on the envelope generator. The
signal timing of this circuit is shown in Fig. 3-4.
The basic advantage of this circuit is that it allows the use of
inexpensive (possibly surplus) one-bus keyboards. The control
voltage is more susceptible to drift than other designs using
more than one keyboard bus due to the droop rate of the sample
and hold. Droop rate is the rate at which the storage capacitor
looses its charge. The key voltage is sampled only once and for
a very short time for each key depression. After the trigger
samples the sample and hold, ClO begins to discharge at a rate
dependent on the input bias current of A6, the type of capacitor
used for CI0, and whether the printed circuit layout around Cll
and A6 is clean of contaminants. A guard ring is shown on the
schematic. This is an actual printed circuit trace on the board
that encirclcs thc traces leading from the top of storage
capacitor CI0. The guard ring is connected to the negative
input of A6. Since the level on this guard ring is thc same as
that on ClO (but at a lower impedance) there is lcss leakage
from CI0. Othcr circuits, using more than one keyboard bus,
gate the sample and hold on with a second bus. Thus droop rate
does not become a factor until a key is released.
47
I I
I I Al CONTROL VOLTAGE
I I OUTPUT
I
I I I
I I I
--1"----
OV
, I I
I
I A5 CONTROL VOLTAGE
I
I OUTPUT
I
I I
ov -----t-------i--- I 1-----------
':::rnj. nLnUr-
I I I I
1
A3 OUTPUT
-------------------
GATE OUTPUT
I I I I
I I I
:: i,,--I-t'---,!I ::------i'11-+---1----
I 1.25 ms :
I
TRIGGER OUTPUT
ICI OUTPUT
: : -,----I
, - - - I
25 ms
A Duophonic Interface
The circuit of Fig. 3-5 is a duophonic, 3-bus, keyboard inter-
face that appeared in CFR Technotes. 2
Op amp A3 and transistor Q7 form a constant-current source
much like the one in the circuit of Fig. 3-3. Op amp A5 buffers
the level of the voltage on the bus. The wire from the voltage
bus to A5 is shielded to eliminate any 60-Hz line noise from
entering the circuit. The first voice gate signal originates from a
separate keyboard bus. It turns on sample and hold FET Q8
whenever a key is down. Op amp A4 buffers the voltage stored
on the control voltage/portamento capacitor.
The portamento circuit in this design performs differently
than the circuit in Fig. 3-3. In Fig. 3-3 the control voltage
changes in abrupt steps at the output of A6. The output of A7
will always eventually reach the same level of A6 at a rate de-
termined by the setting of R26. In Fig. 3-5, however, if the first
voice key is released, FET Q8 turns off and the voltage remains
48
TRIGGER
BUS
PART OF
KBD ASSY _/
oI I _/ +-_-..---....-{
-/ 68K
t cot
+lSV +15 V
-15 V
-15 V
+15 V -15 V
2nd VOfCE
5.lK
lYo
OUTPUT
- TOP OF TO + IN
KBD IN914 AI eX'"
VOLTAGE 10K
KEYBOARD BUS
DIVIDER lsi VOICE
j
100 "
1%
TYP
r:
I
M __________ __ 15_V________________________
__
GAlE
390 L2K
2N4091 D ZNJ904.
2H3906
A2,M.AS = BIFEl lf3S6
OR SIMILAR
SQGICASEI
BOTTOM
oE8 C
VIEW aoTIOM
VIEW
49
A third keyboard bus pulses Q I whenever keys are pressed.
Transistor Q I triggers the 555 one-shot to output a 5-ms pulse.
The negative-going edge of this pulse is inverted by Q2 and
bufJered by Q3. The pulse is then fed into FET switches Q4
and Q5. When there is no second voice, comparator Al outputs
-15 volts, turning the first voice FET, Q5, on and turning off
the second voice FET, Q4. When there is a second voice, Al
will output + 15 volts, turning off first voice FET Q5 and turn-
ing FET Q4 on. Thus the trigger pulse is gated to the correct
voice trigger output.
The second voice trigger lockout circuit (A6, A7) prevents the
second voice from retriggering if the second voice is held down
and a series of notes is played on the first voice. It consists of
two comparators that sense a difference between the voltage
stored on C t and the control voltage output from A5. As long as
the first voice is changing these voltages will be different due to
the charging time of Rt and Ct. This locks out the second voice
trigger.
The gate bus of this circuit could possibly be eliminated by
using a comparator referenced close to ground to monitor the
trigger bus. Any time a key is pressed the comparator would go
high, generating a gate signal and enabling the sample and
hold.
For proper operation of this circuit, the key control voltage
bus must be the first to make and the last to break contact. This
ensures that the control voltage is ready to be loaded into the
sample and hold before the gate signal appears. Also, clean con-
tacts arc a necessity with all keyboard interface circuits. Con-
tacts can be cleaned with rubbing alcohol and cotton swabs.
50
CV
IN 39K
SCALED
1 V/oCT
+15 V 33K
COARSE
CV OUT
lOOK 39K
-15 V
+15 V
FINE
lOOK 3M
-15 V
Joystick
A joystick interface circuit is shown in Fig. 3- 7. A joystick
allows control over two parameters with one control. The sec-
ond voice lockout circuit (A6, A 7) of Fig ..3-5 could possibly be
used in conjunction with this circuit to provide a gate signal
whenever the joystick is moved.
A Pressure-Sensitive Controller
The black conductive foam used to protect static-sensitive les
from damage during handling and/or shipping can prove to be a
useful material for controllers. The resistance of the material
varies with its density. If a piece of the foam is placed between
two metal plates the resistance between the two plates will de-
crease as the foam is compressed. This forms the basis of a
pressure-sensitive controller.
Fig. 3-8 shows a circuit for such a pressure-sensitive control-
ler. Resistor Rl sets the overall gain of the circuit. If the output
voltage range is too large or too small, change the value of Rl.
51
+15 V GAIN
lOOK
10K
JOYSTICK R2
POT RI
10K
SI IK
IK
10K
-IS V
RI z R2
DUPLICATE FOR X AND YAXIS POTS
A Ribbon Controller
A ribbon controller can be made using conductive foam. This
is shown in Fig. 3-9. A strip of foam is laid out on a noncon-
ductive surface. Metal conductors are glued to the ends of the
foam strip. A piece of aluminized Mylar film is fixed above the
conductive foam. Pressing down on the Mylar film will cause it
to contact the foam and pick off the voltage at that point. This
voltage is then applied to interface circuitry for a final control
voltage output. The circuitry of Fig. 3-3 can be used by sub-
stituting the ribbon controller for the keyboard.
Envelope Generators
An envelope generator generates a control voltage or
envelope that is usually nonperiodic. The envelope, initiated by
a timing signal, begins at 0, rises to some positive level, and
then falls back to 0.
There are several types of envelope generators, including the
attack-release (AR), the attack-decay (AD), and the popular
attack-decay-sustain-release (ADSR).
Fig. 3-10 shows a basic attack-release (AR) circuit. The stor-
age capacitor (Cl) is charged at a rate determined by its
capacitance and the setting of the ATTACK control (Rl).
Capacitor Cl discharges through D2 and DELAY control R2. The
52
RI
IK
FOAM
>-+---0 0-10 V
-15 V
(A) Circuit.
PRESSURE
(8) Construction.
T = RC
where
R is in ohms,
C is in farads.
53
r"---'F"",,OQ ..IE
IL.._ _ _IN_T_ER_FA_C_E_ _
. ::TE
TRIGGER
(A) Circuit.
+ 15 V
CONDUCTIVE FOAM
NONCONDUCTIVE BASE
(8) Construction.
01 Rl
IN914 5M
ATTACK
02 >--+----oENVElOPE
R2 OUT
GATE IN914 5M
DECAY + Cl
I2.2P.F
(A) Circuit.
AR
ENVELOPE J '-,---
(8) Waveforms.
54
+15 V
R6 47K
CI .001 p.F
R5
4001
02 R3 R7 lOOK
RI 1M 5 M LOG
ATTACK
03 R4
>-------0 ENVELOPE
OUT
GATE C2 5 M LOG
DECAY
.001 p.F C3 r+ 2.2 p.F
R2 1M Al,A2 LM307 OR LMI458 DUAL
7 01.03 IN914 OR SIMILAR
GATE
AD J\..... _ _ __
ENVELOPE
55
+15 V
RI 47K (lOV!
+15 V
R2 lOOK 14016!
R3
DECAY R4 I M LOG SI
RI6
5K LIN S2
SUSTAIN I MLOG R5
I M LOG
RELEASE
GATE 01
RI)
.........
GATE
TRIGGER L-L-_-----'-_ __
56
RI2
DELAYED
lOOK GATE
+15 V
DELAY
2M
R6 R7
,---'WV----,-'W'.---<) + 15 V 12K
02 C1
R9 10K
0101 IN914
GATE INPUT 1
555 OUTPUT
(PIN 3)
r T-]
l U l L .___
r f-]
DELAYED GATE
OUTPUT _
n U r - - II
.57
TIME CDNSTANT AD)
RI
-15V +15V
<9 +15 V
MAX SUSTAIN
R3 TRIM
+15 V 330K R4 RI7 RIB
R2 330K lOOK
RELEASE 330K 20K s
RB SUSTAIN
+15 V R5 14 RIG
DECAY lOOK 270K 33K R19
-15 V NC 2
R6
lOOK +15 V R9
-15V ICI 12
270K
RIO SSM2050
R7 R20 ENY
lOOK 270K CI DUT
ATTACK IK 010 V
10
-15 V
0.01 JlF
9 NC
R12" 2.2K
CMOS TTl
RI4 IK
R11" 2.2K R15" -15 V
TRIGGER
L-.+-----vw--o +15 V
MANUAU TTl B.2K
CMOS
GATE
:------------ --- -- i
, , +15 V "RI5.Rll.RI2 FOR TTL INPUTS ONLY
,,
,
,,
l",J SI ,,
,
,,,
,
RI3
IK
R4
IK
TIMING SIGNALS
5V
,, (SEE TEXn
,, 10K 10K 10 V
, ,,, C4! 10 JlF
15K 15K 15 V
,, 25 V
-15 V
, 0---
,, 15K S2
__________________I
58
Quite a large variation in device characteristics can occur be-
tween different SSM2050 chips due to variations in input im-
pedance. This impedance can be measured with a high-imped-
ance ohmmeter between pins 1 and 7. Typical input impedance
is 3.1 kil. Matching will be required if several 2050s are to be
used in a system. Also, time constants can vary 50 percent be-
tween devices. Devices can be matched, however, by setting all
controls to their minimum settings and adjusting Rl for an at-
tack time of 2 ms.
Fig. 3-1.5 shows an ADSR circuit using the SSM2055, an im-
proved version of the SSM2050. The SSM2050 has a timing
range of 50,000 to 1, minimum. An exponential converter is also
contained in the chip, as was the case with the SSM20.50. All
input control voltages are positive (referenced to ground) with
an input sensitivity of 60 mV per decade. The gate and trigger
input circuits can accept a variety of input levels where the
logic threshold is at about 2 V. Unit-to-unit time constant varia-
tions are greatly reduced-eliminating the necessity of select-
ing ICs for polyphonic systems. The SSM2055 was designed
with polyphonic systems in mind, because the control input
pins can be ganged with other units.
In the circuit of Fig. 3-15, provision is made for external con-
trol. As the control voltage increases, the attack or decay time
will increase. Controls RI, R3, R5, and R7 are limited by resis-
tors, so that a maximum of 10 volts can be output. This voltage
or the external control voltage is then buffered and fed into a
divider network voltage network, such as RI3 and R14. This
network sets the control range. If other control voltage ranges
are to be used (such as 0-5 V), the network resistor values will
have to be altered. Low-value resistors are recommended for
RI4, R16, and RIB when the divider is driving more than one
SSM2055. The sustain level trimpot (R9) adjusts the maximum
sustain dc level to be equal to the maximum attack level. The
time constant trimpot (R20) is adjusted to match time constants
between separate units. This is done by matching the maximum
attack times between units. If the envelope generator is not to
be used with other units, the trimpot can be eliminated and pin
2 should be grounded. A control voltage (perhaps the 1 V/OCT
from the keyboard) into resistor R23 can be added to control all
time constants of the IC simultaneously. Output buffer Al is
included as a safeguard. The SSM2055 has the capability to
59
O'l
o + IS V CONTROL BUS
R8 CV INPUTS iTO PINS l.3.4.12 OF OTHER UNITS) R23"
." 33K (0-10 V)
cp' SUSTAIN R9
CAl
U; LEVEL 25K RI9 "TIME CONST
, TRIM -
, RI lOOK lOOK e ADJUST
,. R21
::I SUSTAIN -15 V R20 + IS V
,. 120 fI 50K
+15 V RI3
R2 47K n R +V
i R'4i'OO fI TRIM NC
jo lOOK 0 SSM2055 S 112
ca RELEASE
A
+15 V RI5 C2 5 10 1
R4 41. 33K TRIG OUT" 010.
; oc R6 1000 NC
5'
ca R5 lOOK R22
10K 7 GND -V b!!--o -15 V
;. DECAY
CD
R7 GATE 6
ATTACK IN 'OPTIONAL SEE TEXT
drive a 2 ..5-kfl load with less than .5000 pF. Capacitor Cl is the
storage capacitor for the circuit and should be a polyester or
polystyrene capacitor for good stability.
Fig. 3-16 is a similar circuit for an ADSR envelope generator
designed by R.C. Blakey of Digisound. 6 The circuit uses a Cur-
tis Electromusic Specialties CEM3310 Ie. The control voltages
into the "attack," "release," and "decay" inputs of the
CEM3310 can range from 0 to -.5 volts. Increasingly negative
voltages will result in longer attack, decay, and release times.
The sustain input requires a positive voltage of 0 to +.5 volts.
This voltage will be the sustain voltage of the output envelope.
Control input pins of similar tracking units in a polyphonic sys-
tem may be ganged. One input attenuator can then control sev-
eral ICs. The time constants of CEM3310s can vary 1.5 per-
cent and can be matched using a trimmer (PRl).
In the circuit of Fig. 3-16, IC2A, IC2B, IC2C, and IC3A in-
vert and attenuate the incoming control voltages. A voltage con-
nected to EXT CONTROL A, D, and R will change the attack, de-
cay, and release time constants simultaneously. Circuit IC3A
inverts and attenuates the sustain voltage and IC3B inverts it
again to the proper voltage range (0-.5 V) required by the
CEM3310. Pin 3 of the CEM3310 outputs the attack peak
threshold voltage internal to the IC. Circuit IC3C limits the
maximum sustain voltage on pin 9 at this level, preventing a
voltage jump that would occur if the sustain voltage was higher
than the internal peak attack voltage.
The intcrnal output buffer of the CEM3310 has a relatively
high output impedance. Performance is improved if it is bufT--
creel, as with IC.5A. Circuit IC.SB converts the CEM3310s nor-
mal 0-.5 V output to 10 V. The attack output pin (pin 16) shifts
from 0 V to a negative voltage (-0.4 to -1.2 V) when the circuit
is in the attack phase. This turns on comparator IC6A and LED
1. Comparator IC6B turns on LED 2 whenever a gate signal is
present. The gate signal is fed directly into pin 4. The trigger
input signal in this circuit is derived from the gate signal by C8
and R4. This also triggers monostable ICIA and ICIB with an
output pulse duration set by RVl. The output of the monostablc
is converted to a second trigger pulse by R.5, CI0, and ICIC. In
the delay mode (S 1 open) only this pulse goes to the CEM331O.
The circuit then functions as an AD generator. "Vith Sl in the
retrigger position, this second trigger pulse is mixed with the
61
Rl
10K
+15 V R2 .",. 5.6K
oV
O
C2 .,.,10 f,1F
.-4-
C4 1T01 F C6 I O.l of,1F
Il_
EXT Dl
-15 V TRIGGER D4
GIl
0.0033f,1F
Cl2
I
1 0.033 f,1F
R34
OUTPUT
lK
lOOK
IC4
R33
R36 lOOK
NOTE
ICI IS 4001
IC2 IS LM348
IC3 IS TL084
IC4 IS CEM3310
IC5 IS TL082
IC6 IS LMI448
D1.D2.D3 ARE IN4148
62
+S V FOR
MANUAL
RS lOOK GATING
AND RVI
GATE
DELAY I RETRIGGER
SI
-IS V
R41 lOOK
R4S
1.2K "
LED 2
14
RI4
13 SEE TEXT
62K lOOK
12 RI3 EXT
CONTROL +IS V
11 lOOK (R)
+lSV
RI2 RV3 lOOK
10 LIN
RI6 RELEASE (R)
ISOK
10K
R17
4700
R21 R20
SEE TEXT
62K lOOK
RI9 EXT
CONTROL
lOOK (D) +l5V
RI8 RV4 lOOK
R22 LIN
lS0K DECAY (D)
D2 10K
63
undelayed trigger pulse, creating a noticeable delay in the out-
put envelope contour. It may also be desirable to use a separate
trigger input to allow retriggerlng from the keyboard. This is the
purpose of diode D4.
Sequencers
A sequencer is basically a circuit that generates preset control
voltages in a desired sequence. The complexity of sequencers
varies greatly. The rate at which the sequencers "step" from
one control voltage to the next sequential voltage (the scan rate)
can be controlled by an oscillator or an external trigger. The
number of different control voltages generated is up to the de-
signer. Individual sequence times can also be preset with some
designs. In simple designs all the sequence times are equal.
Sequencer control voltage data can be read from potentiometers
or a digital memory.
Fig. 3-17 shows a simple sequencer using a CMOS 4017B
decade counter/divider. Each time a clock pulse occurs on pin
14, the counter in the 4017 is incremented. This count is then
decoded internally and, as a result, one of the 10 outputs (0-9)
goes to a logic 1. All of the other outputs go to a logic O. The 555
in this circuit is used as an oscillator whose rate is controlled by
Rl. Other clock circuits can be used. Switch SI prevents the
oscillator from clocking the 4017, and it allows the use of either
an external clock or the manual trigger circuit. In the manual
trigger circuit, NOR gates 1 and 2 are configured as a monosta-
ble. When S2 is Closed this circuit will output a pulse that will
clock the counter one step. Pin 13 of the 4017B is the clock
inhibit pin. A logic 1 on this pin will inhibit the counter regard-
less of the clock input status. When th.is input goes to a logic 0,
the counter will continue counting where it left off. The cir-
cuitry associated with NOR gate 3 debounces the inhibit switch.
A logic 1 on the reset pin (pin 15) will cause the counter to reset
to zero. If this pin is connected to an output pin, the counter
will count up to the number represented by that pin, reset, and
then start counting from zero again. This is the function of S4. If
a full sequence (10 states) is desired, pin 15 must be grounded.
In addition to S4, the outputs are connected to two 100-ko. con-
trols and an LED circuit. The LEDs will light as the counter is
sequenced. Each divider output also drives two 100-ko. poten-
tiometers. By adjusting these potentiometers, the user can "pick
64
flANIEIT
o SI S2 d
C3
+l5V
0.01,."
+15 V
0103 IN914
NOR GATES 400IICMOS)
+15V
RS.Jm IK DUPLICATE
SEEIB) LENGTH OF SEQUENCE
FOR OTHER
9 STACES
LED 0 '-------1.---1
M ,
A9 CONTROL VOLTAGE !
OUT !
IDUPLICATE FOR BI).B9 i
_____________________________________________________
Rl1 0.47 (l
SI Cl
1-
1M
TIME
R2 27K
R5 27K
8 4 7
C5
__ __ 6 .iI--:t. 555
0.1 fL START 1
S2
2 555
3
5 fLF C6
0.1 fLF
R4 OUTPUT
10K
""i'" TO CV
SUMMER
Noise Sources
Noise sources generate a spectrum of frequencies at random
(or appearingly random) intervals. The majority of noise sources
are in one of three groups: white noise, pink noise, and low-
frequency random voltages.
White noise has a flat spectral density (all frequencies have
equal amplitudes). The interstation hissing you may hear when
tuning between fm stations on your stereo is much like white
66
noise. Pink noise is low-pass filtered white noise, where a note
in a higher octave has an amplitude that is 0.707 less than the
same note in the next lower octave (3 dB per octave). Low-
frequency random voltages are obtained by low-pass filtering
the pink noise with a filter with a cutoff frequency of less than
10 Hz.
The majority of noise sources rely on the noise generated by a
reverse-biased semiconductor junction. Another method uses
digital shift registers. Such a circuit is called a pseudo-random
sequence generator (prsg). The noise and output level of such a
circuit is uniform, but the sequence generated actually repeats
at certain intervals.
Fig. 3-19 shows a noise source using a semiconductor junc-
tion. s Transistor Ql can be any npn transistor. In fact, what you
are looking for here is the noisiest transistor you can find! The
noise from this transistor is small in amplitude and is amplified
by op amps Al and A2 for a +5- to -5-volt output. Depending
on the transistor, R5 or R6 may have to be changed in order to
obtain this output level. Op amp A3 is a low-pass filter with a
C5
0.001 JLF
RIO C6
47K 0.01 JLF
Rll
+15 V 270K
R12
1K
R9
>--+--'W'v---O PINK
R1 lOOK R13
lOOK R14
R4 R5 R6
C7 lOOK
5lOK 2.2K
R8
1K WHITE
R1S
1K
Q1 1M
2N3904 6.8 pF
OR RANDOM LF
SIMILAR
67
3-dB/octave roll-off providing pink noise. Op amp A4 is another
low-pass filter with a cutoff frequency of about 10 Hz which
generates the random low-frequency signal. It should be noted
that levels in this circuit will probably have to be trimmed, as
the output of Q1 will vary transistor to transistor.
Fig. 3-20 shows a white-noise source using the pseudo-
random generator technique. This circuit is used in the Maplin
3800 and 5600 series synthesizers. 9 The four NOR gates are
configured as a 35-kHz oscillator to clock the 18-stage shift reg-
ister ICl. The white noise output is a result of gating (the three
EOR gates) the outputs of the 5th, 9th, and 18th stages of the
shift register. The white noise is also fed back into the D input
of the shift register. Resistor R1 and C1 ensure that the system
will start. The sequence output of this circuit will repeat every
few seconds but for most applications appears random.
+15 v
68
0.001 J.tF
47K
MM5837
,>-'+---0 OUTPUT
2
-15 V
69
R5 R6
R8
SINE
IK
01 SINE
D2 10K TRIM R7 10K
R3
lK TRIANGLE
CI
RI2
PULSE
1K
_ _ _ _ _ _ _3_3_K lOOK
390K FREQUENCY 0.120 Hz
RI4 IK
ALL OP AMP 741 OR SIMILAR
DI02 IN914
70
+ 15 V
RI lOOK
TRIANGLE
OFFSET
R2 lOOK
LINEAR
R9
R3 lOOK R4
lOOK RATE 1M
27K
-15V R7 10K
R5
10K
TRIANGLE PULSE
+/-5 V 14 V
(A) Circuit.
TRIANGLE V A V L IV """i
" " ""'-lI
50% 10% 90%
PULSE
8LJ Ar==u
(8) Effect of symmetry control.
71
OV INPUT
1
1
1
1
1 I
I I
I 1
I 1 1
I I I I I
SAMPLE
IIIII
PULSES
I I
OUTPUT
ov
Fig. 3-24.
cJ The effect of a sample and hold on an input signal.
mined by R12 and C3. Pin 3 is the output ofIC1. This 0- to 15-V
level is converted to +/-15 V by A3. A + 15-V pulse will be
blocked by D 1 and the output of Al will pass through R2 to the
gate of Q 1. This will turn on Q 1 and pass the analog signal to
storage capacitor Cl and buffer A2. A -15-V level out of ICI
will turn on D I and the gate voltage will be approximately
-14.3 V. This turns Q1 off. Therefore, when an external clock
input is used, each time the external clock input rises above
ground the input signal will be sampled for a duration equal to
the 555 monostable multi vibrator output pulse period. When in
the AUTO mode, the input signal will be sampled for a duration
equal to the 555 pulse period and at a rate set by the rate control
(R6).
The on resistance of Q1 and the capacitance of C 1 form a time
constant that dictates the time required for accurate sample
voltage acquisition (by Cl). If the sample period (set by R12
and C3) is not long enough, the capacitor will not have enough
time to charge up to the level of the input voltage. A smaller
value of Cl will remedy this, but the capacitor will be dis-
charged faster by the input impedance of A2. Increasing the
sample time period would help, but it will also lower the
maximum usable sample frequency.
72
R3
>--+--'\IVI,..---Q OUTPUT
IK
INPUT
+/-5 V
RI lOOK
Al.A4 = LM307 OR SIMILAR
R4 A2.A3 = TL081 OR SIMILAR
r----'\N\r---<l + IS V QI = MPFl05.2N3819.0R SIMILAR
18K CI = POL YCARBONATE.
R5 POL YESTER. OR POLYSTYRENE
01 TYPE
UK 01-03 = IN914
+15 V
C2 +15 V
rj
OJ p.F
"7
RI2 22K
4 8
6
555
5M 2
RATE C3 10.01 p.F
D2
R7 8.2K SI EXT
10.01 p.F
CLOCK
C4 r 0.47 p.F
AUTO
Rll
+ IS V
22K
R9 C5 0.01 p.F
EXT
CLOCK 03
10K
R8 lOOK RIO OK
73
The 4016 CMOS quad analog spst switch can be used in
sample and hold circuits, as shown in Fig. 3-26. The analog
signal to be sampled must be within the 4016 power supply
limits. The 4016 has a typical on rcsistance of 300 ohms, but this
will vary with the input signal polarity. Other CMOS switches
and multiplexers have lower, more consistent on resistances but
may have higher droop rates due to higher internal leakage
currents.
4016
OUTPUT
INPUT o---.----l
+/-5 V
ON = +7.5 V
OFF = -7.5 V
Fig. 3-26. A sample and hold circuit using a CMOS 4016 switch.
Slew Limiters
Slew limiters lengthen the rise and fall times of an input
waveform. The portamento circuit of a keyboard interface is a
slew limiter. Such a circuit is shown in Fig. 3-27A. The time
constant of the circuit is determined by the choice ofCI and the
setting of R2.
Fig. 3-28 shows a linear slew limiting circuit. The heart of
the circuit is the integrator formcd by R2, R3, C 1, and A2. The
voltage across capacitor C 1 (and thus the output) will be a linear
ramp because the capacitor will be charged and discharged at a
constant rate (current). Op amp Al acts as a comparator. Its out-
put normally would be either high or low (+/-14 V). Resistors
R2 and R3 determine the charging current from the output volt-
age of Al (the current in the feedback path of A2 is equal to the
current through R2 and R3). The output of A2 is fed back into
comparator AI. The output of Al corrects for any voltage differ-
ence between the inverting (-) input of Al and the output of
A2. If the input level remains constant, Al output oscillates at a
74
DELAY R3
R2 OUTPUT
INPUT IK
I M AUDIO
BI-FET OP AMP
RI lOOK CII01PJ
(A) Circuit.
INPUT
J
(
OUTPUT
J I....
(8) Waveforms.
75
CI
DELAY
INPUTo-_---i:::-.. R2 R3
R4
RI lOOK 5 M AUDIO 2.2K 0UTPUT
lK
(A) Circuit.
INPUT
OUTPUT
(8) Waveforms.
+15 V
r----------------------------t
R1
R2
,
I
R5
--'VYv-----op----O OUTPUT
01 -0.7 V to VD1
INPUT D2
R4
R3 ,
I
I
IL____________________________ _
76
If the input to the circuit of Fig. 3-29 is unstable or has noise
imposed on it, the comparator may change states several times,
as shown in Fig. 3-30. This is not very desirable. Hysteresis is
added to allow the circuit to "ignore" the noise and jitter of the
input signal. Hysteresis is the creation of two voltage thresholds
caused by the addition of positive feedback to the circuit. This
is shown in Fig. 3-31. Resistors R3 and R4 fi:mn a voltage di-
vider between the input voltage and the output (saturation)
voltage of the op amp. Resistor R4 adds positive feedback to the
circuit. As the value of R4 is increased (or R3 decreased) the
amount of positive feedback will decrease and there will be less
of a voltage difference between the upper threshold points (less
hysteresis).
A similar circuit designed with the 4050 CMOS buffer is
shown in Fig. 3-32. This circuit is commonly termed a Schmitt
trigger. The threshold point of the CMOS 4050 is normally
- - UPPER THRESHOLD
INPUT SIGNAL - / - - - - \ - - - - , f - - - - - - - - \ - - + - - \ - - NO HYSTERESIS
HYSTERESIS J U .
.....-_-_-_-_-_-_--
OUTPUT OF
COMPARATOR,_ _ _ _ _- f_ _ _ _ _ _ _ _----if----_ _ __
WITH
HYSTERESIS
77
Rl R2
+15 Vo--w,r-...---vvv------O -15 V
R3
Vin 0--vvv----....---1
R2
78
Vout----,
Voo
I
-11- t = RC In IVool(voo - VT +)]
Voo
Vout
Fig. 3-33. Signal conditioning and trigger circuits using the CMOS 4093
Schmitt trigger. (Courtesy National Semiconductor Corp.)
79
01
Rl Cl
INPUT o-----W.-----j R4 10K
lK 01 fF 03 51
_' BOTH
RG 10K
-15 V 04
R7 10K
R8
+5 V
+5V 120K 9011'F
D1D4 lN914
Al A1 LM1458.TL071 OR 2 4 8
EQUIV IDUAII 2 4 8 R9 220K
555
TRIGGER OUT
12 ms)
(A) Circuit
INPUT
, __dJ ---
J--4
I I I I
Al OUTPUT iliL
: -Tnl-
: I
OV
(8) Waveforms.
I I : : I ' ::
, ,
TRIGGER OUT
lSI = BOTH)
I I I I I I II 0V
80
wave rectified and then filtered to obtain a relatively smooth dc
output. This type of circuit is used to obtain an amplitude
"envelope" of an input signal. The output can then be used as a
control voltage for other modules such as a voltage controlled
filter or voltage controlled amplifier.
An envelope follower circuit is shown in Fig. 3-35. It origi-
nally appeared in Electronotes. 13 Op amps Al and A2 form a
precision full-wave rectifier. The output of half-wave rectifier
Al is summed with the input signal to obtain a full-wave output.
For negative input signals the output of Al is 0 V and the input
signal flows through resistor R4 and R3 to op amp A2. For posi-
tive input signals the signal will How through half-wave rectifier
Al and resistors R4 and R3 to op amp A2. Resistor R5 sets the
gain of the circuit. Capacitor C2 filters (integrates) the full-wave
peaks to provide a stable output from op amp A2. If the value of
capacitor C2 is too small, the output of A2 will vary slightly, or
R4 C2
DI 20K 1% LO IlF
R5
IN914
R2 R3 33K
R6 6_2K
RI2
GATE
2K AI-A4 lM307. 741. ETC.
03 IN752
Rl6
+15 V r---'V\/'v---.() + IS V
O.lIlF
RI8
RI4 IGGER
(= 10 ms)
IK
05 04 IN752
IN914 RI3 lOOK
OR .,.- 1M
SIMILAR
81
ripple. Op amp A3 is a comparator with hysteresis and gener-
ates a gate signal if the input rises above ,500 m V peak to peak.
Op amp A4 generates a trigger signal when the gate signal oc-
curs. The type of op amp used in this circuit is not critical.
One-percent resistors are used in the rectifier circuit for preci-
sion. For some uses., 5-percent resistors may be fine, It may be
necessary to experiment with values for capacitor C3 and/or re-
sistor R13 for proper trigger generation.
REFERENCES*
1. Hutchins, Bernie, "The ENS-74 Home Built Synthesizer, Part 1," E/ec-
tronotes, Vol. 6, No. 45, October 1974, pp. 11-13.
2. CFR Technotes, Vol. 3, Issue 7, pp. 10-14.
3. Hutchins, Bernie, "The ENS-74 Home Built Synthesizer, Part 1," Elec-
tronotes, Vol. 6, No. 45, October 1974, p. 14.
4. Hutchins, Bernie, "A Gate and Trigger Delay Unit," E/ectronotes, Vol. 7,
No. 51, March 1975, pp. 20- 22.
5. Blakey, R. C., "Envelope Shaper," ETI Magazine, Vol. 9, No.7, July
1980, pp. 88-90.
6. Blakey, R. c., "Envelope Shaper," ETI Magazine, Vol. 9, No.9, Sep-
tember 1980, pp. 93-96.
7. Hutchins, Bernie, "Some Initial ENS73 Sequencer Design Ideas,"
E/ectronotes, Vol. 5, No. 35, February 1974, pp. 6-7.
8. Hutchins, Bernie, "ENS-76 Random Source," E/ectronotes, Vol. 9, No.
76, April 1977, pp. 3-4.
9. Maplin Electronic Supplies, Ltd., Map/in 3800 & 5600 Stereo Synthe-
sizer Handbook, 1979, p. 23.
10. Hutchins, Bernie, "Theory and Application of Noise Generators in
Electronic Music," E/ectronotes, Vol. 8, No. 64, April 1976, pp. 12-14.
11. CFR Technotes, No.3, p. 2.
12. Lutz, Peter, "LFO with Ramp, Inverted Ramp, Triangle, Pulse Width
from 10% to 90%," E/ectronotes, Vol. 11, No. 88, April 1978, pp.
24-25.
13. Iodice, Robert, "One-Chip Envelope, Gate, and Trigger Extractor,"
E/ectronotes, Vol. 20, No. 86, February 1978, pp. 20-22.
82
VOLTAGE CONTROLLED
OSCILLATORS (VCO'S)
83
rLINEAR
FM INPUT
LINEAR
CONTROLLER CV OUT EXPONENTIAL
(KEYBOARD, ETC) CONVERTER
EXPONENTIAL
CURRENT
OUT
BASIC OSCILLATOR
WAVESHAPE
NOR N\
WAVEFORM CONVERSION
CIRCUITRY
1111
N\ ru 'V /V\
FINAL OSCILLATOR OUTPUTS
84
'TEL LABS Q81C R3 AND QI-Q2
RI R3 IN THERMAL CONTACT
CV IN O---J\Nv--p---\IV',--, ----j
/
CV IN O----'\N'v---<I-!
lOOK
R4
R6 390
+15 V
R7
lref + 1.5 M
RIO
LINEAR FM
470K
20 pF
R9
10K
Ql.Q2 ANALOG DEVICES AD821
R8 Al LM307 OR SIMILAR
A2 LM308
where
VB = voltage on the base of Q 1 in millivolts,
q = charge of a single electron (1.60219 x 10- 19 coulomb),
k = Boltzmann's constant (8.6167 X 10- 5 electron volts per
kelvin),
T = temperature in kelvins.
85
+15 V +15 V
Rl 33K
LM307. 741. ETC
11
R4
Q2
IN914 IK
10
+15 V
R2 10K R5 330 n
e R6 47 n
R3
IK
TEMP
TRIM
Q1.Q2 CA3046 ARRAY
86
VOLTAGE CONTROL IN THERMAL CONTACT
RI
__ - \
lOOK 1% R3 2K TC TEllABS -\
o------"I'-"'+--J:::-- Q81C \
307 0 VIOCT \
R6 100 \
r----- ---------
R5
+15 V R7 390 .--"-7-----'
R8
15 M
RII
R9
15K
I
68K
CI 180 pF
RI2 6.8K
RIO IK
-IS V
RI3
330K RI4 UK
o HIGH-END
RI5 IK CORRECTION
TRIM
-IS V
the transistor pair, which flows through Q3. This is the function
of resistor RIO in Fig. 4-2.
M
J--i
(A) Sawtooth oscillator.
TRIANGLE
OUT
1\/\
88
changes states, and the polarity of the charging current is re-
versed. The charge on the storage capacitor will then ramp
down until it reaches the lower threshold of the Schmitt trigger.
The output frequency of the oscillator is dependent on the
charging current and the value of the storage capacitor. The
output amplitude is set by the thresholds of the Schmitt trigger.
The device used for the current reversing switch is an opera-
tional transconductance amplifier, or ota. An ota is an op amp
with a current output, the magnitude of which is a function of
the differential input voltage and a bias current (Ie). For input
voltages of 10 m V or less the op amp operates linearly and Ie
will function as a gain control. If the input voltage of the ota is
large (more than 1 volt), the input will be saturated and the out-
put will be a current with a polarity of the input voltage and an
amplitude equal to the Ie control current. Thus, if a square wave
is input to an ota, the output will alternately source and sink a
current equal to 1(. RCA was the first manufacturer to produce a
commercially available ota: the CA3080. Lately, dual ota's have
been introduced by several manufacturers. These include the
RCA CA3280, the National Semiconductor LM13600, and the
Signetics NE5517. These new ota's contain input (linearization)
diodes that can be biased to predistort the input signal. The
input transistors in an ota already distort the input signal in one
direction, and so the two distortions cancel, allowing larger
input signals. Linear uses of ota's are covered in Chapters 5 and
6. The linearization diodes in ota's are generally not used in vco
circuits, because input saturation is desired.
Fig. 4-6 contains an oscillator circuit using ota's based on a
circuit in the RCA CA3280 data sheets. 4 Op amp IC2 bufTers the
voltage across capacitor Cl. This op amp (a CA3l60) may be
replaced with a TL08l or similar FET input op amp to elimi-
nate the necessity of +1-7.5-volt supplies. Op amp ICIB acts as
a threshold detector to alternate direction of current out of cur-
rent source ICIA. The voltage drop across diodes D1 and D2 is
fed to the ICIB noninverting input by resistor R14. Op amp
ICIB changes output states whenever the input to pin 10
reaches the threshold level set at pin 9. Note that the frequency
of this circuit (monitored at IC2 pin 6) is controlled by the cur-
rent through pin 3 of ota ICIA. If we apply the output of the
exponential converter to this pin, we will have a basic vco. This
circuit was intended as a function generator with a large
89
R4
FREQUENCY 36K
CENTERING
MIN RI -15 V RIO +15 V
+7.5 V
lOOK ..
R5 200 Il
R7
910K
R6 200 fl
-15 V
R9 2K
02 IN914
'NOTES
I. IC2 MAY BE TL081. LF356, OR SIMILAR (SEE TEXTI
2, CI WILL HAVE TO BE INCREASED
.001 - .01 pFI FOR AUDIO FREQUENCIES
3 C4 AND RI4 MAY BE ELIMINATED
(CONNECT ICiB PINS 9 AND 121
90
THERMAL CONTACT
Rl
CONTROL lOOK 1% R2
VOlTAGE IN
lOOK 1%
R9 SQUARE
-15 OUT
1.5 M
UNEAR FlilN
02
04
+15 V 62K
SINE
TRIM
R24
R25
lOOK
. 1M
R26 lK
R29
IK
TRIANGLE
OUT
-15 V R30
SINE OUT
IK
PWII/SM IN
R40
R31 SAW OUT
lOOK 47K lK
R36 300K
+15V
R35 -15 V
R34
lOOK 150K
INITIAL PUlSE R43 1 M
WIDTH/SAW
SHAPE -15V
'" R44
+15V
lOOK
SAW TRIM
91
from PWM/SM control R31. When the output of IC9 is fed into a
ground-referenced Schmitt trigger, such as IC 11, a periodic
pulse is output. The duty cycle and pulse width of the pulse
will vary as the average dc level of the triangle waveform varies.
Op amp IClO is made to invert the output of IC9 with a switch
signal from IC2. If FET Q3 is switched on, IClO acts as an in-
verter. If Q3 is off, IClO is a noninverting unity-gain amplifier.
If the output of IC9 is trimmed to 0-5 volts, the output of ICIO
will be a +/-5-volt sawtooth wavefonn. By varying the average
dc level of the triangle waveform the output of IClO will vary
from a normal sawtooth to a low-level sawtooth with twice the
nonnal frequency, as shown in Fig. 4-8. Op amp ICII acts as a
zero-crossing Schmitt trigger. It generates a pulse waveform
with a duty cycle determined by the dc level of the triangle
output of IC9. Resistors R48 and R49 attenuate the output of
ICll to +/-5 V peak to peak.
A vco circuit using a sawtooth current-controlled oscillator is
shown in Fig. 4-9. 6 The AD818 is a logarithmic amplifier
manufactured by Analog Devices. The exponential conversion
circuitry can be replaced with the lower-cost circuit in Fig. 4-4.
Op amps IC2 and IC4 make up a sawtooth oscillator with an
IC2 X
----uLJLIL
92
output of 0-5 volts. In operation the exponential current from
transistor Q2 charges integrator capacitor Cl. The voltage out-
put of IC2 rises linearly until it reaches the threshold of com-
parator IC4. The output of IC4 then switches from -15 V to
ground. This enables FET switch Q3 and discharges Cl.
Capacitor C4 and resistor R12 allow Q3 to fully discharge
capacitor Cl by creating an RC time delay of the voltage ap-
pearing at pin 2 of IC4. Without this delay, IC4 would oscillate
at a very high frequency, determined by its internal switching
time.
The sync input gives us the ability to reset the sawtooth oscil-
lator (the integrator) with an external pulse. This pulse is usu-
ally generated by another vco. Synchronizing oscillators in this
J u u u l
(e) Pulse output: le11
=fl,------,R,------,R,------,rL
93
RI
c>-N----,
THERMAL CONTACT
CONTROL lOOK 1% R2 /---\
VOLTAGE IN \
R3 lOOK 1%
lOOK 1%
R4
!OOpF
Rll 15K
39pF
10K
+15 V
R13 10K
C8
SYNC IN O-----j
100 pF R14
SYNC OUT 10K
R35
10K
R34 18K
R38
-15 V R39 2K
R423K
PULSE
OUT SINE
+15V( \3TP3 SHAPE -
R43 15K lOOK -15 V rRIM V
TRIANGLE DC TRIM R56 rp4 SINE
lK
PC3 04
lOOK R48 1M
R50 150
1:' V( INITIAL
PULSE WIDTH ALL DIODES IN4148 ETC_
ALL RESISTORS '/4 WATT
94
slave vco is modulated while the master oscillator frequency is
held constant.
Resistor R5,S in the integrator corrects for high-frequency
tracking error caused by the finite switching time of the FET
switch. The inclusion of this resistor in the integrator causes the
output of the oscillator to reach the threshold point of the com-
parator sooner, making up for this switching delay. If the value
of this resistor is increased, it can also correct for the bulk emit-
ter resistance problem in the exponential convelter. This resis-
tor generates a similar linear term that only becomes apparent at
high frequencies. The value of this resistor may have to be ad-
justed for best tracking.
Op amps IC5, IC6, and IC8 form a sawtooth to triangle-wave
COIl\'elter. Op amp ICS amplifies the sawtooth output of the
integrator (IC2) to +/-10 V. Inverter IC6 pH)\'ides an inverted
sawtooth output signal to attenuator resistors R28 and R29. Di-
odes DI and D2 sum the positive ramp of the sawtooth
waveform from op amp ICS and the negative ramp from IC6,
resulting in a triangle wa\'e of 0-10 volts. Op amp IC8 amplifies
and shifts the level of this signal. Capacitor C6 and resistor R26
(on the output of IC5) compensate for "glitches" that occur in
the triangle waveform due to the drops across diodes D I and
D2, by introducing a similar glitch of reverse polarity. Capacitor
C7 (in the feedback of IC8) filters out or reduces any residual
glitch present. The output of IC6 can be used to sync similar
oscillator circuits. Op amp IC9 functions as a Schmitt trigger,
providing a pulse whose width is determined by a reference
voltage from op amp IClO.
Sine wave conversion is achieved hy FET Q4 and op amp ICll.
The resistance of Q4 will vary with the voltage appearing at its
gate. As the signal level of the triangle wan-form increases, Q4
attenuates or "rounds off" the peaks. Thus the signal across resis-
tor RoSO resembles a sine wave. This signal is amplified and
fered by op amp ICll. Trimmer resistors TP4 and TP5 adjust the
symmetry and "roundness" of this sine wave.
The last two vco circuits (FigsA-8 and 4-9) included various
types of w(lvcslwlJing circuits. The f()llowing arc additional
examples of methods used in \'CO circuits.
95
It is possihle to perform a triangle to sine-wave conversion
using piecewise linear approximation techniques (Fig. 4-10).
The diodes in this design each begin to conduct at different
input signal amplitudes. As each diode begins to conduct, it
shorts a portion of the input signal to ground through one or
more resistors. This has an overall effect of rounding the peaks
of the input triangle waveform to form a sine wave. Capacitor
Cl blocks any dc offset in the input waveform. It may be left out
if the input signal doesn't contain an offset, or if an offset trim-
mer is added to ICIA.
+15 V
RB 2.2K
01
R9 56 n
R4 D2
B.2K
RIO
R2 03 120 n Rll
220 n
R3 R5 04 R12
10K 27K 220n
05 R13 120 n
Rl
lOOK
.R14 56 n
06
R6
R15 2.2K
-15 V
SINE OUT
01-06 IN914 OR DIODE ARRAY +/-5 V
SUCH AS CA3039
96
+15 V
INPUT
LEVEL TRIM R4 27K
RI R2 IIzCA3280
INPUT
+/-5 V lOOKs 10K
TRIANGLE
R5 +15 V
lOOK
R9 R6 51 {)
1M
-IS V 9 BIAS
R7 200 {)
R8 +15 V R13
lOOK
SINE
OUTPUT
+/-5 V
Rll 1M RI2 2K
o RI4
+ 15 V -15 V
lOOK
97
+15V +15V
TRIANGLE
INPUT o---+---J\IYV-----t--{ 1--__
+/-5 V 47K S SYMMETRY
+15 V 330n
-15 V
SHAPE 47K
27K Q1Q2 = 2N3417
-15V -15V
ever, generally had too Iowa frequency range and used linear
rather than exponential voltage control. As music synthesizers
became more and more popular, a market was created for cus-
tom vco ICs that could be used in electronic instruments. Such
ICs would reduce cost by cutting down parts inventory re-
quirements, testing time, and pc board space. Solid State Micro
Technology for Music was one of the first to introduce such an
IC-the SSM2030. This IC performs well enough to be used in
polyphonic synthesizers.
A block diagram of the SSM2030 is shown in Fig. 4-14.1 Ex-
ponential converter transistors (commonly called "log" transis-
tors) are provided in the Ie. The current controlled oscillator
contained in the chip is similar to the circuit (IC2 and IC4) of
Fig. 4-9. The exponential current generated by the transistor
pair is "mirrored" and used to charge a capacitor. When the
voltage across the capacitor reaches the threshold of the com-
parator, the comparator triggers a one-shot. This one-shot gen-
erates a pulse that causes a transistor to turn on and discharge
the capacitor. The capacitor voltage is buffered and brought out
on pin 6 as a lO-volt sawtooth.
The falling edge of a pulse connected to the "hard sync"
input (pin 7) will cause the oscillator to be rcset. The same
input to "soft sync" input (pin 11) will reset thc oscillator only if
the internal sawtooth ramp is near (.5 percent) the discharge
level. This method does not "chop up" the output waveforms as
98
+15 V +15 V
R6
R1 33K
R2 33K
"TI
cpo 1'\/'v TRIANGLE R3
10VPP IN R7 SINE OUT
of" 18K
.... ! 150 n
R4 47K
14 R9 S SYMMETRY
SIN,
3 2 13 20K
c
;:;:-
-S'
c...
R5 330
SG1858
RIO
a
47K o-15V
"C (CA3054)
0 IC2
III Rll +15 V +15V
III 4
R12 6.8K
III
< lOOK I R14U3K
III
0 8
11 I C4
-3 01
..,0 9
:::I -15 V 7
<
III +15 V +15 V 6 lOpE
;:l. R19 10K WIDTH
III
..,... PWM
R28
AUDIO
R21 R16 4.7K 12
! R20t:J+l" Q2 MODULATED
IN TAPER lOOK lOOK -15 V PULSE OUT
..,=rc -15 V R17 lK R18 5.1K
!=+' + 15 V 390
R22 R24 10K -15 V RI0K 0-10 V
20-100K n R27h5K
LINEAR R29 300K R23
TAPER TRI/SIN o-.;v<;
-15 V IN lOOK
'"'"
1
1
-v
+15 V
4K SOFT
SYNC
11
8K
hard sync does. Typical waveforms for both types of syncing are
shown in Fig. 4-15.
An emitter follower in the SSM2030 is biased to generate the
top half of the sawtooth waveform at pin 5. The sawtooth is sub-
tracted from this signal by an external op amp to provide a
triangle waveform.
An internal comparator in the SSM2030 is available for use in
pulse width modulation. Its output appears at pin 8.
Fig. 4-16 shows a complete vco circuit using the SSM2030.
The voltage control circuitry should be relatively familiar to
you. The elimination of any high-frequency tracking error is ac-
complished by feeding back a portion of the SSM2030 emitter
current at pin 13 through diode D2 and resistor R31 to the base
of the first log transistor. Thermal compensation is provided by
a positive temperature coefficient (3600 ppm) resistor that is
placed in physical contact with the SSM2030. Op amp IC3 and
its associated resistors modulate the width of the pulse gener-
ated by the 2030. A voltage of 0 to 10 volts on pin 9 of the
SSM2030 will vary the pulse width output on pin 5, from 0 to
100 percent. Control R55, IPW (initial pulse width), allows man-
ual control of pulse width with or without a modulation input
on the PWM IN control, R53. Op amp IC4 transforms the -0.5- to
7-V pulse output on pin 5 to +/-5 V. Op amp IC5 transforms
the 0- to 10-V sawtooth at pin 6 to +/-5 V.
Op amp IC6 subtracts the sawtooth wave from the "half-
sawtooth" signal of pin .5 to create a triangle waveform. A low-
100
HARD SYNC
INPUT
I I I I
I I I I
/W1V1VL1
I I I I
1
I
:
I
i
I
iI lOY
SAWTOOTH I I I I
OUTPUT
SOFT SYNC
INPUT
I I I I
I I I I
/Vl/l&V1
I I I I
,1 I I' I IOV
SAWTOOTH
OUTPUT
101
f-'
o HARD
t:-O SYNC IN a Cl i HARD Hf15V
SYNC
R2 R7 R8 1000 pf V_ 1 - 15V
1 VIOCT
lOOK 1%1 90.9K 20K
+15 V 20T
VIOCT
PULSE +1-5 V
OUT R22
"T1
cE' SAWTOOTH
I -". n" t +1-5 V
... OUT
SAW 6 1 +1.5 V WoK R?oLOOK I
2030
IC7
YAR
l> R6
470K
< lOOK
(')
o
lN9l4
C
III C2 t [;
3' LINEAR R32 C6
13
CQ CY IN lOOK 1.5 M 0.1 p.f
:r'
..
CD CAP
3 47K
en C5l1000 pf
en R49 POL YSTYRENE
r
3: SOFT 15
SYNC IN _ _ _- , CaMP R42 $1K
1 I ] DIS 1000 pf
e #2
o 11 SOfT GND
r; lOOK SYNC
PWM R53 PW
IN lOOK GND
MOD
i+I-5V)
+5V
o OUTPUT OF le6
-5V
Fig. 4-17. The signal levels of the sawtooth to triangle-wave
conversion circuitry of Fig. 4-16.
10.3
Rl Rl
R2 R4 R2 R4 (INTERNAL)
R3 R3
SUMMING SUMMING
/
NODE NODE
(Ie PIN)
104
CONTROL 1
VOLTAGE ! VI. lOOK lOOK
INPUTS 2 R'
+15 V
R6
COARSE lOOK 300K
-15 V
R7 R8
." SCALE
cpO FINE lOOK 13M RII RI2 +15 V
-IS V R9 16
10K e Rl3 24K
'#< IS
.... 5.6K It I 141 Rt5 RIG _ MUll ERROR
!D CEM3340 TRIM
8200
RI8 IN
:to , "'"
C1 2'
POS o---1f-- _____ R11 lOOK
...<
o HARD O,QOl ).iF 1M Ol"f _
R13 C5-
Q. SYNC
C3
... NEG o--H-
C 0001 "f
;:;:
C 1-'"
<II -15 V R16
:i' PWM
CQ IN
.. R28
::r
CD
C')
m IK
10K CIO
w
w
lOOK
? IPW
I'
+/-5 V
SINE
.....
o
CJt
the log transistors is achieved by converting the exponential
current on pin 7 into a voltage and feeding it back into the con-
trol input pin (pin 15). Trimmer R25 is set to minimize high-
frequency tracking error. Initially the wiper of R25 is moved to
the ground position and the 1 V/OCT scale is adjusted for low
octaves with trimmer Rll. Trimmer resistor R25 is then ad-
justed for minimum tracking error between low and high
octaves.
The CEM3340 is capable of both hard and soft sync. Soft sync
is achieved by applying negative pulses (0 to -5 V) through
capacitor C7 to pin 9. Positive voltages should not be applied to
this pin. If this input is not used, it is recommended that it be
bypassed to ground with a O.I-JLF capacitor to prevent possible
triggering due to spikes on the power supplies.
Two variations of hard sync are provided in the circuit of Fig.
4-19. The basic current controlled oscillator in the CEM3340/
45 generates a triangle wave. Hard sync causes the triangle
ramp to reverse direction. A positive pulse applied to the posi-
tive sync input in Fig. 4-19 will force a rising triangle wave-
form to reverse direction. A negative pulse applied to the nega-
tive sync input causes a falling waveform to reverse direction.
The pulse signals into the sync pin (pin 6) should be from 0 V to
a maximum of 3 V.
Pulse width modulation is achieved by a 0- to 5-V level on
pin 5 of the CEM3340. Op amp IC2 and its associated resistors
R26-R33 allow manual and/or external control over the pulse
width. The pulse output of 3340 appears on pin 4. The level at
this pin is normally 0 to 12 volts for a 15-V positive supply. A
zener diode (Dl) is used to drop this level to 0 to 10 V. This can
be level shifted to +/-5 V, if desired. The pulse output on pin 4
will have a slower fall time compared to the rise time, due to
limitations in the internal comparator. An external circuit such
as Fig. 4-20 can be used for rise/fall times.
Op amps IC3 and IC4 in Fig. 4-19 condition the sawtooth
and triangle outputs of the CEM3340 to +/-5 V. Load varia-
tions on the triangle output of the CEM3340 (pin 10) wry the
frequency of the oscillator. Therefore a buffer or constant load
is required fiJr this pin if it is used. Triangle to sine-wave con-
version is achieved by the circuitry of IC5 and IC6.
Not to be outdone, Solid State Micro Technology for Music
has recently introduced the SSM203.3 vco IC. This is an im-
106
IPW
lOOK
PWM 300K
IN
+1-5 V lOOK lOOK
+1- 5 V
300K 2K PULSE OUT
lK
O-IO-V SAWTOOTH IN
(PIN 8 CEM3340)
Fig. 4-21. A block diagram and Ie pinout of the SSM2033 yeo. (Courtesy
Solid State Micro Technology for Music, Inc.)
107
generates an exponential current to enable further trimming of
the high-frequency tracking error. A diagram of the voltage con-
trol circuitry is shown in Fig. 4-22.12
+V
VlOCTAVE
'-. J A, =0 3.01M 1%
I V. V, + V2 V.
R.
1%
F\ + f\ = lK
REFERENCES
1. Hutchins, Bernie, "Voltage-Controlled Oscillator Design:' Musical
Engineer's Handbook, 1975, p. 5B (10).
2. Hutchins, Bernie, and Doug Fullmer, "Readers' Ideas," Electronotes,
No. 52, April 1975, p. 13.
3. Mikulic, Terry, "New VCO Circuit from Terry Mikulic," Electronotes,
No. 62, February 1976, pp. 13-14.
4. RCA Data Sheet CA3280, File No. 1174, Somerville, NJ 08876,
1979.
5. Hutchins, Bernie, and Bill Hartmann, "ENS-76 VCO Option 2," Electro-
notes, No. 75, March 1977, pp. 10-14.
6. Hutchins, Bernie, and Terry Mikulic, "ENS-76 VCO Option 1," Electro-
notes, No. 75, March 1977, pp. 6-9.
108
Rl
+lS V 54.9K 1%
'RS AND R6 CHOSEN fOR BEST
R1H800 +lS V HIGH fREQ TRACKING
R5&R6"lK
Cl
+lS v
!
0.1 !If
I h.
"
cP' TO R18
SOFT IS
.p. 1=1 I I 'R5 I 'R6
SYNC R3 Cl I
---<---
14K 300 pf ICI 15M f--o LINEAR FM
1 R7 SSM
1033 11 R18 C4 . 0.1 !If INPUT
l> CONTROL lOOK Rl1 RH3.3K V/OCT R16 "
VOlTAGE 470 R19
< 1 V/OCT 3 R8 C3 10K CERMET C6 P 0.1 !If 301 M I'
8 11 IOLY:RENE . C7
y, +lS V
n +15V JiOOOpf
RIO I 10 pf RIO
t 10 pf
Rll ,'""u 0 ""'"
lVVf\ +15 V 300K lOOK
c COARSE R16$15K
;:;.' DI.5 lOOK
-15 VV vv- R19 +1-5V
c FINE 100Kr- 3."3M 91K
911 1%
en R14 SAWTOOTH
CI0 lK
-15 V -15V lOOK"
cc o--H-
HARD 1000 pf 11K C8
J
..:i'
(II SYNC -H-
ID pf R15
VI ---w-.-
VI lOOK
s:: ICI ."
N lOOK
lK TRIANGLE
e C9
<
n ROUNDNESS
o 47K
R31 "lOOK
?> lK R49
+1-5V +1-5V
---0
NOTE lK SINE
MAY SUBSTITUTE ONE R43ilK PULSE R33 lK
TL081 fOR TWO n081
OR
USE SIMILAR fET INPUT R45tK 0-15 V
f-' TYPE OPAMPS SINE
oCO SYMMETRY
7. See No.4 above.
8. CFR Technotes, No. 11.
9. CFR Technotes, Vol. 3, No.5, pp. 4-5.
10. Solid State Micro Technology for Music, Santa Clara, CA.
11. Solid State Micro Technology for Music, Santa Clara, CA.
12. Solid State Micro Technology for Music, Santa Clara, CA.
llO
FILTERS
FILTER BASICS
Filters are characterized by the frequency portion of the input
signal they allow to pass through, unattenuated, to the output.
Some of the more typical filter responses are illustrated in Fig.
5-1. The most popular type of filter used in electronic music,
the low-pass filter (lpf), passes low frequencies and attenuates
higher frequencies. A high-pass filter (hpi) does just the oppo-
lli
site. A bandpass filter (bpi) attenuates those frequencies higher
and lower than the desired pass frequency. An all-pass filter
shifts the phase of an input signal. As a very simple example,
the all-pass filter would delay the signal as it passes through the
filter. Thus, if we look at both the input and output signals, the
minimum and maximum of the output signal will not occur at
the same time as those of the input signal. Thus they are out of
phase. Higher frequencies are shifted more than lower fre-
quencies with this type of filter. When the shifted signal is
summed with the input signal, notches are created in the fre-
quency response where the two signals are 1800 out of phase (a
half-cycle apart). This type of filter produces the popular "phase
shifter" sound often used with an electric guitar.
The rate of a filter's attenuation is called its rolloff. The
sharper the rolloff is, the more noticeable the filter's effect be-
comes. Filter rolloffs are specified in terms of decibels per oc-
tave. The decibel (dB) is a unit of measure for comparing
FREQUENCY
AMPLITUDE
FREQUENCY
112
relative signal levels in a circuit. The formula for measuring
decibels for voltages V and V 2 having equal impedances is
j
AMPLITUDE
FREQUENCY 20 kHz
AMPLITU DE """"".,.......,...........".".
FREQUENCY 20 kHz
filter responses.
113
24
22 /
20 ------ /
18 ---- /
16 /
iO 14 /
:s
en
.....
.... 12 /
""
c::;
....
c 10 -,/
8 -
7/
4
3 /
/
2
;(
1.3 1.4 1.6 2 2.5 3.1 4 6.3 8 10 12.6 15.8
114
resonance in a low-pass filter is shown in Fig. 5-5. Increasing
the resonance in a bandpass filter will sharpen the rollofl and
peak the response amplitude at the filter's designed center fre-
quency. The circuit's Q is defined as the filter's center fre-
quency divided by the filter's bandwidth (defined as the differ-
ence in frequency between the two cutofl frequencies). Higher
Q's mean sharper frequency responses. This concept is illus-
trated in Fig. 5-6.
Resonant filter banks (sometimes called responding filter
banks) are designed with a group of high-Q bandpass filters that
are all fed the same input signal. The filter outputs are summed
in a proportion determined by the user to obtain a desired out-
put timbre. A common filter bank is the graphic equalizer, used
in pa systems and recording studios. Fig. 5-7 shows a filter
bank using bandpass filters.
If the resonance of a filter is set so high that the filter is close
to the point of oscillation, a sharp pulse fed into such a filter
will cause it to ring or oscillate for a short time at the filter's
center frequency (Fig. 5-8). This effect is utilized in many
rhythm percussion boxes to simulate congas, drums, and so on.
The complexity of a filter circuit is directly related to its
rolloff rate. A simple passive filter, using only a resistor and a
capacitor, has a rolloff of -6 dB/octave (see Fig. 5-9A). This
matches the curve of the capacitive reactance for the circuit.
The order of a filter relates to the number of such RC sections
in a filter circuit. The simple RC filter is a first-order filter. A
simple active low-pass filter, using an op amp, two resistors, and
two capacitors (such as the one shown in Fig. 5-9B), is a
second-order filter.
The order of a filter circuit also relates to the number of fre-
quency poles it contains. A frequency pole is the cutofl fre-
quency of an RC circuit in the filter circuit. A fourth-order
low-pass filter may have four poles of the same frequency or of
scattered frequencies. A sharper rolloff is obtained if the poles
are slightly scattered. However, the audible difference is not
worth the extra design effort if the filter is to be voltage con-
trolled. The majority of filter circuits used in electronic music
are made up of combinations of second-order filters. Generally,
a fourth-order filter can be made by cascading two second-order
or four first-order filters. The sharpness of a filter's rolloff is di-
rectly related to the filter's order by
115
rolloff slope = filter order x -6 dB/octave
OSCILLOSCOPE
VERT
INPUT
+2 em
1--I------j------'\--l-----+------1 + 1 em
1 - - - - - ! - - - - - - I - - \ - - - - 1 - - - 1 - -1 em
----'--------'---"""'-'""""'----- -2 em
(8) Passband frequency adjusted to +/-2 cm.
116
design of their vcf circuit(s) since they realize that the result
will affect the synthesizer's sound capabilities. Generally, a
higher-order vcf is more useful than a lower-order vcf. The
closer a filter's rolloff approaches a complete cutoff, the more
impressive it sounds. As mentioned earlier, to obtain higher-
order filters lower-order filters are cascaded (put in series). Each
stage in the filter is identical in design.
A typical first-order low-pass filter is shown in Fig. 5-10. At
low frequencies the capacitor is effectively out of the circuit and
the circuit is an inverter with a gain that is determined by the
resistors (usually unity gain). At higher frequencies, however,
the capacitor begins to look more and more like a resistor and
finally assumes a resistance less than the effective resistance of
resistor R f . Thus the output will have a frequency-dependent
gain, A, found by the formula
.-------,--------,-------,-------,+2cm
1.4
f----I------\---+-----+ --l---\------I----+---+-I + 1 em
1.4
_ _ _ _ _ _ L __ _ _ _ _ _ ____ -2cm
117
SWEEP
OSCILLATOR
SAW
OSCILLOSCOPE
N--.. 010 V (EXT
.y HORIZ
IN)
FIL TER
VCO UNDER OUT .X (VERT
TEST INPUT)
SINE/IN
/
2 Hz 20 kHz
-
-
I
-
-
('\
f\ -
-
\J
-
-
-
-
(8) Sample low-pass response.
creases at a rate of llf, we see that for a I-octave change the gain
is 112, for a rolloff of -6 dB. What remains is to find a way to
control the cutoff frequency of the filter circuit by applying a
voltage to it. This is where the ota comes to the rescue. Several
voltage-controlled, first-order, low-pass filters using ota's are
shown in Fig. 5-11. The signal is attenuated before being fed
into the ota to prevent overdriving the input (we don't want a
triangle-wave to sine-wave converter here!). The input signal
118
CUTOFF
FREQ
dB
dB
T
-3 dB
Q _ CENTER FREQUENCY
- BANDWIDTH
FREQUENCY
BANDPASS
FILTERS
INPUT OUT
ETC.
1
INPUT
PULSE
HIGHQ
BANDPASS
FIL TER
OUTPUT
120
(A) A first-order low-pass filter.
121
R;
INPUT
>--._--0 OUTPUT
122
lOOK
2N3819
OR
SIMILAR
IN PUT c-----'\N\r----.--l
lOOK
10K OUTPUT
-15 V
INPUT
INPUT
lOOK
220 n INTERNAL
BUFFER
OUTPUT
nOn 10K
-15 V
123
HI
control voltage offsets that will have to be trimmed out, and will
end up costing almost as much as a custom IC. Custom ICs have
an excellent signal-to-noise ratio (typically 90 dB), low distor-
tion (0.02 percent), and high control-voltage rejection (low con-
trol voltage feedthrough to the filter circuit, signified by "pop-
ping" or changes in the average dc level of the signal).
124
1 VIOCT
CONTROL VOLTAGE
SIGNAL
INPUT
OUTPUT
RESONANCE
F = SINGLE-POLE LOW-PASS FILTER
125
CO""TROL
,
CAP
G e
126
ENVELOPE
IN
R2
RI -----,
+15V
b 141 0.001
POL YSTYRENE
SSM 2040
IC2
OUTPUT
INITIAL Q
R34
-15 V +15 V
lOOK
(A) Circuit.
IREMOVE 1C4.IC5.IC6
CIRCUITRYI
127
(A) Pin diagram. (B) Functional block diagram.
INCREASING OSCILLATION
Q
A ------------ --
M R
E 1
s R'-
4J4T
I
T
0
N
A J
/
N
U c
o E
E - __________ --
/
FReaUENCY "
" FfEDBACK " ..
(A) Amplitude vs. frequency. (B) Resonance vs. feedback.
128
+ 15 V Q REJECTION TRIM
(OPTIONAL)
R3 R4
Rl 50K
." SIGNAL
IN 16 R5 -15 V
68K +15 V
R7
CfI 15 SIGNAL IN
15K
...!lO C5
+15 V ) 14 'V/OCT
l>
R12 15 pF C3 SSM 2044 O.OI/lF R13 o R15 R16
<
n R8 IC2 13
-6' 47K 470 pF 150K 50K
c: 1%
12
-UI
:j' R9 C4 C6
R19 R17 CV
CQ 470K 1 VIOCT
5K Q 6 11 *R14 lOOK
:T REVERSE 1%
..
CD
AUDIO
O.OI/lF lK
(J) RIO 10 TC
(J) 18K +15 V
.. OUT 150K
3: +15 V R18
N 8 1% R21 FREQ
0 -15 V
o R20 FREQUENCY lOOK
'OPTIONAL (SEE TEXT) 50K OFFSET TRIM
(OPTIONAL) -15 V
RESISTORS '/, W 5%. UNLESS OTHERWISE NOTED
-15 V
CAPACITORS POLYSTYRENE OR DIPPED MICA
f-'
tv
CO
signed so that the maximum peak-to-peak voltage at pin 13 will
correspond to the maximum sweep range desired when the out-
put of the op amp swings from supply rail to supply rail. This
corresponds to 90 m V at pin 13 and a 1000-to-1 sweep range
for 15-V supplies.
Fig. 5-19 is a block diagram of the Curtis Electromusic Spe-
cialties CEM3320 vcf IC. This IC contains an exponential cur-
rent converter, four gain cell/huffer stages, and a variable trans-
conductance cell useful for voltage controlled resonance. The
gain cells are of a different design from typical transconduc-
tance cells (used in the SSM2040) in that they are current-in,
current-out circuits (rather than voltage-in, current-out). Each
cell is temperature compensated. The IC has a signal-to-noise
ratio of 85 dB, low distortion, and can he configured for several
filter structures.
The input to the CEM3320 gain cell is essentially a forward
biased diode to ground. It is therefore a low-impedance sum-
INPUT A 1 h-----,
GROUND 3
CAPACITOR B 4
CAPACITOR A 5
OUTPUT A 7
RESONANCE
INPUT '1 CAPACITOR D
RESONANCE
CONTROl.
130
ming node at a nominal 650 m V above ground. The required
input currents are thus created with input resistors to this node.
For dc stability and a constant reference current to bias the
input diode, a feedback resistor is connected from the buffer
output to the summing node. The output current of the gain cell
is given by the formula
where
V T = KT/q,
V c = voltage applied to pin 12,
AlO = current gain at V c = 0 (nominally 0.9),
[rd = (0.46V cc - 0.65 V)/(105 n 25%).
Vode = 0.46V CC
The output impedance of the gain cell has a finite value and
looks like an ac resistance of 1 megohm in parallel with the
feedback resistor Rf (l00 kilohms) to the input. The pole fre-
quency of each stage is determined by the total equivalent
feedback resistance (R"q) and the pole capacitor C p as
131
where
Req = (R f x 1 MO)/(RJ + 1 MO),
Aro = current gain at V c = 0 (nominally 0.9),
V c = voltage applied to pin 12.
132
CI
SI ,NAl
IN PUT R3 22 pF
R2 36K
RI - C2 R5 RIO RII
lOOK lOOK ICI
, -15 V
+ 91K 240K lOOK
Tl081 R6 RI2
'" R4 15K
"TI lOOK 91K
cp' R7 RI3 CONTROL
... VOLT AGE INPUTS
U! 91K lOOK
R8 RI4 I VIOCT
'-<I 18 p- FREQ
lOOK 91K
R9 RI5 RI9
2 17 ENV IN +15 V
-15 V 240K C5 240K -15 V lOOK
3 R18 lOOK *
CEM 3320 16 >j';"1 R17
1% R20 150K
IC2 1%
4 15 RI6
c C4 lOOK lOOK 1"1.
'"
:;' 14 0--0+15 V R22 R21
CI:I 5 -
H07 R24 +15 V
6 13 j'20K8 9IKI"I.
=r
.. IK 1.5K e CV HEJ
R23
(") 7 12 IC3A 180K
56K 1"1. +
"m C6 R27 1"1.
8 R261lK 'j, TL082 cc
S 11 f-;!O( pF 1 TC
EXT R28 -15
REJ 9 10
CONTROL lOOK TELLABS
< C8 C7 Q81C
!l. R29 47K R31 ro. R32
f) R30
,, 51K I lOOK !I-:--
22 pF R33
+15 V I
lOOK I 300K
R35 ,Jo...
MANUAL R36
RESONANCE M 180K rlC3B
e R38
Q
f-' C3, C4,C5, C6 = POLYSTYRENE DC TRIM
FEEDTHROUGH
W (OPTIONAL)
W
REGENERATION
CI RI
IO.O"F
C4 R3
n2 lOOK
C5 R4
lOOK
INPUT
R6 10K HOSITION
R7 ROTARY SWITCH
10K
R9 " RIO
IC2 8.2K 5K
+ CANCELLATION
R8 IK
AUTO
134
quency sweep with fast sweep rates. However, this is not
objectionable -it is often preferable. The O.l-p,F capacitors
shown in the shifting networks are chosen for phasing action in
the lower frequencies. Some users may prefer a higher value,
such as 0.01 p,F. The phase shifter sounds best if all of these
capacitors are of the same value.
The setting of switch S 1 determines if the circuit acts as a
phaser or a vihrato. With S 1 open the circuit will be a vihrato
since the signal is being shifted in time (phase). With S 1 closed
the shifted signal is compared with the un shifted signal, creat-
ing notches in the frequency response where the two signals are
1800 apart. Switch S2 switches between phase stages. As the
number of phase stages increases, so do the number of notches.
A variation in the control voltage will shift these notches up and
down the frequency spectrum. Trimmer RIO (near IC2) is ad-
justed for optimum notch depth. The regeneration control (Rl
near ICl) feeds the output signal back to the input, thus increas-
ing the intensity of the effect.
A lot of experimentation can be done with this circuit. For
example, the source of regeneration can originate from the
phase shifting circuitry (connect regen pot to wiper of S2) be-
fore being summed with the "clean" signal at IC2. The number
of phase shift sections can be increased. Peaks will be created
in the frequency response (instead of notches) if the shifted
output is inverted before being summed with the clean signal.
Also, the circuit is designed for unity gain. If lower-level signals
are to be used (such as those from a guitar) a better signal-to-
noise ratio will be obtained if the gain of ICI is increased, caus-
ing a larger signal to pass through the shifting circuit. The out-
put and the clean signals are then attenuated as they are mixed
by using larger values for resistors R6 and R9. Notice that in-
creasing regeneration will increase the signal level (or even
cause oscillation). Therefore you will have to leave some head-
room for this increase in signal level throughout the circuit.
Fig. 5-22 contains a two-notch, voltage controlled, all-pass
circuit using the CEM3320. 2 Much of the control circuitry is
similar to that in the vclpf circuit seen previously (Fig ..5-20).
Fig. 5-23 contains a voltage controlled, all-pass/low-pass
filter using the SSM2040. An all-pass response (two notch) is
achieved by switching all the capacitors to the previous stage.
Grounding the capacitors as shown will produce a four-pole,
135
CI
RIO RII
-15V
RI 240K RI2 lOOK
10011.
RI3 CONrROl
VOLTAGE INPUTS
10011.
1 VIOCT
fREQ
Ri RI9
-15V + 15 V
ENV lOOK
IN RI8 lOOK
lOOK
100 pf R17
15
lOOK lOOK
+ISV CV RE]
14 TRIM
13
IK 1.511. 0
12
C6
II
EXT 100 pf -15 V
R28
REJ 10
CONTROL lOOK
R29 17K C8
R30 210K
+15V R32
lOOK C7
TO POINT R37 lOOK
MANUAL Q
X
lOOK
136
(A) Circuit.
INCRE",SIN(;
a
WITH
", REGENER ... TlON ,
--:
lOOK
1.5 M
CA3080.ETC
INPUT O----.----JlNv---+--p..
lOOK
OUTPUT
>-----0 (0-1800)
27K
-15V+15V
Vc
Fig. 5-24. A voltage controlled phase shift network using an ota.
137
noise increases as more stages are added. The use of the new
dual ota's with linearized inputs will reduce this problem
somewhat.
State-Variable Filters
The state-variable filter (sometimes called a universal active
filter) is a filter that provides low-pass, bandpass, and high-pass
responses simultaneously. The basic configuration is shown in
Fig. 5-2.5. This circuit will have 12 dB per octave high- and
low-pass responses and a second-order bandpass response. The
high- and low-pass outputs are 11'>00 out of phase. Comhining
these two outputs will give a notch response. This type of re-
sponse, however, is not very useful, as it is hard to notice any
difference in the sound unless the notch is wide. Control-
ling this type of filter with a variable voltage is accomplished
using voltage controlled integrators for these two outputs.
A yoltage controlled state-variable filter using ota's appears in
Fig. 5-26. 3 Emitter follower Q1 sets the minimum output cur-
rent for the exponential current converter circuit at 100 /LA. The
collectors of Q2 and Q3 must go to a point more negative than
their emitters to enable them to source current. The maximum
limit of this current will be set by resistors R13 and R14 (15
VIlS kn = 0.S3 mA). The maximum value of this current will
Rl
Rl R R
INPUT O--'I/V'or........-l
BP
138
Rl
139
the full range of frequencies by capacitors C1 and C3 (on the
outputs of IC2 and IC4, respectively). These provide a phase
lead for high frequencies, making up for phase lag caused by
the internal circuitry of the ICs.
To determine the high-frequency cutoff for this circuit, we
must know the formula for the ota output current. For the
CA3080 this is
where
lout = output current in amperes,
Ie = control current in amperes,
V[)f = differential voltage, in volts, between ota inputs.
V[)f = 22 V in = 0.011 V or 11 mV .5 V)
10000
1
16.9 kHz
6.28 X 28.6 kn X 330 pF
Trimmers R25 and R32 are for adjusting the rejection of the
control voltage by the filter. Initially they are set to their mid-
140
range and then each is adjusted for a minimum output dc shift,
while the coarse frequency control is varied over its full range.
A similar state-variable design using the SSM2040 is shown
in Fig. 5-27.4 In this circuit two second-order state-variable
filters are cascaded to form a fourth-order filter. Switch S 1 will
switch between 12 and 24 db-per-octave responses for the var-
ious filter responses. Since the SSM2040 does not have on-chip
voltage controlled resonance, an LM 13600 is used in the "front
end" of the filter. The signal input to this filter should not ex-
ceed 10 V peak to peak. The voltage control circuitry of IC5A
should be familiar to you by now. If desired, a positive tempera-
ture coeflicient resistor can be substituted for R47 on the output
of IC5A. Trimmers PRI and PR2 must be adjusted to obtain the
correct filter responses. Initially, set them to their midrange and
monitor the BP2 output. Adjust PRI until an abrupt change from
a low-pass response to a bandpass response is heard. Leave PRI
at this setting. Then monitor the LP4 output and adjust PR2 for
a low-pass response at the output. Refer to Fig. 5-4 for more
preGise adjustment of these trimmers.
This filter is not designed to oscillate at high Q. Therefore the
1 V/OCT trimmer can be adjusted in one of two ways. The first is
to monitor the voltage at ICl, pin 7, for an lS-mV increase for
every 1 V increase in control voltage. The second method is to
track a calibrated sine wave vco that used an identical control
voltage. Adjust the control voltage (to the vcf and vco) for a vco
frequency of about 250 Hz. Adjust the filter frequency controls
for a peak in the bandpass output amplitude. Then increase the
control voltage (to both vco and vcf) 1 volt and adjust trimmer
PR3 for a peaking in the bankpass output amplitude.
Fig. 5-2SA contains a voltage controlled state-variable filter
using the CEM3320. This circuit is similar to the last one, ex-
cept some changes are necessary because of the 6.9-V offsets of
the gain cells. An LM13600 is used to provide voltage con-
trolled resonance. Its input is ac coupled to prevent level shift-
ing of the CEM3320 gain cell. Op amps (IC2-IC5) are neces-
sary for buffering the filter outputs and level shifting for a
ground-referenced output signal. The circuit shown is a
second-order filter. To obtain a fourth-order response, it is
necessary to casade two filter circuits as shown in Fig. 5-2SB.
(This is the same scheme used with the SSM2040.)
Unfortunately, this design requires a lot of external parts (op
141
...........l'O R9 SP2
." R16
cpo
30K 10K
U1 SIGNAL I
N
o"j RVI R51 Rll lP2
lOOK 10K 11K
LIN Rll
):>0 10K
< 11I'F R4 NPl
n-
0'"
c: III
CD CD I I C7
'" n
'<:0
ma
-i"" 10K
-0 RI6
OUTPUT
10K 1r7 I .11I'F 10K ICI8
OJ Q.
SIA IK
co (II
-111
...
::J ... R13 SP4 NOTE:
(1) CD ICI IS SSM1040
Q) < R14 15K lP4 ICllS TlO81CP
:;, III IC3 IS lMI3600
Q. ::!. 11K IC4.ICI ARE nOS1CP
tJIII Rl1 NP4
<Ci!:!: 14K PR3 VIOCT
(;i. CD R40
-II V
o ::!I R41 300K e 10K
c: ;::; CONTROL 1 CONTROL I MT
:;, CD ,
,Q. "" R41 lOOK
RV3
r-; lOOK lOOK TO PIN 7
..., _. LIN R43 OF ICI
Q.:l . +11 V
-IIV IIOK
...:r R37 DHJ R44 IK
CD +11 Vc c
en CI 471'F
en OVa 30K
MANUAL RVl
s:N -IIVo
1
C1 I 471'F
RESONANCE
R39 , ftL.'Io!UL' .... i RV5 tlCI PIN 16 = HI
CONTROL CONTROL lOOK LIN tlCI PIN 9 = -VI
0 TO PINS _
I & 16 (lCI PIN 8 = I
? OF IC3
R4
RIO <--w-r--+-p...
lOOK
IP
R23 lOOK
R21 10K
R33 R34
+15 Vo---""'---__
180K
+1511
FREQ EXT R41
R46
+15 lin
lOOK MANUAL
-15 V Q
lOOK
cvo--v.......J>-I::..... PINS 116
IMI3600
IC)-ICS = FET-INPUT TYPE IIC61
ITL08l OR SIMILAR)
(Al Circuit.
OUTPUT
HP2 ,
BP2 J
NOTCH
2-POLE,7-POSITION
ROTARY SWITCH
143
+15 V
180K
lOOK
lK
ROTARY
SWITCH ---o..
I LM356. Tl071
OUTPUT
(e) Output buffer.
Fig. 5-29. Output coupling methods for the circuit of Fig. 5-28.
144
SIGNAL
IN 91K C LP
lOOK
13 " lOOK
HP 0
H5V
-15 V
(A) Circuit.
POINTS A.B.C.D
(4 IDENTICAL CIRCUITS) lOOK OUTPUT
IK
"lOOK 180K
DC LEVEL
TRIM
vided for each section. For signals applied to the "fixed" input
(pins 2 and 12), the signal amplitude in the filter passband will
remain constant (.50 mV p-p) as the Q is varied. However, the
amplitude at the filter cutoff frequency will peak higher than
the passband amplitude as Q is increased. For some applica-
tions the input signal will have to be reduced in amplitude to
prevent a curious amplitude "jump" that occurs as the signal
frequency approaches the filter cutoff frequency. This jump in
amplitude occurs because the increased amplitude ati", due to
the high Q, overloads the gain cells in the filter.
A second input, called the "variable" input, limits the
amplitude at the filter eutafl frequency to 50 m V and at the
14,5
V+ VBP2 V1V2 VLP2 V1F2 VCQ2 VCF2 GND
11 10 9
CEM3350
GND
VIF1 Vlf2
146
*TH IS RESISTOR IS SELECTED FOR A CURRENT OF 400 pA
PIN liS 1.5 V ABOVE V-.
SIGNAL
INPUT +15 V
+15 V
Vee 400 J1.A t *68K
-15 V
VEE
V+ IREF
47K 16
220 !1
8 11 10 15 13
VLP1 VSP1 VCFl VeQ1 VeQ2 Vm VSP2 VLP2
0.02 J1.Q:
]02J1.F ..,.,- Q ]02J1.F ]02 J1.F
CNTL
INPUT D9.lK
5.6K 100 !1
100 !1
47K
+15 V
1 V/OCT
FREQ IK
lOOK 150K 91K 020K
-15 V
CONTROL SIGNAL
VOLT AGE O--.JvIOVlOK.---.I OUTPUT
I V/OCT
VARIABLE
INPUT Vee = +30 V TO 24 + VEE
VEE - 3 V TO - (24 - Vee)
lOOK 47K
D Q IS DOUBLED FOR EVERY -18 mY. INPUT RANGE
IS +30mV TO -90mV (PINS 6, II)
147
capacitor is buffered and amplified by an op amp for the final
output.
Fig..5-33 illustrates the required connections for two inde-
pendent state-variable filters. Note that for each filter only two
of the three possible responses are available at a time. The
normal outputs are the low-pass and the bandpass. By feeding
the input through a capacitor as shown, however, these switch
to bandpass and high-pass, respectively. The diode networks
shown in the schematic will reduce Q at large signal levels,
thereby eliminating the amplitude jump problem discussed
earlier.
OPTIONAL j,
LOW-PASS
OUTPUT
*tBANDPASS
OUTPUT)
BANDPASS
OUTPUT
IHIGHPASS'
OUTPUll
VARIABLE !-----,------ V
10 Vpp { INPUT
!--+------";IS':,-K- -15 V
+3'
TO
+151,1 NOTES
OUTPUTS WHIN SIGNAL
APPLIED TO HIGH-PASS INPUT
.1 OPTIONAL CIRCUIT TO PREVENT
JUMP RESONANCE" REDUCES
Q FOR LARGE OUTPUTS
VARIABLE o CNn
ovpp { INPUT 10K 15K -25 no +7.5 v
I FIXED ------"M----1 FREO CNTL
INPUT 10K -IIVlO-IV
BANDPASS
\--'Nv-"--"--'----
OUTPUT)
1.2K
LOW-PASS
OUTPUT
(BANOPASS OPTIONAL . ::.
OUTPUT)'
148
The frequency control input is meant to work with the now
familiar inverting summing stage common to other circuits in
this chapter. The control voltage range into pin 8 or pin 10 is
-200 mV to 0 mY. The scale is the standard -18 mV per octave.
The Q control input (pin 6 or pin 11) control range is +30 mV to
-90 m V. The Q increases by a factor of 2 for every -18 m V.
")
I I
I I
I I
I
I
I
Rs I
I
L
I
= = AT FULL CUT I I
vin 3K + Rs
I
I
(10) :
----------------
= 3K + Rs = AT FULL BOOST
Rs
149
,r--------,, IC2
100 {)
4.7 I'F
10 20K :
47K
lOOK
820 pF
L= ilRl QR2
hI, 2TI,
C2 = 1
(hliL
(A) Circuitry.
11
__
15 P-.,----f-....
"
-J
-.-.
-" 1----,...;.... ---+-,--......1-
-15
All CONTROlS flAT
-11 1 kHl BOOST, All OTHER FLAT
1 kHz CUT, All OTHER FUT
-Z1 AU CONTROLS BOOST
All CONTROLS CUT
FREQUENCY (Hzl
(B) Response.
fo(Hz) C, C2 Rl R2
32 O.12jJF 4.7jJF 75kQ 560Q
64 O.056jJF 3.3jJF 68kQ 510Q
125 O. 033 jJF 1.5jJF 62kQ 510Q
250 O.015jJF O.B2jJF 68kQ 470Q
500 8200pF O.39jJF 62kQ 470Q
1k 3900pF O.22jJF 68kQ 470Q
2k 2000pF O.1jJF 68kQ 470Q
4k 1100pF O.056jJF 62kQ 470Q
8k 510pF O.022jJF 68kQ 510Q
16k 330pF O.012jJF 51kQ 510Q
150
Vocoders
An interesting device using two sets of fixed filter banks is the
vocoder. Fig. 5-36 is a block diagram of a vocoder system. A
vocoder uses one bank of high-Q bandpass filters to frequency
analyse the input signal. The output of each bandpass filter is
connected to an envelope follower. The output of each
envelope follower is used as a control voltage to a voltage con-
trolled amplifier that follows another identical high-Q bandpass
filter. This second bank of bandpass filters is fed a different
input signal. The net effect is that the timbre of the first bank of
filters will control the timbre of the second bank. This leads to
some bizarre sound effects.
Due to the complexity of a typical vocoder system it can
hardly be termed a synthesizer module. Some useful effects,
however, can be experienced with fewer filter sections. If you
are thinking of designing a large vocoder system the following
two references can help you out:
ETI Magazine, September, 1980:
14-band unit with timbre "freeze" switch and slew rate
control (kit available from Powertran, Portway Industrial
Estate, Andover, HANTS SPlO 3NM, Hampshire, Eng-
land).
TIMBRE
CONTROL
SIGNAL
FHll F2FI3
OUT
151
Electronotes, No. 100; 16-band unit using state-variable
filters.
REFERENCES
1. ETI Magazine, Vol. 9, No.5, May 1980, pp. 20-25.
2. ETI Magazine, Vol. 9, No.5, May 1980, pp. 20-25.
3. Hutchins, Bernie, "The ENS-76 Home Built Synthesizer System-Part
5," Electronotes, No. 71, November 1976, pp. 14-18.
4. ETI Magazine, Vol. 9, No.7, July 1980, pp. 84-87.
5. National Semiconductor Corp., AudiolRadio Handbook. 1980, pp. 2-59
through 2-61.
6. Ibid.
152
ANALOG MULTIPLIERS
153
2 +
I-I x 1+1 =H 1+1 x 1+1 = 1+1
10 V
8V
6V
4V
x 2V
CONTROL
Y VOLTAGE
1010 VI 3 y - 4
154
2 + Y
+
x
ZIOUTPUT)
4
Discrete yeAs
The heart of most vca designs is a variable transconductance
amplifier (transconductance gm = Moutl6Ein). Before this became
available in IC form (ota) it had to be constructed with discrete
components. Fig. 6-3 contains a discrete vca using a CA3046
transistor array.l It consists of a differential amplifier (transistors
Ql and Q2) driven by a variable current sink (transistors Q3,
Q4, Q5 and IC2). The inputs of the differential amplifier (+IN
and -IN) will saturate with voltages approaching 100 mY. Up to
this point the collector currents and the input base voltages will
be exponentially related, as we have seen before. If the peak
input voltage level is kept very small, say below 10 m V, distor-
tion (due to the exponential function) is around 1 percent.
In Fig. 6-3 op amp ICI also acts as a differential amplifier,
sensing differences between collector currents and generating a
voltage that corresponds to this difference. As the emitter cur-
rents are increased by the current sink the corresponding col-
lector currents will increase and the magnitude of the differ-
ence between these two collector currents will also increase.
This has the effect of varying the gain of the circuit.
Op amp IC2 and transistors Q3, Q4, and Q5 form a linear cur-
rent sink for the differential transistor pair Ql and Q2. Since the
base-emitter voltages of transistors Q3 and Q4 are the same,
155
+15 V
lOOK lOOK
OUT
IK
+IN -IN
lOOK lOOK
22O!l
+15 V
+15 V
39K
1M
INITIAL DC
GAIN BALANCE
10K
lOOK
-15 V
CONTROL 680K
VOLTAGE IN 1N914
VARIABLE 220K
CV IN
The OTA
The ota has become the workhorse of many gain control ap-
plications. As shown in the last chapter, the gain of the ota is
controlled by varying the control current (1(,) of the amplifier.
The output current is then converted to a voltage by a load re-
sistor or current-to-voltage converter (Fig. 6-4). The internal
156
R
>---4---0 (INVERTED)
I" c:I
Vau! BUFFER
R
where
Ie is the control current in amperes,
Vdif is the voltage, in volts, between pins 2 and 3.
157
LINEAR
R2 220 (l
R6 R7 GAIN
SIGNAL RI TRIM
IN
+/-5 V lOOK -0+15 V
OUTPUT 300K
IK
R3 +------VVv-O - 15 V
220 (l RI5 INITIAL
RI4 36K GAIN
THERMAL + 15 V
CONTACT t---'VV'r-''''S
lOOK
R5 RIO
-15 V
lOOK +15V 3.3K QI
RI9 lOOK
OFFSET TRIM
Q2 2N3906
01 8.2 V CV IN
EXP RI3 R20 36K
-15 V
oLIN
Rll 10K SIA
RI2 lSI = OPOTI
25K
-IS V
158
ZERO TRIM
R2
- IS VC).-.,e,....Jl.J\/Vv---C> + IS V
lOOK
+15 V
R3 680K
INITIAL
R4 R5 GAIN
lOOK
CV RI 220K
IN -15 V
105 VI lOOK
SIGNAL R6
IN
+/-5 V lOOK R7 R9
./--+--"'VV\,.-o OUTPUT
IK
Dl D2 IN914
}59
ENVELOPE IN
OFFSET RAISED
NORMAL
OFF OFF
_ _ NORMAL ENVELOPE _ _
TIME
'TRUNCATED" ENVELOPE _ __
TIME
Fig. 6-7. The effect of offsetting the zero trim of Fig. 6-6.
160
Vee - VEE
RD
where
Vee = positive supply voltage,
VEE = negative supply voltage,
RD = diode bias current-limiting resistor.
ID. AI LINEARIZATION I
AI EMITTER 2
A2 EMITTER 1
1 0 , A2 LINEARIZATION e
,2CS-!ISOO
161
+15 V
>---.ploul
+15 V
(1/2 CA3280)
-15 V
where In is in milliamperes.
To calculate the gain of the CA3280, we must first know the
typical transconductance (gm) with a given control current (I c).
The transconductance gm of a CA3280 is
where
gm is in millisiemens,
I c is in milliamperes.
162
If the input diodes are biased oJf, the CA3280 will act like a
CA3080 ota, except for the (lower) 16 millisiemens value of gm
as compared to 19.2 for the CA3080. The output gain A in
kilohms will then be
where
gm is the transconductance in millisiemens,
R[, is the load resistance in kilohms,
rd is the diode resistance in ohms,
R inl , R in2 are in ohms.
68K
SIGNAL 16 'hCA3280
+15 V IN 14 13
10 V PP OUTPUT 21 V PP
DC
OFFSET lOOK 330K
TRIM e
15K'
-15 V 10K
20K
Vc
'NOTE DISTORTION IS REOUCED IF AN
OP-AMP IN CONVERTER IS USEO HERE
163
Another feature of the CA3280 is that the differential am-
plifier emitter connections are brought out on pins 2 and 7.
These were used in a triangle-wave-to-sine-wave converter in
Chapter 4. These pins could possibly be used as control inputs
in conjunction with the Ic pin. All in all, this IC has many
possibilities which are just beginning to be explored.
This is because the diode bias current is split between the two
diodes. If the signal current exceeds the diode current, the
diode will be biased off and distortion will occur.
The dynamic resistance r d in ohms of each diode is
52 104
or for both diodes
gm = 19.2 Ie
164
ONE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
y+
04 0&
BUFFER
OUTPUT B.9
DIODE
2.15
OJ OUTPUT
5.12
_ ... +lNPUT
AMP BIAS
INPUT
1.16
05
y-
165
with Ie in milliamperes. Note that this is the same equation as
for the CA3080. If the input diodes are biased off (diode pins
open), the ota's perform as CA3080-type ota's. The output cur-
rent of the LM13600 is found by the equation
where
I s is the signal current,
I e is the control current,
Iv is the diode bias current.
166
30 K
GAIN
\r---O CONTROL
+Vs
.........-----'" OUTPUT
-vs
10
.-
10-15
lOUT = 15-14 - lOUT = IS ell:BC)
"2
-Vs
167
DC OFFSET
+ 15 V RII
DI D2 -15 V +15 V
+15 V lOOK e
RI2 68K
RI3
Rl
SIGNAL RI4
INPUT 10K R3 10K R7 13 RI5
1 10K OUTPUT I
1538 IK
+15 V
DC OFFSET
RI7 RI6
lOOK
e
R4 10K -15 V
R5 10 R20
SIGNAL OUTPUT 2
INPUT 10K IK
2
-15V
R22 2.4K
R24 R23
Vc
1010 VI lOOK
The SSM2020
The SSM2020 is a dual vca designed to be used with external
op amps. Simultaneous linear and exponential control of gain is
possible using the temperature compensated matched transis-
tors contained in the IC (Fig. 6-16). Each vca has independent
control inputs, differential signal inputs, and current outputs.
The control range is 100 dB with an 86-dB signal-to-noise ratio
and less than 0.1 percent thd.
One half of a dual vca circuit, using the SSM2020 and offering
linear or exponential voltage control, is shown in Fig. 6-17. Op
amp IC2 and the internal transistors of the SSM2020 work to-
gether to form an exponential/linear current sink for the vca.
The reference current should be set to one-half of the desired
logarithmic control current range. Design formulas are given in
Fig. 6-18.
For simple linear control applications the circuit of Fig. 6-19
can be used. Resistor Rc limits the maximum control current.
168
+15V
RI5 10K
14 11
2 20 pF RI9
RIO
1538 RI7 10K
R5 33K 13
10K RI8
10K R6 10K R9 33K 10 1---"""-"-.-1
-15 V0----+---+_--1 10K
R20
R7 10K CI 10K
R8
50K '" 150K 20 pF
CONTROL -IS V 10K R21 IK
VOLTAGE RI4
RE) 100 !!
We RII RI2 RI3 OUT
(010 VI lOOK 2.4K
The SSM2022
Another dual vca introduced by Solid State Microtechnology
for Music is the SSM2022 (Fig. 6-21). This IC has internal con-
trol op amps (they were external to the SSM2020 in Figs. 6-17,
6-18, and 6-20). The op-amp summing nodes are brought out
as IC pins. The specifications are not as good as those of the
SSM2020 (snr of 76 dB and 0.2 percent thd). The SSM2022 was
designed for ease of use and polyphonic systems.
169
50 pF
170
lOUT +V
1 - SIG IN 2 OUT
1 + SIG IN 2 - SIG IN
-v 2 CON COll
TOP
(A) Pin diagram.
OUT
CURRENT
+ SIGNAL 0---1 TWO-QUADRANT MIRROR
INPUT
TRANSCONDUCTANCE
- SIGNAL 0---1 MUl TIPLIER
INPUT
1 . . . - - - - -_ _----"1--__-0 - V
+ CONTROL
BASE
171
SIGNAL
INPUT lOOK
SIGNAL
+15 V OUT
lK
eN
REJ 1M 170K
e 47K
-15 V
+15 V
11K
RF 100 pF
10M IN914
17K
7191
10K
61101
51111
1N914
41111
15K
Vc
IN 415 V
105 VI 68K 680K
3K
MANUAL 39K
GAIN lOOK
IDPDT 18K
SWITCHI
The SSM2010
The SSM2010 is a single-vca Ie with a signal-to-noise ratio of
90 dB and 0.05 percent thd. It offers linear and/or exponential
gain control. It is packaged in an 8-pin minidip package (Fig.
6-23). The above and its low external parts count make
it a very powerful yet easy to use component. A suggested vca
circuit using the SSM2010 appears in Fig. 6-24.
172
v = I V 15K/14 Volts
oul C In
Rc
SIGNAL IN c>--_":':-:..:.j
SIGNAL OUT
1115)
ve F DeSIgn Equlll,ons
R=15K.
Ra - 28K @ Ie = 500
AO - (20 - 1) H
A - 2 -l1Q
P::: CH : _
50'lA"':' Ie "':'500 uA
173
(A) Pinout-top view.
The CEM3360
The CEM3.360 (Curtis Electromusic Specialties) is a dual vca
offering a signal-to-noise ratio of 100 dB, linear or exponential
control, and very low control voltage feedthrough (10 m V
maximum for lO-V Pop output). The IC is packaged in a 14-pin
dual in-line package (Fig. 6-2S).
The CEM3360 is designed using a low-voltage IC design
technology. The supplies can range up to 12 V. The IC may
operate at IS V but it is not designed or guaranteed to do so.
lt is suggested that zener diodes be used to drop the IS-V
supply levels to 12 V.
Note that if the 47-kn load resistor is placed in an op-amp IN
converter, an inverting op amp at the signal input will be re-
quired to keep the same phase relationship, input to output.
Also, an attenuator will be necessary to reduce the normal 0 to
+ lO-V control voltages to 0 to +2 V. At a control voltage of 0 V,
the input signal will be fully attenuated (O-V input).
The CEM3330
The Curtis Electromusie Specialties CEM3330 is a dual vea
offering linear and/or exponential voltage control of gain. A pin
174
lOOK lOOK
tiN 21N
lOUT 20UT
tUN f \ r - - - o 2 UN
1 EXPO (}---J\v'V'\r---_._----l
33K
DISTORTIOND
TRIM 1 8 +V
GND 3 6
-v 4 5 LINEAR
CONTROL
CURRENT
MIRRORS
V.
-
EXPONENTIAL
I] CONTROL
-v GAIN CEll
"
:-e
-"
LINEAR lOUT
GND CURRENT
MIRROR
'41 -v
(B) Block diagram.
175
input current (into pins 7 or 12). The exponential inputs have a
sensitivity of 18 m VI -6 dB. Thus the more positive the control
voltage, the more the output is attenuated. An external inverting
33l!
For be,! results, select Rm to
gl\le a 501" A "lPUt signal
CUrren! lor the maximum
input Signal level
MAXIMUM INPUT
SIGNAL lEVEL
50K 2 5V !VSE HllAIIS
lOOK ! 5.0V A,' ''" -2OcIblV
TYPE 01' FOil
"' ... n_sr.... ,Llfyj
200K .. 10.0V ". < '.9", I... -&.oWV
CNTL SIGNAL
47K INPUT INPUT
SIGNAL oTO + 1.5 V
OUTPUT 47K
+3T0 Vee 10 VE Vo Ve VREF
+12 V 14 13 12 11 10 9 8
V+
2 3 4 5 6 VEE
10 VE Vo Vc II -3V TO
SIGNAL -12 V
OUTPUT 47K
47K CNTL
INPUT SIGNAL
o TO +2 V INPUT
176
op amp is required for the output to increase with an increase in
the control voltage. The signal input pin and linear control
input pin for each vca are an internal op-amp summing node.
This makes external control and signal interfacing easier.
The CEM3330 vca has a control range of 120 dB and a signal-
to-noise ratio of more than 100 dB. Distortion is typically less
than 0.1 percent. The idle current of the two vca circuits can be
set by an external resistor placed from pin 8 to pin 5. Increasing
the idle current will decrease distortion, increase the slew rate,
and increase the maximum output current at a cost of increased
noise and control voltage feedthrough to the output. The vca's
should be operated with low idle currents when control of low-
frequency signals is desired (less control voltage feedthrough).
The effect of idle current on vca parameters can be seen in
graphs appearing in the CEM3330/CEM3335 data sheet in Ap-
pendix B.
A dual vca circuit using the CEM3330 appears in Fig. 6-27. 6
Op amp IC2B inverts the exponential control input voltage to
cause an increase in signal output with an increase in control
10K 47K
OU T
+ 12 1 ()
2.2K
()
Vee 10 VE Vo Vc II VR
) CEM3360
G 10 VE Vo Vc II VEE
+ v u
L12V
OU T
2.2K
47K
10K 47K
CNTL INPUT SIGNAL
oTO +2 V INPUT
177
fOP
VIEW
voltage. The switching input jacks shown for this input and the
linear control input cause a unity-gain signal output to be gen-
erated when no plugs are inserted. This is useful for oscillator
tuning or setting up patches. Resistors R25 and R48 (just below
the CEM3330) can be switched to both control inputs with a
dpst switch (for unity gain), eliminating the need for switching
jacks.
The AM input shown for each vca can be used to modulate the
linear input control voltage (as tremolo). A IO-V dc signal con-
nected here will cancel out a lO-V linear input control voltage at
pin 7 (pin 12) because op amp IC2A is an inverter. The STOP
input is meant to cut off the vca output on activation of a foot
switch connected to -15 V. A 9- V battery (placed in an external
foot switch housing) can be used instead of -15 V if R5 (R29) is
changed to 91 kn.
The idle current of the vca's is set by resistor R9 (between
pins 5 and 8 of the CEM3330). The output current for the
CEM3330 is determined by
where
lin = signal input current,
VT = KT/q ;:; 26 mV at 25C, room temperature,
V G = voltage applied to direct current input pin 2 or pin 15
(from log converter).
178
C9 0102 IN9141lN4148 CI-G5C7C8CIOCI2 CI3 POLYESTER
ICI CEM3330 C6.C6C11C14 POLYSTYRENE
IC2.IC4 LMI458
IC3 TL072CP
18
+15 V
IK CI4
+15 v R22 ",,---,-," lOOK
0-----'V'A 17
150K
o R45
0." C7
cE' AC SIGNAL lo-------jf-f- - - - - , 16 R47
CD' CEM3330 OUTPUT 2
(ng, DC SIGNAL I c M--j ICI IK
"'N RI3 R43 R40 R39
m"-l IS +15 V
-- I 5 Vo---:",,,.,--.,.------M--, 150K
:::!'
$: EXPONENTIAL
CONTROL 14
INPUT I
a> o 10 V
S'C 750
CD IA
'" :S' AM INPUT I RI6 IK R9 6.8K
:::.11:1
Q ... 010 v R8 SIGNAL 2
CJ::r 12
lOOK
CD
<5'
(;j'0 Gil GIO
om R32
! ISO pF OOII'F lOOK
,Qw
,....w
(1? STOP I 0
R5
IIOK
d R4
IK
C5 C6f
pF
't
10 f----o +15 V
.,.
150K
R26
oSTOP2
LINEAR
LINEAR lOOK lOOK CONTROL
RnlM 1M
CONTROL R2151K INPUT 2
INPUT I 51K OIOV
+ IS v R25 R48 +15 V '--15 V 6
OIOV v+15V e PR4
+15 v 15 V
lOOK 24K 24K lOOK +15 V
ISEE TEXT, ISEE TEXT)
+ 15 Vo lCI IC3
oVo 047 1 01 rF
C2 C4:
...... --15Ve
r
-1
<:.0
The output of the log converter is determined by
where
lref = current sourced by resistor connected to pin 2 or pin 15,
R22 and R43 in Fig. 6-27 (typically 50-150 /LA),
I CL = linear input control current (through input resistors
connected to pin 7 (and pin 12),
VCE = exponential control voltage at pin 6 and pin 14.
180
Control voltage feedthrough is nulled out by trimmer PR2
(PR5). This is adjusted to 0 V at the output with the signal input
grounded. Output distortion is minimized by the adjustment of
trimmer PR3 (PR6). Connect a fresh 9-V battery (or stable dc
supply) between the DC SIGNAL input and ground. Measure the
output voltage of the vca. Reverse the dc voltage source con-
nections and measure the vca output voltage again. Trimmer
PR3 (PR6) should be adjusted so that the voltages above and
below ground are equal.
Trimmer PR1 (PR4) adjusts for precision cancellation of the
linear control voltage by the am control voltage. Connect a 0- to
lO-V signal to the dc input of the vca. Then apply a 1O.0-V dc
voltage to the am input. Turn the am level control clockwise (no
attenuation) and adjust PR1 (PR4) for a cancellation of the vca
signal output.
The CEM3335
The CEM3335 is a dual vca, similar to the CEM3330, with
the exception that the linear control circuitry is omitted. This
allows a smaller IC package, as shown in Fig. 6-2S.
FOUR-QUADRANT MULTIPLIERS
TOP
VIEW
.:.A
CELL
RF 51 K
SIGNAL
EXP. SIGNAL -15V
OUTPUT
CNTL. INPUT
INPUT
182
TPI TRIM
+15V -15V
lOOK 8
R9 1M
D2
+15 V +15 V
s
7 6 RI3 TP3 DC TRIM
22M lOOK
-15 V
Xin
R2 220K
1% CI
R8
OUT
R3 IK
n
5
R4 D4
220K
1%
DIN IN914
RII 1M
TP2 8
+15 V TRIM
lOOK -IS V
183
A buffer circuit suggested for the Vx and Vy inputs is shown
in Fig. 6-30D. The buffer presents a low-impedance source to
the input resistors in the multiplier. Signals from high-
impedance sources would invalidate previous gain and offset
adjustments and should be avoided. The Vy inputs of the previ-
ous circuits cannot be directly ac coupled. The buffer in Fig.
6-30D provides ac or dc coupled inputs for Vx and/or Vy (Note:
Four-quadrant multipliers can be designed, using this same
technique, with any of the current-output vca Ies shown previ-
ously in this chapter.)
Vy
20K
eY TRIM
-15 V
50K
OUT
lK XV
Vx 5
lOOK
39K
Vy
47K
X TRIMe
+ 15 V
lOOK
DIODE BAIS
TRIM
+15 V
Vx lOOK e lOOK
20K
>-"""'\N'v--{) 0 UT
lK '[1
47K 5
(8) Using a CA3280.
184
Multiplier Ie Designs
The RC4200 (Raytheon) is an 8-pin multiplier IC that has an
excellent nonlinearity specification of 0.3 percent maximum.
A four-quadrant multiplier can be designed fairly easily with
this chip (Fig. 6-32). The offset adjustments (Vx and Vy null)
are carried out using the same procedure as the previous cir-
cuits. However, be sure the input level controls are set for
maximum input when performing the adjustment procedures.
The LF351 op amp provides a low-impedance output. One-
percent resistors are suggested for use in this circuit for precise
gain matching.
Another multiplier IC that can function as a four-quadrant
multiplier is the XR-2228. This IC contains an internal op amp
that can serve as an output amplifier for the multiplier section.
A four-quadrant multiplier using the XR-2228 is shown in Fig.
6-33. To trim this circuit, first ground both inputs and adjust the
output offset for a O-V output. Then connect a +/- 5-V sine
wave to the Vx input and ground the Vy input. Adjust the Y
offset trimmer for minimum output signal. Switch the input
connections and adjust the X offset trimmer for minimum output
>-+--A/V\.---Q OUT
lK !y
5
5K
10K
TO
Vx OR Vy
1. 0 llF
185
+5 V
OV Vx INPUT
-5V
+5 V
\AAAAAAAAAAAI
vmvvvvvvvv
OV Vy INPUT
-5V
OUTPUT
REFERENCES
1. Hutchins, Bernie, and Dave Rossum, "Voltage-Controlled Amplifier De-
sign," Musical Engineering Handbook, p. 5C (9).
2. Mikulic, Terry, "Reader's Equipment: Four Analog Circuits From Terry
Mikulic," Electronotes, No. 34, January 1974, p. 16.
186
"T1
Vx DC
f(I +/-5V H
Co.) 1.0 JlF
!'J
0'
c
.
l:J
c
DI +15 V
c..
iil Vx NULL
::l lOOK
..
3
c -15 V
..
':
-15V .,!,-
I +15 V
.
c
VI
:i'
cc
..
:r
CD
::D
DI
-:s.:r +/-5 V
CD _rr
o *1 % RESISTORS
::l 5
SUGGESTED
::D
f-'
C1J
-1
24K 470K -
GAIN
50K s
24K V
I 16 15
XR2228
v, 2
I
3
4
5 X
I
-
+
II
12
IK
120 pF
OUT
XY
T
+15 V
OFFSET
8
16 7 8 9 13 lOr -15 V
25K
-15V +15 V 300K
(3
188
MISCELLANEOUS
CIRCUITS
2f
where
N is the number of stages,
f is the clock frequency.
The output of a bbd device is made up of a series of de volt-
age steps. If the clock frequency is low, the input signal must
189
INPUT 1--__- - 0 OUTPUT 1
1-----+--0 OUTPUT 2
(A) Circuit.
PHASE I HIGH
EJ PHASE 2 HIGH
PHASE 1 HIGH
190
frequency. The output of the delay line will also have to be
filtered to remove clock noise from the output and to "smooth"
the de voltage steps. The noise is due to high harmonics created
by the steps in the output waveform.
Delay lines are inherently quite noisy and accept relatively
small input signal levels. When the input to the delay line is
overloaded, severe distortion occurs. Given this information,
there are two ways to use bucket brigade delay lines. One is to
use a low-level signal with the device, making sure that the
signal peaks do not overload the input of the device. This re-
sults in a low signal-to-noise ratio. Another method is to run a
constant (or nearly so) maximum level (before distortion)
through the device. For the majority of uses in a synthesizer, we
will be using constant level signals ( 5 V) with the delay
module. All we must do is attenuate the signal going into the
bbd, and amplify it when it comes out.
If you wish to run a varying amplitude signal (such as the
signal from a guitar) into a delay line and wish to conquer the
noise problem, the solution is to use a compander. One section
of a compander, called the compressor, attenuates the input
signal as it rises in amplitude. The higher the input signal tries
to go, the more the compressor tries to cut it down. This signal
is then fed into the bucket brigade device. The output of the
bucket brigade device is fed into the second half of the com-
pander, called the expander. This portion does the exact oppo-
site job of thc compressor. It will have higher gain for lower
input level signals. Thus it boosts the output of the bucket
brigade back up to the original signal level. Several compander
circuits are available, such as the Signetics NE570/571 (Fig.
7 -2). These work well for most applications. Companders can
also be made discretely with vca's and envelope followers (Fig.
7-3).
191
N PACKAGE
, of 2 R3
R3
20K
R2 20K
6G IN
output
VREF
R4 1.8V
R1 10K 30K
REel IN
':'
192
I-----.--.() COMPRESSOR OUTPUT
R
INPUT
R
INPUT o---.-------I+'_
EXPANDER OUTPUT
I
I
I
rCOM-PRESSOR: :
___ ...J ENVELOPE __ ...J
-------- J
: FOLLOWER
193
vice. Manufacturers of bbd and/or CCD devices include Reti-
con, Panasonic, Signetics (Philips), and Fairchild. Devices are
available with less than 256 stages up to 4096 stages or more.
Devices with at least 512 stages can be used for vibrato, chorus,
and flanging effects. Echo usually requires devices with more
stages.
A simple circuit for a voltage controlled clock is given in Fig.
7 -5A. Here, a voltage controlled oscillator is formed with a
4007 CMOS building block. It consists of two inverters and one
transistor functioning as a voltage controlled resistor. The out-
put of the oscillator is fed into a 4013 CMOS flip-flop which
VIBRATO FREQUENCY SHIFTER
("--...... = LOWER
FLANGING
FREQ HI
(e) Flanging.
INPUT OUTPUT
BBD
REGENERATION
194
divides the input frequency by 2 and generates two out-of-
phase clocks. The output frequency can range from 20 kHz to 60
kHz with a 0 to + 15 V control voltage. A low-frequency oscil-
lator that can be interfaced with the vc clock for automatic
sweep is shown in Fig. 7 -5B.
Sample bbd circuits are shown in Fig. 7-6. As can be seen,
the devices are easy to work with. All require trimming the dc
CHORUS
INPUT
(D) Chorus.
ECHO
LONG DELAY
...--..JV\/V'v-----0 + 15 V
L -_ _ _ _ _ --o-< REPEAT
(E) Echo.
195
+15 V
HIGH-FREQ
CLOCK OUT 10 II
CD4007
12 6
50 pF 10K
1M
220K
+15 V
330K
10 \I CONTROL VOLT AGE
INPUT
d= O.IJ.tF 14 11
(0 IS VI
,1>1
OUT OUT
+ 15 V
100K(21
LMI458 (DUAL)
OR SIMILAR
100K(21 +15 V
RATE
1M
220K AUDIO
>... TO VC INPUT
WIDTH AUDIO OF CLOCK
+ IS V
10K
DELAY
196
+15 V
I----+--I'v---<J + IS V
PANASONIC 10 n
4096 1-"-..........",---'VII'v-_._-<J + 15 V
STAGE
MN3005
INPUT o-----!lF-+
1.3 V RMS 10.0 JlF 10K NOISE REI lOOK
lOOK
2.5% THD
.-"''''WVV---O + IS V OUTPUT
10K
BIAS TRIM
+15 V
10 \l
BIAS TRIM
+15 V
10K 0
6.7.9.11
OK
RETICON
SAD-I024
__-,I_.4_.1_3.1_6__
IN PUT o-----jjf-+--'WI,-J
10.0 JlF 10K IN91412)
+----+-----0 OUTPUT
<I' I <1,2
10K
lOOK
OK
RETICON
SAD 512 OUTPUT
10K
OK
CLOCK INPUT
197
level of the input signal (bias) for minimum distortion. This is
accomplished by observing the device output on an oscillo-
scope and, with a maximum level input signal input, adjusting
the trimmer for minimum distortion on both the positive and
negative signal peaks. Some circuits also contain a clock noise
trimmer that cancels clock transitions imposed on the output
signal.
When laying out a printed circuit board for a delay circuit, be
sure to keep traces short. The clock inputs of most bbd rcs have
relatively high input capacitances. This will reduce the
amplitude of high-frequency clock signals if the traces are long
and/or the output impedance of the clock is high. Keep the
clock circuitry separated from the audio portions of the circuit to
prevent superimposing clock noise on audio lines. Some manu-
facturers recommend double-sided pc boards for bbd circuits.
One side is used as a ground plane (all ground connections are
common to this side). This is said to result in a higher signal-
to-noise ratio.
MIXER CIRCUITS
TIMBRE MODULATORS
198
lOOK!
. OFFSET
COUPLING
TL082
AC
lOOK lOOK
PHASE
:!! + IOOK(4)
1.0 J-lF
....
lOOK
)0
i lOOK IK
lOOK OUTPUTS
0-
c
lOOK 10K IK
b
III 1.0 J-lF lOOK "". LEVEL
:::I lOOK
:::I
!l
3 AC
)C' 4 SPOT SWITCHES
CD UP = IN PHASE AT OUTPUT
::"
DOWN = OUT OF PHASE AT OUTPUT
INPUT 4
.....
1.0 J-lF lOOK
'"'"
INPUT
ADD
Sl 47K
-15V DCTRIM
, +15 V
<1>
lOOK
lOOK
220K lN9l4
[NV 19M
IN
lN91412)
33K
lOOK
200
TRIANGLE INPUT
SMALL
INPUT ADD
I
EFFECTS OF
SWITCH CLOSED
INCREASING
ENVELOPE
A A. I\. A
LARGE
INPUT ADD
SWITCH OPEN EQUAL SHAPE SETTINGS
o
UNEQUAL SHAPE
u SETTINGS
The comparator outputs are then summed together for the final
bank output. The original signal can also be summed in with
the closing of the MIX switch, S 1. An identical bank of Ifo/ com-
parators will accept the same input (if no input is connected to
input 2) due to the switching jack used. The BOTH output will
be either an inverted version of the bank 1 output (with 50 per-
cent gain) or a sum of the two bank outputs, depending on the
setting of the OUTPUT MIX switch, S2. Fig. 7-13 shows typical
(instantaneous) single-bank signal outputs for a triangle wave
input. This circuit is used to increase the harmonic content of
an input signal. The sound of the output is "fatter" than the
input. This module can be placed in front of a vcf to produce
more natural sounding timbres.
201
30K
lOOK 02
-15 V
30K
-15 V
REFERENCES
1. Hutchins, Bernie, "Timbre Modulation-Option 1," Electronotes, No.
72, December 1976, pp. 24-16.
2. Hutchins, Bernie, "An Odd-Harmonic to Even-Harmonic Timbre Mod-
ulator," Electronotes, No. 84, December 1977, pp. 9-13.
202
SINE RECT FULL WAVE RECT
SINE SQUARE
(B) Output of le11 as control input voltage is varied (SHAPE set at SINE).
BANK I
MIX
INPUT 1
OUTPUT 1
BOTH
;;UK,
OUTPUT
MIX
INPUT 2 _OUTPUT 2
Ie
20.3
INPUT
204
THE MODULAR SYSTEM
205
CONTROLLER -- T ENVELOPE
GENERATOR
r--
G
1 V/OeT GATE TRIGGER
I
CV
! !
ev ev
!
CV
veo VCF veA
OUT IN OUT IN OUT
l I t TO AUDIO
AMPLIFIER
Fig. 8-1. A basic monophonic synthesizer.
The first module that you will want to build will probably be
the vco. It is always satisfying to build something that you can
listen to right away. You can vary the frequency with a front-
panel FREQUENCY control and listen to the differences in sound
between the various output signals. You will, however, have to
attenuate the +/- 5-V signal generated by the vco with a
potentiometer to prevent overloading (clipping) the input of
your audio amplifier (see Fig. 8-2).
The next module that you will want to build is the vcf. Most
general-purpose vcf's are 2- or 4-pole, low-pass filters. With a
vcf you can change the timbre of the YCO sound with the vcf
cutoff frequency control (Fig. 8-3). You can also listen to the
FREQ
o
PULSE WIDTH
o
veo
WAVEFORM Fig. 82. Using a potentiometer to
OUT reduce the signal level of a vco.
+/-5 VPP
POTENTIOMETER
IOKAUDIO
206
FREQ FREQ
C) C)
PULSE WIDTH RESONANCE
C) 0
VCO VCF
WAVEFORM SIGNAL
OUT IN OUT
I f AUDIO
10K TO AUDIO
AMPLIFIER
-
Fig. 8-3. Using a vd to filter a veo waveform.
207
ENVElOPE GENERATOR
I - - - GATE
I---- TRIGGER
CONTROllER
A D S R
1 V/OCT UUUC)
CV OUT
U C)
ENVELOPE IN
C)
VCO VCF VCA
CV CV CV
IN r--- 1 V/OCT ENV IN
WAVEFORM SIGNAL SIGNAL
OUT IN OUT IN OUT
I I t I
TO AUDIO
AMPLIFIER
Fig. 8-4. Adding an envelope generator, controller, and vca to the
system.
208
CONTROLLER
1 VIOCT
CV CV SIGNALS
OUT OUT IN 1 IN 2 OUT
t I
r---.r- 1
(A) Summing two vco signals with a two-input vd.
1 VIOCT
veo 1 HARD;?
@SYNC
SOFT
CV ........ f.-.. CV veo 2
PULSE OR SYNC
SAWTOOTH IN OUT
I i ,'----_
(8) A patch for syncing two vco's.
FREQ FREQ
C) 1 PW C) PWM
veo 1 0 C)
LINEAR
,
FMC)
SINE OR veo 2
TRIANGLE
OUT PW FM OUT
t t r
(e) Using a vco to modulate frequency (FM) and pulse width (pw).
209
hear by various module interconnections and control settings
(see Polyphony magazine, listed in Appendix A). Rather than
our delving into this subject full tilt (which would triple the size
of this book), the various modules will be described as to their
use and possible placement in a "programmed" synthesizer
patch.
Controllers
Controllers can be used in a number of applications, as illus-
trated in Fig. 8-6. The joystick pressure-sensitive controller
and ribbon controller can be used to generate a control voltage
for a module. For example, the voltage generated by a ribbon
controller can be summed with a keyboard 1 V/OCT at a vco, as
in Fig. 8-6A. The voltage generated by such a controller can
also be used to control a vca that generates a modulation
waveform (Fig. 8-6B).
Sequencers
Common uses of sequencers are shown in Fig. 8-7. Se-
quencers generate a control voltage that can be used to control
another module's operation. They are commonly used to control
the frequency of one or more vco's, to generate tone sequences.
A sequencer can also be used to control a vca for rhythmic or
percussive effects.
Noise Sources
Noise sources are used with vcf's to generate whistle tones,
cymbal sounds, or the common rain, surf, and wind sounds. The
noise source can be used as a random modulation source for
vcf's, vco's and vca's. Also, the noise source is often used with a
sample and hold and lfo module to generate random control
voltages. Two noise source applications are illustrated in Fig.
8-8.
LFOs
Lfo's act as valuable modulation sources for other modules
(Fig. 8-9A). Often a triangle lfo is used to modulate the pulse
width of a vco square wave. An Ifo can also be used to sweep
vcf's and to pan a signal between two vca's, as in Fig. 8-9B.
The square wave output of an Ifo can be used as a gate signal for
sample and holds, vca's, or envelope generators.
210
External Signal Processors
A synthesizer can be used to modify the timbre and dynamics
of an externally audio signal, as in Fig. 8-10. A gate
and trigger extractor derives timing signals from the audio
signal's amplitude envelope. These timing signals can be used
COARSE FINE
FREQ FREQ
C) C)
VARIABLE
INPUT PWM
C) C)
FM IPW
C) C)
VCO
VAR RIBBON
CVIN CVIN CONTROLLER
f
I I
I
I V/OCT
FROM KEYBOA RD
FREQ INITIAL
C) C)
GAIN
VCO VCA
SIGNALS
CV ----- CV
OUT
CONTROllER
RIBBON.
JOYSTICK.
ETC.
OUT IN OUT
r NY f r MI'I\IV TO VCFHC.
211
00000000
3 4 5 6 7 8
1 2
SEQUENCER
SEQUENCER
Filter Modules
Generally, filters are wired directly to the output of the sound
source(s), such as a vco, external audio, and the like, in a system
patch (Fig. 8-12). Usually, as large a signal as possible is used
with the filter, to obtain a respectable signal-to-noise ratio.
212
FREQ
VCF C)
NOISE RESONANCE
PINK OR WHITE
S&H FREQ
NOISE CLOCK nru veo C)
PINK OR WHITE IN OUT CV OUT
Nv-A
(B) A random tone patch.
010 V
N >O---+-lCV CV
LFO 10 V 0 V
f1.
(B) Using a 0-to-l0-V triangle output of Ifo to pan a signal between two
output amplifiers.
213
GATE AND TRIGGER
IN EXTRACTOR
ENVELOPE
GENERATOR OUT
VCF VCA
SIGNAL SIGNAL
IN
MODIFIED AUDIO
SIGNAL OUT
ENVELOPE OUT
IN FOLLOWER
FREQ
QUADRANT
MULTIPLIER
VCO
OUTPUT
WAVEFORM XII1 YII' OUT
r t r
EXTERNAL AUDIO
SIGNAL
214
VCO VCF TO VCA, ETC,
EXTERNAL
AUDIO SIGNAL .
FILTER 1----. OUT
FREQ
0
Q'
G
VCF
00000000 oV
SEQUENCER OUT IN SIGNAL OUT
/
(B) "Ringing" a highly resonant filter with pulse signals.
1 V/OCT
FREQ FREQ
0 0
veo 1 veo 2 4QUADRANT
MULTIPLIER
CV CV
rv rv X," y,"
OUT OUT OUT
I r i l r TO VCF
AND VCA
Fig. 8-13. Creating bell sounds with two yeo's and a four-quadrant
multiplier.
215
Kl
......
0')
ONE VOICE
---0
CV
'- OUT VOICE I
FREQ NOISE IN OUT OUT
IPW A SIGNAL IN
KEYBOARD CV B SIGNAL IN
FM CUT OFF VCF
RESONANCE ADSR
ATTACK
KEYBOARD CV ENVELOPE
DECAY GENERATOR
ENVELOPE
2
SUSTAIN
OUT
RELEASE
FM
I
SYNC GATE
FREQ N'-
ENV AMT 0
:J TRIGGER
IPW VCO M
8
ATTACK ADSR
KEYBOARD CV ru, I I
ENVELOPE
L. ____ ....l DELAY GENERATOR
SUSTAIN 1
."
tiS' OUT
RELEASE
qo
... GATE
TRIGGER
'tI
n'
!!.
VOICE
'tI OUTPUTS
o veo A
-< $- TO ALL GLIDE
'tI
::r FREQ veos KEYBOARD
o
::J FINAL
n' TUNE
OUTPUT
II> 2131415161718
ALL
1::r IPW f .TOA veos
N
I'D
veo B
rD
=" ev G
TO ALL
FREQ fS veos TO ALL VCF
At- At- NOISE f- VOICES TO ALL
CUTOFF Ir VOICES
TO ALL TO ENV Dt- TO ENV
IPW f s veos GEN I GEN 2
(ALL VOleESI (ALL VOICES I RESONANCE
st- st-
ENVELOPE
AMT
Rt- Rt
r---,
IU , 0-:- = ANALOG
r-----, SWITCH
LFO M
' ,
V 0-:....-.
L ___
FM 1TO ALL = FRONT PANEL
N'-- , , CONTROL
L ___ ...l
,----,
VCOs f-
o-f---- PWM
l.. ___ ...J
FREQ
1:>0
f-'
-:t
Analog Multipliers
Voltage controlled amplifiers are used anywhere amplitude
control is desired. They can be used in panning circuits and
voltage controlled modulation circuits, and they have a mul-
titude of other uses. In addition to modifying an external
signal's tone characteristics, a four-quadrant multiplier can be
used with two vco's to create interesting, sometimes bell-like,
timbres (Fig. 8-13).
218
SYNTHESIZER
CONSTRUCTION AIDS
219
CFR Technotes
CFR Technotes is a newsletter dealing with electronic music
circuitry. It has not been published for some time but may be
back in print soon.
CFR Technotes
clo CFR Associates, Inc.
Newton, NH 03858
Modmags, Ltd.
145 Charing Cross Road
London WC2H OEE, U.K.
Polyphony
Polyphony is a magazine that deals with system patch theory,
new developments, and some circuit theory. The magazine is
affiliated with PAIA Electronics.
Polyphony
P.O. Box 2030.5
Oklahoma City, OK 73156
Engineering Magazines
Technical publications aimed at electrical engineers can con-
tain useful circuit information and theory, which can be applied
220
to electronic sheet music. Many contain a reader submitted
"circuit designs" section that is often valuable.
EDN
270 St. Paul St.
Denver, CO 80206
Electronic Design
50 Essex St.
Rochelle Park, NJ 07662
Electronics
1221 Ave. of the Americas
New York, NY 10020
Contemporary Keyboard Magazine
Contemporary Keyboard Magazine is a magazine devoted to
keyboard instruments and players in general. It usually contains
one or more columns dealing with system patch theory.
Contemporary Keyboard
GPI Publications
Box 615
Saratoga, CA 95070
IC Cookbooks
Several books are available that detail uses of CMOS, TTL,
and linear ICs. Some useful books of this type include:
1. Berlin, H.M., Design of Op-Amp Circuits, With Experi-
ments. Indianapolis: Howard W. Sams & Co., Inc., 1978.
2. Lancaster, D., The TTL Cookbook. Indianapolis: Howard W.
Sams & Co., Inc., 1974.
3. Berlin, H.M., Guide to CMOS Basics, Circuits, & Experi-
ments. Indianapolis: Howard W. Sams & Co., Inc., 1979.
4. Berlin, H.M., Design of Active Filters, With Experiments.
Indianapolis: Howard W. Sams & Co., Inc., 1978.
5. Jung, W., The Op-Amp Cookbook. 2nd ed. Indianapolis:
Howard W. Sams & Co., Inc., 1980.
IC Manufacturer's Data Books/Application Notes
Several IC manufacturers offer data books that contain refer-
ence data on their ICs as well as application notes. Some
suggested application books are the following;
221
National Semiconductor Corp., 2900 Semiconductor Drive,
Santa Clara, CA 95051:
Linear Applications Handbook
Voltage Regulator Handbook
Audio/Radio Handbook
Analog Devices, Inc., Norwood, MA 02062:
Nonlinear Circuits Handbook
Signetics, P.O. Box 9052, 811 East Arques Ave., Sunnyvale, CA
94086:
Analog Applications Manual
SYNTHESIZER KITS
Aries
Rivera Music Services now markets the Aries modular syn-
thesizer kits. This line consists of a large variety of modules.
222
Applied Synergy
Applied Synergy has a complete line of services and products
for the hobbyist. These include circuit boards for custom ICs, a
polyphonic keyboard, silk-screening and panel construction,
custom modifications, and more.
Applied Synergy
311 West Mifflin St.
Lancaster, PA 17603
Powertran
Powertran has several synthesizers and a vocoder available in
kit form. Many of these circuits were published in ETI Maga-
zine.
Powertran
Portway Industrial Estate
Andover, Hants SPIO 3NM U.K.
Digisound
Digisound has a complete line of synthesizer module kits
(including some circuits in this book). They also offer a con-
struction manual for a complete system.
Digisound, Ltd.
13 The Brooklands
Wrea Green, Preston
Lancashire PR4 2NQ U.K.
CfR Associates
CFR Associates has several synthesizer module kits available.
CFR Associates
Newton, NH 03858
Serge Modular
572 Haight St.
San Francisco, CA 94117
223
Maplin Electronic Supplies, Ltd.
Maplin has a large line of products in kit form (including syn-
thesizers).
E-mu Systems
417 Broadway
Santa Cruz, CA 95060
PARTS
Curtis ICs
Curtis Electromusic Specialties
110 Highland Ave.
Los Gatos, CA 950.30
PArA Electronics (also a source for keyboards)
Digisound, Ltd. (also a souree for tempeo resistors)
224
Solid State Micro Technology for Music, Inc. (SSM)
Solid State Micro Technology for Music, Inc.
2076B Walsh Ave.
Santa Clara, CA 95050
Digisound Ltd.
E-mu Systems (small quantities only)
B & B Audio
Aphex Systems, Ltd.
7801 Melrose Avenue
Los Angeles, CA 90046
BUILDING A SYNTHESIZER
225
paper should be fairly thin, with blue grid lines. You also need
to buy several permanent-ink, fine-point, felt-tipped markers.
Back home, it is time to layout your circuit board on the
graph paper. Tape a sheet of white paper to your desk top. Then
tape a sheet of the graph paper over this. The blue grid lines
should now stand out. The next part is the hard part. If you like
jigsaw puzzles, you will enjoy laying out pc boards. When you
are laying out a board, the following rules should be abided by:
1. Make supply and ground traces as large as possible.
2. Bypass supply lines to ground with O.l-ILF ceramic
capacitors in several places on the circuit board (by each
IC is great) (Fig. A-I).
3. Where the supply lines attach to the pc board, install
O.l-ILF or larger tantalum capacitors between the supply
voltages and ground (Fig. A-2).
4. Keep op-amp summing node (" -" input) traces short. Mak-
ing these long will invite oscillation, rf pickup, and noise.
Also, keep in mind the suggested guarding method for
sample and hold circuits (given in Chapter 3).
5. Try and avoid ground loops by using a single-point ground
(all ground connections go to a single point), or by organiz-
ing ICs according to signal flow. Those ICs closest to the
module input should be farthest away from the external
supply connections. Those ICs close to the module output
can go closer to the external supply connections (Fig. A-3).
Get out a couple of your electronic magazines and take a look
at how they designed their pc boards. Don't be afraid to add
jumpers where necessary. This writer has found that the best
procedure is to layout a board using the symbols shown in Fig.
A-4 for ICs, resistors, capacitors, and jumpers. Use dots for
holes. Connect the dots with a single line. You should be able to
space lines on the pc board 0.1 inch (0.25 cm) apart with no
problem. Note that the layout is done from a topside view.
Once you have finished the layout with the permanent-ink
marker, cut a piece of circuit board to size and tape the grid
paper layout over the fiberglass side. Cover the grid paper lay-
out with invisible-type tape. This is to protect it from damage
during the next step.
Now it is time to drill the board. A good size drill bit to use is
a No. 60. Drill holes everywhere you see a dot in the layout.
226
0.1 J1F
CERAMIC
/ CAPACITOR
V+
II II
Fig. A-1. Bypassing Ie with
I I
ceramic capacitors. V- :;-;;
O.lJ1F /
CERAMIC
CAPACITOR
2 TANTALUM
CAPACITORS
Once you are sure you have drilled them all, carefully remove
the layout from the pc board. Hold the layout up to the light to
see if you missed any holes. If you did, stick the layout back on
the board and drill the remaining holes. Save the layout as a
reference of all circuit traces on the board.
Use a blunt metal edge of some type to scrape off burrs sur-
rounding the holes on the copper side of the pc board. Once
this is done, you should clean the copper with steel wool or a
powder cleanser and water until it has a bright shine. Make sure
it is clean of dirt, corrosion, and fingerprints .
Turn the layout upside down on the white paper taped on
your desk. You should be able to see the circuit traces through
the paper. Now you can use the felt-tipped pen to draw the cir-
cuit traces on the pc board, using the upside-down drawing for a
reference. If you make a mistake, you can use a pencil eraser or
227
INPUT
OUTPUT
- INPUT OUTPUT -
small knife to remove the ink. Be sure that the ink is going on
thick and black. Don't be miserly with the pens or you will re-
gret it when you see your finished board.
After you have finished drawing the circuit with the pen, you
can etch the board. Ferric chloride is the most popular chemical
for this purpose. It can be obtained as a solid which you dis-
solve in water or as a solution from most chemical supply
houses (at a cost much less than at your electronic store). The
etching process should be done at a location far away from
everyone and everything. The fumes will etch metal, so guess
what they do to your lungs. Wear old clothes when etching your
boards. Ferric chloride stains will not come out. The actual
etching is best done in a Pyrex (glass) cooking tray. Pour about
an inch of etch into the tray. Place your boards copper side
down on top of the etch (so they Boat). If the board sinks, you
will probably have to turn it over, let it sink, and agitate the tray
until the board is etched. If your board Boats, you can leave it
there for 10 to 20 minutes and let it etch. A Boodlight placed
over the board will heat it and the etch and speed up the etch-
ing time, or the Pyrex tray could be put on a hot plate set on its
lowest heat setting.
228
8-PIN IC RESISTOR CAPACITOR JUMPER
TO LE VEL
CONTROL
229
If you wish to make another board, re-cover the top side of
the layout with tape. This is so you can tell if you have drilled
all the holes when you use it again.
When you have finished with the etch, pour it back into the
container. It can be reused many times. Never pour the etch
down the sink, as it can etch through pipe.
MODULE CONSTRUCTION
T
OJ 75 IN '"""'-,rr'--,r-c...,,-"""'-,rr'-..,,'
(0952 eM)
1:::::-1
_1-
(A) Male header connector.
10 0 o 0 0 01
; ; ; ; ; I
LOllN
I (025 eM)
Use the thickest sheet aluminum you can find or afford for the
front panels. Metal salvage yards are a good source for small
sheets (usually sold by the pound). Have it sheared into several
3-inch by 9-inch (7.6- by 22.8-cm) pieces.
You may wish to tape some of the O.l-inch grid paper (the
same type used in the pc layout process) over the panel to help
you center the holes. Suggested hole spacings are given in Fig.
230
A-6. Cover the grid paper with invisible tape to make it durable
and reusable for additional panels. Mark the hole locations
through the paper and into the aluminum with a punch or nail.
Remove the paper and drill the holes. It is the best to start out
with small drill bits and work up to the final bit size. You can
deburr the drill holes with a larger-size drill bit.
TOP
MOUNTING ! I h O.251N
lr--'-...:..:(0c.c6..:....
3 .:. :.CM:: . ). - - - - - , . - - - r -
HOLES """I + .1 +
0.25 IN 125 IN
+ (3 171CM) +
(0 63[CM)
CONTROL
T
MOUNTING U51N
HOLES +
1 +
(4.4 CM)
SPACE FOR
MOUNTING PC 91N
BOARD AND ANY 0.75 IN 0.75 IN (22.86 CM)
NECESSARY SWITCHES CM.) (19 CM)
+_l
I
_15IN __
(3.81 CM) I
+ --r
liN
+
(2.54 CM)
PATCH
JACK
HOLES
+ + liN
+
(2.54 CM)
+ + liN
+
MOUNTING
HOLES
(+ (2.54I CM) +
I 31N
------=(7.62
I
Once all the holes are drilled, you can "frost" the front side of
the panel with a wire-brush "grinding" wheel. This gives the
panel a nice appearance and removes any corrosion marks on
the aluminum.
A piece of sheet metal bent in a 90 angle can be used to
mount the circuit board. Leave an extra V2 inch (1.27 cm) on the
231
circuit board to allow for mounting. You can also use pieces of
aluminum "L" channel to mount your board. Pop-rivets or
screws can be used to mount the channel pieces to the front
panel. Both methods are shown in Fig. A-7.
Rub-on letters can be used to label your front panels, but they
take a lot of time and effort. You might try a hand labeler (Dymo
or equivalent) for a quick and easy method. It doesn't look too
bad either.
CIRCUIT BOARD
MOUNTING HOLES
SIDE REAR
232
possibly starting at the control voltage section. Get as much of
the circuit working as you can. If you are using a custom Ie,
check out all of the external circuitry. If that seems to check out
satisfactory, try testing the custom Ie on your prototyping
board.
You may experience unwanted oscillations in some of the
op-amp circuits. This is more likely to occur with the FET-input
op amps. Try installing small-value (10-50 pF) capacitors across
the op amp feedback loop. This will reduce the high-frequency
gain and possibly stop the oscillation. Other causes can be
ground loops or long unshielded lines coming from the Ie
inputs.
The Cabinet
You can make a cabinet for your synthesizer using I-inch by
lO-inch (2.54- by 25.4-cm) pine. See Fig. A-8 for some sugges-
tions.
The modules are installed using small pan-head sheet-metal
screws. Start out with just two screws per panel until you are
sure you have all of the modules situated where you want them.
REINFORCE CORNERS
WITH ANGLE IRONS
\ ::-:.------ liN x 10 IN
. .. . .-_-_-- . (2.54 x 25.4 CM) PINE
liN x liN
n . (2.54 x 2.54 CM)
1,1 11 00 STRIP PINE OR HARDWOOD
li!/
1:\ \I 0 0 MODULE
i\\\\
d\\
./
\'! II
:!:::::;:;::;;::=====I. 0
I;t::''=' 0 i====::::;:;;;;::;:;::;:::==-
____ _
233
Ie DATA SHEETS AND
PIN DIAGRAMS
234
FUNCTIONAL BLOCK DIAGRAM
1- +VCC
MUL TIPLIER
X-INPUTS
L ...z I
OP-AMP
<I: INPUTS
I a:
Oc:
MUL TlPLIER <l:w
Y-INPUTS :::J:;
0,,-
L :::J....I
COMPo
...
O:::J
::;: OP-AMP
OUTPUT
Y-GAIN
-VEE
X-GAIN X-GAIN
235
OBJECTIVE SPECIFICATION
FEATURES
Complete compressor and expandor In ABSOLUTE MAXIMUM RATINGS
1Ie PARAMETER RATING UNIT
Temperalure compensated
Grealer than HOdS dynamic range POSitIVe supply Vdo
Operates down to 6Vdc 570 24
System levels adjustable with external 571 '8
components TA Operating temperature range -40 to +70 c
Distortion may be trimmed out Po Power dissipation 400 mW
CIRCUIT DESCRIPTION
BLOCK DIAGRAM
The 570/571 compandor building blocks,as
shown in the block diagram, are a full wave
rectifier, a variable gain cell, an operational
amplifier and a bias system. The arrange-
ment of these blocks in the IC result in a
circuit which can perform well with few
external components, yet can be adapted to
many dIVerse applications
The full wave rectifier rectifies the Input
current which flows from the rectifier input,
to an internal SL.:mming node which is bi-
ased at VAEF The rechfled current is aver-
aged on an external filter capacitor tied to
the C AECT terminal, and the average value pressor application. thiS would lead to third A compensation scheme built into the .6.G
of the input current controls the gain of the harmonic distorhon, so there is a tradeoff to cell compensates for temperature, and can-
variable gain cell. The gain will thus be be made between fast attack and decay cels out odd harmonic distortion. The only
proportional to the average value of the Irmes, and distortion. For step changes in distortion which remains is even harmonics,
mput signal for capacitlvely coupled voltage amplitude, the change In gain with time is and they eXist only because of mternal
inputs as shown in the following equation. shown by this equation offset voltages. The THO trim termmal pro-
Note that for capaCltively coupled inputs VIdes a means for nUlling the internal offsets
there IS no offset voltage capable of pro- for low distortion operation
ducing a gain error. Theonly error will come
from the bias current of the rectifier (sup-
plied internally) which is less than .1/lA
The operational amplifIer (which is internal-
The variabte gam cell is a current In. current
G ly compensated) has the non-inverting in-
out device with the ratio lOUT/liN con-
put tied to VREF. and the inverting Input
trolled by the rectifier. liN is the current
connected to the .o.G cet! output as well as
G I VIN I ave which flows from the.6.G input to an internal
brought out externally. A resistor, R3 is
c
-----..:-- summing node biased at V REF. The follow-
brought out from the summing node and
ing equation applies for capacitlVely cou-
The speed With which gain changes to fol- allows compressor or expandor gain to be
low changes m Input signal levels is deter- pled Inputs. The output current lOUT. IS
determined only by Internal components.
mined by the rectifier filter capacitor, A fed to the summing node of the op amp.
The output stage is capable of 20mA out-
small capacitor Will yield rapid response but put current. This allows a +13dBm (3.5V
will not fully flUer low frequency signals. rms) output into a 300n load which, with a
Any ripple on the gain control signal will serres resistor and proper transformer, can
modulate the Signal passing through the result in +13d8mwltha600n
vanable gain cell. In an expandor or com-
S!!IDIlIICG
236
EI EI D
BUCKET BRIGADE DEVICES MN3004
';claY-l,l, DATA
APPLICATIONS:
The MN3004 is suitable for audio signal processing, e.g.;
Variable speech control of playback and voice control of
-
tape recorders
Reverberation effect of stereo equipments
Tremolo, vibrato and/or chorus effects in electronic mu-
sical instruments
Variable or fixed delay of analog signals
Telephone time compression and'voice scrambling in communi
cation systems; etc
The deVICe are subject to change tor ,mprovement w,thout proor notice.
While every precaution has been taken ,n the preparat'on of th,s data sheet,
the publosher assumes no respOnsibility for patent liability with respect to the
use of the information contained herem
237
MN3004------------------_________________________
----t--
Clock Voltage "l" VCPt Voo
kH,
Clock F'E'Quency
-
Clock RIse TIme '00
- - .
Clock Fall Time 01< 1 tCPI
--------- - --- '00
__
fcp 40 kHz f .., 1 kHz dB
" 4
fcp 100kHz
*, Clock Waveforms
--- OV
CPl
ICPf
238
TERMINAL ASSIGNMENTS
(Top VIew)
CIRCUIT DIAGRAM
l l - f .... Vout-Vin
Input Frequency f,,, (Hz) Input SIgnal level V", (dBm) Input Signal Level V,n (dBm)
239
MN3004 ______________________________________________
CIRCUIT EXAMPLE
---- '. VOD
'::;
(J Oeldyed
iI
,MN30()4'
i
OUTLINE DIMENSIONS
UnIt mm (.nchl
240
MOS
CMOSIC
DIGITAL INTEGRATID CIRCUITS MN3101
PRELIMINARY DATA
Clock Generator / Driver for BBD's
.
generate low Impedance two clock phases reqUIred for
driVing BBD's, In addition, the MN3101 prOVides the optl"
Ul
mum VGG for BSQ's when the MN3101 IS used With BBD's
on a common VOD supply
If!f3I\.
* Matsushita Electrol"llCS Corporation's BBD ploduct range
MN3001. MN3Q02. MN3003. MN3004. MN3005.
8-Lead Dual-tn-Line PlastIC t'ackage
MN3006. MN3007. MN3008. MN3009. MN301 0
MN3011 (Developmental)
NOl8 The MN3003 '<, pro",ded wtlh ar> 'nternal osc" 310!
Features:
_BBD direct driving capability-up to two MN3005
types (equivalent to 8192 stages)
eEither internal or external oscillator can be used
Two phases (1/2 duty) output
eProvided with Vee supply circuit
eOperates on a single power supply: -8--16V
.8-lead dual-in-line plastic package
Application
eBBD clock generator/driver
241
MN31 01 ______________________________________________________
.. '
11
_-
----
Absolute Maximum Ratings (Ta= 25'C)
...... - - -
--
-18- + 0.3 V
_T_ p,
Topr
200
- 10-+ 70
mW
'C
T... - 30- + 125 'C
Wit'! ,"peel to GND-=OV.
GNO- OV
V. 0 -, V
......_ V"
V, - O- - 15V
Voo+ ' Voo
"-
I" 3D pA
o X> 0,,,",
I,", V, - - 'OV DO mA
I,,, V, - -14V 05 mA
I.", v, - Voo 30 ,A
I,,", V, - GND 30 ,A
0>3 0,,,,",
I,", V,-- 'OV ,. mA
I" V, - - 14V ,0 mA
I""
I,,",
v, - Voo
V, - GND
.- 1_ 30
30
pA
pA
C.t CPl 0,,,.", T._
I,", v, - - , Ov '0
I" V, - -14V '0 mA
v, - voo
I"" 30 ,A
I,,", V, - GND 30
242
Terminal Assignments
(Top View)
PIn No.
1-_---1_G_ N_O_
IJ- I
1
I/O
SUPPl y __
l
I
I
____
._-
Outputs 1/2 duty cycle clock pulse at frequency 1/:2 of an oscdlahon frequency. havln", an
-
___ _
ep,
OPPosIte phas.e relationship with respect to CP2
1----'-1
__ __L __
- --- __
-15V supply voltage Input
4 CP2 0 CNtpulS. Clock pulse having an opposite phase relaMnshlp WI!Il respect to CPl
'
OX3 Internal External Oscillallon
r-;-- OX2
F
C, R network connect,on to the Pins i An external oscdlabon Input to OXt,
.
*
-,-'-
C. R. and R2 Value Examples
(!)
4>
ill
-
Rt (0,
,2k
m
Clock output frequency fO! CP1 or CP2
'" OSCIllabon frequency
0
,------
52-440
14-280
_I
I 'c;t'.(IcH&)
7 5-750
-
2 6 -220
o 7-- 140
--
--
243
_____________________________________________________ MN3101
fcp- R2
Po-fcp
Fig 2 Power ConsumptIOn '.IS Clock Frequency Fig. 3 Maximum Clock Frequency '.IS Load Capacitance
at 150mW Power Consumption
244
- -- - - -- -- - - - - - - -- -- - - - - - - -- -- - - -- -- -- - - - - -- -----MN3101
Application Circuit Example 1----- Echo Effec t Generation C"CUlt With The MN3005
II
II
II
II
_ 43io.O UI'FII
IN PUT 1)-=-If',"""'>-Nor+-'1
3.3,.,F
245
tv
....
O'l
Application Circuit Example 2 - - - Echo Effect Generation Circuit With The MN3007
247
tv
00
*'"
Electrical Characteristics of The Application Circuit Using The MN3007 (Vcc=9V. Ta=25'C)
I Item I Symbol I Condition I Min. : Typ. L l -__
DEVICE DESCRIPTION
The SAD-512D is a 512-element Bucket-Brigade Device
(8BD) with internal clock drivers that require only a 5 volt
(or higher) single-phase clock input.
The device has its output split into two channels to provide
output over each full clock period in normal operation. The
SAD-512D is manufactured using N-channel silicon-gate
technology to fabricate a chain of MOS transistors and stor-
age capacitors into a bucket-brigade charge-transfer device_
It is packaged in a standard 8-lead dual-in-line package with
pin configuration as shown in Fig. 1. The functional equiv-
alent circuit is shown in Fig_ 2. Several of the many applica-
tions are listed above. Figure3. SAD-6120 Clock Waveforms.
put waveforms are shown in Fig. 3. For convenience, Vee
may be biased to the same potential as VDD. However, for
optimum performance, it is recommended that VBB be
adjusted approximately one volt lower than Vee.
If the sync input is unused pin 7should be connected to ground.
If either output is unused it should be connected to Voo.
As with all sampled-data devices, the input bandwidth should
be limited to a value less than one-half the sampling clock
frequency (usually to a value less than 0.3 f5)' Further, to
recover a smooth delayed analog output a post filter having
steep cutoff (e_g., 36 dB per octave or more) is desirable.
249
saturation. For inputs less than approximately 500 millivolts filter and a sample rate of 100 KHz or faster. With a 20 KHz
rms the distortion is less than one percent. Between this filter and 50 KHz sample rate the dynamic range is 63 dB.
point and the noise floor there is approximately 70 dB of Broad-band dynamic range is better than 55 dB for all sample
dynamic range. This dynamic range assumes a 20 KHz audio rates.
SPURIOUS t.(lISE
I
FLOOR SELOW-15db
: "",,,,.
LOAD RESISTANCE (K ohms)
-50 -30
INPUT LEVEL Idb)
-20
w
EJ1t-:- -
SAMPLe fREO '10 .......
-20 '"lid ".,IIO\.TS
--;;"';.-,--------;;;.0"
FREQuENCY lHz)
z
Q
2
... 4!iJLfi
10 15
INPUT LEVEL (Volt$ P-P)
2.0
"'" .......... ,.oc... """"V
F9".16. SA0-512D Oisto"ion 'II. Input Lev... Figure 9. Nomtal Operating Conf;guratton.
250
CIRCUIT CONFIGURATION for this requirement is that all input components become
modulated by the sampling frequency to generate (fs - fin)
The normal operating configuration is shown in Fig. 9. The and also many other products. The result is to "fold" the
odd and even outputs are summed to provide continuous input about fsl2 so that components above fsl2 reappear an
output and cancellation of the clock waveforms. The even equal distance below fsl2. Limiting the input to fs/3 provides
output contains the same information as the odd output, a filter "guard band" to permit adequate attenuation of the
only delayed for onehalf clock period, or a total of 513 ele" otherwise disturbing highfrequency components. .
ments of delay_ The data input, odd and even outputs, and The output should. be filtered because even after fullwave
summed output are also shown in Fig. 9. combination, the output is only stepwise continuous. Clock
A sync input is included on the device and the waveform is ing steps and transient "glitches" appear at the times of clock
shown In Fig. 3. This input allows synchronized operation of transitions. The high frequencies contained in the abrupt
multiple devices in either serial or parallel configuration when changes and in the clocking glitches are all extraneous and
the same sync pulse is applied to each individual SAD512D. for best performance should be removed by a filter with cut
If the devices are used individually the sync input (pin 7) off at approximately fsamplel2 or less and rolloff of as much
should be grounded as 36 dB/octave or more. Also, overload should be avoided
because increased signal amplitude near overload gives rise to
PERFORMANCE CONSIDERATIONS rapidly increasing highorder intermodulation products which
lie within the useful pass band and which thus are not nor
The SAD-512D. because of its low cost and clock-fixed mally reducible by output filtering.
delay independent of input frequency, has marly applications For optimized performance, care should be given to layout
in the consumer area, particularly for providing delay and its and design as well as to the filtering requirements. Ground
associated effects for audio-frequency devices (e.g., reverber- planes are required on circuit boards to reduce crosHalk, and
ation, vibrato, speed change or correction, etc.l. It is very im- high-quality summing operational amplifiers are required to
portant to remember that the device is a sampled..data device, obtain maximum cancellation of clock pedestals and glitches.
and as such has important requirements on filtering of the
For many applications, cost is a more important factor than
input and output signals and on control of the clock fre-
quency.
the ultimate in performance, and relaxed filtering is permis-
sible. However, the user should be well aware of the cost/
The analog input should be filtered to limit input compo- performance tradeoffs involved. For such relaxed require
nents to less than fsamplel2. Normally a stricter limiting is ments, a simple output circuit such as that shown in Fig. 10
desirable - to a limit more nearly 0.3 fsample- The reason is often useful.
Signal F requllncy
Bandwidth (Jdb pomt) See Fig. B 300 KH,
Signal to Noise See Fig.?
Distortion See Fig. 6
Galn 2
Video Input Capacitance Cm 15 pf
Video Input Shunt
Resistance 3 R 300 Kohms
OUtput Resistance
'" See Fig. 7
Ro
Optimum Signal Input Bias4 4.2 Volts
Maximum Input Signal
Amplitude Volts p-p
Sync Pulse Amplitude VOD Volts
251
Figure 10. Simple Output Summing Amplifier.
87270
252
SAD-1024 DUAL ANALOG DELAY LINE
SAD-S12 ANALOG DELAY LINE
The SAD-l024 is a general-purpose Sampled Analog Delay device fabricated using N-channel silicon-gate
technology in a bucket-brigade configuration to obtain flexible performance at low cost.
Low noise
Two independent 512-stage delay sections. Single 15 volt power supply.
Clock-controlled delay: 0.34 sec to less than
340fJsec.
N-channel silicon-gate bucket-brigade Voice control of tape recorders.
technology. Variable signal control of amplitude or of
Designed for self-cancellation of clocking equalization filters.
modulation. Reverberation effects In stereo equipment.
Wide signal-frequency range: 0 to more than Tremolo, vibrato, or chorus effects in electronic
200KHz. musical instruments.
Wide sampling clock frequency range: 1.5KHz Variable or fixed delay of analog signals.
to more than 1.5MHz. Time compression of telephone conversations
Wide dynamic range: SIN> 70db. or other analog signals.
Low distortion: less than 1%. Voice scrambling systems.
DEVICE DESCRIPTION
The SAD-l024 is a dual 512-stage Bucket-Brigade
Device (BBO). Each 512-stage section is indepen-
dent as to input. output. and clock. The sections
may be used independently. may be multiplexed to
give an increased effective sample rate. may be
connected in series to give increased delay at a
fixed sample rate. or may be operated in a differen-
tial mode for reduced even-harmonic distortion and
reduced clocking noise. Each section has its out-
put split into two channels so that in normal oper-
ation output is provided over each full clock period.
or 1M SAD-1Q24.
'.... 2. EffUhr-.nl Circuit D.8Ift of either 512....... s.cllon
The SAO-'024 is manufactured using N-channel
silicon-gate technology to fabricate a chain of MOS GNO are common to the two separate delay sec-
transistors and storage capacitors into a bucket tions. Figure 2 shows the functional equivalent cir-
brigade charge-transfer device. It is packaged in a cuit diagram. Some of the many applications are
standard l6-lead dual-in-line package with pin con- listed above.
figuration as shown in Figure 1. Only Vdd and
GND , ,. NC
Normal voltage levels and limits are given in the
tabular specifications. Clock inputs are two-phase
square waves (02 is the complement of 0,) which
IN A 2 IN. swing between ground and Vdd. For convenience,
2A
, ,. '2.
Vbb may be biased to the same potential as Vdd.
However, for optimum performance, it is recommen-
OUT A
NC
, "
"
NC
OUT B
ded that Vbb be adjusted approximately one volt
lower than Vdd. and that the clock amplitude equal
V dd. Unused outputs only should be connected to
Vdd; other unused terminals (including those mar-
OUT A'
Vdd
7
"
'0
OUT S'
".
ked N.C.) should be connected to ground.
The input analog signal is connected through the
first MOS transistor to the input storage capacitor
while Ql is high; the charge is then transmitted to
'A Vbb the next bucket-brigade stage when Q, is low. Q2
high. Thus the signal samples are those values in
FltUre ,. Pin Conf.......Uon. SAD-1024. Note: U-..d existence at the positive-to-negative transitions of
ahould be connected to V.; .., ohr _ _ _ pi", ,hould be
_11K," 10 GND (pin 1). Indudlftg ItI-. mIIrQcI N.C. (I, and the input sample rate fs is the same as fQl.
253
As with all sampled-data devices, the input band-
width should be limited to a value less than one-
half the sampling clock frequency (usually toa value
less than 0.3 15)_ Further, to recover a smooth de-
layed analog output a post filter having steep cutoff
(e.g., 36 db per octave) is desirable.
PERFORMANCE
Typical performance of the device is shown in the
specifications and in the curves of Figures 4-7.
These data were obtained with the test configura-
tion 01 Figure 3. Internal dispersion becomes the
limiting factor lor sampling clock frequencies above /
/
1.SMHz.
_..... /
//
/
"5-----;;2.0
INPUT LEVEL (Volts P-P)
'..... I. IArHC114 D............ L.....
16
12
z
g
Flguras 4 and 5 indicate the linearity and show the
rapid increase in distortion as the input level is t5 08
increased toward saturation. For inputs less than SAMPLE RATE- 150 KHz
INPUT LEVEL o.5v p-p
approximately SOO millivolts rms the distortion is 0.4 SIGNAL FREQUENCY 10 KHz
less than one percent. Between this pOint and the
noise floor there is approximately 70 db of dynamic
range.
LOAD RESISTANCE (K ohms)
SPECTRUM ANALYZER IF BANDWIDTH'1KHz ......
Odb REFERENCE 2 VOLTS PEAK TO PAK
INPUT SIGNAL FREOUENCY
SAMPLE FREOUENCY- IMHz
Figure 7 shows the frequency response 01 the de-
vice when terminated as shown. The dotted lines
indicate the range of variation from device to device.
I
---:::.- .....
-5 ())TPU'" CiRCuIT CONFIGURATroN
" "- "- "-
w '\ '\
'\ '\
"n
-1
\ \
ii!
-15
> SAMPLE FREO 10 MHz
g
C
-20
'del' VOLTS
Figure 6 shows the loading effect 01 the output ter- CIRCUIT CONFIGURATIONS
minating resistor. The data indicate the output source
Each SAD-1024 consists of two 512-element delay
followers have approximately 400 ohms internal
sections electrically independent except for com-
impedance. For this test each output was connected
mon grounds and power supplies. The sections
through a terminating resistor to ground, thus
may be used in series, in parallel mUltiplex, in a
isolating any interaction between the two output
differential mode, or as completely separate de-
followers.
254
vices. But note that for a given system sample rate,
the perallel or differential configuration may be pref-
erable to the series configuration. A number of
possible arrangements using one or two devices
are described in the following sections.
2. Serial configuration
This configuration doubles the permissible delay
time for a given sample rate. It is generally pre-
ferred when longer delays are required than can
be obtained from a single section.
In the serial configuration, output from channel
A is slightly attenuated to restore the level to
tt .
1 .0 ... ..
equal that originally input to A, and this modified
signal then connected to input B, as in Figure 9.
III A and g, B are connected together as are
G2A and IJ2B. Under these conditions the in-
255
tive portion of Q1A, data is input to section A, 5, Multiple-device Operation,
to be held and propagated down the bucket bri- Extension of any of the above methods of oper-
gade at the value present when 0i A falls. Data ation to multiple devices is possible. Serial oper-
to section B is input during the positive portion ation is restricted by the requirement of gain
of 01 B, which is the same as 02A, so that data restoration between sections, by increased dis-
is alternately sampled into section A and section persion as the number of BBD cells increases,
B, one sample per half-period of the clock. At and by all the switching noise of single devices.
the outputs we now sum either outputs A and B Note that the SAD-l024 itself exhibits slightly
(for 512 clock half-peri'>ds of delay) or outputs more than unity gain, so that direct serial con-
A' and B' (for 513 clock' half-periods of delay), nection through a resistance network Is possible.
but now there are two samples overall per clock
period instead of only one. Thus the Nyquist Additional units may be multiplexed in the
frequency overall is FN = fsamplel2 = fclock, parallel-multiplex configuration by shifting the
or double thatforthe single section or serial sec- phase of the clock to successive devices by71"/N
tions operating at the same clock rate. One could radians where N is the number of devices. Thus
thus halve the clock rate to keep the overall sam- in the case of two devices, for example,.device
pling rate and Nyquist frequency the same as #2 has its clocks shifted by 71"/2 radians or 90
for the single or serialed sections, but delay is from those of device #1.
twice that for a single section (equal to that for
the serialed sections.) Multiplex operation is
generally preferable only when operating at high PERFORMANCE CONSIDERATIONS
sample frequencies, as a means of reducing in-
dividual section rates. For sample rates of 200 The SAD-l024, because of its low cost and clock-
KHz or below, other limitations generally favor fixed delay independent of input frequency, has
serial operation. As before, unused outputs many applications in the consumer area, particu-
should be connected to Vdd and other unused larly for providing delay and ita associated effects
pins grounded. for audio-frequency devices (e.g., reverberation,
4. Differential Operation, vibrato, speed change or correction, etc.). It Is very
important to remember that the device Is a sampled-
In this configuration, more effective cancellation data device, and" as' such has Important require-
of clocking glitches is possible, because the ments on filtering of the Input and output signals
same clock transitions are combined differen- and on control of the clock frequency. Also,
tially and even-harmonic distortion cancels. The increased signal amplitude near overload gives rise
arrangement is as in Figure 11. Operation is simi- to rapidly increasing inter",odulatlon products
lar to that for singlEH:hannel operation except which lie within the useful passband and which
for the differential cancellation of the output thus are not normally reducible by filtering. In the
pedestals and clocking glitches, and cancella- first place, the analog input must be filtered to limit
tion of even harmonics, as in push-pull opera- input components to less than fsamplel2. Nor-
tion. It should be obvious that two devices could mally a stricter limiting is desirable-to a limit more
be combined in parallel-multiplex, with each de- nearly 0.3 fsampl e. The reason for this require-
vice differentially connected, to give the benefits ment is that all ,"put components become modu-
of a Nyquist frequency equal to the clock fre- lated by the sampling frequency to generate (fs-fl n)
quency, as well as the benefits of differential and also many other products. The result is to "fold"
operation. the input about fsl2 so that components above fsl2
reappear an equal distance below fsl2. limiting the
.. ...
input to fsl3 provides a filter "guard bend" to penmit
adequate attenuation of the otherwise disturbing
high-frequency components. In the second place,
even after combination as indicated, the output Is
only stepwise continuous, and clocking "glltch..-
appear at the times of clock transitions. The high
frequencies contained in the abrupt chang.. and In
the clocking glitches are all extraneous and for belli
perfonmance should be removed by a filter with cut-
off at approximately fsamplel2 or 1_ and roIIoIf
of as much as 36 db/octave or more.
256
For optimized performance, care should be given
to layout and design as well as to the filtering re-
For evaluation purposes or for relatively high
quirements. Ground planes are required on circuit
performance operation, a circuit board is avail-
boards to reduce crosstalk, and high-quality sum-
able from Retiean. This board encompasses the
ming operational amplifiers are required to obtain
maximum cancellation of clock pedestals and desired filters, clock control, and ground plane.
glitches. External balanced + and - power supply (nom-
For many applications, however, cost is a more in.ally "15 volts) and TTL clock drive is required.
important factor than the ultimate in performance, Figure 13 is a photograph of the board and Figure
and relaxed filtering is permissible. However, the 14 is its schematic diagram. Note that the board
user should be well aware of the cosVperformance is arranged such that the two halves of the SAD-
tradeoffs involved. For such relaxed requirements, 1024 may be operated independently, or in series
a simple output circuit such as that shown in Figure as desired. The separate connection also permits
12 is often useful. parallel multiplex or differential operation; the se-
ries connection is useful for longer delay.
"'",
SECTION Each output filter amplifier is n9minally designed
A
"""
------OUT as a two-pole maximally flat filter with cutoff fre-
SECTION , quency of approximately 20KHz . They follow stand-
ard active two-pole filter design, with the source
impedance of the SAD-1024 and the balance ar-
rangements taken into account. Change of cutoff
frequency requires component changes. For the
separate configuration, each section of the SAD-
1024 is provided with its own two-pole filter; for
the series configuration, the filters are cascaded
to improve the out-of-band attenuation. The SAD-
+VOD SUPPLY
1024 provides output from terminal A (or S) during
the period 01 is high and output from A' (or S')
when 02 is high. These outputs are summed at the
OUTf--.--- balance potentiometer whose adjustment permits
equalization for slight differences in the source-
A, B t--------o follower outputs from the SAD-1024. The board
10.' SC-l024A is designed to handle a wide range of
ouT'f-->--- bandwidths and clock rates; as a consequence no
Figure 12b. Feedback Impedance COnvert Circuit. Provides improved frequency
attempt has been made to provide band limiting at
I ponn end low output impedance. Connect unuSed outputs to the input. Anti-aliasing filters should be provided
Vckjlnd aU othe, unused pins to ground
externally if the input is not otherwise limited to a
bandwidth less than f sample / 2.
Figure 13. Photograph 01 SC\02." Enlulllion Bo.rd. Figure 14. Schemalic Diagram of evllluahon Circuil SC-102'(A
257
DEVICE CHARACTERISTICS AND OPERATING PARAMETERS
PARAMETER SYMBOL MIN TVP MAX UNITS
Clock Voltage 1 10 15 t7 Volts
Drain Supply
Voltage) Vdd 10 15 17 Volts
Bias Voltage! Vbb Vdd- 1 Vdd Volts
Sampling Freq. 101, flll:2 0.0015 1.5 MHz
Clock Rise
Time 30
Clock Fall
Time leI 50
Clock line
Cap ce 110 pI
Signal Freq.
Bandwidth 200 KHz
(3db pOlntl
Signal to NOise See Fig. 4
Distortion See Fig. 5
Gain' 1.2
pI
Rm 200 Kohms
Output Ro See Fig. 6
Optimum Bias +6 Volts
Maximum Input
Signal Amplitude Volts pop
Average Temp
CoeffiCient of Game - 01 dbJ'C
Average Temp.
Coefficient of Opti-
mum Input 8ias 6 mvj C
.
'0
" 'bb
Information fumllhed herein II believed 10 be aeeurate and reliable. Howwer. no mponlibillty II ...umed by AETICON Corporation for itl UIIII
nor lor eny Infringement of petenUt or other rlghta of third partl.. which mey mult from ttl u ... No Ileenllll is gr.nted by Implication or other
wlM under eny pa'enl or patent rlghtl 01 AETICON Corporation
Copyright RETICON Corporllion 1977 COnlentl mey not be reproduced in whole or in pert without the wrlt!en con'ent 01 flETICON Corporauon 08300
Specification. ere lubjllCllo chenge WIthout notice Pru,ttd in U.S.A
258
PRELIMINARY DATA SHEET
COMMON .,
01 Hie
v Signal In
88
Hie Hie
Hie Hie
Hie Hie
Hie VDD
OUT A OUT A
259
Absolute Maxlltun Ratings
'I'errIlerature (operating) 0 to 70 C
NoImal voltage levels and linits are given in the specifications, Table 1. '!be
clock. inputs are ronnaUy OCIIIplemantaJ:y square waves. '!be timing relationships
are roncritical, so long as the crossing level is below the top quarter of the
wave.
t ol tc
-2-- - 50 50 0 nsec
01
02
tr 50 10 nsec
tf 50 10 nsec
tal tr tf
-2-
RET ICON Corporation a sub'<;dla'y of EGRtG. I", W",lIps!ey. Massa, hysells.
Copyright RETICON "'ay "01 110 t('J..j.och.... l'r1 >1\ w"ot.! or ." ,-,;.. t ..... ;'hOIlI H'1l ,',,'dh'" ',1.111
sent of RETICON CorporatIOn. Specifications are suhject to change ""ill)au I notice ,..., ;nte,! in
Informat!on furrllshed hereir ,s helteved 10 he accurate and ,elh,loI(>. HOwever, "0 'esuollsi!>:",y is assu'netJ IJV AI::TICON
Corporat,a!, for liS use, nor for .;lOy Infrlngem.ent of oatents or other "q"'H; of third ..unf!s ""tw:h rn,)y res,.I' hom iU'JSt?
No tieetlse IS hV impliciitton o. other .... 'se under any P'Il"nl or p;n!!'..,t rtqhlS of Rl- r CUN Corporahon.
260
TABLE I
V
iIl l H,
8 (1)
V 12-15 18 Volts p
iIl2H,
3 (2) 6 Volts dc
VIB Input Bias 0.3
--
vin (V 11.5 2 volts p-p
JlIi>ts)
C. Input 2 pf
ill
capacitance
(1) '!be device is operable to clock and supply voltages as law as S volts,
but at substantially reduced signal levels.
(2) Input bias is dependent on the particular values of VBB ' Vill and VDD '
so that adjustment provision should be made to fit the circumstances
used.
(3) WARNING: Observe M:S Handling and Operating Procedures. Maximum rated
supply voltages must not be exceeded. Use decoupling neb;orks to sup-
press IXJWer supply turn on/off transients, ripple and switching transients.
Do not apply independently powered or OC coupled signals or clocks to the
chip with IXJWer off as this will forward bias the substrate. Damage ll'ay
result if external protection precautions are not taken.
-3-
261
SIK
<0
'0
E-< S.lK
:0
"
E-<
:0
3.0K
0
-5
IJK
Ol
>
H
E-<
-10
1/4 1 4 16 64
Rl, KILOHMS
(LOG SCALE)
-;7J
Output Level.
------,- - - - - - T - - - -
ii;
'0
M
+
f:J
<>:
E-<
:0
-20
-40
""""'2 :
":0E-<
o
-60
-4-
262
l'ioure 5. spectrum Analyzer Response Showing
a 3 KHz Signal and Four Traces of
Noise Background at Sample Rates of
20, 40, 100 and 200 Kilohertz.
Note:
Due to the sinx
sampling, thEf re-
sponse is down
3.92 db at the
Nyquist frequency.
-5-
263
Figure B. SIMPLE OUTPUT CIRCUITS
VOO SUPPLY
..---.----,
IK 101ll"
RL
20K
OUTPUT CIRCUIT OF + (---o0UTPUT
10UF TO FILTER
DELAY LINE
20K
b) CURRENT MIRROR oUTPUT
Good Summer
RelatIvely low Zout
limit ed goin
Voo SUPPLY
J[:=r:===lj!rIA-L-AN"""cr ',>--oM,",
loUF TO FILTER
-6-
264
ell
.001 II(.
CLOCK IN
U'-
"1'+
L
1.0
INPUT lII11\'5: DTMEItWI5[ S.PEC.IFIE.O
"'+ \. I\l L "ESIS\'!.\Nc..t. Vl\lUE'. S
lOOK
- 1.
':- -= ",
1001<.
t. !\Ll V"lUES. "p.r.
1'J,\C.P.QFA,'jI.,A,tlS
3 ALL DEL (6) LA1!>ELE 0
<I'" WITH THE. So\v"E I\M..
101<
+1l..V
....rr
10,", 10"
'-2>oL-'---f.-____-"> A TesT
""0 ,,'-,
S_IAK
"'S "to
-'.OK
e.s co OlD
004-1 .J;._DO'"
co. "'\1
004-1 t'K -=
)f-
KEFEIlf.NtE
&--UI-I4-
L _ _ _ _... ) " OUTPUT
!\lOT
..r:-- UI -'
"'ll
!:I( 1001\
ell I'"
&--U3-1'I- U3 !l_9K.
"''''
1.
t-o
Ol
Figure 7. SC4096 Evaluation Board Schematic
CEM3310
2900 Maurica Ave .
San ta Clara, CA 95051
(40812478046
266
CEM 3310
Electrical Characteristics Application Hints
Vee +15.0V VEE " -5.0 to -15.0V RX 24K TA =25C Supply
MIN TYP MAX Units Since the device can withstand
no more than 24 volts between
Time Control Aange 50,000:1 250,000: 1
its supply pins, an internal 6.5
Attack Asymtote Voltage IY Z ) 61 6.5 69 V volt 10% zener diode has been
Attack Peak Voltage (Yp) 4.7 5.0 5.3 V
Attack Peak to Asymptote Tracking 1.5
provided to allow the chip to run
Control Scale SenSitivity 58.5 60 61.5 "
mY/Decade
off virtually any negative supply
voltage It the negative supply is
Temperature Coefficient of Control Scale +3,000 +3,300 +3,600 ppm
ATK, Dey, RLS Scale Tracking -300 0 +300 )J V/Decade
between -4.5 and -6.0 volts, it
may be connected directly to
E)(ponential Full Scale Control Accuracy
0.3
the negative supply pin (pin 6).
SOnA < '0 < 50 "A
2nA < 10 < 200/JA 2
1.5
10 "
%
For voltages greater than -7.5
volts, a series current limiting
Attack C.Y. Feedtnrough 2 6 90 "V
Decay C.y, Feedtt'lrough 2 NONE
resistor must be added between
Release C.v. Feedthrough 2 NONE pin 6 and the supply. Its value is
Sustain Fmal Voltage Error (VoNes) -3 .23 mV
calculated as follows'
'10
Release Final Voltage Error IYO) -3 "0 ,]3 mV REE (VEE - 7211.010.
0
267
Absolute Maximum Ratings
current), every 100n wIll cause
Voltage Between VCC and VEE Pins 24V
a 1% increase in control scale
error. As the times are increased, Voltage Between Vce and Ground Pins +18V
this error will decrease in direct
proportion Voltage Between VEE and Ground Pins -6.0V
The voltage applied to the
sustain level control input will Current Into VEE Pin 50mA
directly determine the sustain Voltage Between Control and Ground Pim 6.0V
voltage of the output envelope
(minus the sustain final voltage Voltage to Gate and Trigger Input Pins VEE to Vee
error). Voltages greater than the
threshold voltage will cause the Storage Temperature Range -SS""c to +150C
envelope to ramp up to thiS - 2SoC to +75C
higher voltage when the peak Operating Temperature Range
threshold is reached_ The rate at seen from the envelope equa fer With a low output impedance.
which this OCcurs will be equal tions, the sustain/final lIoltage RO may be lowered by adding a
to the fastest attack rate. error, the asymptote error, and resistor from the output pin to
Since all four control inputs the control voltage feedthrough VEE. However, every 1mA of
are connected only to the bases are all affected by RX. A prac current drawn from the output
of NPN transistors, the control tical maximum of 240K is pin may increase the buffer
input pins of tracking units may recommended for RX when the input current as much as 5-6
be simply tied together. There internal buffer is used and 1 M If nA with consequent degradation
fore. in the case of the time an external FET buffer is used. in performance.
control inputs, only one atten-
uator network is required to Trimming the Envelope Times Envelope Equations
control the same parameter in The RC time constants of the Attack Curve
a multiple chip system. output envelope will typically
track to within t 15% from unit VO A '" Vl.. !l-exp{- e VCANT))
Selection of RX and Cx to unit. even at the longest time Decay Curve
As IS shown in the envelope settings. If better tracking is
VO D = (Vp-Vcs )exp(- eVco/VT)+Vcs
equations. the RC time constant required, the best method for
of the attack, decay and release trimming the time constants is Release Curve
curves is given by RXCX times to simply adjust RX with a VOR = Ves exp(- RxtCx e VCR/VT)
the exponential multiplier. trimming potentiometer.
exp(-Vc/VT). Practical circuit Sustain/Release Final Voltage Error
limitations determine RX and Output Drive Capability
The buffer output can sink at (F = Vos + IB1 Rx -IB2Rx/1+e VcA/VT
the multiplier, from which eX
can then be calculated, The peak least 400 JJ.A and can source up Attack/oecay/Rete.e Asymptote Error
capacitor charging and discharg- to 10mA, but with considerable
ing currents is given by (VZI degradation in performance. An A "" Vos + IS1Rx -IB2Rx e-VCA,Q,R/VT
Rxiexp(VeAiVTi. (Ves/Rxi output load no less than 20K to VCA == Attack Control Voltage
exp(VcoiVTL and (Vp/Rxiexp ground is recommended.
VCD = Decay Control Voltage
(VCR/VT) for the attack, decay, The buffer has a somewhat
and release phases respectively. high output impedance. As a VCR = Release Control Voltage
For the best scale accuracy and result of this, small steps (50mV) Ves = Sustain Control Voltage
tracking at the shortest times, appear in the output waveform
these currents should be kept at the phase transitions, due to Vas == Op Amp Offset
Jess than 100 and in all the sudden change in drive the 'B1 Op Amp Input Current
cases they should not be allowed output must provide to RX. The
to exceed 300 JJ.A. This sets the largest step is at the beginning of 182 = Buffer Input Current
minimum value for RX at 24K. the envelope and is given by Vz == Attack Asymptote Voltage
larger values of RX will allow (RO/RXIVz. It may be de Vp = Envelope Peak Voltage
positive time control voltages to creased by i.ncreasing A X. lower-
be used. However, as can also be ing RO. or using an external buf- VT = kTA
268
Input and Output Waveforms
v,-sv constant ofAxCx(exp(VCA/
VT) + 1) (I.e. a rapid attack With
only a 2:1 control rangel. To
prOVide the normal full range of
attack control under thiS mode
of operation, 01 should be dis
LJ LJ
Use of External Buffer
at least -500mV at the base of
02. ThiS resistance may be
calculated as follows:
A o110012VEE-l)
For various reasons, it may be The result will be 5,000 times or
desired to use an external buffer more sustain and release final
One possible benefit might be a voltage shift with the attack.
lower mput bias current 082), control voltage. If external Clr
with consequent Improvement in cuitry is added to apply the
the associated errors The exter- -500 mV only when the gate IS
nal buffer should be connected high, then only the sustain final
as shown in Figure 1 For proper voltage will exhibit slgnlflCant
operation, the buffer should shift
be capable of sourcing at least
RX 700 J.l.A and should have a POSI- Use of the Attack and
tive current flowing into the Threshold Voltage
input Pin, such as that resulting Output Pins
from NPN or P channel JFET The attack output pin (pin 16)
Inputs and the peak threshold voltage
pin (pin 3) have been prOVided
Disabling the Control to allow additional fleXibility.
Voltage Rejection Circuit Since pin 16 outputs a -.4 to
The purpose of 01 (see block -1.2 volts only dUring the
diagram) is to greatly reduce the attack. phase, It may be used to
control voltage feed through. provide a logiC Signal which
During the attack phase, the the attack phase (see
base of 0115 brought negative figure 21, ThiS Signal may be
effectively disabling it and allow ANDed with the gate to prOVide
mg 02 to control the charging a logiC signal Indlcatmg the decay
current, During the decay and phase. As was mentioned above,
release phases, however, the base a sustain control voltage greater
of Q1 IS at ground, causing neg than the threshold voltage will
ative voltage excursions on the result in a "jump" to the sus tam
base of 02 to vilry the charging level. By U510g the threshold
current only a maximum of 2: 1 voltage pin as shown In figure 3,
(as opposed to the normal the sustain voltage can be pre
10,000:1 or greater), Under vented from [Ising above the
normal triggering conditions envelope peak. thus eliminating
(applymg a trigger and a gate), thIS undesirable effect. (This
thiS has no consequence, except effect can also be elimlOated by
to reduce the attack control dlsablmg the control voltage re
voltage feedthrough to a negli lectlon Circuit as descrrbed above)
(ftS
gible amount. However, it only
a gate IS applied with no trigger,
the output '111111 ramp up to the
Fttu1e J. Addition of SUlt.ln C.V.lnput llTflllCf
sustain level, approaching it
asymptotically with a RC time CI..m1S ELECTROITIlJ3K.
2900 Maurica Ave
Santa Clara, CA 95051
(408) 2478046
269
SSM
2033
VOLTAGE CONTROLLED
DESCRIPTION
The SSM 2033 is a precision voltage controlled oscillator rlesigned specifically for tone generation in electronic music. It has saw-
tooth, and variable width pulse outputs. Simultaneous exponential and proportional linear sweep inputs C3l control
operating frequency over a 5OO,OOO-to-' range. On-chip low input bias summer and control op amps have been provided. The pulse
comparitor. which has builtin hysteresis for clean switching. can control pulse width dutY cycle from 0 to 100%. Hard and soft
sync inputs make possible a rich variety of modulation and harmonic locking effects. In addition, the operating temperature of the
chip is regulated making external temperature compensation unnecessary. Only one trim (volts/octave) is required for normal
operation.
FEATURES
Full on-chip temperature compensation. All outputs are short circuit protected.
5OO.000-to-1 sweep range. Hard and soft sync inputs.
Simultaneous sawtooth, triangle, and variable Pulse duty cycle voltage controllable from 0 to
width pu I.. outputs, 100%
Simultaneous exponential and proportional linear Pulse comparitor has built-in hysteresis.
sweep inputs. 100 nsec sawtooth discharge time.
On-chip summer and control op amps. Only volts/ octave trim required for normal
Excellent exponential conformity. operation.
- 5 SUM 11
+ OUT
LIN '3 _
15
PULSE
MOO IN
Solid Sme Micro Technology for Music,lnc. 20768 Walsh Avenue, Santa Clara, CA 95050, USA
14011 727..Q117 Telex 171119 PATENTS APPLIED FOR
270
SPECIFICATIONS OPERATING TEMPERATURE STORAGE TEMPERATURE
25C _10C to +55C -55C to +125'C
Vee = +15, -v = Internal Reference
NOles:
121 current limiting resistor reqUired for negBtive supplies greater than -6 V.
The schematic above show the tYPical connection of the SSM 2033 as an electronic music veo. The control circuit section is
redrawn for easy reference (figure 1). Any number of input voltages can be summed by amplifier A, which drives the exponential
input attenuator to pin 14. Amplifier A2 forces the current in 01 to be equal to the sum of the reference current, established by
R1 , and the linear FM voltage. The current in the output transistor 02 is:
-V q/kT
io=(V+/R, +V L/R 2 )e e
Propagation delay and discharge time can cause a deviation from true exponentiality at high frequencies. To correct for this effect,
transistor 03 provides feedback to the exponential control input. At low frequencies (currents), 03 will have a negligible effect
on the voltage at the base of 0,. At high frequenCies (currents), 03 will correct for the tendency of the oscillator to track flat.
271
LINEAR FM
-15V +15V
24K 300pf 27K
) I -- ---::L 0I f
54.91<
1%
S 1 )'NPUT.,J.OP,T'ONAL) 68Q!1
O.lJ.1-f -,-
lOOK 11% "-J
3.01M1% ,
L-cl 16P-
r:-
n TRI r"2 15P---
J
OUT
lOOK 1% L 3 2 14P---
V/OCT
4 0 13 P - - - 470
911<1%
I.
tt;
20K 3
5 12P-- .....
P ULSE 6
3
MOD INPUT R.
P ULSE ICP---- SAW
OUT
l()(X)pf 9r- R]+f\",IK
I
15K 3.3K 22K'
: l000pf 'Polystyrene
ARO SYNC All resistor values 5%
f--<:iwUT (OPTIONAL
unless noted.
TYPICAL CONNECTION --
- ----- --------
+V
VlOCTAVE
Ra 1.5M
"',I R, = 3.01M 1%
13 4711
lOOK =
v, r--+-'------w.-----,
,*0.11"
lOOK
V,
1%
lOOK 4
V, V, 54.91< V. 14
1% A,
+ 1%
3.3K R,
1%
l000pf
J v. = V, +v,. .. Vt4
R.
1%
R, + R. IK
55.91<
The SSM 2033 has an on.-chip temperature sensor and heater which tgulates thll chip temperature to 5SoC. The kT/Q term in the
exponent of the equation above is now a fixed value independent of ambient temperature. Operating temperature is reached
30 to 40 seconds after device power-up. Current drawn by the heater will deer ,se as ambient temperature rises. The temperature
stabilization also insures that errors caused by offset drift with temperature in the summer and control op amps will be extremely
small.
272
The output current of the control circuit is fed to an integrating amplifier which creates the sawtooth waveform. The instantaneous
sawtooth output is compared to a reference voltage that is two-thirds of the positive supply. Sawtooth discharge is accomplished
by a capacitorless one-shot which delivers a pulse to the discharge transistor when triggered by comparator C t -
The triangle converter and pulse width comparator shape the sawtooth to provide the other two waveform outputs_ The 27K
resistor between the positive supply and the soft sync pin centers the sawtooth for proper triangle conversion_ Comparator
compares the pulse width modulation input voltage to the instantaneous sawtooth output to create a pulse that can have a duty
cycle between 0 and 100%. The control range on the PWM input is between 0 and 10 V. C:2 has about 180 mV of built-in hysteresis
to give fast clean transistions on both the rising and falling edges of the output.
The hard and soft sync features provide additional means for timbre modulation and additive synthesis. The hard sync input senses
a falling edge, such as another 2033's sawtooth discharge, and forces an immediate discharge of the synced 2033. The resulting
waveform has a complex harmonic structure whose pitch is that of the incoming oscillator (figure 2). The soft sync input also
accepts a falling edge but it will force discharge only if the synced 2033 is within 240K/(R 3 + 2.4K) % of discharge. This enables
one to phase-lock two oscillators to frequencies that are exact small integer ratios of one another (figure 3). By mixing the wave-
forms of the two oscillators. complex additive synthesis can be performed.
l000pf
>-------j 1--"+---w.---1
HARD
SYNC IN
TO INTERNAL
LOGIC
273
SSM
2056
The SSM 2056 is a preCision, self-contained. four section voltage controlled transient generator designed for easy use in program
mabie electronic music systems. The device offers near zero offset and control faedthrough, standard 5V peak output and an
exponentially controlled 50,000 to 1 range on all timing inputs. Sustain voltage level can be varied from 0 to 100%. In addition,
all control inputs are gangable and referenced from GND up allowing easy interface with electronic controllers and programmers.
FEATURES
TRIG OUT
GATE SUBSTRATE
GND -v
COMPARATOR
+.v
UNTERNALI
PIN DIAGRAM - TOP VIEW
Solid State Micro TeehnolDfW for Musk:. 2076B Walsh Avenue. Santa Clara. CA 95050, US.""
14081248-0917 Telex 17189
274
GND
GATE
..,....-----11 ____
GATE
u u m u ____ -,-I_ __
TRIG L.-_ _ _ _---' LJ'---_ TRIG
DIAGRAM DESCRIPTION
AT, 10, FD indicate times controlled by Attack, Initial Decay and Final Decay Time Control inputs respectively (A positive going
voltage increases the time constant.) All phases of the waveform are true exponential approaches to +6.5 V, Sustain Voltage and
Ground respectively.
Variation (untrimmed)
NOTES
-Final :opel;ifications may be 10 change
(1lPin9ls used for negative supply voltage5 -4 V # Vee;;' -7 V.
Pin 8 is used for negative supply voltages --8 V ;;> Vee;;' -18 V
275
BUS) 'OOK
TO PINS 1, 3,4 AND 12 TIME
OF OTHER UNITS 50K CONSTANT
sv 1 AoJ
",
Fo
R,
10
AT
", SIMULATED
LOAD
COMMON
CONTROl
NETWORK
R,
l-"IcJIU,11 for Ca[1ac'tor ilnd III(lht un,t to un,t v,lr'dIIO" ("OLlflrj p,,, 2 d not rpqu'riJ
TYPICAL CONNECTION
The diagram above shows the typical connection for a polyphonic system The control attenuators on the left are common to all
2056's used for the same function Within a vOice; such as control of the final VCA. The sense of the control is from Ground up
with minimum time periods at GNO and Increasing times at positive voltages. Somf recommended resistor values for oftenused
sensitivities are given along with the general design equations below. The temperature coefficient of the time sensitivities can be
compensated by using Tel Labs type 08' C resistors for the R,'s
The time constant adjustment is necessary In polyphonic systems to make all voices sound the same for long attack times The
procedure is to set the AT control for the longest required attack time, ground 1.0. F.D. and S.V., and adjust each 2056 to gIVe
exactly the same attack period; 10 to 20 seconds IS about the longest that is musically useful The adjustment can be Ignored In
manually controlled monophonic systems
The Gate/Tngger Input(s) can be driven directly from the outputs of all TTL and CMOS logic families. The ADSR output can dnve
any grounded load RL > 2 5K, C L < 5000pf
ttTel Labs Type Q81C = 60 n @ 2S'C R t should be kept as small as possible when the conlrol anenuetor is driVing many uniU.
276
CURTI$ EUCI'ROf'Il.JSI SPECA.T1E3
277
CEM 3330/ CEM 3335
Electrical Characteristics Application Hints
278
Absolute Maximum Ratings
lel' (pin 7 and pin 12) while
transmitting the exponential Voltage Between Vee and VEE Pins +24V.-O.5V
control input, VeE, (pins 6 and
14) unchanged to its output. Voltage Between Vee and Ground Pins +18V,-O.5V
The transfer function for each Voltage Between VEE and Ground Pins -S.OV,+O.5V
log converter is:
Voltage Between Output and Distortion Trim
ICL or Ground Pins +18V.-O.5V
VOle =-Vr In - - + VeE =VG
IREF Voltage Between All Other Pins and Ground Pin S.OV
10 = -liN .-VcEIVT
CEM 3335 Circuit Block and Connection Diagram
'REF
For proper operation, the linear EXP.
SIGNAL SIGNAL
control current. 'el, refer- CNTl.
INPUT
OUTPUT INPUT
ence current, 'REF, are positive
in polarity; that is, they flow
into the device. A negative input
current for leL will simply
shut the gain completely off,
while a negative reference cur
rent should be avoided. The
signal input current may, of
course, be either polarity.
The Block Diagrams show
typical external components
connections to the devices.
The signal inputs and the linear
control inputs are virtual ground
summing nodes; therefore, the
signal input currents and linear
control currents may be ac-
curately generated from their
respective voltages simply
with resistors terminating at
these nodes. Note that these
virtual ground inputs also allow
multiple input voltages to be
mixed (linearly added) on-chip
by merely adding more input
resistors.
Although the voltage com-
pliance of the gain cell outputs
ranges from -O.3V to Vee -
1.5V. best results are obtained
by feeding the outputs into
virtual ground inputs. Thus. in
the Block Diagrams, the output
currents are converted to
voltages with external op amps.
279
CEM 3330/ CEM 3335
CHlCURREliTGAIH>'ARIES
fROM TO ATTENUATION
--------------
10klll if'
I
I 60 ---___
I lOKHZ- __
IIIHZ---------:
I
/
/ "
/
/
/ .. ..
//OISTORTION IDLE CURRENT IN"_
...... lRIMONI
EVEN "AAUONIC DISTORTION
10 20
lOll CURREN'
CONTROL FHOTHAOUIiH
EQUAlSUJrIlTY
. -so
, 10' .100"A
;
... --:----"c-----;;;,,---::,,;----c!::----::;--:!
IDlCURANTIN"A
ODD HARMOllllt IlISTOAIION
OUTPUT CURRENT SLfWUH
,,"
,,,"
CEll CliARl.' GAIIil
EQUALS UNITY
I_UlTl'lY IY l,D
fOR HAil CHt tURRUIITI
".. -+--'-"",;;-,--;."C----;:;;--;;;;,--;;.
1:t:---
.,t . . ,. . '"
.lIt I - - - ; , - - ; , ; - .--i;;1O-----;;
..;----;;.---;;.
IOU IDLE eURRE"T I""A
I'tAkOUT'UTCURRElnBHOREClI"UIG
280
Selection of for these conditions is unity, but determines the most negative
Component Values the voltage gain for the circuit value of VeE required to gen
is RF fR I and may be greater erate the maximum voltage gain,
Selection of the input and or less than unity. Note also that If the exponential input is not
output resistor values requires the current gain may be made used, then it may be grounded
consideration of the preferred greater than unity for inputs less (VeE = 0), and only the values
and maximum operating current than VIN MAX. of leL MAX and IREF juggled
levels of the device as well as to obtain the maximum gain
the available input voltages and Although RI and RF have
been selected using maximum factor.
desired output voltage. In gen-
input and output conditions,
eral, the input signal current
the device should nominally
Selection of the
should be made as large as pos- Quiescent Operating
sible to obtain the best signal operate at least 6 to 20 dB
below these maximum levels Current
to noise ratio. However, for
either peak inputs currents or (corresponding to 100iJA or less A unique feature of the device
peak output currents greater input and output currents) for is that the quiescent standby.
than several hundred microam- best distortion performance. or idle, current of the signal-
peres, distortion begins to in- With the values of RI and RF carrying transistors can be set
crease significantly. until the selected, the maximum linear anywhere between one and
total cell current (input peak control current, ICL. and most several hundred microamperes,
current plus output peak negative exponential control thus effectively allowing the
currentl exceeds the maximum voltage, VCE (VG in the case of user to set the operation of the
value specified in the specifica- the 3335), are selected to give gain cells anywhere between
tions for 'CPo At this point, the maximum desired voltage Class B and Class A. Since the
clipping occurs. resulting in gain in accordance to the follow- quiescent operating point
severe distortion. ing equations: affects all VCA characteristics,
For optimum noise per- improving some while worsen-
formance, it is recommended ing others, the idle current is
that the input resistor. Rio selected to optimize those
be selected so that the maximum or parameters important to the
peak input signal voltage causes particular application.
% the peak cell current to flow As shown in the graphs of
Av 3335 = e- VGIVT Figure 1, increasing the idle
in the input: RI current decreases distortion.
RI = VIN MAXf% Icp The maximum gain is only improves slew rate. and in-
limited by either the total cell creases available output cur-
Note that the input could current exceeding Icp, or exces rent, but all at the expense of
handle up to 6dB more current. sive noise and DC output shift increased noise and greater
but the cell current gain would with cell current gains much control voltage feedthrough,
have to be reduced so signifi- greater than unity 1>+4OdB). Thus, if the application is to
cantly to prevent clipping. that For greatest linear scale control the level of low fre-
the signal to noise ratio would accuracy, the maximum value of quency control signals where
actually be degraded_ (Output leL should be restricted to control voltage rejection is
noise increases roughly by the 100iJA or less, although currents critical. then the VCA is best
square root of an increase in up to 3QOiJA can be used with operated Class B. For the pro
cell current gain1- If more than increasing error. For best distor-' cessing of audio signals, however,
one signal is being summed in tion performance, the reference the VCA should be operated
the input. then the total of all current. 'REF, should also be Class AB to Class A, with the
peak input currents should be set between SOIlA and 200pA; best compromise between dis
no greater than % Icp. Next, the it may be generated simply with tortion, noise and bandwidth.
output resistor. RF, is selected a resistor to Vcc. The linear The quiescent idle current is
so that the desired maximum for control input resistor. RCL. is set the same for both VCAs by
the peak output voltage before thus selected so that the maxi placing a resistor between the
clipping is produced with the mum available linear control idle adjust pin (pin B on the
maximum input signal. Thus. voltage produces the desired 3330. pin 6 on the 3335) and
RF = Vo MAX/ll lep maximum value for ' CL. the lEE pin (pin 5). Figure 2
Finally, the selected value of shows the idle current versus
Note the cell current gain 'REF together with leL MAX the value of this resistor. With
281
CEM 3330/ CEM 3335
internal resistors. In most cases, the peak signal level at which it
this idle current tolerance is is desired to trim the distortion.
acceptable because the \'CA The output voltage is measured
parameters will vary to ii much to four digits with a DVM for
lesser extent. However, the idle each of the three input condi-
current may be set more pre- tions. and the trim adjusted
cisely by measuring the die so that the output voltage
current and adjusting thl! value change is the same going from
of RIDLE with a trim pot until the grounded to positive input
the desired value is obtained as it is going from the grounded
The idle current is measured by to negative input.
measuring the output current Although the second harmonic
with no signal input and at a may be trimmed out to better
current gain of unity while than BOdB at almost any gain
putting roughly -0.5 to -1.5 setting and input signal level, it
volt on the distortion trim pin is best to perform the trimming
(pi ns 3 and 17 on the 3330. at a current gain of zero and
pins 3 and 13 on the 3335). input signal level around 10dS
below the clipping point. This
Trimming of the Second procedure wi II yield, in general,
Harmonic Distortion the best distortion performance
at all input levels and gain
When operating the VCAs less
settings except at the very
than Class A, internal transistor
" RIOlE IN
... mismatches will cause the gain
during the positive portion of
the input signal to differ from
highest (last 10 to 6dB before
clipping at the output). And
since in the case of the music
and speech signals, the last 15
IDLE CURRHITV$ ItIU IlDJUST RESISTOR that during the negative portion,
to 20dB should be reserved for
thus introducing even h,lrmonic
headroom. this result is
no resistor (R1DLE = 00) the distortion (predominanTly
acceptable.
idle current is typically at 1,uA second), In Figure 3 is st10wn a
As most of the odd order
and the VCAs will operate graph of typical untrimmed
harmonic distortion is due to
Class B. second harmonic distortion
crossover distortion, there is no
As can be seen from Figure 2, (distortion trim pins connected
way to trim it out; it may be
the idle current may vary sig- to ground) versus the id'e
reduced only by increasing the
nificantly from deVice to device current. This distortion may be
idle current
for any given value of RIDLE. acceptable in some appl'cations.
due to the 25% tolerance of the but will have to be trimmed
out in others. Trimming is
Optimizing the Bandwidth
accomplished by adjusting the As can be seen from the Block
voltage on the distortion trim Diagrams, the log converters are
30 pins (pins 3 and 17 on tl1e stabilized with a series 1K re-
3330, pins 3 and 13 on the sistor and .01,uF capacitor com-
3335) somewhere between pensation network from the
1KHZ 10mV, as shown in Figure 4. linear control Input to ground,
The even harmonic distortion while each of the gain cells
may be trimmed to near mini- may be compensated with a
mum with the following simple capacitor from the com-
procedure: The signal input is pensation pins (pins 9 and 11
alternately switched between on the 3330, pins 7 and 9 on..
ground, a positive voltage source the 3335) to ground. This gain
(such as a battery) and a nega- cell compensation is good for
tive voltage source of the exact low frequency control applica-
same magnitude (best accom tions, but may result in inade-
10 "L -,---.:----c;;--,,"'o--''" 100 201l plished by simply reversing the quate large signal bandwidth for
IDLE CURRENT IN leads to the positive vol1age qua I ity audio appl ications.
source). The value of the voltage Figure 5 shows an improved
fiGURE 1 SECONO HARMONIC DISTORTION,
source is selected to be f!qual to compensation technique for
282
greater bandwidths and slew and no temperature compensa
rate: By placing a series 1K tion is necessary.
resistor and .01pF capacitor To use the 3330 for exponen
'l
network from the signal input tial gain control only. the entire lDOH
to ground, the .005pF com- log converter may be bypassed, 15DK
pensation capacitors may be reducing the number of external
reduced to 150 pF, resulting in components and potential errors
the bandwidths and slew rate introduced by the log converter.
-15V
shown in Figure 1. This is accomplished by simply
leaving the linear and exponential
Control Inputs control inputs open, and apply
As was discussed earlier, the ing the exponential control
linear control input resistor, voltage directly to the IREF pin
RCL. should be selected so that
(which is also the direct input,
the linear control current reaches VG. to the gain cell) as shown in
a maximum of 50,uA to 200pA. Figure 6. The scale sensitivity is
This level is low enough so as the same as that of the exponen FIGURE 4: DISTORTION TRIM
not to cause significant control tial input to the log converter,
scale nonlinearity, but high and therefore requires the same
enough to swamp out the considerations as discussed maximum control voltage rejec
toffects of the internal input above. tion is to simply set the gain to
bias current. Since the actual For best distortion per maximum and adjust the pot
current controlling the linear formance, it is recommended for zero DC quiescent output
gain is the input control current that the impedance at both current. (The DC output current
minus this bias current. the the distortion adjust inputs at zero gain is always zero.)
input control voltage at which and direct control inputs (3330 The other method for mini-
the gain becomes zero is given or 3335) be kept below several mizing control voltage feed
by: hundred ohms. through is to balance the two
circuit halves by adjusting the
VelO = laACl +Vos Trimming of the Control second harmonic distortion trim
Voltaga Feedthrough discussed above. This method,
This cutoff point may be although usually reducing the
increased by injecting a small The shift in the qu iescent DC
output voltage as the gain is distortion below that of the un
constant negative current into trimmed value. will not adjust
the control input. or decreased changed is due to several factors.
by injecting a small positive One cause is the internal bias
current into the input. current at the signal current
As the scale sensitivity of the input, being only of concern at
exponential control inputs on idle currents less than 1
both the 3330 and 3335 are The other cause is the same po
18mVl-6dB, an attenuation tential imbalance between the
network will in most cases by two signal processing helves
required. An increasing positive which also is responsible for
control voltage decreases the even order harmonic distortion. ",N914
LATCHUP
gain. Thus, there are two methods PREVENTION
The basic gain cell is fully for minimizing the control DIODES
temperature compensated. The voltage feedthrough: One is to
only first order temperature inject an adjustable DC current
effect is the exponential control into the signal current input pin.
factor tempco 11NT). This as shown in Figure 7. The range
effect may be substantially of this current should be roughly
reduced by using a +3300ppm equal to plus and minus the idle
tempco resistor ITel Labs 081) current. (For idle currents less SIGNAL
INPUT
for RCE1, shown in the Block than 5pA, it is not necessary that
Diagrams. If only the linear this current be adjustable to FIGURE 5: GAIN CElL COMPENSATION
FOR LARGER BANDWIDTH
control input is to be used, then negative values.) The best tech
the exponential input is grounded nique for adjusting this trim for
283
the distortion to its potential Shown in Figure 1 are typical
minimum. Conversely, mi'li- values of control feedthrough
mizing the distortion with this versus idle current for un
trim does not necessari Iy trimmed. trimmed with the in-
minimize the control voltage put current adjust only, trimmed
ExP
/ feedthrough. (At high values of
idle current, it may even increase
it.) The technique for using this
with the distortion adjust only,
and trimmed with the input
adjust after the distortion has
CNTL
INPUTS trim to maximize the control been trimmed for minimum.
rejection is the same as before: For best overall VCA per-
I the pot is adjusted for zero OC formance at any idle current,
current output at maximum where both distortion and feed-
RCEI gain. through are important, it is
At idle currents less than recommended that the second
10llA, it is recommended that harmonic distortion is first
the input trim of Figure 7 be trimmed for minimum, and then
FIGURE 6 BYPASSING HIE lOG CONVERTERS the control voltage feedthrough
used rather than the distortion
trim, as the distortion trim trimmed with the technique of
tends to increase the distortion Figure 7.
above the untrimmed value when
SIGNAL feedthrough has been minimized.
INPUT Layout Considerations
At higher idle currents. however,
it is recommended that the dis- In the usual case where the out-
"I
tortion trim be used to minimize puts connect to the summing
V
feedthrough, since it will also inputs of op amps, these output
tend to reduce distortion below traces should be kept short to
_
the untrimmed value. In fact, prevent their high impedance
HIN914 this is a good method for from picking up extraneous
15V lATCHUP improving (but not necessarily signals.
PREVENTION Since capacitance greater
optimizing) both distortion and
jV_
DIOOES
control rejection with only a than 50pF at the idle adjust
-vvv---+-----, single trim. For absolute best pin may cause high frequency
'IV control voltage rejection, where oscillation, care should be
[ioLE the distortion is not as critical exercised in the layout to
as control rejection. it is recom minimize stray capacitance at
-15V
mended that both the input this pin.
SIGNAL current adiust of Figure 7 and
INPUT
the distortion trim be simul
FIGURE 7: CONTROL REJECTION TRIM taneously adjusted to produce
minimum feedthrough.
284
CURTIS ELKmOIn.JSIC. SPECA.T1Ea
285
CEM 3340/ CEM 3345
Electrical Characteristics Application Hints
286
Absolute Maximum Ratings
pin 16 on the 3345) internally
connects to the control input Voltage Between Vee and VEE Pins +24V,-O.5V
of the exponential generator Voltage Between Vee and Ground Pins +18V, -O.5V
(base of 0 1 ). This output is a
current and is given by: Voltage Between VEE and Ground Pins -6.0V,+O.5V
Voltage Between Frequency Control Pin
22VT or Reference Current Pin and Ground Pin 6.0V
10M " - - (1 -I C RZ/3.01
RT Voltage Between Multiplier Output Pin
and Ground Pin +6.0V, -lV
where V T '" KT /q = 26 mV
Current through Any Pin 40mA
@ 20C, and where Ie is the
total current flowing into the Temperature Range _55C to +150C
frequency control pin and must _25C to +75C
Operating Temperature Range
remain positive for proper
operation (a negative input
current will produce the same
output as a zero input current). CEM 3345 Circuit Block and Connection Diagram
Since the frequency control
fRlQCNlL
input pin is a virtual ground IIIPUH
summing node, any number of
control voltages may be summed
simply with input resistors to
"l
IOU::
this pin.
The current output of the
multiplier is converted to the
required drive voltage with a
resistor from the multiplier
output pin to ground. For
greatest multiplier accuracy,
this resistor, R S, should be 1.8k
and the current flowing out
of pin 2, 22VT /R T, be
close to the current flOWing
out of pin 1, 3.0/R z .
Since the components asso
ciated with the tempco generator
and multiplier determine the
maximum voltage
possible at the base of
should be selected to
desired frequency range
of the oscillator. The exponen
tial generator itself is capable of
delivering a current for charging
and discharging the timing
capacitor from greater th an
.5mA down to less than the C F , the timing capacitor. The rtor, such as mica, should be
input bias current of the buffer, oSGillation frequency is given by used for C F ).
thus allowing for a typical fre- Next the reference current
quency range greater than f"3IEG/(VCC eFI
for the exponential generator
500,000:1. The most accurate where I EG is the output current (Current into pin 13 on the
portion of thiS current range, from the exponential generator. 3340, pin 15 on the 3345) is
from 50nA to 100J,JA, should be If, for instance, the most impor selected. This current ideally
used for the most critical portion tant frequency range is from shou Id be the geometric mean
of the desired frequency range. 5Hz to 10kHz, then C F should of the selected generator current
Consideration of this critical be 1000pF at Vee" +15V (a range, but consideration of
range determines the value of low leakage, low tempco capac- the temperature coefficient of
287
the bias current for op amp A2
usually dictates a higher value
for the reference current. AI
though this bias current has
been temperature compensated,
it cou Id have a worst cast
tempco of 1000ppm and maxi
mum value of 400nA. Under
these conditions, a reference
h""av//1l)r1V /1l)r1V /1
V
/1 r1
l) V
/1
V
/1
V
..-1
V
/1
I
current of 10pA th rough Q 1,
"::LJlJUUlrLJU1flJlJL
for instance, would have a
tempco of 40ppm. It is recom
mended that, In general, the
reference current be selected in
the 3J.1A to 15jJA range
Since the reference current
pin is a virtual ground summing
node, the reference current may
be set up with a temperature
stable resistor to Vee, or other
positive stable voltage source. quency at some initial value is best accomplished by bypass-
A negative current into this pin with no control voltages applied. ing Rs to ground with a capac-
will simply gate the exponen- The frequency control scale itor, where the corner rolloff
tial generator completely off. is determined by the value of frequency is given by: fLP ;;::
With the value of C F and the input resistor to the control 1/(2.RsCi.
reference current now selected, pin, the value of the Q, base
the voltage excursion at the resistor, Rs , and the multiplier
multiplier output. which drives Trimming The Scale
current gain. Since the multiplier Error
the base of 01. is now deter- current gain, set by the ratio of
mined for the desired frequency the pin 2 current to pin 1 cur- There are two basic sources
control range. If this range were rent, should be near unity and producing exponential can
1Hz to 20kHz, the exponential Rs should be 1.8K, the control formity error in the control
generator current, lEG, would input resistor is the component scale: One is the exponential
have to range from 10nA to which should be selected for the currert generator and the
200t-/A in the above example, desired control scale. For the other ;s the precision multiplier.
requiring the base drive voltage, industry standard scale of 1 The error from the exponen-
VB, to vary from +180mV to octave/volt, the input summing tial converter is due partly to the
-78mV, since resistors become lOOk. The bulk emitter resistance of Q2'
lEG =0 IREF e- VBIVT recommended method for beconling significant at gener-
trimming the control scale is ator c Jrrents greater than 1DOpA,
The most positive voltage at to tweek the multiplier current and pilftly to the comparator
the base of 0, occurs when the gain by adjusting the value of delay, becoming sig
control current, Ie, is zero, and AZ 20% about the nominal nificant at frequencies greater
is 22VT Rs/RT' Therefore, in value. than 5KHz. These two effects
the above example, RT =22V T . Both the multiplier and the cause the oscillator frequency
1.8K/.18V = 5. 72K, and Rz exponential generator are com to go flat, but only at the
3.0RT/22VT '" 30K nominal. pensated with the 470n - .OlJ.1F uppermost octaves.
Finally, since the multiplier networks shown in the Block Circuitry has been provided
output current must range from Diagrams and are therefore to correct for these effects. The
+100pA to -43t-/A to produce necessary in any application. output of the hi-frequency
this desi red voltage excursion at Since the bandwidth of the track pin (pin 7 on the 3340,
the multiplier output and on the multiplier extends beyond the pin 8 on the 3345) is a current
base of Q, the control input audio range, it may be desirable which is one fourth the gen-
current, Ie. ranges from 0 to to limit the bandwidth to re- erator output current, lEG.
143t-/A. A resistor from Vee to duce possible noise at the base This current may be converted
the control input pin may be of 0" thereby reducing FM ,I
with grounded resistor to a
used to set the OSCillator fre noise and frequency jitter. This voltage, a portion of which IS
288
then fed back to the control octave, the scale factor could be
input pin. As the frequency is 0.4% different worst case, pro-
increased, this feedback voltage ducing a volts/octave error of
will tend to sharpen the control 0.4% x 18mV -" 72/1V. ThiS fifth
scale, but only at the upper octave would thus be 0.28%
end, since the feedback voltage (5 cents) sharp or flat. Note that
becomes significant only at if octaves above the adjusted
the higher generator currents. octaves were sharp, those
The amount of voltage fed octaves below the adjusted
back is adjusted so the scale octave would become increas-
is sharpened just enough to ingl-y flat, and vice versa.
compensate for the inherent Typically the error produced
high end flatness by the multiplier is much less
The method recommended than the above example. How
for trimming the control scale is ever, if maintaining a tighter
as follows: The hi-frequency
track adjust is first set so that
no correction voltage IS fed to
tolerance is required for the
particular application, the mul
tiplier error may be trimmed out
"JL>
""
the control input. The oscilla for each device. The trimming
tor frequency IS set around procedure I-equires that both R z
200Hz and the scale adjust and RS be made adjustable
trimmer is adjusted for the 3000 about the nominal value,
desired scale factor (e.g. 1.000 Rz IS first adjusted that the could lower the frequency by
octave/volt). Then the oscillator mUltiplier gain is constant over 150/10QK '" 0.15% (2.5 cents)
frequency is set to around the selected input current worst case. A load capacitance
10KHz, and the hi-frequency range; then Rs is adjusted for will act like a resistor with a
track trimmer is acUusted for the the desired scale factor (adjust value 1/(2fC L) and requ ires the
same scale factor. ing RS will reintroduce some same considerations as above.
The source of error from the error, so Rz may have to be A continuous load no greater
precision multiplier is due to the readjusted) . than 10K and/or 1000pF to
multiplier's gain (nominally Should for some reason it be ground is recommended.
unity) changing as the control desired not to use the tempera Since the sawtooth output
input current changes. This type ture compensation circuitry, the IS buffer isolated from the
of error causes the frequency to multiplien'tempco generator OSCillator circuitry, it can sink
become increasingly sharp or flat may be bypassed simply by at least .6mA and source over
as the control current is in- leaving pin 1, pin 2, and the several mA with no effect on
creased. The percentage differ- control input pin open, and oscillator performance, and only
ence in multiplier gains. and applying the control voltage to negligible effect on sawtooth
hence scale factors, at any two the base of 01 via the waveshape. Stray capacitance at
inputs to the multiplier may be output pin. this output greater than 40pF,
calculated as the percentage however, will cause a small high
error given in the specifications Waveform Outputs frequency oscillation. A 100n
'
times the difference in iJ.A AI! waveform outputs are short resistor between the output and
between the two corresponding CirCUit protected and may be load is all that is required to
outputs_ For example, suppose shorted continuously to any isolate more than .Ol/1F.
82
the scale were adjusted for Without damaging the
precisely 1 octave/volt at mid- Each output, however,
range. At one octave above this has differing drive capabilities
adjusted octave, With the mul- Although the triangle output cn'l140
tiplier output lO.uA different. can sink at least .4mA and , "
the scale factor cou Id be .08% source over several mA, care >-_ ... , ., '"''
different worst case. This must be exercised in loading
PULSE
"'.
would produce a volts/octave this output. Because the output OUT !. 'VI/\,-- !QI'. 0_,'1
289
to finite comparator gain. It 3 volts maximum for best
may be speeded up considerably operation.
by adding hysteresis as shown in Another method of hard
Figure 3. Care should be exer- synchronizing the oscillator is
cised in the layout to prevent shown in Figure 5. Negative
stray capacitive coupling be- pulses only are coupled into the
tween the pulse output and base of the PNP transistor, with
the PWM input,as this can cause a peak amplitude of 8 to 10
comparator oscillation. volts for best results at Vce =
The square wave output (pin +15V. This method will produce
7) from the CEM 3345 also the same waveforms generated
FIGUAE.METNOOFOASYIICOIiAISIIIIIORFAlllIlGEOGI. requires a pull down resistor to by the conventionally syn-
any negative supply greater chronized sawtooth oscillators.
The pulse output is an open than -4 volts. It provides an Finally. the oscillator may
NPN emitter, and therefore output swing from nominally be soft synchronized by negative
requires a pulldown resistor to 1.3 volts below the hard sync pulses applied to the threshold
ground or to any negative reference voltage to a level voltage pin (pin 9 on the 3340,
voltage. Any pull-down voltage nominally the same as the hard pin 10 on the 33451. These
between ground and .5 volt sync reference voltage. The pulses cause the triangle upper
above the voltage on the negative Block Diagram shows a con- peak to reverse direction pre-
supply pin will precisely deter- venient way of generating a maturely, causing the oscillation
mine the lower level of the full swing square wave from period to be an integral multiple
pulse wave. For pull-down this output. The current pulled of the pulse period. The peak
voltages more negative than this, down from this output should amplitude of these negative
the lower level will be nearly also be limited to a maximum pulses should be limited to 5
the negative supply pin voltage. of3mA. volts maximum and positive
The nominal upper level of the pulses should be avoided en
pulse wave is given by: Vcc - Frequency Synchronization tirely. If this input is not used
0.3V -1.3K IpLO for IpLO > The oscillator frequency may be for synchronization purposes, it
0.6mA, and Vce - O.9V for hard synchronized in several is recommended that it be by-
I PLo<O.6mA, where IpLO is the different ways. One way is to passed with a O.1IJ.F capacitor
pull down current. A maximum couple positive pulses, negative to ground to prevent synchroni-
value of 3mA for IPLO is recom- pulses, or both, into the hard zation or jitter to noise pulses
mended. For those applications sync input pin (pin 6 on the on the Vee supply line.
which require a more stable, well 3340 and 3345). A positive
defined upper level, the circuits sync pulse will cause the triangle
Linear FM
shown in Figure 2 may be used. wave to reverse directions only The reference current input
The pulse width of the pulse during the rising portion of the pin may be used for linear
output may be set from 0 to triangle, while a negative sync modulation of the frequency.
100% with a 0 to +5V external pulse will cause direction reversal The external input is summed
voltage (Vee = +15Vlapplied only during the falling portion. with the reference current
to the PWM control input pin The resulting waveforms are simply through a resistor ter-
(pin 5 on the 3340 and 3345). shown in Figure 1, and provide a minating at this pin. For audio
The fall time of the pulse wave wider variety of synchronized FM, it is recommended that a
is slower than the rise time due sounds than possible through coupling capacitor be used to
conventionally synchronized prevent frequency shift when
oscillators. Simple capacitive connecting to the external
coupling as shown in the Block source. The value of the input
Diagrams allows hard synchron- resistor should be selected so that
ization on both the rising and the maximum peak to peak input
falling edge of a rectangle wave. signal produces a plus and minus
Figure 4 shows circuitry for current equal to the reference
allowing only one or the other current.
of the edges to synchronize the
oscillator. The peak amplitude
of the pulses actually appearing
on the sync pin should be re-
stricted to 1 volt minimum and
CI!S
ruma ucrROIIUIC. aPE<IRIJlE&
2900 Mauricia Ave.
Curtis Electromusic Specialties ICES)assumes no responsibility for use of any Santa Clara, CA 95051
circuitry dMcribed. No circuit licenses are implied. eES reserves the right, at 1408) 2478046
IIny'time without notice,to change said circuitry. Printed U.S.A. 1980
290
C\RT1& EIi<l'ROIIUIC. aPECIFUIE&
..
Low Distortion in Passband:
0.1% typical
Low Warm Up Drift
,
RR.
Configurable into Low
Distortion Voltage Controlled
RESOIIA.eE Sine Wave Oscillator
eMiL l.fUT
tl5 Volt Supplies
291
CEM3320
Electrical Characteristics Application Hints
Vee - +15V R, = lOOK T A = 25C Supplies
In order to minimize the power
Parameter Min. Typ. Max.. Units
dissipation, the negative supply is
Pole Frequency Control Range 3500:1 10,000:1 regulated at -1.9 volts with an
Sensitivity of Pole Frequency
internal shunt regulator. This
Control Scale, Midrange 57.5 60 62.5 mVldecade not only reduces warm-up drift
Tampeo of Pole Frequency of the pole frequencies at power
Control Scale 3000 3300 3600 turn-on, but also allows vir-
Exponential Error of Pole tually any negative supply
Frequency Control Scale 1 12 % greater than -4 volts to be used.
Gain of Variable Gain CeU The current limiting resistor,
at VC=O 0.7 0.9 1.3 R EE , must always be included
Max Gain of Variable Gain Cell 2.4 3.0 3.6 and is calculated as follows:
Tampeo of Variable Gain CeU2 500 1500 ppm
Output of Gam Cell 2 0.5 1.0 2.0 Mn VEE -2.7V
Pole Frequency Control
Feedthrough 60 200 ,nV
As can be seen from the Block
Pole Frequency Warm-up Dnft .5 1.5
Gm of Resonance
" Diagram, an internal lOOn reo
sistor is in series between the
Control Element at ICR"'100uA .8 1.0 1.2 mrnhos
regulator and pin 13. This resis-
Amount of Rnonanee Obtainable
Before Oscillation 20 30 d8
tor, which allows for trimming
Resonance Control Feedthrough3 0.2 1.5 V
of the control voltage feed-
through (explained in further
Output Swing At Clipping 10 12 14 V,P.P. detail below) results in an actual
Output Nolse re Max OU1Put4 -76 -a6 dB voltage at pin 13 of around -2.7
Rejection in Bandreject 73 83 dB volts.
Distortion in Passband5 ,7 0.1 0.3 % Although the circuit was
Distortion in Bandrej8Ct6.7 0.3 % designed for a positive supply
of +15 volts, any voltage between
Sine Wave
0.5 1.5 % +9 and +18 volts may be applied
Internal Aeference Current. IAEF 45 63 B5 A to pin 14. The only effect, other
Input Bin Current of FreQuency
than power dissipation, is the
Control Input 0.2 0.5 1.5 .A maximum possible peak-to-peak
Input Impedance to Aesonance output swing in accordance
Signal Input 2.7 3.6 4.5 Kn with:
Buffer Slew Aate 1.5 3.0 \i/uS VO UT IV.P.P.I = Vee - 3V
Buffer Input Bias Current
!IEE-BmAI .8 >30 100 ,A
Buffer Sink Capability .4 .5 .63 .nA Operation of Each Filter
Buffer OutPUt Impedance2 75 100 200 n Stage
Positive Supply Aange +9 +18 V Each filter stage consists of a
Negative Supply RangeS -'I -IB V variable gain cell followed by a
Positive Supply Current 3.8 6.5 mA high input impedance buffer.
Note 1: -25mV < Vc < +155mV. Most of thiS error occurs In upper two octaves.
The variable gain cell is a current-
Note 2: VC" 0 in, current-out device (as opposed
Note 3: Untrimmed. 0 < ICA <
to the traditional voltage-in,
Note 4: Filter is connected _ low pass and set for 20 KHz cut-off frequency.
current-out device) whose out-
Note 5: Output signal is 3dB below clipping point.
put current, lOUT, is given by
Note 6: Output signal is 3dB below passband level, which is 3dB below clipping point. In general,
the following expression:
this is worst case condition.
Note 7: Distortion is predominantly second harmonic. lOUT'" (lAEF - liN) AIO e-VC/VT
Not. 8: Sinewave is not clipped by first stage.
Note 9: Current limiting resistor always required. where VT = KT/q, Vc is the
292
Absolute Maximum Ratings
voltage applied to pin 12, A IO
is the current gain of the cell
Voltage Between Vee and VEE Pins +22V.-0.5V
at Ve = 0 (Nominally 0.91.
and Voltage Between Vee and Ground Pins +18V.-0.5V
.46Vee - .65V Voltage Between VEE and Ground Pins -4V.+0.5V
IREF =--==--- Voltage Between Cell I nput and Ground Pins +0.5V.-6V
lOOK"
Voltage Between Frequency Control and
"25% Ground Pins 6V.
As the input to the variable Voltage Between Resonance Control and
cell is a forward biased diode to Ground Pins +2V.-1BV
ground, it presents essentially Current Through Any Pin 40mA
a low impedance summing node
at a nominal 6S0mV above Storage Temperature Range -55'C to +150'C
ground. The required input Operating Temperature Range -25'C to +75'C
currents may therefore be
obtained with resistors ter-
minating at this input node.
For normal operation of any The output impedance of the If the signal is from the output
filter type, each stage is set up variable gain cell, although high, of a previous filter section. it
with a feedback resistor, RF has a finite value. This imped- will have a quiescent level of
from the buffer output to the ance is reflected back to the .46Vee (6.9 volts for a +15 volt
variable gain cell input. and with input as an A.C. resistance of supply). Therefore, part of liN
the pole capac.itor. Cp, connected nominally 1 megohm in parallel will be supplied by this voltage
to the output of the variable with the feedback resistor. R F , through Re while the remainder
gain cell. This setup is shown regardless of control voltage will be sourced through R F .
in Figure 1. In the D.C. value. The pole frequency of The voltage gain in the pass
quiescent state. the buffer out- each filter section is determined band is given by REo/Re, In
put will always adjust itself so by the total equivalent feedback general. this gain should be set
that a current equal to IREF resistance, REO, and the pole to unity for stages two. three
flows into the input. capacitor in the expression: and four. The input resistor to
For lowest control voltage stage one can be scaled for any
feedthrough and maximum fp = e-VeNT size of the external input signal.
peakto-peak output signal, the 211' REOCp The resistance value should be
quiescent output voltage of each selected so that the maximum
buffer, VODe, should be: where: external input signal produces
RF lMU" the maximum passband output
VODe = .46Vee
signal before clipping.
Thus. in the simple case of REO = RF + 1 MU"
Figure 1, RF is calculated as
follows: --50%, +100%
VaDe - .65V
RF = -"'''''--- Signal Coupling into a
IREF Filta. Saction
= lOOK nominal For the fi Iter section to provide
the low pass function. the input
Since IREF can vary 25%. signal is coupled via a scaling
VaDe can vary nearly 30% from resistor, Re. into the input. If
device to device using a standard the signal is the external input to
5% resistor for RF . In the typical the entire filter. it will in general
case where Vee = +15V. IREF is have a D.C. quiescent voltage
nominal, and the D.C. level of zero. and all of liN equal FIGURE 1: ONE OF FOUR STAGES
output of each buffer should be to IREF for the first stage will be
set for +6.9V nominal. provided by its feedback resistor.
293
ces
To generate the hi-pass func- resonance feature. Note that due
tion, the input signal is coupled to the configuration of the
into the variable gain element resonance feedback, the reso
output via the pole capacitor. nance frequency of the high-pass
Cpo Therefore. any D.C. voltage will be approximately 2.4 times
level is blocked by the capacitor higher than that of the low-pass.
and lIN equal to 'REF for each while the resonance frequency
input is supplied only through of the band-pass and all-pass
the feedback resistors. The wi II be 1/2.4 = .42 times lower
voltage gain in the pass band is than that of the low-pass, for the
simply unity, regardless of the same component values. For the
value of R F . For best results, the state variable. resistor Ra adds
output impedance of whatever positive feedback to increase
is generating the external input the maximum Q, which is other
signal to stage one should be low wise limited by the reflected
compared to RF/4. 1M.Q impedance across the
integrators.
Sample Filter Circuits
The Block Diagram shows the
Pole Frequency Control
external components connec- Scale
SIGNAL INPUT
tions for a four-pole, low-pass The current gains of each of the
filter designed to operate off four sections (and consequently FIGURE 2: HI PASS FILTER WITH V.C. RESONANCE
15 volt supplies. The values their pole frequencies) are
for A F Re. and Rs were chosen controlled simultaneously with
so that a) when the 1 megohm a voltage applied to pin 12. (pin 8), a separate control cur-
reflected resistance is in parallel Since the scale is exponential rent input with a modified linear
with R F , the gain of stages two, with the standard 18mV loctave scale (pin 9)' and a current
three and four is unity. and b) (60mV/decade). an input atten- output internally connected to
with the buffer outputs at the uator network will in most cases the input of stage one. With an
proper Quiescent level of 6.9 be required. An increasing posi- impedance of 3.6K 900n, the
volts. the total current into each tive control voltage lowers the input is referenced to ground;
input is the required 63I-(A:.For pole frequencies of the fHter. thus, connection to the filter
stage 1, all of this quiescent For best results over a thousand- output win require a coupling
current is sourced by the feed- to-one control range. the voltage capacitor.
back resistor. For stages two. on pin 12 should be maintained
three. and four, 631-(A is sourced between -25mV and +155mV.
by the feedback resistor. while Unlike the typical variable
"t."
7Op.A is sourced by the coupling transconductance cell used in
resistor for a total sourced cur- most V.C. filters, the four stages 1001.
rent of 133,uA. Thus. to end up in the CEM 3320 are fully tem-
with a net quiescent input perature compensated. The only
current of 63liA. 70pA is sunk remaining first order temperature
out of the input by bias resistor. effect is that of control scale
RB- sensitivity (l/VT ). This effect
If connecting the filter input may be compensated in the
to an external signal causes the usual manner with a +3300ppm
D.C. level of the filter output to tempco resistor (Tel Labs 081).
change more than several volts,
it is recommended that an input
coupling capacitor be used such Resonance Control
as shown in Figure 4. The variable gain cell used to RfSDUICE
CIlL.IIPUT
Figures 2. 3, 4. and 5 show control the amount of resonance
high-pass, bandpass. all-pass, SIGUL IIPUT
is the traditional transconduc-
and state 'w'ariable realizations, all tance type of amplifier. It has a FIGURE 1: lAID PASS FILTER WITH V c. AUOIAICE
with the voltage controlled separate signal voltage input
294
Control of the transconduc- While operating the filter in
tance is accomplished with a the resonant mode, care should
current input. As the control in- be taken not to overload the
put is a low impedance summing input to the filter. If the signal
node at a potential near ground, output of stage one is allowed to
the control current may be become clipped, then not only
derived from the resonance con will the apparent resonance
trol voltage with an input re- of the signal at the filter output
sistor, RRC, terminated at pin 9. appear to be reduced, but the
This resistor should be selected D.C. level of the output signal
so that the maximum available will shift.
resonance control voltage pro When the resonance control
duces the maximum desired is advanced until sustained
control current. oscillations are produced. ad
Figure 6 shows a graph of vancing the resonance control
the transconductance versus further will merely increase the
control current. As can be seen, amplitude of the oscillation. A
the slope of the curve becomes lesser effect is the shift of the
more gradual as the control oscillation frequency. For
current increases. This feature minimum shift (typicady less
allows the resonance to be con- than 0.5%), the oscillation
FIGURE 4: ALL'AS$ FILTER WITH V,C. RESONAHCE
trolled with finer resolution as amplitude should be kept below
the critical point of oscillation the clipping level of the first
is approached. stage output. Allowing the with a series resistor and trim
The maximum control oscillation to be clipped will pot. The fixed resistor. RE. and
current is therefore selected in produce frequency shifts in series trim pot, RT should be
accordance with the amount of excess of 5%. selected so that the current
control sensitivity which is into pin 13 may be adjusted
desired at the top of the control Other Uses of the from SmA to 12mA. Or:
range. The value of the input Resonance Control Cell VEE - 3.2V
resistor, RRIo is then selected
depending on where in the con- Other than controlling the
trol scale oscillation is desired resonance, the variable trans-
to begin (when the control conductance amplifier may be
voltage is 90% of the maximum used as an independent VCA
value, for instance). The follow controlling the amplitude of the
ing formula may be used: input signal to the filter. Or the
cell may be set up as a sym-
metrical limiter/clipper for
RRI ::: 3.6K'" (Gmosc REO -1 either preventing large dynamic
Aosc
input signals from overloading
the filter or for providing addi-
"25% tional coloration to the input
signal.
where GmOSC is the transcon-
ductance corresponding to the Pole Frequency Control
control current at which oscilla
tion is desired to begin; and Voltage Rejection
where Aosc is the overall gain The D.C. voltage shift at the
from the resonance signal input filter output due to the fre
resistor, RRI. to the filter output quency control voltage may be
required to sustain oscillation. minimized by adjusting the
If the gain of stages 2, 3 and 4 current into the minus supply
are unity. then Aosc ::: 12dB or pin. pin 13. This is accomplished
4 in the case of the low pass by replacing the negative supply FIIiURE 5: STATE VARIABLE FILTER WITH V.C. "Q"
filter. current limiting resistor, REE.
295
and may begin to degrade the per
formance of the filter, especially
if the loads on each buffer
differ by more than this amount
The maximum recommended
These components are O.C. loads are 1mA source,
shown in the filter circuits of sink, and a 150.uA load
.J
output is already D.C. blocked
ming should be necessary. by the resonance input
However, if required, the r9S0' coupling capacitor, thus pro
nance control voltage feed viding a convenient output
through may be minimized by
...fl..""
.i.
-
,',
- lOOK
--
+
500j..(A. However, any D,C 10ild
greater than 200,uA to l::,OO,uA
Ilot short the outputs to ground
or either supply .
[EM,]10 10 l-
711 SIGNAL
OUTPUT
Ci!S
C\.RTIS ELECrROII1USK. SPECIALTIES
2900 Mauricia Ave
Santa Clara, CA 95051
14081247-8046
296
INDEX
A Analog-cont
output structure, 26
Active filter, 1l.5
signal levels, 26-27
Additive synthesis, n-17 timing signals, 23-26
Adjustahle-voltage IC regulators, Applied Synergy kit, 223
36-40 Aries kit, 222
Advanced modular system, 208-21 S Attack, 11
analog multipliers, 218
controllers, 210 B
external signal processors, 211-212
filter modules, 212-218 B + B Audio 153S, 166
Ih/s,210 Balanced modulator, 153-154
noisc sources, 210 Bandpass filter, definition, 112
sequencers, 210 Basic modular system, 205-208
Aliasing, 190 Basics of filters, 111-116
All-pass Bbd's. See Bucket brigade delay lines
filter definition, 112 Bucket brigade delay lines,
voltage controllcd filters, 132-13S discussed, IS9-191
common ef/ects using, 191-198
Analog
Building a synthesizer, 225-2:30
delay lines, IS9-UJI
making your own pc boards, 225-
multipliers, 1.53-188, 21S
230
advanced modular system, 218
test equipment required, 225
!<lllr-quadrant multipliers, IS 1-
186
multiplier IC designs, 18.5-186 c
using a single ota, 182-184 CA3080, 157-1.59
using two ota's, IS1-1S2 CA32S0, 159-164
references, 186-1S8 ceo, See Change-coupled device
twO-'l uadran t m ul tiplier vca's, CE\1331O, 61-64, 266-269
1.54-liH CEM3320, 291-296
B + B Audio 1.53S, 166 CE\13330, 174-1S1
CA3080, 157-159 CEM:3:3:30/33:3.5, 277 -2S4
CA32S0,1.59-164 CEM3.33.5, 181
CEM33.30, 174-181 CEM334013345, 103, 106, 2S.5-290
CEM3:j,j,5, 181 CEMT3.50, 114
CEM3360, 174 CE\IT360, 174
discrete vca's, 1.5.')-156 CFR Associates kit, 223
LMI3600,164-166 Charge-coupled device, 193-194
ota, 1.56-1.57 Chorus, 192
SSM201O, 172 Common eHects using bbd's, 191-198
SSM2020, IfiS-169 Compander, 191
SS \12022, 169-172 Compressor, 191
synthesizer system design, 21-27 Construction
control voltages, 2.3 aids, synthesizer, 219-2:3:3
input structure, 26 building a synthesizer, 22.5-230
linear and exponential voltage re- modlde construction, 230-233
lationships, 21-23 parts, 22,1-225
297
Construction -cont Decay, Il
aids, synthesizer Decibel, unit, 112-113
suggested reference material, Delay lines, analog, 189-191
219-220 Digisound kit, 223
synthesizer kits, 222-224 Digital t(J analog converter, 13
module, 230-233 Discrete
cabinet, 233 vca's, two-quadrant multipliers,
testing the module, 232-233 155-156
Contemporary Keyboard Magazine, vco circuits, 90-94
221 Droop rate, 47
Controllers Drop-out voltage of regulator, 29
advanced modular system, 210 Duophonic
control voltage, 43-52 feature, 19
control voltage ranging and scal- interface, control voltage control-
ing,50 lers, 48-50
duophonic interface, 48-50 Dynamics, sound, 11
keyboards, 43-45
joystick, 51 E
monophonic keyboard approach,
45-47 Electronotes, 219
pressure-sensitive, ,51 E-mu Systems kit, 224
ribbon, ,52 Engineering magazines, 220-221
Control voltage Ensemble effert, 21
analog synthesizer design, 23 Envelope
controllers, 43-52 followers, control voltage pro-
control voltage ranging and scal- cessors, 80-82
ing,50 generators, control voltage, 52-64
duophonic interface, 48-50 sound. 11
keyboards, 43-45 ETI Magazine, 220
joystick, 51 Expander, 191
monophonic keyboard approach, Exponcntial converter,
4,5-47 function, 22
pressure-sensitive, 51 veo,83-87
ribbon, 52 External signal processors, advanced
generators, 52-70 system, 211-212
envelope generators, 52-64
low-frequency oscillators, 69- 70 F
noise sources, 66-69
sequencers, 64-66 Ferric chloride, 228
processors, 70-82 Filter
envelope followers, 80-82 active, 115
sample and hold circuits, 70-74 capacitor, regulated power supply,
slew limiters, 74-75 31-32
trigger and gate extractors, 75-1)0 frequency poles of, 115
ranging and scaling, 50 modules, advanced system, 212-
references, 82 218
Converter order of, 115
exponential, vco, 83-87 passive, 115
triangle to sine wave, 96-97 Filters, 111-152
Current controlled oscillator, 87-90 basics of, 111-116
Custom vco circuits, 97-108 fixed filter circuits, 149-152
Cutoff frequency, filter, 113 graphic equalizer, 149
vocoder, 151-152
D references, 152
Dac. See Digital to analog converter voltage controlled, 116-149
298
Filters -cont J
voltage controlled Joystick, control voltage controllers,
all-pass, 132-138
.51
low-pass, 122-132
state-variable, 138-149
K
570/571, 236
Fixed Keyboards, control voltage controllers,
filter circuits, 149-152 43-45
graphic equalizer, 149 Kilohertz, defined, 10
vocoder, 151-152 Kits, synthesizer, 222-224
voltage Ie regulators, 3.5-36
Flanging, 192 L
Flat of a note, 21 Lfo. See Low-frequency oscillators
Four-quadrant multipliers, 181-186 Linear and exponential voltage rela-
Ie designs, 18.5-186 tionships, analog synthesizer de-
using a single ota, 182-184 sign, 21-23
using two ota's, 181-182 LM317 adjustable regulator, 34
Frequency LM399 voltage reference, 40
cutoff, filter, 113 LM13600, 164-166
defined, 10 Low
modulation, 16 -frequency
poles of a filter, ll5 oscillators
Fundamental, defined, 10 advanced modular system, 210
G control voltage generators,
69-70
Gate signal, 25 random voltages, 67
Generators, control voltage, .52-70 -note priority, 43
envelope generators, 52-64 -pass
low-frequency oscillators, 69-70 filter, definition, III
noise sources, 66-69 voltage controlled filters, 122-132
sequencers, 64-66
Graphic equalizer, 149 M
H Maplin Electronic Supplies, Ltd., kit,
Harmonics, defined, 10 224
Heat sinks, Ie regulators, 32-33 Mixer circuits, 198
High-pass filter, definition, lll-ll2 MN3004, 237-240
MN3101, 241-248
Modular system, 205-218
Ie advanced system, 208-218
cookbooks, 221 analog multipliers, 218
manufacturer's data books/ applica- controllers, 210
tion notes, 221-222 external signal processors, 2ll-
multiplier designs, 185-186 212
regulators, power supply, 32-40 filter modules, 212-218
adjustable-voltage, 36-40 lfo's, 210
fixed-voltage, 35-36 noise sources, 210
heat sinks, 32-33 sequencers, 210
regulator types, 33-34 basic system, 205-208
stability and protection circuitry, polyphonic system, 218
34 Modulation index, 16
Input Modulator
characteristics, regulator, 21 balanced, 153-1.54
structure, analog synthesizer design, ring, 153-154
26 timbre, 198-201
299
Module construction, 230-233 Ota. See Operational transconduc-
cabinet, 233 tance amplifier
testing the module, 232-2.3.3 Output structure, analog synthcsizer
dt'sign 26
feature, 19 p
keyboard approach, control voltage
controllers, 4.'5-47 PAIA Electronics, Inc., kit, 222
Multipliers, analog, 15:1- 188 Paramett-rs of sounc!.
four-quadrant, lill- I H6 dynamics, II
IC designs, IH5-IH6 pitch, 10-11
using a .singlc ota, IH2-1S4 timhre.11-12
using two ota's, IS1-182 Partials, defined, 10
references, IH6-1HH Parts, syntht'sizt'r construction, 224-
two-quadrant multiplier vca's, 225
154-1Hl Passi\t' filter, 11.'>
B + B Audio 1538, 166 Pink noi.,e, 67
CA30S0, 157-159 Pitch, sound, 10-11
CA32S0, 159-164 Poles, frequency, 115
CEM3330,174-181 Polyphonic
CEM3335, lSI featurE', 19
CEM3360,174 systems, 21S
discrete vca's, 155-1.56 Polyphony magazine, 220
LM13600, 164-166 Portamento, 43
ota, 156-157 Power supply circuits, 2H-41
SSM2010, 172 IC regulators, 32-40
SSM2020, adju ,tahle-\oltage, 36-40
SS\12022, 169-172 fixed-voltage, :3.5-.36
heat sinks, 32-:3:3
N regulator types, :3:3-34
stahdity and protection circuitry,
Noise sourc"s .34
advanced modular system, 210 regulated supply, 2H-32
control \ oltage gt'nenltors, 66-69 filter capacitor, 31-32
Nonlinear synthesis, 16-17 rectifier, 30-31
regulator input characteristics, 29
o transformer, 29-30
Octaves, 21 suggestions, 40-41
Operational transconductance am- Powertran kit, 223
plifier Pressure-sensitive
analog four-quadrant multipliers, controllers, control voltage, 51
IS1-1S4 keyboards, 45
using a single ota, IS2-1H4 Printed circuit boards, making, 225-
lIsing two ota's, lS1-182 230
description, S9 Processors, control voltage, 70-S2
two-quadrant multiplier vca's, envelope f()lIowers, HO-82
156-157 sample and hold circuits, 70-74
Order of a filter, I 1.'5 slew limiters, 74-7.'>
Oscillators, voltage controlled, 83-110 trigger and gate extractors, 75-S0
current controlled oscillator, S7-90 Pseudo-random sequence generator,
custom vco circuits, 97 -lOS 67
discrt'te n'o circuits, 90-94
exponential converter, H.3-87
references, lOH-110 Real time, 16
waveshaping circuits, additional, Rectifier, regulated power supply,
95-97 30-31
300
Reference material, synthesizer con- SSM2044, 126-130
struction, 219-220 SSM20,SO, 57-59
Hegulated power supply, 28-32 SSM20,S,S, 59-61
filter capacitor, 31-32 SSM20,S6, 274-276
rectifier, 30-31 Stability and protection circuitry, Ie
regulator input characteristics, 29 regulators, .14
transformer, 29-:30 State-variahle \' oltage controlled
Regulators, power supply Ie, :32-40 filters, 138-149
adjustable-voltage, 3G-1O String synthesizer, 20
fixed-voltage, :3,S-3G Subtractive synthesis, 17-21
heat sinks, :32-33 Suggested referencc material, syn-
regulator types, :3:3-34 thesizer construction. 219-220
stability and protection circllitry, Suggestions on power supply circuits,
34 40-41
Regulator typcs, Ie, 33-34 Sustain, 11
Resonance, added to filter, 114- 115 Synthesis techniques, 12-21
Resonant filter banks, 115 additive, 13-17
Ribbon controller, control voltage, 52 Ilonlinear, 16-17
Ring modulator, 153-154 suhtractive, 17-21
Rollofl: definition, 112 Svnthesizer
Root-mean-square voltages, 29 . constrllction aids, 219-233
RMS voltages. See Root-mean-square building a synthesizer, 22,5-230
voltages making your own pc boards,
225-230
test e(plipment required, 225
5 module construction, 230-233
SAD-,SI2, 2.SH cabinet, 2.3.'3
SAD-,SI2D, 249-2.S2 testing the module, 2:32-233
SAD-1024, 253-2,'5H parts, 224-225
SAD-4096, 259-2G,S suggested reference material,
Sample and hold circuits, control volt- 219-220
age processors, 70-74 Contemporary KeyiJoard Maga-
Sawtooth oscillator, 87 -HH zinc, 221
Schmitt trigger, 77-78 ElectrorlOtes, 219
Sequencers engineering magazines, 220-
advanced modular system, 210 221
control voltage generators, 64-66 ETI Magazine, 220
Serge Modular Music Systems, kit, Ie cookbooks, 221
223 Ie manufacturer's data books/
723 voltage regulator, 36-37 application notes, 221-222
Sharp of a note, 21 Polyphony, 220
Signal levels, analog synthesizcr dc- synthesizer kits, 222-224
sign, 26-27 Applied Synergy, 223
Slew limiters, control voltagc pro- Aries, 222
cessors, 74-7,S CFR Associates, 223
Sound, parameters of, 9- 12 Digisound, Ltd., 22:3
dynamics, 11 E-mu Systems, 221
pitch, 10- 11 Maplin Electronic Supplies,
timbre, 11-12 Ltd., 224
SSM2010, 172 PAIA Electronics, Inl'., 222
SSM2020, 1G8-169 Powertran, 22,3
SSM2022, 169-172 Serge tvlodlllar Music Systems,
SSM2030, 98- 103 22:3
106-107,270-273 system design, 9-27
SSM2040, 125-126, 135, 136, HI analog, 21-27
301
Synthesizer-cont u
system design Universal active filter, See State-
control voltages, 23 variable filters
input structure, 26
linear and exponential voltage
relationships, 21-2,3 v
output structure, 26 Vcf. See Voltage controlled filters
signal levels, 26-27 Vco. See Voltage controlled oscillator
timing signals, 23-26 Velocity-sensitive keyboards, 44-45
parameters of sound, 9-12 Vocoder, 151-152
dynamics, 11 Voltage controlled
pitch, 10-11 amplifiers
timbre, 11-12 two-quadrant multiplier, 154-181
synthesis techniques, 12-21 B+ B Audio 1538, 166
additive synthesis, 13-17 CA3080, 157-159
nonlinear synthesis, 16-17 CA3280, 159-164
subtractive synthesis, 17-21 CEM3330,174-181
CEM3335, 181
T CEM3360, 174
Timbre discrete vca's, 155-156
modulators, 198-201 LM 1,3600, 164-166
sound, 11-12 ota, 156-157
Time constant formula, 53 SSM201O, 172
Timing signals, analog synthesizer SSM2020, 168-169
design, 23-26 SSM2022,169-172
Tonal character. See Timbre attenuator. See Voltage controlled
Top-octave generator, 20 amplifiers
Transformer, regulated power supply, filters, 116-149
29-30 all-pass, 132-138
Triangle oscillator, 88-89 lows-pass, 122-132
Trigger state-variable, 138-149
and gate extractors, control voltage oscillators, 83-110
processors, 75-80 current controlled oscillator,
signal,25 87-90
Two-quadrant multiplier vca's, 154- custom vco circuits, 97-108
181 discrete vco circuits, 90-94
B + B Audio 1538, 166 exponential converter, 83-87
CA3080, 157-159 references, 108-110
CA3280, 159-164 waveshaping circuits, additional,
CEM3330,174-181 95-97
CEM3335, 181
CEM3360, 174 w
discrete vca's, 155-156 Waveshaping circuits, vco, 95-97
LM13600, 164-166 White noise, 66-67
ota, 156-157
SSM201O, 172
SSM2020, 168-169 x
SSM2022, 169-172 XR-2228, 235
302
To better serve you, the reader, please take a moment to fill out
this card, or a copy of it, for us. Not only will you be kept up to date
on the Blacksburg Series books, but as an extra bonus, we will
randomly select five cards every month, from all ofthe cards sent to
us during the previous month. The names that are drawn will win,
absolutely free, a book from the Blacksburg Continuing Education
Series. Therefore, make sure to indicate your choice in the space
provided be10w. For a complete listing of all the books to choose
from, refer to the inside front cover of this book. Please, one card
per person. Give everyone a chance.
In order to find out who has won a book in your area, call (703)
953-1861 anytime during the night or weekend. When you do call,
an answering machine will let you know the monthly winners. Too
good to be true? Just give us a call. Good luck.
It has been aur objective, as The Blacksburg Group, to develop timely and effective educational
materials that will permit students, engineers, scientists, technicians and others to quickly learn
how to use new technologies and electronic techniques. We continue to do this through several
means, textbooks, short courses, seminars and through the development of special electronic d.
vices and training aids.
Our group members make their home in Blacksburg, found in the Appalachian. Mountains of
southwestern Virginia. While we didn't adively start our group collaboration until the Spring
of 1974, members of our group have been involved in digital electronics, minicomputers and
microcomputers for some time.
Same af our past experiences and on"9oing efforts Include the fallowing.
-The design and development of what is considered to be the first popular hobbyist computer.
The MarkB was featured in RadioElectronics magazine in 1974. We have also designed several
SOSO-based 'computers, including the MMD1 system. Our most recent computer is an SOasbased
computer for educational use, and for use in small controllers.
-The Blacksburg Continuing Education SeriesTII covers subjeds ranging from basic eledranics
through microcomputers, operational amplifiers, and active Test experiments and examples
have been provided in each book. We are strong believers in the use of detailed experiments and
examples to reinforce basic concepts. This series originally started as our Bugbook series and many
titles are now being translated into Chinese, Japanese, German and Italian.
-We have pioneered the use of small, self-contained computers in hands-on courses far micro-
computer users. Many of our designs have evolved into commercial produds that are marketed
by E&L Instruments and PACCOM, and are available from Group Technology, Ltd., Check, VA
24072.
-Our short courses and seminar programs have been presented throughout the world. Programs
are offered by The Blacksburg Greup, and by the Virginia Polytechnic Institute Extension Divi
sian. Each series of courses provides hands-on experience with real computers and electronic
devices. Courses and seminars are provided on a regular basis, and are also provided for groups,
companies a nd schools at a site of their choosing. We are strong believers in pradical labora-
tory exercises, so much time is spent working with electronic equipment, computers and circuits.
Additional information may be obtained from Dr. Chris Titus, the Blacksburg Group, Inc. (703)
9519030 or from Dr. Linda Leffel, Virginia Tech Continuing Education Center (703) 9615241.
Our group members are Mr. David G. Larsen, who is on the faculty of the Department of Chem-
istry at Virginia Tech, and Drs. Jon Titus and Chris Titus who work full.time with The Blocksburg
Group, all of Blocksburg, VA.
A profusely illustrated, up to date, broad coverage of
electronic music circuits
ELECTRONIC
MUSIC CIRCUITS
Is the most comprehensive book available dealing with
analog circuitry for music synthesizers.
Discusses design of synthesizer elements so that the
reader can begin to design his or her own system.
Details the custom ICs used in the majority of synthesizers.
Describes construction methods.
Gives secrets of many special-effect devices used by
musicians.
Is written for studio engineers, musicians, computer and
electronic music hobbyists.
Contains a minimum of mathematics.