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30/01/2017 ExamenVHDL1eresession2008Dr.

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ExamenVHDL1eresession2008
Exercice1:(10points)

Il sagit de dvelopper un modle structurel dun registre N bits avec une entre srie et une
sortieparalllebassurlescomposantsdesbasculesD.

Lentres:HorlogeCLK(1bit),resetRST_Bremisezro(1bit)asynchroneactifauniveau
bas (0), donnes srie DIN (1 bit) et les Sorties: Contenu du registre DOUT (N bits). N un
paramtregnrique.FaireunedescriptionstructurelleenlangageVHDL(entityetarchitecture)
dunregistreRegistresrieparallle16bits(voirshmacidessus).Lusageduneinstruction
generateestrequise.


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Exercice2:(5points)


S'abonner
Onconsidreleprogrammecidessous(critenVHDL): Abonnezvouspourtreavertidesnouveaux
articlespublis.
Libraryieee
useieee.std_logic_1164.all exemple@adresse.com S'abonner

entitytransitmisport(clk,e:inbit
Pages
s:outbit)
endtransitm
AlbumCNR'IUT

architecturequasi_structoftransitmis
Albumphoto
signalqa,qb:bit
ApplicationMobileAndrodepourunesystme
d'automatisationdomestique

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30/01/2017 ExamenVHDL1eresession2008Dr.MohamadAlwan
begin
CompteurdElectricitNumriqueDomicile
schem:process(clk)
begin
Contributionltudedelimpactdes
If(clk'eventandclk='1')then
dgradationsdorigineslectriqueset
qa<=e
thermiquessurlesperformancesdutransistor
qb<=qa VDMOSdePuissance
endif
endprocessschem Coursetdocumentation
s<=qaxorqb
endquasi_struct DynamicsCharacteristicsVDMOSSimulation
(ATLAS)
1.Dduiredeceprogramme,paruneconstructionmthodique,unschma(bascules
ExamenVHDL1eresession2008
etporteslogiques).
1.Complterlechronogrammecidessous. ExamenVHDL1eresession2009

ExamenVHDL1eresession2010

ExamenVHDL2emesession2008

ExamenVHDL2emesession2009

Exercice1VHDL

Exercice2VHDL

Exercice3:(5points) Exercice3VHDL

Exercice4VHDL

Lesystmeconcevoirdisposededeuxentresetdedeuxsorties.Lesentressontlhorlogeclk Exercice5VHDL
etlacommandeClessortiessontS1etS2.Lesentresetlessortiessontdetypestd_logicsauf
Cestdetypebit.Lesystmeestactifsurfrontdescendant.Lesystmerpondauchronogramme Exercice6VHDL
suivant:
Exercice7VHDL

Exercice8VHDL

HomeAutomationControlsystemThrough
TheMobileInternet

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DonnerladescriptionenlangageVHDL(EntityetArchitecture)decesystmeenutilisantun SimulationVDMOS(BreakdownVoltage)
process.Dansleprocess,utiliserlinstructioncase.iswhen,etlinstructionif..then. TensiondeClaquage
else.
StaticcharacteristicsVDMOSsimulation
(ATLAS)

StaticcharacteristicsVDMOSsimulation
(ATLAS)

Correction VDMOSSTRUCTURE(SLIVACO)ATLAS
Exercice1:

VehicletrackerMobileApplication
Libraryieee
useieee.std_logic_1164.all
Catgories
EntityD_RAZisport
(D,clk,CLR:instd_logic Article 5
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30/01/2017 ExamenVHDL1eresession2008Dr.MohamadAlwan
Q:outstd_logic)
EndD_RAZ Confrance 5

Architecturearch_D_RAZofD_RAZis LEMI 2
Begin
process(clk,CLR) Blueball 1

Begin Bluetooth 1

IF(CLR='0')thenQ<='0'
CURRICULUMVITAE 1
ELSIF(clk'eventandclk='1')thenQ<=D
ENDIF
ImageProcessing 1
ENDprocess
ENDarch_D_RAZ
Labview 1
Libraryieee
useieee.std_logic_1164.all Movingontruck 1

entityregistreisport Redball 1
(DIN,clk,REST_B:instd_logic
DOUT:outstd_logic_vector(15downto0)) Robot 1
Endregistre
visionmotion 1
architecturearch_registreofregistreis
componentD_RAZport(D,clk,CLR:instd_logic
Q:outstd_logic) Archives
endcomponent
2016
signalS:std_logic_vector(15downto0)
2015
constantNb_bits:integer:=15
2012
begin
cellule:foriinNb_bitsdownto0generate 2010

cellule_16:ifi=Nb_bitsgenerate 2009
D_RAZN_1:D_RAZportmap(DIN,clk,REST_B,S(15))
DOUT(i)<=S(i) 2007
endgeneratecellule_16
2006
cellule_int:if(i<Nb_bitsandi>0)generate

D_RAZint:D_RAZportmap(S(i+1),clk,REST_B,S(i))
DOUT(i)<=S(i)
endgeneratecellule_int

cellule_0:if(i=0)generate

D_RAZ0:D_RAZportmap(S(i+1),clk,REST_B,S(i))
DOUT(0)<=S(0)
endgeneratecellule_0

endgeneratecellule

endarch_registre

Exercice2:

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Exercice3:

Libraryieee
useieee.std_logic_1164.all

entityseqisport(clk:instd_logic
C:inbitS1,S2:outstd_logic)
endseq

architecturearch_seqofseqis
signalEtat:std_logic_vector(2downto0)
begin
process(C,clk)

begin

if(clk'eventandclk='0')then

caseEtatis
when"000"=>S1<='0'S2<='0'
ifC='1'thenEtat<="001"
elseEtat<="000"
endif

when"001"=>S1<='1'S2<='0'

ifC='0'thenEtat<="010"
elseEtat<="001"
endif

when"010"=>S1<='1'S2<='1'
ifC='0'thenEtat<="011"
elseEtat<="001"
endif

when"011"=>S1<='0'S2<='1'
ifC='0'thenEtat<="100"
elseEtat<="001"
endif

when"100"=>S1<='0'S2<='0'
ifC='0'thenEtat<="000"
endif


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30/01/2017 ExamenVHDL1eresession2008Dr.MohamadAlwan
Whenothers=>Etat<="000"
endcase
endif
endprocess
endarch_seq

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