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Les Mmoires en vhdl

Cr 13
Mai 2017
TYPES utiles
Integer types:
type integer is range -2147483648 to +2147483647;
type short is range -128 to 127;

Subtypes:
subtype natural is integer range 0 to integer'high;

Enumeration:
type std_logic is ('U','X','0','1','Z','W','L','H','-');
type bit is ('0','1')
type boolean is (false, true);

Array:
type memory is array (0 to 2**bitsAddr -1) of std_logic_vector (WL -1
downto 0);
Mmoires
Les Mmoires : utilises pour le stockage.
Il s'agit d'un tableau (array) d'emplacements
2^n, dont chacun on stocke des mots de m
bits.
Chacun des emplacements a une adresse de
0 2^n -1.
Par consquent, l'adresse de la mmoire est
reprsent par n bits..
On peut lire dun / crire un emplacement
de mmoire en slectionnant son adresse.
Types de Mmoires
Mmoire interne (nous pouvons les crer dans le FPGA):
RAM: Random Access Memory (on peut lire et crire).
ROM: Read Only Memory (valeurs fixes que nous ne pouvons
pas les modifier).
Mmoire externe (en dehors de la FPGA):
RAM et ROM: Ils peuvent tre externes ainsi.
SRAM: Static RAM (= statiques n'a pas besoin de
rafrachissement).
SDRAM: Synchronous Dynamic RAM (= dynamiques besoins
de rafrachissement).
DDR SDRAM: Double Data Rate SDRAM
FLASH (non volatile = le contenu n'est pas effac hors
tension).
Carte DE2 contient 8 MB SDRAM, 512 kB SRAM et 4 MB
FLASH.
ROM enVHDL
Exemple dune ROM de 8 addresses et 4 bits de donnes:
...
type ROM_mem is array (0 to 7) of std_logic_vector (3 downto 0);
constant Contenu_ROM: ROM_mem := (0 => "0001",
1 => "0101",
2 => "0000",
3 => "0111",
4 => "0001",
5 to 7 => "1111");
signal Addr: std_logic_vector (2 downto 0);

begin
z <= Contenu_ROM(to_integer(unsigned(Addr)));
...
RAM enVHDL
type RAM_mem is array (0 to 2**bitsAddr -1) of std_logic_vector (WL -1 downto 0);
signal contenu_RAM: RAM_mem;
signal Addr: std_logic_vector (bitsAddr -1 downto 0);

begin
process (clk)
begin
if rising_edge (clk) then
If we = '1' then -- Write enable signal
contenu_RAM(to_integer(unsigned(Addr))) <= data_in;
end if;
end if;
end process;

data_out <= contenu_RAM(to_integer(unsigned(Addr)));


RAM DUAL-PORT
Dual-Port: mmoire dans laquelle il est
possible d'crire sur un emplacement de
mmoire et lire un autre.
De toute vidence, il utilise plus de ressources.

WADDR: Adresse decriture;


RADDR: adresse de lecture
process (clk)
begin
if rising_edge (clk) then
if we = '1' then
RAM_content (to_integer(unsigned(wAddr))) <=
data_in;
end if;
data_out_reg <= data_out; -- if we want to register
the output
end if;
end process;
data_out <= RAM_content
(to_integer(unsigned(rAddr)));
Mmoire ROM
Le code VHDL

ENTITY memory1 IS
PORT (address: IN INTEGER RANGE 0 TO 9;
data: OUT BIT_VECTOR(6 DOWNTO 0));
END memory1;
ARCHITECTURE compo OF memory1 IS
TYPE memory IS ARRAY (0 TO 9) OF BIT_VECTOR(6 DOWNTO 0);
CONSTANT rom: memory := (
"1111110",
"0110000",
"1101101",
"1111001",
"0110011",
"1011011",
"1011111",
"1110000",
"1111111",
"1111011");
BEGIN
data <= rom(address);
END compo;
Synchronous RAM with separate data I/O
buses
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------------------------
ENTITY memory2 IS
GENERIC (N: INTEGER := 8; --Width of data bus
M: INTEGER := 4); --Width of address bus
PORT (clk, write: IN STD_LOGIC;
address: IN INTEGER RANGE 0 TO 2**M-1;
data_in: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END memory2;
ARCHITECTURE memory2 OF memory2 IS
TYPE memory IS ARRAY (0 TO 2**M-1) OF STD_LOGIC_VECTOR(N-1 DOWNTO
0);
SIGNAL ram: memory;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (write = '1') THEN ram(address) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= ram(address);
END memory2;
Chronogramme de lecture et criture

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