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Hardware Architecture, pinouts Functional Building Blocks of Processor

Memory organization I/O ports and data transfer concepts Timing
Diagram Interrupts.

8085 Processor:

The 8085 has been one of the popular microprocessor of its time. Due to its unique
characteristics, this processor is still regarded as a standard by both industries and
academics for imparting skills sets on microprocessor basics.

Comparison with the predecessor 8080:

1. The 8085 removed certain architectural disadvantages of 8085.
2. The 8085 also provided some additional features over and above the 8080.
3. The 8085 operates from a single +5V power supply, it uses a single clock signal
of 320ns pulse width.
4. The 8085 has on-chip I/O serial compatibility as well as an interrupt request
pins for hardware generated vector interrupts, which are not present in 8080.

8085 Introduction:
The salient features of 8085 p are:
a. It is a 8 bit microprocessor.
b. It is manufactured with N-MOS technology.
c. It has 16-bit address bus and hence can address up to 216 = 65536 bytes
(64KB) memory
d. Data bus is a group of 8 lines, D0 D7.
e. Address bus is a group of 16 lines, A0-A15.
f. The first 8 lines of address bus and 8 lines of data bus are multiplexed and
forming as AD0 AD7.
g. It has five hardware interrupts and eight software interrupts.
h. It supports serial communication
i. It has Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
j. It has four special purpose register naming as an 8-bit Accumulator, a 8-bit
Flag register, a 16 bit stack pointer (SP) and a 16 bit program counter (PC)
k. It requires a signal +5V power supply and operates at 3.2 MHZ single phase
l. It is enclosed with 40 pins DIP (Dual in line package).


8085 consists of various units and each unit performs its own functions. The
various units of a microprocessor are listed below

Arithmetic and logic Unit

General purpose register
Temporary register
Program counter
Stack pointer
Instruction register and Decoder
Timing and Control unit
Interrupt control
Serial Input/output control
Address buffer and Address-Data buffer
Address bus and Data bus

Arithmetic and logic Unit (ALU)

The ALU performs the arithmetic and logical operations. The operations
performed by ALU of 8085 are addition, subtraction, increment, decrement,
logical AND, OR, EXCLUSIVE -OR, compare, complement and left / right

General Purpose Registers:

It is a 8 bit general purpose register.
It is connected to ALU (Arithmetic Logic Unit)
So most of the operations are done in accumulator
Programmable Registers:
The general purpose registers are used to store the temporary information during
the execution of a program.

Fig. 8085 Hardware Architecture

There are six other general purpose registers in 8085 namely B, C, D, E, H and L.
these are used for various data manipulators. Each is 8-bit registers.
A pair of register together can be used as a register pair to hold 16-bit. There are
BC, DE and HL register pair.

Temporary Register: (W, Z)

It is not available for user
All the arithmetic and logical operations are done in the temporary register
but user cant access it.

Special Purpose Registers:

There are two special purpose register in 8085. They are
SP-Stack Pointer -16 bit
PC-Program Counter 16 bit
Flag register 8 bit

Program Counter:
It is a 16 bit register used to point the location from which the next instruction is to
be fetched
When a single byte instruction is executed PC is automatically incremented
by 1.
Upon reset PC contents are set to 0000H and next instruct is fetched

Stack Pointer:
This is a temporary storage memory 16 bit register. Since there are only 6 general
purpose registers, there is a need to reuse them.
The 8085 maintains stack in memory
Whenever stack is to be used previous values are pushed on stack and then
after the program is over these values are popped back.

Flag register:
It is a group of 5 flip-flops used to know status of various operations done
The flag register along with the accumulator is called PSW

PSW- Program Status Word

Flag register is given by:

7 0
S : Sign flag is set when result of an operation is negative.
Z : Zero flag is set when result of an operation is zero.
AC: Auxiliary Carry flag is set when there is a carryout of lower nibble or lower four
bits of operation.
CY: Carry flag is set when there is a carry generated by an operation.
P : Parity flag is set when result contains even number of 1s rest are done care

Instruction Register:
When an instruction is fetched, it is executed in instruction register. This register
takes the op-code value only

Instruction Decoder:
It decodes the instruction from instruction register and then to control block.

Timing and Control:

It accepts clock input from external crystal source.
This is the control section of microprocessors.
It produces required control signals for all the operations with suitable timing.

Interrupt Control:
There are five interrupt request pins through which the 8085 may be interrupted.
These are 1) TRAP, 2) RST 5.5, 3) RST 6.5, 4) RST 7.5 and 5) INTR.

Serial I/O Control:

This section is used for Serial data communication.
The Microprocessor can send data to external devices using SOD (Serial Output
Data) pin.
The Microprocessor can receive data from external devices using SID (Serial Input
Data) pin.

The serial communication can be performed by using SIM and RIM instructions.

SIM - Set Interrupt Mask

RIM - Read Interrupt Mask
Address buffer and Address-Data buffer
The contents of the stack pointer and program counter are loaded into the address
buffer and address-data buffer. These buffers are then used to drive the external
address bus and address-data bus. As the memory and I/O chips are connected to
these buses, the CPU can exchange desired data to the memory and I/O chips.
Address bus and Data bus:
The 8085 has 16 address lines and 8 data lines.
The data lines (D0 to D7) are multiplexed with lower address lines (A0 to
Thus AD0 to AD7 and A8 to A15 form the 16 unidirectional address lines and
AD0 to AD7 forms 8 bidirectional data lines.
These are tri-state lines ie., they can go to the high impedance state when
The lower order 8 lines (AD0 to AD7) contain the address and data
information, both at different times.
The 8085 outputs an Address Latch Enable (ALE) signal which indicates
the presence of address on AD0 - AD7. The ALE is used to hold the address
present on lower order AD0 - AD7 into the Address Latch.

The 8085 clock:

An external crystal or R.C network
can be connected between X1 and X2
pins of 8085 in order to drive the
internal clock logic. The input
frequency (6MHz) of the clock should
be twice the operating frequency
(3MHz). Fig. 8085 Clock
Direct Memory Access (DMA):
The DMA controller is incorporated into the 8085 for accessing large amount of
data from memory by the IO devices.

Two signals are associated with Direct Memory Access naming as HOLD and

The HOLD is produced by the DMA controller for requesting the busses from the
Processor control.

It indicates that another master is requesting for the use of address and data buses
and control busses.

Then the HLDA is produced by the Processor to the DMA controller as the
acknowledgement of receiving the HOLD signal.

Now the CPU completes the current machine cycle and then relinquishes the use of
buses to the DMA controller.

The processor can regain the buses only after the HOLD is removed. i.e., after the
completion of data transmission between Memory and the IO device.

The 8085 Reset:

Two signals are associated with the reset logic input signals, when goes low, resets
the processor.

The PC (program counter) is set to zero, and interrupt enable and HLDA flip-flops
are reset. The program execution starts at zero location. The input signal need not
be synchronized with the clock.

The CPU outputs the RESETOUT signal which is synchronized with the clock. It
may be used to reset the other associated circuits.
THE 8085 PINOUT and Signals:

The 8085 microprocessor is available on a 40 pin Dual-in-line package (DIP). The

pin configuration is shown in the diagram below.

Some important pins are,

of Description Type
Multiplexed Low order Address and Data lines;
AD0 Lower 8 bits of the memory address or I/O address
8 Bidirection
appear on the bus during first T state of the
AD7 al Tristate
machine cycle. It then becomes the data bus during
the 2nd and 3rd T states.
High order Address lines; These lines are used to
A8 A15 8 Output,
address the most significant 8-bitsofmemory address
or the 8-bits of the I/O address.
Address Latch Enable goes high when operation is
ALE 1 started by processor. It occurs during the first T Output,
state of a machine cycle and enables the address to Tristate
get latched into the on-chip latch.
RD 1 Read is active low input signal used to read data Output,
from I/O device or memory Tristate
WR 1 Write is active low output signal used to write data Output,
on I/O device or memory Tristate
Input/Output or Memory Indicator signal used to
IO/M 1 Output,
indicate whether 8085 is working i I/O mode (I/O
=1) or memory mode (I/O =0).
Bus State Indicator used to indicate type of operation

S0, S1 2 Output

Wait State request; This signal is used to check the

READY 1 status of output device. If it is low, microprocessor Input
will wait until it is high.
Serial Input Data pin is used to accept serial 1 bit
SID 1 data. The data on this line is loaded into accumulator Input
bit 7 whenever a RIM instruction is executed.
SOD 1 Serial Output Data pin is used to send serial 1 bit Output
data. The output SOD is set or reset as specified by
the SIM instruction.
HOLD 1 HOLD request is produced by the DMA controller Input
for requesting the busses from the Processor control.
HOLD Acknowledge is produced by the Processor
HLDA 1 to the DMA controller as the acknowledgement of Output
receiving the HOLD signal.
Interrupt request is used as a general purpose
interrupt. If it is active, Program Counter will be
INTR 1 quiet from incrementing and an INTA (low) will be Input
issued. A RESTART or CALL instruction can be
inserted to jump the ISR. It is enabled and disabled
by software. Lowest priority interrupt.
Trap interrupt is a Non-maskable Restart interrupt.
TRAP 1 It has the highest priority of any interrupt. It is Input
unaffected by any mask or interrupt Enable.
RST 5.5 1 Hardware vectored interrupt request; Input
RST 6.5 1 These interrupts have a higher priority than INTR Input
and they may be individually masked out using the
RST 7.5 1 SIM instruction. Input
INTA 1 of (and has the same timing as) RD during the Output
instruction cycle after an INTR is accepted.
System reset; Reset sets the Program Counter to
zero and resets the Interrupt Enable and HLDA flip-
RESET 1 Input
flops. None of the other flags or registers (except the
instruction register) are affected The CPU is held in
the reset condition as long as Reset is applied.
RESET 1 Peripherals reset; Indicates CPU is being reset. The Output
OUT signal is synchronized to the processor clock.
These are clock signals and are connected to
X1 , X 2 2 external LC or RC circuits. These are divide by two Input
so if 6 MHZ is connected to X1, X2 the operating
frequency becomes 3 MHZ
Clock Signal is used as System clock also used to
CLK 1 synchronize all the devices which are connected with Output
(OUT) the processor. The period of CLK is twice the X1, X2
input period.
Vcc , Vss 2 Power supply Vcc = +5 volts, Vss = -GND reference
The 8085A is a complete 8 bit parallel central processor.
It requires a single +5 volt supply.
Its basic clock speed is 3 MHz thus improving on the present 8080's
performance with higher system speed. Also it is designed to fit into a
minimum system of three IC's: The CPU, a RAM/ IO, and a ROM or
PROM/IO chip.

The 8085A uses a multiplexed Data Bus. The address is split between the
higher 8bit Address Bus and the lower 8bit Address/Data Bus.
During the first cycle the address is sent out. The lower 8bits are latched into
the peripherals by the Address Latch Enable (ALE). During the rest of the
machine cycle the Data Bus is used for memory or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control.
An Interrupt Acknowledge signal (INTA) is also provided.
Hold, Ready, and all Interrupts are synchronized.
The 8085A also provides serial input data (SID) and serial output data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts
and one non-maskable trap interrupt. The 8085A provides RD, WR and
IO/M signals for Bus control.

Status Information
Status information is directly available from the 8085A. ALE serves as a status
strobe. The status is partially encoded, and provides the user with advanced timing
of the type of bus transfer being done. IO/M cycle status signal is provided directly
also. Decoded So, S1 Carries the following status information:

S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of
address are multiplexed with the data instead of status. The ALE line is used as a
strobe to enter the lower half of the address into the memory or peripheral address
latch. This also frees extra pins for expanded interrupt capability.

Interrupt and Serial l/O

The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and
INTR is identical in function to the 8080 INT.
Each of the three RESTART inputs, 5.5, 6.5. 7.5, has a programmable mask.
TRAP is also a RESTART interrupt except it is nonmaskable.
The three RESTART interrupts cause the internal execution of RST (saving
the program counter in the stack and branching to the RESTART address) if
the interrupts
are enabled and if the interrupt mask is not set.
The non-maskable TRAP causes the internal execution of a RST
independent of the state of the interrupt enable or masks.
The interrupts are arranged in a fixed priority that determines which
interrupt is to be recognized if more than one is pending as follows: TRAP
highest priority, RST 7.5, RST 6.5, RST 5.5, INTR lowest priority.

This priority scheme does not take into account the priority of a routine that was
started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the
interrupts were re-enabled before the end of the RST 7.5 routine.

The TRAP interrupt is useful for infected errors such as power failure or bus error.
The TRAP input is recognized just as any other interrupt but has the highest
priority. It is not affected by any flag or mask. The TRAP input is both edge and
level sensitive.

Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the
lower 8bits of address on the Data Bus. The figure shows an instruction fetch,
memory read and l/ O write cycle (OUT).

Note that during the I/O write and read cycle that the I/O port address is copied on
both the upper and lower half of the address. As in the 8080, the READY line is
used to extend the read and write pulse lengths so that the 8085A can be used with
slow memory. Hold causes the CPU to hand over the bus when it is through with it
by floating the Address and Data Buses.

System Interface
8085A family includes memory components, which are directly compatible to the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156,
and 8355 will have the following features:
2K Bytes ROM
256 Bytes RAM
1 Timer/Counter
4 8bit I/O Ports
1 6bit I/O Port
4 Interrupt Levels
Serial In/Serial out Ports

In addition to standard l/O, the memory mapped I/O offers an efficient l/O
addressing technique. With this technique, an area of memory address space is
assigned for l/O address, thereby, using the memory address for I/O manipulation.
The 8085A CPU can also interface with the standard memory that does not have
the multiplexed address/data bus.

Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch
and call instructions use 16-bit addresses, i.e. they can be used to jump/branch
anywhere within 64 KB. All jump/branch instructions use absolute addressing.
Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
Stack memory is limited only by the size of memory. Stack grows downward.
First 64 bytes in a zero memory page should be reserved for vectors used by
RST instructions.

Memory Interfacing:
The main step in the design of microprocessor system is to interface the
microprocessor with memory.

The following logically clear points need to be kept in mind to interface 8085
microprocessor with memory.

Since 8085 has 16 address lines upto 64 KB memory space may be

interfaced. A number of memory chips both RAM and ROM can be
connected within this space.
The 8085 will have to issue read and write control signals to memory to
carryout these operations
Since the lower order address lines AD0 to AD7 are used for data as well in
time multiplexed function there is the necessity to have a signal that informs
us as to whether these address lines contains data or address
Since a number of memory chips can be connected and the use of memory
space can be planned based on application, there would be the necessity of
generating a chip select signal for the memory chip where the Read/Write
operation is to be performed. This is done by decoding the address bits and
determining the chip where the specified memory address is located.

Fig. Memory Chip

Fig. 8085 Memory Interfacing Signals

Address Bus of 8085:

Address Bus - Used to address memory and I/O devices
8085 has a 16 bit address bus

Higher Order Address A15 to A8

Lower Order Address AD7 to AD0 (Data bus)
Data Bus used to transfer instructions and data
8085 has a 8 bit data bus

Higher Order Address Bus:

It is unidirectional bus
It carries most significant 8 bits of a 16 bit address of memory or i/o device
Address remains on lines as long operation is not completed

Lower Order Address/ Data Bus:

This bus is bidirectional and works on time division multiplexing between
address and data
During first clock cycle it serves as a least significant 8 bits of memory i/o
For second and third clock cycles it act as data bus and carries data.

Fig. Memory Interfacing of 8085

De-multiplexing Address/ Data Lines:

8085 identifies a memory location with its 16 address lines (AD 0 to AD7) &
(A8 to A15)
8085 performs data transfer using its data lines AD0 to AD7
Lower order data bus and address bus are multiplexed on same lines ie., AD 0
to AD7
De-multiplexing refers to separating address & data signals for read/write
Memory Interface:
The memory us made up of semiconductor material used to store the programs and
data. The types of memory is
Primary or main memory
Secondary memory
Primary Memories : RAM, ROM
Secondary Memories : floppy, Hard disc, CD-ROM, Magnetic tape

Interface with multiple chip:

In case of multiple chips decoder circuits like 3 to 8 decoder circuit 74LS138 are
used to produce chip solid signal. These circuits are called address decoders.

Fig. Interfacing with multiple chips

Decoder Chip 74LS138:

The decoder is selected when G1: (. )=1. When selected the input signals at A, B, C
get translated to Y0 to Y7 in the following manner.
Consider that a 2 KB chip 2716/6116 is to be interfaced to the microprocessor for
address starting from 0000 to 07FFH. In this case A15, A14, A13, A12 and A11
are all equal to 0. Thus 2716/6116 can be interfaced to 8085 in the following

An interface is a concept that interfaces refers to a print of interaction between

components and is applicable at a level of both hardware and software. This allows
a component to function independently while using interfaces to communicate with
other components us an input/output system and an associated protocol.

Interfacing I/O devices:
Using I/O devices data can be transferred between microprocessor and the
outside world
This can be done in groups of 8 bits using the entire data bus. This is called
parallel I/O
The other method is serial I/O where one bit is transferred at a time using the
SID and SOD pins on the microprocessor

Types of parallel interface:

There are two ways to interface 8085 with I/O devices in parallel data
transfer mode
Memory mapped IO
IO mapped IO

Memory mapped IO:

It considers them like any other memory location.
They are assigned a 16 bit address within the address range of the 8085.
The exchange of data with these devices follows the transfer of data with
memory. The user uses the same instructions used for memory.

Fig. Memory Mapped I/O

When a read memory instruction is executed there is no memory signal to indicate

that the address bus contains the memory location address in this. If this memory
location address is same as that of a port number of an I/O device an I/O device
will also get select together with the memory read operation being performed. Thus
there will be confusion between memory location and I/O device. If we sacrifice
some memory locations for the sake of I/O devices, this problem would not arise.
It means that the I/O address and memory addresses wil not be the same.

Since an I/O device is treated as memory location this interface is called memory
mapped I/O.

I/O mapped I/O interface:

It treats them separately from memory.
I/O devices are assigned a port number within the 8 bit address range of
00H to FFH.
The user in this case would access the devices using the IN and OUT
instructions only.

The I/O devices are identified by port number and memory locations are
identified by address. The memory read/write operations and I/O read/write
operations are being performed on different software instructions.

Fig. I/O Mapped I/O

Whether the read/write operations are being performed on memory or I/O or in the
other words whether the information on address and data lines is meant for a
memory location or an I/O device this identification is done by separate signals.
This is called I/O mapped I/O interface since I/O devices are treated separately
from memory


Data Transfer Schemes depend heavily on the environment (online or offline
proceeding), type of I/O device, (capable of parallel or serial data transfer,
synchronous or asynchronous) and the application. Data transfer schemes may be
categorized as shown below

Serial data transfer

Parallel data transfer

Parallel Data Transfer:

Programmed I/O:
In this the data transfer is controlled by the user program being executed on the
type of device data transfer may be synchronous or asynchronous. Synchronous
data transfer is used when the I/O device matches in speed with the
microprocessor. The microprocessor issues the read/write instruction the device
whenever data transfer is required. The actual data transfer takes place in one clock

When the I/O device speed and microprocessor speed do not match ie., when the
I/O device is slower than the microprocessor checks the status of the device. If the
device is not ready the microprocessor continuously checks the status of the device
till it becomes ready

The data transfer instruction is then issued by the microprocessor.

Fig. Asynchronous Data Transfer

Interrupted I/O:
The previous data transfer scheme is quite inefficient since the microprocessor is
kept being for the slower I/O device. The remedy to the problem is to allow the
microprocessor to do its job when the device is getting ready and when the device
is ready the microprocessor can transfer the data. This can be achieved through

Interrupt is the facility provided by the microprocessor to the outside environment

by which the attention of the microprocessor can be diverted to do some higher
priority job clearly the microprocessor should the signal on the interrupt pin during
machine cycle when the interrupt signal is present it should suspend the current
Fig. Interrupt Operation

The microprocessor services the interrupt request by executing an interrupt service


When a device is ready to transmit or receive data it needs an interrupt request

signal. The microprocessor completes the current instruction execution and then
suspends the current job saves the address and the current status in stack and then
executes the Interrupt Routine. On completion of data transfer the microprocessor
retrieves the status of the suspended job and restarts the operation.
Fig. Interrupt Data Transfer

Direct Memory Access:

Following is the operation sequence in case of direct memory access
The microprocessor checks for DMA request signal once in each machine
The I/O device sends signal on DMA request pin
The microprocessor tri-stated the address, data and control buses
The microprocessor send the acknowledgement signal to the I/O device on
DMA acknowledgement pin
The I/O device uses the bus system to perform the data transfer operation on
On completion of data transfer the I/O device withdrawn the I/O request
The microprocessor continuously checks the DMA request signal when the
signal is withdrawn the microprocessor regains the control of buses and
resumes the normal operation.

Fig. Direct Memory Access

Serial Data Transfer:

Some devices like CRT receive and transmit data in serial mode. In addition in
many applications a number of microprocessor systems are connected to each other
in network fashion to form a geographically distributed microprocessor system.
The data transfer between two processor will be in serial mode. The data is
transferred bit by bit on a single line. This minimizes the number of
interconnecting lines. The microprocessor providing the serial data transfer facility
will have two pins for input and output of serial data and special software
instructions to affect the data transfer

8085 Timing Diagrams:

The graphical representation of the instruction execution in steps with respect to
the time (clock signal) is called timing diagram

During normal operation the microprocessor sequentially fetches, decodes and

executes one instruction after another until a Halt Instruction (HLT) is executed.
The fetching decoding and execution of a single instruction constitutes an
instruction cycle, which consists of one to five read or write operations between
processor and memory or input/output devices.

Each memory or I/O operations require a particular time period called machine
cycles. Each machine cycle consists of 3 to 6 clock periods/cycles referred to as 7

There are seven different machine cycles in 8085A

Op-code fetch
Memory read
Memory write
I/O read
I/O write
INTR acknowledge
Bus idle

Representation of Signals:

Clock Signal:
Single Signal:

Group of Signals:

8085 Timing Diagrams:

The graphical representation of the instruction execution in steps with respect to
the time (clock signal) is called timing diagram

The machine cycles are the basic operations performed by the processor, while
instructions are executed. The time taken for performing each machine cycle is
expressed in terms of Tstates. One T-state is the time period of one clock cycle
of the microprocessor.

The various machine cycles are

1. Op-code fetch .. - 4 / 6 T
2. Memory Read . - 3 T
3. Memory Write . - 3 T
4. I/O Read .. - 3 T
5. I/O Write . - 3 T
6. Interrupt Acknowledge - 6 / 12 T
7. Bus Idle - 2 / 3 T

Representation of Signals:

Clock Signal:
Single Signal:

Group of Signals:

Activation of one signal with the change in state of another signal:

Example: Op-code fetch machine cycle of 8085

Each instruction of the processor has one byte op-code. The op-codes are stored in
memory. The op-code fetch machine cycle is executed by the processor to fetch
the op-code from memory. Hence, every instruction starts with op-code fetch
machine cycle.
The time taken by the processor to execute the op-code fetch cycle is either 4T or
6T. In this time, the first 3T-states are used for fetching the op-code from memory
and the remaining T-states are used for internal operation by the processor. The
timings of various signals during op-code fetch is shown in figure.
1. At the falling edge of first T-state(T1), the microprocessor outputs the low byte
address on AD0-AD7 lines and high byte address on A8to A15 lines. ALE is
asserted high to enable the address latch. The other control signals are asserted
as follows. IO/M=0, S0=1, S1=1.
2. At the middle of T1, The ALE is asserted low and this enables the latch to take
low byte of the address and keep on its output lines.
3. In the second T-state (T2), the memory is requested for read by asserting read
line low. When read is asserted low, the memory is enabled for placing the data
on the bus. The time allowed for memory to output the data during which read
remains low RD.
4. In the third T-state (T3), the read signal is asserted high. On the rising edge of
read signal the data is latched into microprocessor. Other control signals
remains in the same state until the next machine low.
5. The fourth T-state(T4) is used by the processor for internal operations to
decode the instruction and encode into various machines cycles, and also for
completing the task specified by 1 byte instructions. During this cycle the
address and data bus will be in high impedance state.

Memory Read Machine Cycle:

The operation during the first two clock cycles T1 and T2 is the same as that of the
op-code fetch machine cycle. However in this case in the T 1 clock cycle the
memory address of the data byte to be read is loaded to the address bus AD 0
AD7, A8 A15

goes high to indicate the end of the read operations
Data is transformed to the register mentioned

If memory is slow is if the data cannot be accessed in one clock cycle it will
pull the READY pin low indicating that memory is not ready to transfer the data.
The READY pin is sampled in the T2 clock cycles of each machine cycle. If
READY is low then wait states are entered between T2 and T3 clock cycles till the
READY pin become high.

Direct Memory Access Timing Diagram:

The HOLD and HLDA signals are used for direct memory access. Using DMA
bulk data transfer can take place between the memory and the I/O device by
passing the microprocessor. DMA is initiated by the external logic. It requests for a
HOLD state by inputting the HOLD signal high. The microprocessor responds by
entering the HOLD state and outputting the HLDA signal high
The signal at the HOLD pin is sampled during T2 in each machine cycle
If HOLD is high at this time HLDA is output high during T3
As soon as high but is detected at HOLD a two clock period HOLD state
initiation sequence begin. HOLD state begins at T4
The HOLD state terminates two clock periods after the HOLD signal goes

External Interrupts Timing Diagram:

The 8085 has five interrupt request pins. These are TRAP, RST 7.5, RST 6.5, RST
5.5 and INTR. The locations of Interrupt Service Routine (ISR) for all interrupts
except INTR are fixed. Interrupt requests on TRAP, RST 7.5, RST 6.5, RST 5.5
cause the 8085 A to generate its own internal interrupt acknowledge instruction
and branch to respective ISRs
The 8085A samples INTR during the second last clock period of each
instructions execution.
Even though memory is not being accessed PC contents are put on the
address bus during T1.
8085A makes S0, S1 and IO/ high. These can be decoded by the interrupting
device as advance acknowledgement.
Goes low during T2. The external logic must use both as device select
signal and as a strode signal to identify the time internal during which the
interrupt acknowledge instruction code must be placed on the data bus.
The external logic may respond to signal by replacing the restart (RST) or
call instruction object code on the data bus.
The instruction code is decoded in the subsequent clock cycles.
If the instruction code is for the call address instruction the interrupt
acknowledgement extends to two more machine cycles.
The second and third acknowledgement machine cycles are I/O read cycle
where IO/ and are output high and is pulsed low.
The external logic pulses two bytes of address (of ISR) on data bus in
synchronization with thus creating a call instruction.

Interrupt is a process by which the external devices use microprocessor for
servicing by suspending the routine process served previously.
After completion of interrupt, the processor resumes its original operation.
The status of peripherals requesting service is checked frequently by the
processor and it is known as polling.

o Hardware Interrupt
o Software Interrupt
Hardware Interrupt:
When the interrupt is due to external peripheral devices then it is known as
hardware interrupts. There are 5 hardware interrupts are available in 8085 from
highest priority to lowest priority are given below.
o RST 7.5
o RST 6.5
o RST 5.5

It is a vectored, high priority, non maskable interrupt.

It can be disabled by any instruction.
Edge and level triggered

There are 2 ways to clear TRAP interrupt.

By resetting processor (i.e) giving a low signal on RESET IN pin.
By giving a high TRAP ACK

RST 7.5:

It is a vectored interrupt.
It has second highest priority.
Positive edge triggered and it is internally stored by DFF until it is cleared
by software interrupt.
It can be enabled or disabled by using SIM instruction
RST 6.5 & RST 5.5:

Vectored maskable interrupt.

Both are level triggered.
Can be masked using SIM instruction.
RST 6.5 has third priority whereas RST 5.5 has fourth priority.

It is a non vectored and maskable interrupt.

It receives the address of the subroutine from the external device.
The following sequence of events occurs when INTR signal goes high.
8085 checks the status of INTR during execution of each instruction.
If INTR is high 8085 completes its current instruction and sends an active
low INTA, if interrupt is enabled.
Maskable/Unmaskable interrupts:

Maskable interrupts are enabled and disabled under program control by

setting or resetting particular flip-flops in the processor interrupts can be
masked or unmasked resp.
In the processor those interrupts which can be masked under software
control are called maskable, whereas the interrupt which cannot be masked
under software control are called non maskable.

EI Enable Interrupt
DI Disable Interrupt
RIM Read Interrupt Mask
SIM Set Interrupt Mask
Software interrupts in 8085:
The 8085 has eight software interrupts from RST0 to RST7. The vector address for
these interrupts can be calculated as follows
Interrupt number x 8 = vector address
Therefore the vector address for interrupt RST 5 is 0028H

Pending Interrupt:
The RIM instruction loads the status of the interrupt mask the pending interrupts
and the contents of the serial input data line, SID into the accumulator.
Thus it is possible to monitor the status of interrupt mask, pending interrupt and
serial input.
There are number of interrupts. When one is being serviced other interrupt requests
may occur. If the interrupt requests are of higher priority, 8085 branches program
control to the requested interrupt service routine.

But when all the interrupt requests are of lower priority, 8085 stores the
information about these interrupt requests. Such interrupts are called pending

The status of pending interrupts can be monitored by using RIM instructions.