5/15/2016

Design of Analog Integrated Circuits

ECE611

Lecture 13
High Accuracy Circuit Techniques
Ayman H. Ismail
ICL
Ain Shams University

Outline
Circuit non-idealities: Mismatch
Mismatch in differential pair
Mismatch in Current mirror
Technology trend
High accuracy circuit techniques
Auto-zeroing
Correlated double sampling
Chopping
Dynamic element matching (DEM)
Calibration

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Mismatch
The parameters of two identically designed devices on an
integrated circuit show a random variation after fabrication,
which is called device mismatch.
Device mismatch limits the accuracy of circuits and has
important implications on the offsets of operational amplifiers
or comparators, and on the power supply-noise and common-
mode rejection ratios in differential structures.
For example, two identical MOS transistors used to implement
an input differential pair exhibits threshold voltage and
mobility mismatch, resulting in voltage offset. Similarly, two
identical MOS used to construct a current mirror suffer from
random mismatch causing offset current.
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Mismatch in Current Mirror

For two identical transistors biased with the same VGS, as for
the case of a current mirror

Therefore

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Mismatch in Current Mirror

Defining small difference between the two MOS transistors

Then

Using first order approximation for the square root

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Mismatch in Current Mirror

Since the variation are random, they are better described with
the standard variation of the random variables

Random offset due to random mismatch in current mirror

comes on top of systematic offset due to Vds inequality or
poor layout.

For better current matching, higher Vgs-Vth is required.

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Mismatch in Differential Pair

For a transistor pair biased with an identical drain current I DS,
as in the case of differential pair

Defining small difference between the two MOS devices

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Mismatch in Differential Pair

Using, first order approximation for the square root.

Therefore

Voff (offset voltage) is the differential voltage that needs to be

applied to balance the diff pair.
Since the variation are random, they are better described with
the standard variation of the random variables

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Models for MOS Transistor

Mismatch
Offset voltage/current is function in Vth and / , which
are given by

where Avth and A are technology dependent constants, W and

L are the device dimensions
Hence, the larger the area of the device, the smaller the
random error. The same applies to resistors and capacitors.

[M. Pelgrom et al., Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits, vol.
24, no. 5, pp. 1433-1439, 1989]

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Addressing Mismatch
Previous equations show that mismatch can be reduced by:-
Increasing devices area. However, this cause increase in
capacitance level, and consequently, power dissipation
Modifying circuit bias (increasing/decreasing Vod).However,
this usually tightens circuit trade-offs.
From mismatch point of view: Higher overdrive voltage is
recommended for current mirrors and lower overdrive
voltage is recommended for differential pair
Applying analog circuit techniques (correlated-double
sampling (CDS), autozeroing, chopping)
Calibration

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Technology Trend

K. Uyttenhove and M. S. Steyaert, Speed-

[K. Bult, Analog Design in Deep Sub- power-Accuracy tradeoff in high-speed
Micron CMOS," in Proc. of the 26th CMOS ADC's," IEEE Trans. Circuits Syst. II,
EuropeanSolid-State Circuits Conference, vol. 49, no. 4, pp. 280{287, Apr. 2002.
2000, pp. 126-132]
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Technology Trend: Is it really

getting better?
For many applications, minimizing the input capacitance at
the same target accuracy is a main design objective. An
example of such applications is flash ADCs designed for wide
band communication systems, where a large input bandwidth
(and hence, a small Cin), in addition to a certain accuracy, are
dictated by the system specifications.

Assuming that the bandwidth of a system is limited by the

input capacitance, and its accuracy by the input referred
offset, then It can be shown that bandwidth-accuracy product
is inversely proportional to A2vthCox/V2DD

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A2vthCox/V2DD?

[A. Ismail and M. Elmasry,A 6-bit 1.6-GS/s Low Power Wide Bandwidth Flash ADC Converter in 0.13-Um
CMOS Technology, IEEE J. of Solid State Circuits (JSSC), vol. 43,no. 9, pp. 1982-1990,Sept. 2008.]

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A2vthCox/V2DD?
For technologies with a minimum feature size less than 0.5
m, A2vthCox/V2DD increases with technology scaling, because
the continuous reduction in VDD almost cancels out the
expected improvement due to the enhancement of the
matching properties of the FET transistor as both AVth and VDD
scale nearly with the same factor.
Since the accuracy depends on the ratio of the offset to the
signal, approximately the same FET area is needed in different
submicron technologies
Thus, the increase in the value of Cox, with scaling, would lead
to a net increase in A2vthCox/V2DD. Hence, as technology scales,
a tighter bandwidth-accuracy tradeoff is obtained.
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Autozeroing: IOS
In input offset Storage (IOS),
offset is stored on the input
coupling caps during unity
feedback phase.
Still the circuit suffers from
residual offset, given by
B. Razavi and B. Wooley, Design
Techniques for High-Speed, High-
Resolution Comparators," IEEE J. Solid-
where Q is the mismatch in State Circuits, vol. 27, no. 12, pp. 1916-
1926, Dec. 1992.
charge injection from
switches S5 and S6 onto
capacitors C 1 and C2
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Autozeroing: OOS
In Output offset storage, the
offset is stored on
capacitors at amplifier
output.
During amplification phase,
the offset is subtracted
from the signal. The
residual offset in OOS can
be described as

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IOS vs OOS
Input Offset Storage Output Offset Storage
IOS requires the use of quite large Since OOS is normally an open-loop operation,
values for A0. to guarantee a low therefore, OOS is typically implemented using a
Vos. single-stage amplifier with a gain of less than 10 to
ensure operation in the active region (avoid
saturation) under extreme variations in device
matching and supply voltage.
The low gain reduces the suppression of following
stages offset when referred to the input
Since the value of the input Input capacitance is that of the preamplifier
coupling capacitors with IOS is
governed by charge injection,kT/C
noise, and attenuation
considerations, the input
capacitance of this topology is
usually higher than that of the
OOS configuration.
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Autozeroing: Multistage
The advantages of IOS and OOS can be combined by using
multi-stages (high gain and low input capacitance)

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Correlated Double Sampling

Correlated double sampling is the discrete time case of
autozeroing

B. Murmann, EE315A(VLSI Signal conditioning

circuits) course slides, Stanford University

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Chopper Stabilization

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Chopper Stabilization
Chopping is a modulation technique, where the input signal is
modulated to higher frequencies, amplified, and
demodulated

The signal demodulator at the amplifier output modulates low

frequency nonidealities to higher frequencies.

The up converted non idealities are then filtered out by the

low pass filter

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Chopped Amplifier
PMOS choppers
demodulate the
signal

NMOS choppers
modulate the
NMOS current
sources

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Chopper Stabilization Non-

Idealities
Mismatched charge injection and
clock feed-through at the input
chopper results in differential
mode chopping artifacts
Demodulation by the output
chopper results in residual DC
offset
The input-referred residual offset is
approximately equal to

Residual offset can be reduced by

reducing amplifier bandwidth
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Chopper Stabilization Design

Selection of chopping frequency fch
Should be higher than 1/f corner
However, high frequency fch
requires fast amplifier. Hence, For DC input
higher power.
Amplifier bandwidth
Reducing amplifier bandwidth
filters spikes
However, reducing amplifier
bandwidth reduce the effective
gain

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Dynamic Element Matching

Dynamic element matching (DEM)algorithms were introduced
in 1974 by Klaas Klaassen [K.B. Klaasen, Digitally controlled
absolute voltage division, IEEE Trans.Instrumentation and
Measurement, vol. 24, no. 2, pp. 106-112, June 1975] who
used DEM to obtain a constant division ratio from a voltage
divider consisting of a mismatched resistors
DEM average out errors due to
component mismatch and
therefore achieves accuracy
beyond intrinsic device
matching

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Dynamic Element Matching

Algorithms
DEM is implemented by using different instances of circuit
elements (transistors, resistors, caps) used to build the system
each time the system the output analog signal is generated
Since different instances introduce different errors. The errors
introduced by instances is averaged out
DEM is used to linearize DACs
Dynamic Element Matching Algorithms:-
Data weighted averaging
Individual level averaging
Vector based mismatch shaping
Tree-structure element selection
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DATA-Weighted Averaging
The data weighted averaging DEM algorithm
rotates circuit elements, insuring that each
element is used the same number of times.
The circuit elements are selected sequentially
from the array starting with the next available
unused element.
Data weighted averaging generates tones at
the output if the DAC input is not busy (DC
input or low frequency input)
It can be shown that DWA is equivalent to
shaping mismatch error (noise) by a first order
high pass filter
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Individual Level Averaging

Individual level averaging (ILA) is basically a DWA carried out
for each code.
Individual level averaging rotates or flips circuit elements in a
periodic fashion, but a separate rotation state is maintained
for each digital level.
The advantage of the individual level averaging algorithm over
DWA is that it ILA is less likely to generate tones even for DC
or periodic inputs
However, compared to DWA, ILA converges more slowly to
zero average condition

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Digital Calibration
Nanoscale technologies allow the efficient implementation
(low power and small area) of complex calibration techniques.

Digital calibration involves implementing digitally

programmable analog components, which can be adjusted
using a digital engine.

Most calibration alternatives do not eliminate the

requirement for some degree of matching, and precise
matching is still required for the design of accurate supporting
circuits such as bias current mirrors

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Calibration Categories: Foreground

Calibration techniques are categorized as either; foreground
or background techniques.
In the foreground technique, normal operation is interrupted
to start a calibration cycle. Many standards define standby
time that would allow foreground calibration. Otherwise,
foreground calibration can be carried once at power up.
However, any temperature or supply variation that occurs
during normal operation can render the measured error (and
consequently the calibrating signal) during initial calibration
invalid

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Calibration Categories: Background

The background calibration techniques do not interrupt the
normal operation, and are assigned a periodic time slot of the
system clock. Since background calibration works
continuously, it is more robust to temperature and supply
variation, compared to foreground calibration.

To avoid the operating speed reduction due to the calibration

time slot, in some implementations, background calibration is
used, along with time-interleaving more than one instance of
the block that is calibrated

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Calibration Engine
Digital calibration involves two important considerations
The error or objective function to be minimized during the
adaptive calibration
The method used to drive the objective function towards
zero
These considerations are independent or orthogonal.

Adaptation engine for digital calibration can be simply an up

down counter that saturates if extreme values are reached or
successive-approximation approach can be used.

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