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QUARTUS II ...................................................1

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XXXX3....................................................................................4
XXXX4....................................................................................6

I
 1 QuartusII
30 506

2016.10.10

EDA

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4 3-8

3-8

1. project
2. VHDL

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3.
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY decoder_38 IS
PORT(a,b,c,g1,g2a,g2b:IN std_logic;
y:OUT std_logic_vector(7 DOWNTO 0));
END decoder_38;
ARCHITECTURE behav OF decoder_38 IS
SIGNAL indata:std_logic_vector(2 DOWNTO 0);
BEGIN
indata<=c&b&a;
PROCESS(indata,g1,g2a,g2b)
BEGIN
IF(g1='1'and g2a='0'AND g2b='0')THEN
CASE indata IS
WHEN "000"=>y<="11111110";

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 WHEN "001"=>y<="11111101";
WHEN "010"=>y<="11111011";
WHEN "011"=>y<="11110111";
WHEN "100"=>y<="11101111";
WHEN "101"=>y<="11011111";
WHEN "110"=>y<="10111111";
WHEN "111"=>y<="01111111";
WHEN OTHERS=>y<="XXXXXXXX";
END CASE;
ELSE y<="11111111";
END IF;
END PROCESS;
END behav;

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 2
30 506

2016.10.24

VHDL

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3 JK
4 JK T 8

Si=AiBiCi-1
Ci=AiBi+Ci-1(Ai+Bi)

JK

1. project
2. VHDL
3.
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5.
6. J=K=1 T
7.T

8.

JK

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY fadd IS
PORT(a,b,ci:IN std_logic;
co,sum:out std_logic);
end fadd;
architecture dataflow of fadd is
begin
co<=(a and b)or(b and ci)or(a and ci);
sum<=a xor b xor ci;
end dataflow;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
package components is
component fadd is
port(a,b,ci:IN std_logic;

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 co,sum:OUT std_logic);
end component;
end components;

JK
library ieee;
use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,clock,reset:in std_logic;
q,qbar:out std_logic);
end jk_ff;
architecture behav of jk_ff is
signal state:std_logic;
begin
process(clock,reset)
variable jk:std_logic_vector(1 downto 0);
begin
jk:=j&k;
if(reset='0') then state<='0';
elsif rising_edge(clock) then
case jk is
when "11"=>state<=not state;
when "10"=>state<=not state;
when "01"=>state<=not state;
when others=>null;
end case;
end if;
end process;
q<=state;
qbar<=not state;
end behav;

T
library ieee;
use ieee.std_logic_1164.all;
entity t_ff is
port(t,clock,reset:in std_logic;
q,qbar:out std_logic);
end t_ff;
architecture behav of t_ff is
begin
process(clock,reset)
variable state:std_logic;
begin

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 if(reset='0') then state:='0';
elsif (rising_edge(clock)) then
if(t='1')then state:=not state;
end if;
end if;
q<=state;
qbar<=not state;
end process;
end behav;

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