GATE DRIVERS

Using Monolithic High

THE POWER MANAGEMENT LEADER
Voltage Gate Drivers
By A. Merello, A. Rugginenti and M. Grasso, International Rectifier

INTRODUCTION
The purpose of this paper is to highlight the most common
subjects driving a half bridge power stage in motor drive ap-
plications (with monolithic IC gate driver) and to suggest ap-
propriate solutions to solve the issues.
In the following sections different topics are discussed: the
sizing of some fundamental components, as bootstrap circuit
and on/off gate resistors; the half bridge parasitic elements
are presented with their effects and some possible solutions
are proposed. In the end section some layout tips are pre-
sented.
All the situations and the solutions proposed are, unless
otherwise specified, for a typical IR monolithic gate driver
with floating bootstrap supply.
time since they are limited by the requirement to refresh the
charge in the bootstrap capacitor.
Proper capacitor choice can reduce drastically these limi-
tations.
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to establish
the minimum voltage drop (VBS) that we have to guarantee
when the high side IGBT is on. If VGEmin is the minimum gate
emitter voltage to maintain, the voltage drop must be:
VBS VCC VF VGEmin VCEon
under the condition:

BOOTSTRAP CIRCUIT VGEmin > VBSUV

DT04-4 revA
The bootstrap supply is formed by a diode and a capacitor where V is the IC voltage supply, VF is bootstrap diode
Using monolithic high voltage gate drivers CC
connected as in figure 1. forward voltage, VCEon is emittercollector voltage of low side
BOOTSTRAP CIRCUIT IGBT and VBSUV- is the high-side supply undervoltage negative
This method has the advantage of being simple and low going threshold.
The bootstrap supply is formed by a diode and a capacitor connected as in figure 1. Now we must consider the influencing factors contributing
cost but may force some limitations on duty-cycle and on-
VBS to decrease:
bootstrap bootstrap
resistor diode
DC+ IGBT turn on required Gate charge (QG);
Rboot
VF IGBT gate-source leakage current (ILK_GE);
Floating section quiescent current (IQBS);
VCC VB
Floating section leakage current (ILK)
bootstrap
Bootstrap diode leakage current (ILK_DIODE);
VBS
capacitor VGE
Desat diode bias when on (IDS- )
VS
ILOAD
motor Charge required by the internal level shifters (QLS);
VCC
Bootstrap capacitor leakage current (ILK_CAP);
VCEon High side on time (THON).
VFP

ILK_CAP is only relevant when using an electrolytic capacitor

DC-
and can be ignored if other types of capacitors are used. It
Figure 1: bootstrap supply schematic is strongly recommend using at least one low ESR ceramic

This method has the advantage of being simple and low cost but may force some limitations on
Foron-time
duty-cycle and since they
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in North Americabycall
the+1 requirement toEurope
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the+49charge theor visit us at www.irf.com
6102 884in311, DT04-04
bootstrap capacitor.
Proper capacitor choice can reduce drastically these limitations.

Bootstrap capacitor sizing

 Using monolithic high voltage gate drivers

Bootstrap diode leakage current (ILK_DIODE);

Desat diode bias when on (IDS- )
Using Monolithic High
Charge required by Voltage
the internal Gate Drivers
level shifters (QLS);
Bootstrap capacitor leakage current (ILK_CAP);
High side on time (THON).

capacitor (paralleling
ILK_CAP is only electrolytic
relevant when using anand low ESR
electrolytic ceramic
capacitor and may the above
can be ignored if otherformulas.
types of
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
result in an efficient solution).
(paralleling electrolytic and low ESR ceramic may result in an efficient solution).
2. This kind of bootstrap sizing approach does not take into
Then
Thenwe wehave:
have: account neither the duty cycle of the PWM, nor the funda
QTOT = QG + QLS + (ILK _ GE + IQBS + ILK + ILK _ DIODE + ILK _ CAP + IDS ) THON mental frequency
DT04-4 revA of the current. It considers only the
QTOT = QG +QLS + (ILK _GE + IQBS + ILK + ILK _DIODE + ILK _CAP + IDS ) THON amount of charge that is needed when the high voltage side
The
Theminimum
minimum size of bootstrap
size of bootstrap capacitor is: Using
capacitor is: monolithic high voltage gatedriver
of the drivers
is floating and IGBT gate is driven once.
Bootstrap QTOT
diode leakage current (ILK_DIODE); Considerations on PWM duty cycle, kind of modulation (six-
CBOOT min =diode bias when on (IDS- )
Desat VBS step, 12-step, sine-wave) must be considered with their own
Charge required by the internal level shifters (QLS);
Bootstrap capacitor leakage current (ILK_CAP); peculiarity to achieve best bootstrap circuit sizing.
Anexample
High sidefollows:
on time (T ).
An example follows: HON

ILK_CAP is only
a) using a 25Arelevant
@ 125C when
IGBTusing an electrolytic capacitor
(IRGP30B120KD) and a high and ignoredConsiderations
can behalf-bridge
voltage if gate types of about bootstrap circuit
otherdriver
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
(IR2214):
a) using aelectrolytic
(paralleling 25A @ 125C IGBT
and low ESR (IRGP30B120KD)
ceramic may resultand in anaefficient
high volt- solution).
age
Then half-bridge
Iwe = 800 A
QBShave:
gate driver (IR2214):
(Datasheet IR2214); a. Voltage ripple
ILK = 50 A (Datasheet IR2214);
QTOT = QG + QLS + (I LK _ GE + IQBS + ILK + ILK _ DIODE + I LK _ CAP + IDS ) THON
Q = 20 nC;
IQBS = 800 A (Datasheet IR2214);
LS Three different situations can occur in the bootstrap capac-
QG = 160 nC (Datasheet IRGP30B120KD);
The minimum size of bootstrap capacitor is:
ILK = 50= A
ILK_GE 100(Datasheet
nA IR2214);
(Datasheet IRGP30B120KD); itor charging (see figure 1):
QILK_DIODE
= 20 =nC;
QTOT 100QA = 160 nC (Datasheet
(with reverseIRGP30B120KD);
recovery time <100 ns);
CBOOT LS min =
G
ILK_CAP =V0BS (neglected for ceramic capacitor);
ILK_GE = 100 nA (Datasheet IRGP30B120KD); - ILOAD < 0; the load current flows in the low side IGBT dis-
IDS- = 150 A (Datasheet IR2214);
An example
ILK_DIODE = 100
THON = follows:
100 s.A (with reverse recovery time <100 ns); playing relevant VCEon
I
a) using
= 0 (neglected for ceramic capacitor);
And: a 25A @ 125C IGBT (IRGP30B120KD) and a high voltage half-bridge gate driver
LK_CAP
I - = 150 A (Datasheet IR2214);
(IR2214):
DS
V =V V BS CC F
VCEon
IT HON
QBS =V=
800
CC 10015s.
= A V (Datasheet IR2214);
ILK = V F=
50 A1V (Datasheet IR2214); In this case we have the lowest value for VBS. This repre-
QLS =V20 nC;
CEonmax = 3.1 V
And:
QG =V160 nC
GEmin = 10.5 V
(Datasheet IRGP30B120KD); sents the worst case for the bootstrap capacitor sizing.
ILK_GE = 100 nA (Datasheet IRGP30B120KD);
ILK_DIODE = 100 A (with reverse recovery time <100 ns);
When the IGBT is turned off the Vs node is pushed up by
the
IV
maximum voltage drop V BS becomes
LK_CAP
CC
= =150 V (neglected for ceramic capacitor); the load current until the high side freewheeling diode gets
IDS- = 150 A (Datasheet IR2214);
VTBS
VHON==1CC100
F V
VVFs.VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V forwarded biased
V = 3.1 V
And: CEonmax
And
Vthe bootstrap
= 10.5 Vcapacitor is: - ILOAD = 0; the IGBT is not loaded while being on and VCE can
GEmin
VCC = 15 V
V = 1290
V nC be neglected
C VF = 3.1 V= 725 nF
the maximum
BOOT voltage drop
CEonmax0.4 V VBS becomes
VGEmin = 10.5 V
VBS =VCC VF
NOTES:
VBS VCC VF VGEmin VCEon=15V 1V 10.5V 3.1V = 0.4V
the maximum voltage drop VBS becomes

VBS VCC VF VGEmin VCEon = 15V 1V 10.5 V 3.1V = 0.4 V - ILOAD > 0; the load current flows through the freewheeling
And the bootstrap capacitor is:
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And the bootstrap capacitor is:
diode 3

290 nC
CBOOT
0. 4 V
= 725 nF VBS =VCC VF +VFP

NOTES:
In this case we have the highest value for VBS. Turning on the
Notes: high side IGBT, ILOAD flows into it and VS is pulled up.
www.irf.com 3

1. Here above VCC has been chosen to be 15V. Some IGBTs To minimize the risk of undervoltage, bootstrap capacitor
may require higher supply to properly work with the boot- should be sized according to the ILOAD<0 case.
strap technique. Also Vcc variations must be accounted in

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 d. off
capacitor sizing. When the IGBT is turned Bootstrap
the Vs Diode
node is pushed up by the load current until
The diode must have a BV > DC+ and a fast recovery time (trr < 100 ns) to minimize the amou
the high side freewheeling diode get forwarded biased
of charge fed back from the bootstrap capacitor to VCC supply.
 ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
Using Monolithic High Voltage Gate Drivers GATE RESISTANCES
VBS = VCC VF
The switching speed of the output transistor can be controlled by properly size the resisto
controlling the turn-on and turn-off gate current. The following section provides some basic rule
b.  ILOAD >Resistor
Bootstrap 0; the load current flows through the freewheeling
Qgc and diode
for sizing the resistors Qtoge obtain
indicatethethedesired
gate toswitching
collector time
and gate to emitter
and speed by introducing th
equivalent outputcharge
resistance of the gate driver (RDRp and RDRn respectively of p and n channel).
respectively.
VBS = VCC VF + VFP The examples always use IGBT power transistor. Figure 2 shows the nomenclature used in th
A resistor (Rboot) is placed in series with bootstrap diode (see
following Sizing
paragraphs. the turn-on
In addition, Vge* gate resistor
indicates the plateau voltage, Qgc and Qge indicate the ga
figure 1) so to limit the current when the bootstrap capacitor
to collector and gate to emitter charge respectively.
In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it
is initially
and V charged. The choice of bootstrap resistor is strictly
S is pulled up. I C
related to VBS time-constant. The minimum on time for charg- C RES

ingTo theminimize the risk of

bootstrap capacitor undervoltage,
or for refreshing its bootstrap
charge must capacitor should be sized according to the
ILOAD<0 case.
be verified against this time-constant. V GE

b. Bootstrap Resistor
t ,Q t ,Q
c.
A Bootstrap
resistor (R Capacitor
boot) is placed in series with bootstrap diode (see figure 1) so to limit the current when
1 GE 2 GC

V
the bootstrap capacitor is initially charged. The choice of bootstrap resistor isdV/dt strictly related to
CE

V time-constant. The minimum on time for charging

ForBShigh THON designs where is used an electrolytic tank ca- the bootstrap capacitor or for refreshing its
I
charge must be verified against this time-constant. C

pacitor, its ESR must be considered. This parasitic resistance 90%

C RES
CRESon

forms
c. aBootstrap
voltage divider with Rboot generating a voltage step on
Capacitor V * ge
V GE

at the
VBSFor firstTcharge
high of bootstrap
HON designs wherecapacitor.
is used an Theelectrolytic
voltage steptank capacitor, its ESR must be considered. CRESoff
10%
andThis parasitic
the related resistance
speed (dVBS/dt)forms
shouldabevoltage
limited.divider with Rboot generating a voltage
As a general 10% step on VBS at the
first charge of bootstrap capacitor.
rule, ESR should meet the following constraint: The voltage step and the related speed (dV BS/dt) should be t,Q

limited. As a general rule, ESR should meet the following constraint:

tSW
tDon tR
ESR
VCC 3 V
ESR + RBOOT Figure 2: Nomenclature

Sizing the turn-on gate resistor

Parallel combination of small ceramic and largeGateelectrolytic
resitances may be chosen in order to fix either the switching-time or the output voltage
capacitors is
www.irf.com normally the best compromise, the first acting
slope. as are
Hereafter Gate resitances
presented maymethods.
both the be chosen in order 4to fix either the
fast charge tank for the gate charge only and limiting the dVBS/ switching-time or the output voltage slope. Hereafter are pre-
Switching-time
dt by reducing the equivalent resistance, while the second sented both the methods.
keeps the VBS voltage drop inside the desired VFor BS
. the matters of the calculation included hereafter, the switching time tsw is defined as the tim
end of the plateau voltage (a total Qgc + Qge has been provided to the IGB
spent to reach theSwitching-time

d. Bootstrap Diode
For the matters of the calculation included hereafter, the
The diode must have a BV > DC+ and a fast recovery time switching time tsw is defined as the time spent to reach the
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(trr < 100 ns) to minimize the amount of charge fed back from end of the plateau voltage (a total Qgc + Qge has been pro- Using mono
the bootstrap capacitor to VCC supply. vided to the IGBT gate). To obtain the desired switching time
the gate resistance
gate). can the
To obtain be sized starting
desired from Qge
switching andthe
time Qgc,
gate resistanc
GATE RESISTANCES Vcc, Vge*
Qgc, (see
Vcc,figure*
Vge 3):
(see figure 3):

The switching speed of the output transistor can be con- Qgc + Qge
I avg =
trolled by properly size the resistors controlling the turn-on t sw
and turn-off gate current. The following section provides and
some basic rules for sizing the resistors to obtain the desired
*
switching time and speed by introducing the equivalent output Vcc Vge
RTOT =
resistance of the gate driver (RDRp and RDRn respectively of Iavg
p and n channel). The examples always use IGBT power tran-
where RTOT = R DRp + RGon , RGon = gate on-resistor and RD
sistor. Figure 2 shows the nomenclature used in the following
paragraphs. In addition, Vge* indicates the plateau voltage, (from the gate driver datasheet)

Vcc/Vb Iavg
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CRES
RDRp
 Using monolithic high voltage gate drivers
c + Qge
Using monolithic high voltage gate drivers
t sw gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and DT04-4
Qgc, Vcc, Vge* (see figure 3):
Using Monolithic
gate). To obtain High
the Voltage Gate Drivers
desired switching time the gate resistance can be sized starting from Qge and
* Qgc, Vcc, V *
ge (see figure 3):
Using monolithic high voltage gate
Vcc Vge Qgc + Qge
I avg =
Iavg t swQ
where Q gc +
TOT DRpgeGon R = R + R , RGon = gatethe
Sizing on-resistor and gate
turn-off external events.
resistor
avg =
Iand
TOT = R DRp + RGon= ,driver
RDRp RGon = gate on-resistor
t swequivalent and (from
on-resistance = driver
RDRp the equivalent
gate driver In on-resistance
this case, dV/dt of the output node induces a parasitic
and
datasheet)
gate driver datasheet) * The worst case in sizing current the turn-off
throughresistor Goff is in
CRESoffRflowing whenRGoffthe
andcollector
RDRn (seeof the IGBT in off
figure
Vcc Vge forced to commutate by external events.
RTOT = 4)1.
* Using
Using monolith
monolith
RTOT =
VccIavg Vge
Vcc/Vb IavgIn this case, dV/dt of the 1
output nodedrop
If the voltage induces a parasitic
at the gate exceedscurrent through
the threshold voltageCRESoff flowing
and R (see figure 4) .
where RTOT Iavg= R
DRp + RGon ,C
DRn
RGon = gate on-resistor and of the IGBT,= the
RDRp device
driver may self turn
equivalent on causing large oscilla-
on-resistance
IfRES
the voltage drop at the gate Sizing exceeds
Sizing the
the the threshold
turn-off
turn-off gate
gate voltage of the IGBT, the device may
resistor
resistor
where
(from the RTOTgate R DRp +datasheet)
= driver RGon , Ron = gate on-resistor
Goncausing andtion
large oscillation and relevant
DRp =relevant
Rand cross
crossconduction.
driver equivalent on-resistance
conduction.
RDRp
(from the gate driver datasheet) Theworst
The worstcase
caseininsizing
sizingthe theturn-off
turn-off resistor
resistor RRGoff is when
Goff is when the
the co
co
Vcc/Vb I forced to commutate by external
avg forced to commutate by external events. events.
RGon Vcc/Vb I InInthis
thiscase,
case,dV/dt
dV/dt ofof the
the output
output node
node induces
induces
dV/dt aa parasitic
parasitic curren
curren
avg
CRES and R (see
HS Turning
figure 4)
ON
11.
and RDRn (see figure 4) .
DRn
CRES IfIfthe thevoltage
voltagedrop
dropat atthe
theCgate
gateexceeds
exceedsthethethreshold
thresholdvoltage
voltage of
of th
th
RDRp RESoff
COM/Vs ononcausing
causinglarge
largeoscillation
oscillationand andrelevant
relevantcross
crossconduction.
conduction.
RDRp RGoff
OFF
Figure 3: RGon sizing RGon ON
RDRn CIES
RGon HSTurning
HS TurningON
ON
eports the gate resistance size for two commonly used IGBTs (calculation made using
atasheet values and assuming Vcc=15V). COM/Vs CCRESoff
RESoff

COM/Vs Figure 4: RGoff sizing: current path when Low Side is off and
Table 1 reports the gate resistance size for two commonly RRGoff
oltage slopeused IGBTs (calculation made using typical datasheet High Side turns on Goff
Figure3:
Figure 4:RRGon
values sizing:
Goffsizing current path when Low Side is off and High Side turns OFF on
OFF
and assuming Vcc=15V). Figure 3: R Gon sizing ON
ON CCIES
RRDRn
DRn IES
gate resistor RGon can1be
Table sized to
reports thecontrol Hereafter
output
gate resistance slopesize(dVisfor
described
OUT /dt).
two commonlyhowHereafter
toused
sizeisIGBTs
the turn-off
described
resistor
(calculation
how tomade made
size the
when the
using output
turn-off resistor when
dV/dt is caused
Table
e output voltage 1
has reports
a the
non-linear gate resistance
behaviour,
companion
typical datasheet values and assuming Vcc=15V). size
the for two
maximum
IGBT commonly
output
turning-on used
slope
(as IGBTs
showncan (calculation
be
in figure 4). using
ated by: Output voltage
typical datasheet slope values and assuming Vcc=15V). the output dV/dt is caused by the companion IGBT turning-on
Other dV/dt cases may be present and must be taken into account. As an example, th
Output voltage slope generated by long motor (as
cableshown in figure(high
coupling 4). frequency spikes).
Figure
Figure 4: RRGoff sizing:current
current path wheninto LowSide Side isis off
off
Iavg Output
Turn-on voltage
gate resistorslope RGon can be Forsized
this to controlthe
reason output Other dV/dt
off-resistance must be 4:
cases may
properly Goffsizing:
be present and must
sized according path betowhen
taken Low
the application wors
CRESoff slope (dVOUTgate
Turn-on /dt). resistor RGon can be sized to control output account.
slope
Hereafter As OUT
(dV an example,
/dt).
is described
described thehowdV/dttogenerated
size the by long motor
the turn-off
turn-off resistor when when theth
Turn-on gate resistor RGon can The
be sized to control Hereafter
outputrelates
slope (dV is
/dt). how to size resistor
While the
While the output
output voltage has ahas
voltage afollowing
non-linearnon-linear equation
behaviour, the cable
behaviour, thethe
companion IGBT
OUT
couplingmaximum (high
IGBT gate threshold
frequency
output
turning-on voltage
spikes).
slope
(as can
shown to
beinthe collector
figure 4). dV/dt:
While the output voltage has a non-linear behaviour, the maximum output slope can be companion IGBT turning-on (as shown in figure 4).
the expression approximated
yielding
maximum Iavg and
output
approximated by:rearranging:
slope
by: can be approximated by: Other dV/dt
For thisdV/dt
Other reasoncasescases may be
the off-resistance
may be present
present
must beand and
properlymust
must beac-
sized
be taken into
taken into acc
acc
dV
Vth (RGoff + RDRn ) I = (RGoff + RDRn ) CRESoff
generated
generated
cording to the byby long
long
application motor
motor cable
outcable
worst case. coupling
coupling (high
(high frequency
frequency spikes).
spikes).
Vcc Vge
*
dVout
dV IIavg
avg Forthis
For thisreason
reasonthe theoff-resistance
off-resistance
dt mustbe
must beproperly
properlysized sized accordin
accordin
out =
dt = CRESoff
dV The following
CRESoff out dt C RESoff
Rearranging the equation The The
yields: followingequation
following equation
equation
relates
relates
the IGBT
relates theIGBT
the
gate threshold
IGBT gatethreshold
gate
volt- voltage to
threshold voltage to
dt age to the collector dV/dt:
inserting
inserting theexpression
the
inserting the expression
expression yielding
yielding
yielding IavgIavg
and andrearranging:
Iavgand rearranging:
rearranging: dVout
dV
ample, table 2 shows the sizing of gate resistance RGoff to get Vthout/dt=5V/nsVwhen
dV RDRnVthth(R (using
Goff ++
RGoff two
RRDRnDRn)) I I ==(R(RGoff
Goff ++R DRn)) C
RDRn CRESoff
RESoff
out

GBTs, typical datasheet values and dV dt

dt
VccVVgege* assuming Vcc=15V.
*
Vcc CRESoff
RTOT
TOT =
= dt
dVout
dV out Rearranging
Rearranging
Rearranging the the
the equation
equation
equation yields:
yields:
yields:
CRESoff
C RESoff
dtdt As an example, table 3 reports RGoff for two popular IGBT to withstand dVout/dt = 5V/ns.
VVthth
As an RRto dV /dt=5V/ns
get R RDRn
an example,
example,table table22shows the
thesizing
showsNOTES: sizing ofofgate
The gateresistance
resistance
above-described
Goffget
Goff
to dV
out
equations out/dt=5V/ns
dV when
dV intended
are
DRn
whenusing two two
using
to be an approximated way for t
As an
popular example,
popular IGBTs, table
IGBTs,typical 2 shows
typicaldatasheet the sizing
datasheetvalues of gate
valuesand andresistance
assuming
assuming Vcc=15V.
Vcc=15V. RESoff CC RESoff
resistances sizing. More accurate sizing dtdt take into account more precise device m
may
to get dVout/dt=5V/ns when using two popular IGBTs, typical
om and parasitic component dependent on 6 the PCB and power section layout and
datasheet values and assuming Vcc=15V. AsAsan
As an
an example,
example,
example, table 3 reports
table
table 33reportsRGoff
reports for
RRGoff two
forpopular
Gofffor twopopular
two IGBT to
popular IGBT to
IGBT to withs
withs
connections.
withstand dV /dt = 5V/ns.
Another way to size the gate resistors is following power dissipation constraints. This wa
out
Sizing the turn-off gate resistor investigated here. NOTES: The
NOTES: The above-described
above-described equations equations are are intended
intended to to be
be an
an
resistances
resistances sizing.
sizing. More
More accurate
accurate
NOTES: The above-described equations are intended to be sizing
sizing may
may take
take into
into account
account
and parasitic
and parasitic component component dependent dependent on on the the PCB PCB and and pow pow
The worst case in sizing the turn-off resistor RGoff is when an approximated way for the gate resistances
www.irf.com 6 6 sizing. More
www.irf.com connections.
connections.
the collector of the IGBT in off state is forced to commutate by accurate Anothersizing
Another waymay
way totosize takethe
size intogate
the account
gate more is
resistors
resistors precise
is following
followingdevice power dissipa
power dissipa
1 investigatedhere.
investigated here.
This is true under the assumption that gate voltage remains fixed during dV/dt. The resu
For more information in North America call +1 310 252 7105, inwhenever
reasonable CIES
Europe cal l +49 is884
6102 at 311,
least twousorder
or visit of magnitude
at www.irf.com greater than C RES),
DT04-04

www.irf.com 11
This
Thisisistrue
trueunder
under the
theassumption
assumptionthat
thatgate
gatevoltage
voltageremains
remains fixe
fixe
 DT04-4 revA
Using Monolithic High Voltage Gate Drivers Using monolithic high voltage gate drivers

Table 1: tsw driven RGon sizing (for RDRp = 7 )

IGBT Qge Qgc Vge* tsw Iavg Rtot RGon std commercial value Tsw
IRGP30B120K(D) 19nC 82nC 9V 400ns 0.25A 24 RTOT - RDRp = 17 18 420ns
IRG4PH30K(D) 10nC 20nC 9V 200ns 0.15A 40 RTOT - RDRp = 33 200ns

Table 2: dVOUT/dt driven RGon sizing (for RDRp = 7 )

IGBT Qge Qgc Vge* CRESoff Rtot RGon std commercial value dVout/dt
IRGP30B120K(D) 19nC 82nC 9V 85pF 14 RTOT - RDRp = 7 8.2 4.5V/ns
IRG4PH30K(D) 10nc 20nC 9V 14pF 85 RTOT - RDRp = 78 82 5V/ns
DT04-4 revA
Table 3: RGoff sizing
IGBT Vth(min)Using monolithic
CRESoff RGoffhigh voltage gate drivers
IRGP30B120K(D) 4 85pF RGoff 4
IRG4PH30K(D) 3 14pF RGoff 35
PARASITIC
ble 1: tsw driven ELEMENT
RGon sizing (for RDRp = EFFECTS
7 )
GBT Qge andQgc
modelling Vge*
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the PCB and std
ercommercial
stage it is value Tsw
very important to know the effects of inductive
In figure 5 a single-phase motor drive power stage and its driver is shown. Some of the
GP30B120K(D) 19nC
power 82nC
section layout 9V
and 400ns
related 0.25A
connections. 24 RTOT - RDRp = 17 elements.
parasitic 18 In420ns
normal operation mode the fast voltage
characteristics of the driver and the power stage will be analyzed.
G4PH30K(D) 10nC 20nC 9V 200ns 0.15A 40 RTOT - RDRp = 33 200ns
Another way to size the gate resistors is following power variations, induced by a fast current change, may influence
DC+ (high voltage supply) L R

ble 2: dVOUT/dt drivenconstraints.

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GBT Qge Qgc Vge* CRESoff Rtot RGon std commercial In presence
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GP30B120K(D)
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GBT Vth(min) ELEMENT
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connections between ground pins and board ground for all
LOAD OUT
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GP30B120K(D) 4 85pF RGoff 4 V SS gate drivers
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G4PH30K(D) 3 14pF RGoff 35
L
low side
In figure 5 a single-phase motor drive power stage and its
driver
DT04-4 revA
ARASITIC ELEMENT EFFECTS
driver is shown. Some of the characteristics of the driver and
GATE DRIVER COM below Ground (Vss-COM)
Q
the power stage will drive
be analyzed.
D V
Using monolithic high voltage gate drivers
power To properly
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L L FDL
figure 5 a single-phase motor stage its driver is shown. Some of the
COM
aracteristics of the driver and the power stage will be analyzed. Low side IGBT is considered to explain COM below Vss
COM
L R event.
below
DC- GroundFigure 6 shows one of the possible configurations of
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DC-
DC+ (high voltage supply) DC+
L R
DC+

GND Low side IGBT the parasitic elements

is considered in the
to explain COMhalf bridge
below Vss configuration
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shows one of the
possible configurations of the parasitic elements in the half bridge configuration (here emitter
Figure 5: Parasitic elements in theis power
sense shunt included stage
for completeness).
QH DH VFDH

To properly drive the power stage it is Vvery important to know the effects of inductive parasitic
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In presence of high and low power signals

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avoid ground loops on boardV or ground planes

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close to the switching portions of the board. This
R VG
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L GOFF
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driver
make star connections between ground pins and board ground for all gate drivers (see layout ON
VE
V
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Q D V L L
COM

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SS

GATE DRIVER

COM
RSENSE

LDC- RDC-
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LDC- RDC-
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Figure 5: Parasitic elements in the power stage Figure 6: Parasitic elements during low-side turn-off

Consider to turn off (dotted arrow) the low side IGBT when load current is flowing through it (bold
properly drivewww.irf.com
the power stage it is very important to know the arrow). effectsAsoftheinductive turns off the current flowing 8
parasitic
power device in the parasitic inductance (LDC-)
ments. In normal operation mode the fast voltage variations, induced by a fast current
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For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us voltage
changes rapidly induced pushes COM below ground. The amount
at www.irf.com DT04-04of voltage
flyback is governed by the well known law:
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presence of high and low power signals both referenced to the same VL ground,
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This equation relates COM undershoot (strictly dependent on inductance voltage) to the slope of
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 RGOFF VG
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ON
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Using Monolithic High Voltage Gate Drivers
GATE DRIVER

emitter sense shunt is included for completeness).
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RSENSE
NOTES: IGBT short circuit desaturation easily generate high
collector dV/dt. IGBT gate is pulled above the local supply by
R DC-gate-collector stray capacitance.

device turns off the current flowing in the parasitic inductance In some cases (usually when turn-on resistor is low) a fast
Figure 6: Parasitic elements during low-side turn-off
(LDC-) changes rapidly and the induced voltage pushes COM diode is needed between IGBT gate and local supply to DT04-4 pro- revA
below ground. tect the driver output (figure 8).
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VOUT
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thevoltage gate drivers
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Figure
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spikes under The advantage of inductance
the zener(LisDC-both , see figure
to protect the driver out-
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As an alternative voltage
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clamp drivers
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put, sinking the current generated by the collector between IGBT gatedV/dt,
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to keep
The advantage IGBT
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the driver output,control.
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This is particularly particularlyduringimportant
IGBT turn-off during IGBT
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www.irf.com spikes under VSS due to DC- stray inductance
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Figure 7: CCOM and RCOM added ON
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To avoid noise coupling to VCC size the rule COM << 1 as requiredC by the application.GND
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size
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NOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulledFigure 9: zener protection for IGBT gate-emitter LDC- flyback

above the local supplyNOTES: IGBT short circuit desaturation easily generate high collector dV/dt. IGBT gate is pulled
by the gate-collector stray capacitance. Figure 9: zener protection for IGBT gate-emitter
above the local supply by the gate-collector stray capacitance.
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
In some cases (usually when turn-on resistor is low) a fast diode is needed between IGBT gate
and local supply to protect the driver
and local supplyoutput (figure
to protect the8).
driver output (figure 8).
For more information in North America call +1 310 252 7105, in Europewww.irf.com
cal l +49 6102 884 311, or visit us at www.irf.com DN04-04
www.irf.com 11
11
 DT04-4 revA
Using Monolithic High Voltage Gate Drivers
Using monolithic high voltage gate drivers
DT04-4
DT04-4 revA
revA Using monolithic
Using monolithic hig
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monolithic high
high voltage
voltage gate
gate drivers
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DT04-4V revA
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(R sizing section). RBOOT+RVS).
GOFF
Resistor between Vs and Vout
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12
 Using Monolithic High Voltage Gate Drivers

2. It is also important to notice that the current developed

across RVS during initial bootstrap charge may be such that
a relevant voltage is developed between the high side IGBT
emitter and the VS pin. This voltage may be brought to the
high side output (usually HO) through the HO-VS ESD prot- DT04-4 revA
ection diode. In this case it must be verified that IGBT gate
Using(gate
doesnt turn on at bootstrap start-up monolithic high
resistor and voltage gate drivers
gate-
emitter capacitance help to filter out this pulse). This may
In this casecause
it must be verified
a short that IGBT
shoot-through gate doesnt
at inverter output.turn on at bootstrap start-up (gate
resistor and gate-emitter capacitance help to filter out this pulse). This may cause a short
shoot-through at inverter output.
3. RVS
3. RVS takes also parttakes also part
in turn-on in turn-on
(RGON +RVS) an(RGON+RVS) an
turn-off turn-offsizing
resistor resis-(RGOFF+RVS) as shown
in figure 12.tor sizing (RGOFF+RVS) as shown in figure 12.

Rboot Dboot
DC+

VCC VB
Cboot
ON RGON

QH DH
OFF RGOFF
VSS VS RVS

GATE DRIVER VOUT

QH DH

Figure 11: RVS connection

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 DT04-4 revA
Using Monolithic High Voltage Gate Drivers DT04-4
Using monolithic high voltage revA
gate drivers
DT04-4 revA
DT04-4 revA
Using monolithic high voltage gate drivers
Dboot
DC+
Using monolithic high
D voltage gate drivers
DC+

Using monolithic high voltage gate drivers

RBOOT R BOOT
boot

DC+ DC+
RBOOT Dboot RBOOT Dboot
DC+ DC+
Dboot VCC VB Dboot VCC VB
RBOOT Cboot DC+ RBOOT Cboot DC+
ON
RBOOT Dboot RBOOT Dboot
RGOFF
CVCC CVCC
VCC VB QH DH VCC VB
Cboot Cboot QH DH
ON
VB
OFF
VB RGON
VCC VCC
VSS VS Cboot RGOFF VSS VSCboot
CVCC VB CVCC ON VB
VCC QH DH VCC
Cboot RGOFF Cboot QH DH
CVCC GATEOFF
DRIVER CVCC ON GATE DRIVER
QH DH RGON
VSS RGOFF VSS VS
CVCC VS RVS VOUT CVCC RVSQH DH VOUT
OFF QH DH RGON
VSS VSS VS DRIVER QH DH
VS
GATE DRIVER GATE
OFF
RGON
VSS VS VSS VS
GATE DRIVER RVS VOUT GATE DRIVER RVS VOUT
GATE DRIVER RVS GATE DRIVER RVS
VOUT VOUT
RVS Figure
V
12: Gate turn-on and turn-off with RVS
OUT
RVS VOUT

Figure 12: Gate turn-on and turn-off with RVS

Clamping diode for Vs only the HV diode is used.
Clamping diode forFigure Vs 12: Gate turn-on and turn-off with RVS
Figure 12: Gate turn-on and turn-off The clampwith must
RVS be connected to COM pin (just in some cas-
In the previous
Clamping paragraph
diode it
for has
Vs been
In the previous paragraph it has been supposed supposed that D BOOT
es to Vss pin)
that DBOOT keeps according to device
switched off datasheet.
considering Thissuch
information
Clamping
keeps switched
events diode
offacting for
considering Vs
at high such events acting at high fre- can be usually found under the absolute maximum ratings.
frequency.
Clamping thediode for
thisVs
quency. InWhenever previous assumption
paragraph is not
it has beenverified,
supposed whilethatVS D follows VOUT, switched
BOOT keeps VB can be off tied to VCC by
considering suchthe
In the boostrap
events
previous acting diode.at
paragraph In
high this case
frequency.
it has
Whenever this assumption is not verified, while VS followsbeenthe difference
supposed between
that D V and
keeps
PCB LAYOUT TIPS
BOOT B V should
switched
S be
off kept inside
considering the
such absolute
In theWhenever
events previous
acting atparagraph
maximum specification
this
high assumptionit has
frequency. (see been
isICnot supposed
datasheet): that DV
verified, while keeps Vswitched
S follows
BOOT OUT, VB can off considering
be tied to VsuchCC by the
VOUTevents
, VB canacting
be tiedattohigh VCC by the
frequency. boostrap diode. In this case
boostrap diode. In this case the difference between V
Whenever this assumption is not verified, while VS followsB VOUT, SVB can be tied to VCC by the and V should be kept inside the absolute
theWhenever
difference
boostrapmaximum between
this
diode. V
assumption and
specification
VB VS < VVBS _ abs max
In this
B case V Sis should
not
(see
the IC be kept
verified, inside
while
datasheet):
difference between the
V SV B andDistance
follows V VS
,from
should
OUT V B high
can
be to
be
kept low
tiedvoltage
inside to V
the CC by the
absolute
boostrap
absolute
maximum diode.
maximum In this case
specification
specification (see (seethe
IC IC datasheet):between VB and VS should be kept inside the absolute
difference
datasheet):
maximum specification
VInB order
VS <toVVBS (see IC datasheet):
keep maxspecification, a clamp device To
_ absin minimize
should be the noise coupled
positioned betweenbetween
VSS the
andsignals
VS asreferred
VB Vshown
S < VVBS in figure 13, where a zener diode and a 600V diode are placed.
_ abs max to ground and those floating its strongly recommended to
VB VInS order
< VVBSto_ abskeepmax in specification, a clamp deviceplace should be positioned
components tied to between VSS and
floating voltage VShigh
in the as voltage
InInorder Zener
shown
orderto to
keep voltage
in
keepinfigure must
specification, be asized
13, where
in specification, clamp afollowing
a zener clampdiode
device the
and
device
should rule:
ashould
be 600Vsidediode
be are placed.
of positioned
device (VB, Vbetween
side) V
whileSStheand V
other as
Scomponents in the
S
In orderinto
shown keep13,
figure in where
specification,
a zener adiode
clamp and device
a 600V should
diode be
are positioned
placed. between VSS and VS as
positioned between VSS and VS as shown in figure 13, where a opposite side.
shownZenerVinand
figure
voltage
V600V 13, where
mustVbe a zener
sized diode andthe
following a 600V
rule: diode are placed.
zener Z a
diodevoltage max are
VB _ absdiode CCplaced.
Zener must be sized following the rule:
Zener
Zenervoltage Vmust
Vvoltage must be sized Vfollowing
besized the rule:
following the rule: Ground plane
InZ most VBof the
_ abs maxcases CCthe use of a zener is not necessary, and only the HV diode is used.
VZ VVB _ abs max VCC
VZ In
VThe
most
VB clamp
_ abs max VCC
of themust bethe
cases connected
use of a to COM
zener is pin (just inGround
some
not necessary, plane
and onlymust
cases not
HVbe
to Vss
the placed
pin)
diode under or
according
is used. to nearby
devicethe high
In mostdatasheet. Thisthe
of the cases information can be
use of a zener is usually found voltage
not necessary, under floating
the
and only the side
absolute tomaximum
HV diodeminimize noise coupling.
ratings.
is used.
In most
Theof the cases
clamp must the use
be of a zener
connected tois not
COM necessary,
pin
In most of the cases the use of a zener is not necessary, and (just inand only
some the
cases HVto diode
Vss is
pin) used.
according to device
datasheet.
The clamp must This informationtocan
be connected COMbe usually
pin (justfound
in someunder the absolute
cases maximum
to Vss pin) ratings.
according to device
The clamp This
datasheet. mustinformation
be connected can to
beCOM
usually pinfound
(just under
in some thecases
absoluteto Vss pin) according
maximum ratings. to device
datasheet. This information can be usually found under the absolute maximum ratings.

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 DT04-4 revA
Using Monolithic High Voltage Gate Drivers
Using monolithic high voltage gate drivers DT04-
DC+ a voltage across the gate-emitterUsing monolithic
increasing high voltage
the possibility of gate
RBOOT Dboot
self turn-on effect. For this reason is strongly recommended to
place the gate resistances close together and to minimize the
IGC
loop area (see figure 14).
VB VB/ VCC
VCC gate
Cboot
ON resistance CGC
Routing and placement example
CVCC HOP/LOP
QH DH HON/LON
VSS or COM
RGON We consider, as example, the IR2214 a high voltage and high
VS
(see comments) output current gate driver, seeGate the lead
Drive assignments in figure
GATE DRIVER 15. Loop VGE
RVS VOUT Figure 16 shows one of the possible layout solutions using a
VS/COM
3 layer PCB. This example takes into account all the previous
considerations. Placement and routing for supply capacitors
Figure
and gate resistances in the14: gate
high anddrive loop side minimize
low voltage
Figure 13: Clamping structure with zener diode respectively supply path and gate drive loop. The bootstrap
Routing and placement diode is placed under the device to have the cathode as close
example
B LAYOUT TIPS
Supply capacitors as possible to bootstrap capacitor and the anode far from high
ance from high to low voltage We consider, as example, voltagethe
andIR2214
close to aVCChigh
. voltage and high output current gate driver
lead assignments
If the output stages are able to quickly turn on IGBT with in figure 15.
minimize the noise coupled between the signals referred to ground and those floating its
high
gly recommended to value of current,
place the supply
components tied to capacitors must in
floating voltage bethe
placed
high as
voltage side of HIN 1 24 DSH
ce (VB, VS side)close
while as
thepossible
other components in the opposite side.
to the device pins (VCC and VSS for the ground LIN VB

tied supply, VB and VS for the floating supply) in order to mini- FLT_CLR N.C.
und plane
mize parasitic inductance/resistance. SY_FLT HOP

FAULT/SD HON
nd plane must not be placed under or nearby the high voltage floating side to minimize noise
SSOP24
VSS VS
ling.
Gate drive loops SSDL SSDH

ply capacitors COM N.C.

LON N.C.
Current loops behave like an antenna able to receive and
e output stages are able to quickly turn on IGBT with high value of current, the supply LOP N.C.

citors must betransmit

placed as EM noise.
close In order to
as possible to the
reduce
deviceEMpins
coupling
(VCC andandVSSim-for the ground VCC N.C.

supply, VB and prove

VS for the
the floating
power supply) in order
switch turn to minimize
on/off parasiticgate
performances, inductance/resistance.
drive DSL 12 13 N.C.

loops must be reduced as much as possible. Figure 14 shows

e drive loops
the high and low side gate loops. Figure 15: IR2214 lead assignments
ent loops behaveMoreover,
like an antenna
currentable
cantobereceive andinside
injected transmit
the EM
gatenoise.
drive In
looporder to reduce
coupling and improve the power switch turn on/off performances, gate drive loops must be DT04-4 revA
Figure 16 The shows one of the possible layout solutions using a 3 layer PCB. This exam
ced as much asvia the IGBT
possible. collector-to-gate
Figure 14 shows the parasitic capacitance.
high and low side gate loops.par-
over, current asitic
can be auto-inductance
injected inside ofthe Using
thegate
gatedrive
loop into
monolithic account
loop via high
contributesthetoIGBT allcollector-to-gate
voltage
develop thegate
previous
driversconsiderations. Placement and routing for supply capac
gate resistances
sitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop in the higha and low voltage side minimize respectively supply path
ge across the gate-emitter increasing the possibility of selfdrive turn-onloop. The
effect. For bootstrap
this reason diode
is is placed under the device to have the cathode as
gly recommended to place the gate resistances close together possible
and toto
IGC bootstrap
minimize area and the anode far from high voltage and close to VCC.
capacitor
the loop
figure 14).
VB/ VCC
gate
resistance CGC
HOP/LOP
irf.com HON/LON 16

Gate Drive
Loop VGE

VS/COM

Figure 14: gate drive loop

uting and For more information

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example DN04-04

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output current gate driver, see the
d assignments in figure 15.
 DT04-4 revA
Using Monolithic High Voltage Gate Drivers Using monolithic high voltage gate drivers

R2 D2
VGH DC+
R3
C1
R4 VEH
IR2214

D1
R5
D3 Phase VCC R1
VGL
R6 C2

R7 VEL

Figure 16(a): TOP Figure 16(b): BOTTOM

Referred to figure 16:

Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3

Figure 16(c): Ground plane

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