SEMICONDUCTOR TECHNICAL DATA


   

  
HighPerformance SiliconGate CMOS J SUFFIX
CERAMIC PACKAGE
The MC54/74HC245A is identical in pinout to the LS245. The device 20
CASE 73203
inputs are compatible with standard CMOS outputs; with pullup resistors, 1
they are compatible with LSTTL outputs.
The HC245A is a 3state noninverting transceiver that is used for 2way
asynchronous communication between data buses. The device has an N SUFFIX
activelow Output Enable pin, which is used to place the I/O ports into PLASTIC PACKAGE
20 CASE 73803
highimpedance states. The Direction control determines whether data
flows from A to B or from B to A. 1

Output Drive Capability: 15 LSTTL Loads DW SUFFIX

Outputs Directly Interface to CMOS, NMOS, and TTL 20 SOIC PACKAGE
1
Operating Voltage Range: 2 to 6 V CASE 751D04
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION
In Compliance with the Requirements Defined by JEDEC Standard MC54HCXXXAJ Ceramic
No. 7A MC74HCXXXAN Plastic
Chip Complexity: 308 FETs or 77 Equivalent Gates MC74HCXXXADW SOIC

LOGIC DIAGRAM
PIN ASSIGNMENT
2 18
A1 B1 DIRECTION 1 20 VCC
3 17
A2 B2 A1 2 19 OUTPUT ENABLE
4 16
A3 B3 A2 3 18 B1
A 5 15 B
A4 B4
DATA DATA A3 4 17 B2
6 14
PORT A5 B5 PORT
7 13 A4 5 16 B3
A6 B6
8 12 A5 6 15 B4
A7 B7
9 11 A6 7 14 B5
A8 B8
A7 8 13 B6
1
DIRECTION A8 9 12 B7
19
OUTPUT ENABLE GND 10 11 B8

PIN 10 = GND
PIN 20 = VCC

FUNCTION TABLE
Control Inputs
Output
Enable Direction Operation
L L Data Transmitted from Bus B to Bus A
L H Data Transmitted from Bus A to Bus B
H X Buses Isolated (HighImpedance State)
X = dont care

10/95

Motorola, Inc. 1995 1 REV 6



MC54/74HC245A

MAXIMUM RATINGS*

Symbol Parameter Value Unit This device contains protection

VCC DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V circuitry to guard against damage

due to high static voltages or electric

Vin DC Input Voltage (Referenced to GND) 1.5 to VCC + 1.5 V
fields. However, precautions must

VI/O DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V be taken to avoid applications of any

Iin DC Input Current, per Pin 20 mA voltage higher than maximum rated
voltages to this highimpedance cir-

II/O DC Output Current, per Pin 35 mA cuit. For proper operation, Vin and

75 Vout should be constrained to the

ICC DC Supply Current, VCC and GND Pins mA
v
range GND (Vin or Vout) VCC. v

PD Power Dissipation in Still Air, Plastic or Ceramic DIP 750 mW Unused inputs must always be
SOIC Package 500

tied to an appropriate logic voltage

Tstg Storage Temperature 65 to + 150 _C level (e.g., either GND or VCC).

Unused outputs must be left open.

TL Lead Temperature, 1 mm from Case for 10 Seconds _C

(Plastic DIP or SOIC Package) 260

(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.

Derating Plastic DIP: 10 mW/_C from 65_ to 125_C

Ceramic DIP: 10 mW/_C from 100_ to 125_C

SOIC Package: 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TA Operating Temperature, All Package Types 55 + 125 _C

tr, tf



Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

v v
VCC 55 to

Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

v
VIH Minimum HighLevel Input Vout = 0.1 V or VCC 0.1 V 2.0 1.5 1.5 1.5 V
Voltage |Iout| 20 A 4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

v
VIL Maximum LowLevel Input Vout = 0.1 V or VCC 0.1 V 2.0 0.5 0.5 0.5 V
Voltage |Iout| 20 A 4.5 1.35 1.35 1.35

6.0 1.8 1.8 1.8

v

VOH Minimum HighLevel Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| 20 A 4.5 4.4 4.4 4.4

v 6.0 5.9 5.9 5.9

v
Vin = VIH or VIL |Iout| 6.0 mA 4.5 3.98 3.84 3.70

|Iout| 7.8 mA 6.0 5.48 5.34 5.20

v
VOL Maximum LowLevel Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V

v
Voltage |Iout| 20 A 4.5 0.1 0.1 0.1

v
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| 6.0 mA 4.5 0.26 0.33 0.40

|Iout| 7.8 mA 6.0 0.26 0.33 0.40

Iin Maximum Input Leakage Current Vin = VCC or GND, Pin 1 or 19 6.0 0.1 1.0 1.0 A

IOZ Maximum ThreeState Output in HighImpedance State 6.0 0.5 5.0 10 A

Leakage Current Vin = VIL or VIH

Vout = VCC or GND, I/O Pins

ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 4 40 160 A

Current (per Package) Iout = 0 A
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).

MOTOROLA 2 HighSpeed CMOS Logic Data

DL129 Rev 6
 MC54/74HC245A

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

v
v
VCC 55 to

Symbol Parameter V 25_C 85_C 125_C Unit

tPLH, Maximum Propagation Delay, A to B, B to A 2.0 75 95 110 ns

tPHL (Figures 1 and 3) 4.5 15 19 22

6.0 13 16 19

tPLZ, Maximum Propagation Delay, Direction or Output Enable to A or B 2.0 110 140 165 ns

tPHZ (Figures 2 and 4) 4.5 22 28 33

6.0 19 24 28

tPZL, Maximum Propagation Delay, Output Enable to A or B 2.0 110 140 165 ns
tPZH (Figures 2 and 4) 4.5 22 28 33

6.0 19 24 28

tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns

tTHL (Figures 1 and 3) 4.5 12 15 18

6.0 10 13 15

Cin Maximum Input Capacitance (Pin 1 or Pin 19) 10 10 10 pF

Cout Maximum ThreeState I/O Capacitance 15 15 15 pF

(I/O in HighImpedance State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).

Typical @ 25C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Transceiver Channel)* 40 pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS
VCC
DIRECTION 50%
GND
VCC
tr tf OUTPUT 50%
VCC ENABLE GND
INPUT 90% tPZL tPLZ
A OR B 50% HIGH
10% GND
50% IMPEDANCE
tPLH tPHL A OR B
10% VOL
OUTPUT 90% tPZH tPHZ
B OR A 50% VOH
10% 90%
A OR B 50%
HIGH
tTLH tTHL
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS
TEST POINT TEST POINT
CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 k
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

* Includes all probe and jig capacitance * Includes all probe and jig capacitance

Figure 3. Figure 4.

HighSpeed CMOS Logic Data 3 MOTOROLA

DL129 Rev 6
MC54/74HC245A

EXPANDED LOGIC DIAGRAM

2
A1
18
B1

3
A2
17
B2

4
A3
16
B3

5
A4
A
15
DATA B4 B
PORT DATA
6 PORT
A5
14
B5

7
A6
13
B6

8
A7
12
B7

9
A8
11
B8

1
DIRECTION

19
OUTPUT ENABLE

MOTOROLA 4 HighSpeed CMOS Logic Data

DL129 Rev 6
 MC54/74HC245A

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC PACKAGE NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
20 11 CASE 73203 POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
ISSUE E 2. DIMENSION L TO CENTER OF LEADS WHEN
1 10
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
MILLIMETERS INCHES
A DIM MIN MAX MIN MAX
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C L C 3.81 5.08 0.150 0.200
F D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
N J 0.20 0.30 0.008 0.012
J K 3.18 4.06 0.125 0.160
H K L 7.62 BSC 0.300 BSC
D G M M 0_ 15 _ 0_ 15_
N 0.25 1.02 0.010 0.040
SEATING
PLANE

N SUFFIX
A PLASTIC PACKAGE
CASE 73803 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 ISSUE E Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
T C 0.150 0.180 3.81 4.57
K D 0.015 0.022 0.39 0.55
SEATING
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F K 0.110 0.140 2.80 3.55
J 20 PL
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M M 0_ 15 _ 0_ 15_
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01

DW SUFFIX
A PLASTIC SOIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER
CASE 751D04 ANSI Y14.5M, 1982.
20 11 ISSUE E 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
B 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

20X D MILLIMETERS INCHES

J DIM MIN MAX MIN MAX
0.010 (0.25) M T A S B S A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
F D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R X 45 _ J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
C R 0.25 0.75 0.010 0.029

T SEATING
PLANE
18X G M
K

HighSpeed CMOS Logic Data 5 MOTOROLA

DL129 Rev 6
MC54/74HC245A

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HC245A/D*
CODELINE MC54/74HC245A/D
MOTOROLA 6 HighSpeed CMOS Logic Data
DL129 Rev 6