ANALOG CIRCUITS:
TECHNIQUES AND APPLlCATIONS
edited by
Lawrence P. Huelsman
University of Arizona, Tuscon
and
Georges G.E. Gielen
Katholieke Universiteit Leuven Belgium
A Special Issue of
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Consulting Editor
Mohammed Ismail
Ohio State University
Related titles:
ANAWG CMOS FILTERS FOR VERY HIGH FREQUENCIES, Bram Nauta
ISBN: 0792392728
ANAWG VLSI NEURAL NETWORKS, Yoshiyasu Takefuji
ISBN: 0792392738
INTRODUCTION TO THE DESIGN OF TRANSCONDUCTORCAPACITOR
FILTERS, Jaime Kardontchik
ISBN: 0792391950
VLSI DESIGN OF NEURAL NETWORKS, Ulrich Ramacher, Ulrich Ruckert
ISBN: 0792391276
WWNOISE WIDEBAND AMPLIFIERS IN BIPOLAR AND CMOS
TECHNOLOGIES, Z.Y. Chang, Willy Sansen
ISBN: 0792390962
ANAWG INTEGRATED CIRCUITS FOR COMMUNICATIONS: Principles,
Simulation and Design, Donald O. Pederson, Kartikeya Mayaram
ISBN: 079239089X
SYMBOLIC ANALYSIS FOR AUTOMATED DESIGN OF ANAWG
INTEGRATED CIRCUITS, Georges Gielen, Willey Sansen
ISBN: 0792391616
AN INTRODUCTION TO ANALOG VLSI DESIGN AUTOMATION,
Mohammed Ismail, Jose Franca
ISBN: 0792390717
STEADYSTATE METHODS FOR SIMULATING ANALOG AND
MICROWAVE CIRCUITS, Kenneth S. Kundert, Jacob White, Alberto
SangiovanniVincentell i
ISBN: 0792390695
MIXEDMODE SIMULATION: Algorithms and Implementation, Reseve A.
Saleh, A. Richard Newton
ISBN: 0792391071
ANALOG VLSI IMPLEMENTATION OF NEURAL NETWORKS, Carver A.
Mead, Mohammed Ismail
ISBN: 0792390407
Contents
Symbolic Analysis of LargeScale Networks Using a Hierarchical Signal Flowgraph Approach .....
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Marwan M. Hassoun and Kevin S. McCarville 31
More Efficient Algorithms for Symbolic Network Analysis: Supernodes and Reduced Loop Analysis
Ralf Sommer, Dirk Ammermann and Eckhard He mig 73
Llbrary of Congrcss CataloginginPublication Data
Editorial
We are pleased to announce that starting with this issue of Analog Integrated Circuits and Signal Processing (Volume
3, 1993), the Journal will appear six times a years instead of four. This increase in issues per year is intended
to keep up with the increased number of high quality papers being submitted for publication.
We are also very pleased to welcome as members of the Editorial Board, Drs. John Choma, Jr., Johan Huijsing,
Edgar SanchezSinencio, Trond Srether and Gabor Ternes, and we look forward to the valuable contributions they
will make to our Journal.
Mohammed Ismail
David G. Haigh
Nobuo Fujii
EditorsinChief
Analog Integrated Circuits and Signal Processing 3, 7 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Guest Editorial
This Special Issue is dedicated to the techniques and applications of symbolic analysis for analog circuits. The
general topic of analog circuit analysis may be divided into two main categories. The first of these is usually called
numeric analysis. In this, numeric values of ohms, henries, farads, gain, and so forth, are assigned to the appropri
ate circuit elements. The interconnection of the elements in the circuit is specified by topological information,
typically given as node numbers. The goal of the analysis is the generation of numeric information giving sinusoidal
steadystate or timedomain response information, which is presented either in tabular form or, more usually, as
plotted information. Examples of numeric analysis are readily seen as the output from the SPICE program or
its PC counterpart PSpice. The second general category of analog circuit analysis is the one addressed in this Special
Issue, namely symbolic analysis. In this, literal names (symbolic values) are assigned to the elements of the circuit.
These literal names represent the symbolic (nonnumeric) values of the ohms, henries, farads, gain, and so forth
of the circuit elements. These names, together with the topological interconnection information, are used to create
a network function in the complex variable s or z which gives a description of the relation between the transformed
output and input variables of the circuit. In such a network function, the coefficients of various powers of s or
z appear as explicit functions of the literal names of the circuit elements.
Symbolic analysis and the computer techniques for automated symbolic analysis, i.e., the automatic generation
of analytic equations describing a circuit's electrical behavior, have reattracted much attention in recent years.
They represent a natural way of analyzing a circuit, a way taught in all basic engineering courses and practiced
by reallife designers. Symbolic analysis is far more general than numeric analysis, since if offers complete freedom
in the choice of applications, and includes sinusoidal steadystate and timedomain studies as special cases. Numeric
simulators such as SPICE have become much more popular than symbolic ones as design supporting CAD tools,
because they can rapidly and accurately simulate a circuit's behavior, including its transient response. They are
also able to simulate largersize circuits. In contrast, however, symbolic analyses can provide many results which
are simply not available from numeric simulation methods. Most importantly, they can provide explicit insight
into the dominant behavior and properties of a circuit. Among the useful applications of this insight are the deter
mination of derivatives of the network function with respect to one or more elements. Such literal information
provides direct application to sensitivity determination. Another application of the insight obtained from symbolic
analysis is the development of the equations which are required in the use of optimization techniques to provide
solutions to specific design specifications. With SPICElike numerical simulators, the same insight can only be
obtained after combining and often extrapolating the results of numerous simulation runs. In addition, symbolic
analysis can also be used in many other applications, such as in compiledcode evaluation for statistical analysis,
and automated synthesis or failure diagnosis of analog circuits, much the same way as symbolic Boolean analysis
is used for synthesis and verification of logic circuits.
For a long time, symbolic circuit analysis has been regarded as an academic topic. It is true that it has computa
tional complexity limits which have prevented it from being feasible for largesize circuits. In recent years however,
enormous progress has been made in developing more advanced techniques and algorithms for symbolic circuit
analysis. This has resulted in an extension of the functionality of symbolic simulators, including for instance the
automatic generation of simplified symbolic expressions or the automatic generation of symbolic distortion for
mulas. At the same time, the capabilities of symbolic analysis have been extended toward larger circuits by the
introduction of hierarchical methods. All these advancements have resulted in the recent development of several
successful symbolic simulators such as ISAAC, ASAP, SC, and SSPICE. As a result, symbolic analysis is finally
becoming an attractive tool to assist designers in reallife circuit design.
This Special Issue contains five selected papers that present recent developments in the field of symbolic analysis
for analog circuits. The first paper, by Amadori et aI., presents original algorithms for the direct generation 0;'
simplified symbolic transfer functions based on the relative magnitudes of the circuit elements. These simplified
expressions, which show the dominant contributions only, provide a good approximation for the overall circuit
behavior. Also, an algorithm for the simplified symbolic computation of the poles and zeroes of the transfer func
tions is described. Hassoun and McCarville, in the second paper, describe an approach to the symbolic analysis
8 Huelsman and Gielen
of largescale networks based on hierarchical decomposition. The total network is recursively decomposed into
smaller subblocks, which are analyzed separately. The expression for the total network is then obained by combin
ing bottomup the expressions for the subblocks. This tremendously reduces the CPU time and the number of
symbolic terms for large circuits. In the third paper, Fernandez et al. describe new criteria and algorithms for
the generation of simplified expressions, both for flat and hierarchical symbolic analysis. A major difference between
this approach and that given by the first paper, is that the simplification is carried out taking into account a range
of element values instead of a single nominal value for the magnitude of each circuit element. The technique of
simplification is also extended to the hierarchical formulas, which would be the result of the decomposition method
of the second paper. This combination opens new perspectives for the fast generation of both exact and simplified
symbolic expressions for large circuits. In the fourth paper, Manetti and Piccirilli show how dedicated simulators
based on compiled symbolic formulas can boost the efficiency of applications requiring repetitive circuit evaluation.
Nonlinear circuits are handled with piecewise linear approximation. The application of the method to nonlinear
circuit fault diagnosis is presented, in which the actual element values and hence also faulty components are extracted
by fitting the simulated to the measured response. Finally, in the short paper by Sommer et al., two alternative
network equation formulations are highlighted: supernode and reduced loop analysis. Compared to the classical
node, loop, and MNA formulations, the described variants result in simpler equations. This is advantageous both
for manual analysis as well as for computerized symbolic analysis.
The editors would like to thank all the authors who submitted papers, all the reviewers who participated in
the final selection of the papers, and the Kluwer Editorial Staff for their efforts in creating this Special Issue.
We hope that this Issue will provide you, the reader, with a useful introduction to the potential and power of the
use of symbolic analysis techniques in analog design.
Lawrence P. Huelsman
Georges G.E. Gielen
Lawrence P. Huelsman received the BSEE degree from Case Institute of Technology and the MSEE and Ph.D.
degrees from the University of California at Berkeley. He is a Fellow of the Institute of Electrical and Electronic
Engineers. He currently holds an appointment as Professor Emeritus of Electrical and Computer Engineering at
the University of Arizona.
Dr. Huelsman is the author or coauthor of sixteen books including: Basic Circuit Theory3rd Ed. published
by PrenticeHall, Inc.; and Operational Amplifiers: Design and Applications. Introduction to Operational Amplifier
Theory and Applications, and Introduction to the Theory and Design of Active Filters, published by the McGraw
Hill Book Company. Japanese, German, Spanish and Russian translations have been made of several of his books.
He has also published many papers in the area of active circuit theory.
He has served as Associate Editor of the IEEE Transactions on Circuit and System Theory and the IEEE Trans
actions on Education and was technical chairman of the IEEE Region Six Annual Conference. He is a member
of the steering committee for the Midwest Symposium on Circuits and Systems. He is a member of several scien
tific, engineering, and honorary societies, including Tau Beta Pi, Phi Beta Kappa, Eta Kappa Nu, and Sigma Xi. He has received the Anderson
Prize of the College of Engineering and Mines of the University of Arizona for his contributions to education.
Georges G.E. Gielen was born in HeistopdenBerg, Belgium, on August 25, 1963. He received the E.E. and
Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1986 and
1990, respectively. From 1986 until 1990, he was appointed by the Belgian National Fund of Scientific Research
as a Research Assistant at the ESAT laboratory of the Katholieke Universiteit Leuven, working on symbolic analysis
and analog design automation. From 1990 until 1991, he was connected to the University of California, Berkeley,
as a Visiting Lecturer and Visiting Research Engineer, working on behavioral models for analog integrated circuits.
In October 1991, he was again appointed by the Belgian National Fund of Scientific Research as a Senior Research
Assistant at the ESATMICAS laboratory of the Katholieke Universiteit Leuven, Heverlee, Belgium, where he is
currently heading the analog design automation group. His research interests are in the design of analog and mixed
analogdigital integrated circuits and in analog design automation (modeling and simulation, synthesis, optimiza
tion, layout and testing). He has authored or coauthored more than 30 papers, including several chapters for edited
books. In 1991, he also published a book on symbolic analysis and design automation of analog integrated circuits.
Analog Integrated Circuits and Signal Processing 3, 929 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Abstract. This contribution presents new algorithms for the automatic simplified computation of symbolic transfer
functions of linear circuits. The problem of symbolic simplification of transfer functions is defined and a set of
algorithms able to cope with this problem and the simplified computation of poles and zeroes is developed and
discussed. Results are reported with examples of circuits analyzed by our algorithms, showing good accuracy in
their approximation, when compared to the corresponding SPICE simulations. Our technique merges the simplifica
tion procedure and the evaluation of the transfer functions, thus achieving significant improvements in terms of
CPU time, compared with direct evaluation of the functions themselves.
its terms. It can be applied to the fully expanded expres P = 2..: ai si (1)
sion of the transfer function. The second and third i=oO
algorithms perform the simplification during the com
where r, maximum degree in s of the polynomial,
putation of the determinant of the admittance matrix
depends upon the number of circut capacitors and the
at zero frequency and in the frequency domain respec
topology of the network.
tively. The fourth algorithm finds the locations of poles
and zeroes of a transfer function by exploiting the pole
PROPERTY 2. If the circu it is stable, polynomial (I) is
splitting and pole clustering hypotheses. All these algo
complete, that is,
rithms are proved to fulfill a consistent definition of
optimal symbolic simplification. The problems raised ai ~ 0, i = 0, ... , r
by symmetric and antisymmetric architectures, due to
the fact that their transfer functions are not in minimal Furthermore all its coefficients have the same sign.
form, are investigated and suitable approaches are sug
gested. The required parameter classification does not PROPERTY 3. The coefficients ai are given by
rely on the user's expertise but is automatic and based Ki
on simulation. a I = L..J
""" A I
k
(2)
The organization of this paper is as follows. In Sec k=l
tion 2 the basic properties of the admittance matrix are
recalled and the symbolic structure of a transfer func where K i indicates the number of monomials in ai and
tion is described. In Section 3 two algorithms for the At is the monomial given by the product of n factors
automatic simplification of a transfer function at zero of the form
frequency are illustrated. Their extension to the general k
Aik = (g\k ... gni
k )(CI ' .. Ck)
i (3)
case in the frequency domain is described in Section
4. In Section 5 the implementation of the algorithms where gf are conductances or transconductances and
is illustrated and results showing the suitability of our Cf are capacitances. If i = 0,
symbolic simplification are reported. Finally, in Section
n
6 some conclusions are drawn.
A~ = II (gt) (4)
i=l
The transfer functions of an nport linear circuit are Unfortunately the symbolic computation of the above
given by the ratios of determinants derived from the polynomials leads to very complex expressions even
nodal definite admittance matrix (DAM) of the circuit. in simple cases [7, 8]. Such expressions are difficult
In what follows we will recall some properties of the to evaluate and to use for design purposes. Consider,
DAM. Proofs of these properties can be found in [17, for instance, the twostage operational amplifier shown
pp. 197 ff], along with a comprehensive survey of this in figure 1, whose equivalent circuit is shown in figure
subject. For sake of simplicity and since our emphasis 2. Its admittance matrix is of the fifth order and, even
is on problems stemming from the linearization of cir keeping the differentialstage transistor matching into
cuits implemented in integrated technology, the only account, it contains 14 different parameters: the exact
circuit elements we consider are conductances, capaci expression of its differential gain has 390 monomials,
tances and voltagecontrolled current sources. 48 in the numerator, and 342 in the denominator.
Giv~n a linear circuit with n + 1 distinct nodes, the Since even for small networks the computed expres
DAM Yassociated with it is an invertible square matrix sions are very complex, it is essential to simplify the
of size n, with the following properties. above polynomials, removing some monomials so as
to minimize the perturbation induced into the function.
PROPERTY 1. The polynomial P given by P = det(Y) The simplification procedure is based on the following
can be expressed as definitions.
Symbolic Analysis of Simplified Transfer Functions 11
Vdd
M6
Vin 1 ~ M1
I4__ _ _._ __ t.l
M2
~ Vi n2 '_~ Cc
Out
Cl
M5
Vbias   l .     H...._:..:..:,
M7
I
Vss
Fig. 1. Schematic of a twostage operational amplifier.
Gm4 v3
Gm2 ( Viol .. v5 ) .. v5
C1
Go?
DEFINITION 1. Let :71 be the set of all the monomials can be partitioned into two or more groups depending
of the coefficients of polynomial P: on their relative magnitudes. For instance, for an MaS
transistor in saturation we can assume:
:71 = {A;k; i = 0, ... , r; k = 1, ... , KJ.
Gm ~ Go (7)
We define the cardinality of P to be the cardinality of
the set :71 associated with it, namely the number of ele where Gm is the transconductance and Go is the output
ments in :71: conductance. Based on the above consideration we in
troduce the following definition.
r
card(P) = ~ K j
;=1 DEFINITION 3. An equivalence class C is the set of
circuit parameters {Ck } satisfying the following
In what follows the notation P j will denote a polyno conditions:
mial P whose cardinality is i.
1. They are dimensionally homogeneous;
DEFINITION 2. Given a polynomial PM and an integer 2. Let Ct , Cs be two classes such that Is I ~ Il I, "Is
m ~ M, the optimal simplified polynomial ofcardinal E Cs , vl E Ct. Then
ity m is the polynomial p~l whose coefficients are ISII + IS2\ ~ \ll, vlECt, VS"s2ECs (8)
composed of terms drawn from :71 and satisfying the
following condition: 1(l l11  Il21)1 ~ lsI,
c
"Is E s ' "Ill> l2 E Cj, l1 l2 (9)
The first condition is required to avoid meaningless
where 1111 indicates a suitable norm. comparisons between symbols. The second condition
allows us to consider the equivalence class as a group
Given M and m, the number of different polynomials with respect to the operation of algebraic summation.
Pm simplifying PM is given by all the combinations of Equivalence classes are based on the observation that
M terms m by m without repetitions, that is, in practical circuits most parameters are clustered in
two or more widely spaced groups. However, it is easy
[~J = (M _M~)!m! (6) to define circuits whose parameters do not satisfy the
last condition. In this case it is necessary to perform
When m is far apart from 1 and M, the number of poly a parameter transformation. If (8) does not hold for two
nomials is very high and the computational cost of an given parameters Sl, S2 E Cs whose sum appears in the
exhaustive search of p;:r is unfeasible. In fact, neglect polynomial to be simplified, then both parameters will
ing the case m :::: M because of the complexity of the be transferred into the class of larger parameters Ct.
expressions, we have that the case m :::: 1 is not rele As a consequence, they will be treated as nonnegligible
vant for applications, since there are minimum require in a number of simplification steps. The simplified ex
ments on accuracy. On the other hand, the accuracy pression will be more accurate although more compli
improves with m, since a larger number of terms makes cated. If (9) does not hold for the parameters ll' l2 E
the simplified polynomial closer to the exact one. There Ct , we introduce an additional symbol III = l2  II
fore a tradeoff is needed between the simplification in the class Cs of the small elements and we substitute
accuracy and the complexity of the final expression. all occurrences of l2 with II + Ill. If III = 0, we
simply associate the same symboll to the two different
parameters l I> l2'
3. Simplification of Transfer Functions at
As an example consider the circuit in figure 2 with
Zero Frequency
two classes of conductances:
The transfer functions for a nonlinear circuit are deter 1. Lg = large conductances
mined by its smallsignal parameters. Considerations 2. Sg = small conductances
on the relative relevance of these parameters have to
and two classes of capacitances:
be drawn in order to ensure a correct simplification.
For a given working point, it is possible to determine 1. Lc = large capacitances
the order of magnitude of each of the parameters. They 2. Sc = small capacitances
Symbolic Analysis of Simplified Transfer Functions 13
If the differential pair is matched, the parameters of exactly a terms from L g Based on this expression, the
the two input transistors are represented by the same following algorithm computes a simplified expression
symbols. When the mismatch is considered, condition for the numerator and the denominator of Ho.
(9) is satisfied if the difference between the transcon
ductances of the input pair is large compared with the ALGORITHM 1. Let Po be a polynomial in the form
output conductances of the same circuit. The classes
are then composed as follows:
1. Sg = {Go 2, Go4, Go 5 , Go6, Go?}
2. Lg = {Gm2' Gm4, Gm6, GOg} where A5
is expressed as in (11) for some integer
3. Se = {Cw , Ci } a E [0, n]. Algorithm 1 is as follows:
4. L e = {CI , CJ
set
where Cw accounts for the capacitance associated with Po = 0
the sources of the differential pair and Ci is the para a=n
sitic capacitance associated with the highimpedance do while (a ~ 0)
node. When the mismatch of the input pair t:.Gm = Add to Po all the monomials A5 with exactly a
G~  Gm\ is small, we explicitly introduce the addi ele!!1ents from L g
tional symbol t:.Gm and associate it with the class of if Po ;r= 0 then
small conductances. The class composition becomes a max = a
the following: m(a max ) = card(Po)
exit
1. Sg = {t:.Gm , Go2, Go4, Go5 , Go6, Go?}
endif
2. L g = {Gm2, Gm4, Gm6, GOg}
a = aI
3. Se = {Cw , Ci }
end do
4. L e = {CI , Ce }
At the end of the algorithm, Po is the optimal simpli
3.1. Transfer Function Simplification fied polyomial of cardinality m(a max ) of Po according
to definition (5). In fact for this polynomial the follow
The zerofrequency analysis of a linear circuit is par ing properties hold:
ticularly simple because the transfer functions are given 1. m(a max ) :S M = cardinality of the complete poly
by the ratio of tWo polynomials of degree 0 in s: nomial Po.
 Ek,Aok' 2. The monomials appearing in Po are a subset of
H.0  k" (10) those appearing in Po.
Ek"A o
where Ar Ar
and indicate monomials as in (4). No
3. Given the m(a max ) provided by Algorithm 1, defini
tion (5) is satisfied since the neglected monomials
capacitances appear in (10). Hence two equivalence are the smallest ones and their algebraic sum is
classes can be defined as follows: negligible compared with Po, by condition (9).
1. L g = the class of large conductances The simplification of the transfer function (10) can be
2. Sg = the class of small conductances carried out by applying Algorithm 1 to its numerator
Since monomials A5 contain n conductances each, and denominator respectively. The fulfillment of con
they can be rewritten in the form: dition (5) for the numerator and denominator does not
imply an optimality condition for the approximation
ex
n(X
Ho of the transfer function Ho expressed by their ratio.
A5 = II g~ II gff (11)
However, it limits the maximum range of the relative
i=\ i=\
error. In fact, let Pm Pd be respectively the numerator
where g~ are conductances in Sg, gff are in Lg, and a and denominator of Ho. Let Pn and Pd be their optimal
is an integer in [0, n]. For a given polynomial Po ap simplified polynomials computed with Algorithm 1 and
pearing at the numerator or denominator of Ho, we t:.Pm t:.Pd the respective errors Pn  Pm Pd  Pd' The
denote by mea) the number of monomials in Po with relative error on Ho is
14 Amadori, Guerrieri and Malavasi
Ii  Gm, + Gm2
o  Gm3 + Gm4
Since in general PdlPd "'" 1, the maximum error in the
transfer function is the sum of the relative errors in its and the error is given by
numerator and denominator respectively, both of which G b
are minimal, because Pn and Pd are optimal simplified EHo "'" I Gml : Gm21
polynomials.
As an example, consider the transfer function If Gmb is put in Lg , the simplified expression becomes
PROPERTY 4. Given the nXn matrix M, if every element (3). The generalization of the procedure described for
of its ith row can be written in the form the zerofrequency case is based on the application of
Algorithm 1 to each coefficient of the polynomials. In
M(i; j) =mil + mil Vj = I, ... , n
general, a simplification corresponds to introducing a
then perturbation in the coefficients of the polynomials. Its
  effects can be studied using the theory of sensitivity
det(M) det(M') + det(M")
of transfer functions [2, Chap. IS] to the variations of
  
where matrices M' and M" can be obtained from M coefficients. The error introduced by the simplification
splitting the ith row: is analyzed below under some hypotheses on the loca
tion of the zeroes of the polynomial.
M'(i, j) = mil Vj = I, ... , n
Since capacitances and conductances are not dimen
M"(i, j) = m'!
IJ Vj = I, .. , n sionally homogeneous, we cannot safely compare the
= = = respective values of these quantities, unless we use the
M(k, j) = M'(k, j) = M"(k, j)
operating frequency as normalization factor. If we want
vk ~ i, Vj I, ... , n to derive simplified equations which are not related to
the specific operating frequency, it is necessary to oper
Proof It can be found in [18, p. 161]. ate separately on capacitances and conductances, keep
ing the dominant elements of both parameter types. The
By using this property, in step 3 we can define a set of tradeoff between precision and number of monomials
matrices, whose determinants are expressed each by a is therefore unbalanced and the optimality achieved in
sum of monomials, all having the same number of lalge the zerofrequency case cannot be fully obtained in
and small conductances. By introducingj rows of Sin this case.
matrix L, we evaluate all the monomials with n  j A further precaution is required when the transfer
large conductances andj small conductances, until the function is not in minimal form. In this case coinciding
determinant is different from zero. This algorithm is zeroes and poles may occur and the final degree of the
most efficient when few substitutions of small terms exact transfer function is decreased by the correspond
allow us to find the simplified determinant. Note that ing cancellations. This is the case, in particular, of sym
an efficient implementation of this algorithm is achieved metrical and anti symmetrical circuits (see figure 3).
observing that when in step 3 j is incremented, most Therefore it is important to distinguish between alge
minors evaluated at step j  1 can be used if properly braic and symbolic simplification. While the latter is
stored. the process of selection of the most important terms
Finally, the results provided by Algorithms I and 2 of the coefficients of the polynomials, the former is the
are the same. In fact any further increase in the number cancellation of coinciding poles and zeroes.
of small terms in Algorithm 2 once condition 4 is ful
filled yields monomials which would be discarded by
Algorithm 1. At the same time, the monomials evalu
ated in step 4 when the condition is satisfied have all
the same (minimum) number of small terms and for
this reason they would be retained by Algorithm 1.
The approach shown for the zerofrequency case can PROPERTY 5. Algebraic simplification and symbolic
be extended to the frequency analysis of transfer func simplification do not commute.
tions. Since in the frequency domain capacitances have
to be accounted for, a transfer function becomes a ratio Proof The demonstration is carried out by construct
of polynomials in s, whose coefficients are of the form ing an example. Let us consider the polynomials
16 Amadori, Guerrieri and Malavasi
H*(s) ~ H(s).
then
As a further remark, notice that even the degrees of
the polynomials in H(s) and H*(s) are different. The Va = Vb
problem is due to small and otherwise negligible terms,
If its inputs are in differential mode, then
needed for the polynomial factorization of numerator
and denominator, which would disappear in the simpli Va = Vb
fied computation of determinants. Correct results are
obtained only if the algebraic simplification is per Proof Each part of the circuit shown in figure 3b is
formed before the symbolic simplification. As a conse described by the same admittance matrix, which im
quence, Algorithm 2 for the computation of simplified plies that
Symbolic Analysis of Simplified Transfer Functions 17
Ia = Yll Va + y 12 Vb + Y13 V I all significant. The algorithm for the simplified compu
{
Ib = Y21 Va + Y22 Vb + Y23 V l tation of determinants in the frequency domain follows.
II = Y31 Va + Y32 Vb + Y33 V I
ALGORITHM 3.
I~ = YIIV~ + YI2 Vt + Y13 V2
{ Ith = = Y2IV~
Y3IV~
+ Y22 Vt + Y23 V2
+ Y32 Vt + Y33 V2
1. Apply Algorithm 2 to matrices Land S. The number
k of iterations executed by this algorithm is also the
number of rows of L Denoting by r the degree in
where the symbols with the prime refer to the right part
s of the determinant, in the simplified expression
of the circuit. The following constraints, imposed by
the antisymmetry of the circuit, r
A = 2.: ai si
1=0
imply that
all the coefficients ai, i = r  k, ... , r have been
(Yll + Y22) Va + (Y12 + Y22) Vb + (Y13 VI + Y23 V2) = 0 defined, provided the zerodegree coefficient is non
zero. In fact after the substitution of k rows they are
(Y12 + Y21)Va + (Yll + Y22)Vb + (Y23 V I + Y13 V2) = 0 given by all the possible combinations of n  r + k
If VI = V2 (inputs in common mode), then conductances and r  k capacitances as in (3).
2. For each of the remaining coefficients aj, j = 1,
(YI1 + Y22  (YI2 + Y21)Va ... , r  k  1:
+ (YI2 + Y21  (YI1 + Y22)Vb = 0 If aj r! 0 it coincides with its best approximated
expressio,!, since the substitution of any further
and, consequently,
rows of S would only decrease the order of
Va = Vb magnitude of the conductance component of the
monomials.
If the inputs are in differential mode (V2 = VI), then
If aj = 0, its approximated expression is given by
(Yll + Y22 + YI2 + Y22) Va n n
+ (YI2 + Y22 + Yll + Y22)Vb = 0 aj = 2.: 2.: (Ci,.I, C i2 ,!2 ... Cij,l)
i" .. ij=l II> . . ,lj=l \.. y I
and, consequently,
j terms
{b
p.I I;Ki
k=O
if x > 0 if (Ki > 1) then
sign(x) = if x = 0 set} = 1
1 if x < 0 do while U < K;)
/* Polesplitting procedure [20J */
Proof. By construction, each ai has been obtained by Sj = bj_l/bj
discarding only the small terms from ai' Since these Sj+1 = b/bj+1
terms must fulfill the requirements of Definition 3, they if (Sj ~ Sj+l) then
cannot change the sign of the expression determined accept(sj)
by the largest terms. if U = K i  1) accept(sj+l)
else
/* Poleclustering procedure */
4.2. Computation of the Zeroes of Polynomials Solve bj +1S2 + bjs + bj  1 = 0
/* .. . using the resolving formula for second order
Poles and zeroes of a simplified transfer function are equations */
the zeroes of its denominator and numerator respec if U + 2 = K;) then
tively, which are polynomials in the form (1). Focusing accept(sj' Sj+l)
on stable polynomials only, zeroes are computed with }=}+2
the following algorithm. else
Sj+2 = bj+2/bj+1
ALGORITHM 4. Let P = I;~=I aisi be the polynomial if (Sj+2 ~ m[Sj], m[Sj+1]) then
whose zeroes have to be determined. This algorithm /* Operator mreturns the real part of a number */
is divided in three phases. In the first phase an attempt accept(sj' Sj+l)
is made to determine the zeroes of P by using poly } =} + 2
nomial factorization. As a result, some of the zeroes else
are found, the others are expressed as zeroes of smaller ErrorFlag
order polynomials. In the second phase, the pole Exit
splitting hypothesis is assumed to compute the zeroes end if
of the reduced polynomials. The values of the zeroes end if
found are checked against the polesplitting hypothesis, end if
to ensure that their orders of magnitude are widely end do
separated. Finally, the polynomials to which the pole end if
splitting hypothesis cannot be applied are reduced by i = i + 1
means of the poleclustering hypothesis, which assumes end do
that the polynomial zeroes are clustered in small groups. end
Symbolic Analysis of Simplified Transfer Functions 19
During the poleclustering procedure, the size of the 5. Implementation and Results
cluster which can be solved analytically could be ex
tended. However, the resolving formulae for third Algorithms 14 have been implemented using a sym
degree equations are too complex to be useful in this bolic manipulator called Maple [21], with about 3500
context. For this reason, it is easy to define a transfer lines of code written in a highlevel Pascallike lan
function which cannot be solved using this algorithm. guage. The structure of the program is illustrated in
However, for most practical circuits the algorithm works figure 4. The input format is a SPICE netlist with anno
successfully, providing an accurate estimation of poles tations specifying the analysis required. Numerical sim
and zeroes of the transfer function. As an example, let ulation with SPICE provides a largesignal de analysis,
us consider the standard twostage operational amplifier which is used to automatically determine the order of
of figure 1. In open loop, the assumption of pole split magnitude of all the parameters in the circuit. Hence
ting is acceptable for the dominant poles. When the all the circuit parameters are assigned to the corre
same circuit is connected as a follower, then the first sponding equivalence classes. The number of signifi
two poles may become very close to each other, thus cant capacitances is critical and must be minimized.
producing a double pole or a pair of complex conjugate In fact they determine the degree of the transfer func
solutions which are far apart from the third parasitic tion and, to a large extent, its computational cost. For
pole. In this case, the splitting hypothesis is valid for this reason, an automatic procedure tries to allocate the
a cluster of poles, which can correctly be evaluated by minimum number of capacitances required to model the
the algorithm. circuit in a proper way. This is accomplished by com
An important property of Algorithms 34 follows. puting the conductance of each node toward ground.
The task is carried out very cheaply by using Algorithm
PROPERTY 7. If algorithms 3 and 4 are applied to a stable 2. Nodes are then sorted according to their impedance:
circuit and do not terminate with an error flag in Algo while external capacitances are always accounted for
rithm 4, the simplified zeroes are associated with a in the analysis, the procedure includes only parasitic
stable system. and intrinsic capacitances to ground for highimpedance
nodes which are not yet connected to ground by other
Proof A successful application of Algorithm 4 requires capacitors. Figure 2 shows an example of a smallsignal
that the zeroes of the original polynomial P can be eval circuit automatically derived with this procedure.
uated by Algorithm 4 using the polesplitting or pole
clustering method. If the polesplitting can be applied, USER INPUT FILE
then zero Sj of the original polynomial is Sj = aj_1laj'
Since by Property 6 the sign of the coefficients cannot
change because of the simplification, then sign(sj) =
sign(Sj), where Sj is the jth simplified zero.
A similar argument holds for the poleclustering
technique. Since the solution of a secondorder equa
Jl 
tion is
_ aj_1 [_
Sj,jl  2 1
4aj aj _2
2
J
aj aj _ 1
J l 2J
sign [ a.a. = J_/
sign [a.a. 2J
aj _ 1 aJl
Symbolic analysis of the
then required transfer function
sign(ffi[sj.j_Il) = sign(ffi[Sj,j_Il).
It must be noted that this algorithm does not prevent
a pair of real zeroes to become a pair of complex con
jugate zeroes after simplification. Fig. 4. Structure of the program.
20 Amadori, Guerrieri and Malavasi
The results shown in this section have been pro derived by our procedure for the differential gain in
duced by the described algorithms implemented on a openloop. Observe that when the PSRR is evaluated,
VAXStation3l00 in Unix environment. Comparisons two different parasitic capacitances to the positive and
with SPICE simulations have been carried out by con negative supply are considered. Also, the parasitic
veniently sizing the devices and computing the simpli capacitance associated with the source of the differen
fied transfer function with the same parameter values tial pair was taken into account. Since the automatic
used by SPICE. More specifically, our procedure com procedure deriving the equivalent circuit does not ex
putes the approximate poles and zeroes of the transfer ploit the symmetry of the inputs when the differential
function, which are then used for comparison, while gain is computed, this capacitance is included even
the numerical simulator takes into account the complete though it does not contribute to this analysis.
smallsignal circuit. In figures 5 and 6 comparisons with SPICE simula
tions are shown. The two curves, plotting the module
(figure 5) and the phase (figure 6) of the differential
5.1. TwoStage CMOS Operational Amplifier gain, are very close to the results of simulation for all
frequencies below about 10 MHz. Beyond this frequency
The twostage CMOS operational amplifier of figure the curves diverge, due to the presence of further poles
1 has been analyzed extensively as a simple test case corresponding to parasitic capacitances not accounted
which shows the potentiality of the algorithms. In table for in the analysis. However, divergence occurs in a
1, the differential gain (Ad), the common mode rejec range well beyond the unitygain frequency. In this ex
tion ratio (CMRR), and the negative and positive power ample, the polesplitting approximation proved to be
supply rejection ratio (nPSRR, pPSRR) are shown. The adequate for polezero calculation. In figure 7 the auto
same expressions can be found in the literature [22, matically derived smallsignal circuit of the same opera
20], but all of them have been extracted by applying tional amplifier in closed loop is shown. Now the high
the described algorithms. In these equations, the small impedance nodes are different from those chosen for
signal circuit shown in figure 2 has been automatically the openloop configuration. In fact the impedance at
Table 1. Differential gain (Ad), common mode rejection ratio (CMRR), and nega
tive and positive power supply rejection ratio (nPSRR, pPSRR) for the twostage
CMOS op amp of figure 1.
Steady State
Zeroes Poles
 Gm 6/ CI
Gos/Ci
CMRR 2Gm 2/Cw Gos/Cw
nPSRR  Gm6GOg (2Go 7Gm.  Gm6Go,)(Go2 + Go.)/
Gm 6  Gog)Cc) (2Gm.(Gm6Ci + CcGo 7
 Gm 6/ Ci
Symbolic Analysis of Simplified Transfer Functions 21
60
I::
.;0
40
o 20
~
::;
I::
QJ
r... o
........
QJ
Slmplltled results
Q
20 SPICE simulation
Frequency ( Hz )
 QJ
QJ
r...

~ 45
~
90
 ...........
"' "'
"'"'
"' \
\
135 Slmpllfled results \
\
\
SPICE simulation
"'
180 L _ _'_ _L_ _ L . ._ _l._ _' L _ _ '   _ ~
Frequency ( Hz )
Vout
T'
 Vin2 Go8 CC
Go?
node 4 in figure 2 is divided by the differential gain of L g = {Gm2' Gm4, Gm6' Gmg)
the op amp. Moreover, now the biasing of the input dif Sg = {Gm2, Go4, Go6, GOg, Go9 , Go lO }
ferential pair has a slight asymmetry due to the presence L c = {CLl
of a finite differential gain in the feedback path. This Sc = {CIO , Cw }
asymmetry has been modeled by introducing an addi
In this case, the automatic procedure correctly finds
tional symbol t.Gm, which was included in the class of
out that this is a singlepole circuit. Since the output
small conductances (see Section 3). The curves shown
node is already connected to ground by the load capaci
in figures 8 and 9 represent the behavior of the approx
tance, no further additional circuit elements would be
imate transfer function for three different situations
required. The user can include other capacitances
compared with SPICE simulations. The curves indi
beyond those associated with the highestimpedance
cated by a refer to the case of a double pole located at a
nodes. In this case elements C lO and Cw are chosen by
frequency of J7 MHz. The curves indicated by b corre
the procedure, as the second most relevant capacitances.
spond to a situation where the two dominant poles are
Results are reported in table 2. Comparison with SPICE
widely spaced in the frequency domain (S2/S1 > 30).
simulation for the differential gain is shown in figures
The curves indicated by c refer to the case of two com
12 and 13. The two curves match up to 100 MHz, where
plex conjugate poles, whose real part is located at
this architecture is not used anymore.
3.7 MHz. The third pole is always far apart from the
two other poles. Curves band c have been computed
5.3. Fully Differential Op Amp in Class AB
using the poleclustering technique. These examples
show that the error introduced by the simplification is
The circuit shown in figure 14 is a fairly more complex
influenced by the location of the poles, especially for
example than the previous ones. The left half of the
"resonant" circuits.
smallsignal circuit for this op amp is shown in figure
15. In this case, parameters have been organized using
5.2. FoldedCascode OTA
the following classes:
Figure 10 shows an operational transconductance ampli L g = {Gm2' Gm4, Gmg, GmlO' Gm12, Gm}
fier (orA). In figure 11 its smallsignal equivalent Sg = {Go 2, Go4, Go s , GOg, Go 10, GO I2 , Go}
circuit is displayed, with the following parameter Lc = {Cl}
classification: Sc = {C}
Symbolic Analysis of Simplified Transfer Functions 23
,,"
"
\
\
4
,,
,,
\
,
2 ,,
~~/
~~~
o r========~~
2
....c
CIl
t' 4
6
Simplified results
8
SPICE Simulation
10 L. .L ' '
Frequency ( Hz )
Fig. 8. Amplitude of the transfer function of the twostage op amp used as a follower with different values for capacitance Cc
The approximate expressions for some transfer func of the input transistors was also considered. The fully
tions are reported in table 3. For some of them, such expanded expressions of the transfer functions exceeded
as the PSRRs, we are aware of no known expressions the storage capability of any available workstation. By
in the literature. means of Algorithms 3 and 4, the simplified expression
was computed in a reasonable time (see table 4). Al
though our approach does not reduce the asymptotic
5.4. Computational Efficiency computational complexity of the problem, the exten
sion of the range of applicability of symbolic analysis
Some considerations about the efficiency of the pro is particularly evident with this example. We expect to
posed technique can be drawn from table 4. Computa be able to cope with even more complex cases with
tion times are reported in column 1 for the computation the systematic use of automatic circuit partitioning
of poles and zeroes using Algorithms 3 and 4, while techniques.
column 2 gives the times required to achieve the same
goal without the matrix simplification detailed in Algo
rithm 3. The first example shows that the higher com 6. Conclusions
plexity of the technique causes an increase of CPU time
for a very simple circuit such as the twostage opera In this paper we have shown algorithms useful to deter
tional amplifier of figure 1. However, the second example mine the simplified transfer functions associated with
shows that the performance of the algorithm improves a linear circuit with a special emphasis on techniques
with a more complex circuit such as the folded cascode suitable to reduce the computational cost of the process.
op amp. The computation of the CMRR is still less effi The task of polynomial simplification has been formally
cient since several iterations of steps 1 and 2 of Algo defmed and new algorithms for the evaluation of simpli
rithm 3 are required before the significant terms are fied expressions proposed. They can be applied to zero
found. In the case of the class AB op amp the mismatch frequency as well as to frequency domain problems.
24 Amadori, Guerrieri and Malavasi
Q)
Q)
s..
~

Q)
~ 45
Q)
tI'l
Cll
~
p..
Simplified results
SPICE simulation
Frequency ( Hz )
Fig. 9. Phase of the transfer function of the twostage op amp used as a follower, with different values for capacitance C  c.
Vdd
M7 M8
1 ~Ml_.,__M2.f ~
Out
Vin 1 Vin2
M5 M6
Vbias3 1 M9 M3 M4
Vss
Qn2 ( Vln2  v5 )
Gmt ( Vinl  vS ) G08 G08
GmS vJ
Out
u6
u8 )
Qn6 Go6
.1
v8
Qn4
Gm4 v8 Go4
Table 2. Differential gain (Ad), common mode rejection ratio (CMRR), and negative and positive power supply re
jection ratio (nPSRR, pPSRR) for the CYrA of figure 10.
Steady State
Ad Gm.Gm6Gm 2/
(Gm.Go 6Go 4 + G02Gm6Go. + Go IO GO.Gm6)
CMRR
nPSRR  2Gm.Gm2Gm6Gm4/
(2Gm6Go.Go2Gm4 + 2Gm.Go 6Go4Gm 4 + Gm.Gm6Go9Go4 + 2Go.Gm6GoIOGm4)
pPSRR  Gm4Gm2/(Go4GoIO)
Zeroes Poles
pPSRR
 Gm.Gm6Go4/
(CIO(Gm6Go4 + Gm 4Go. + Gm6Go.
26 Amadori, Guerrieri and MaLavasi
Folded Cascade
90. r        .        ,      ,      ,        ,
70.
50.
30.
10.
10.
30.
50.
Frequency ( Hz )
Folded Cascade
O. r=~,_r___rl
45.
(l) 90.
VJ
to
...c:
0...
c:
to
'' 135. Simplified results
\
\
_ _ _ SPICE simulalion \
\
,
\
\
Frequency ( Hz )
I
I
Vdd
Me M7
MIO M9
,
Vss
 Vinl
Go2
Gm2 ( Vinl  v3 I
Gm6
Out
lei
v4
Go4
Gm4 (vllv41
Go
Gm GolO GmlO v1
Fig. 15. Smallsignal circuit for the class AB op amp (right halt).
28 Amadori, Guerrieri and Malavasi
Table 3. Differential gain (Ad), common mode rejection ratio (CMRR), and negative and positive
power supply rejection ratio (nPSRR, pPSRR) for the foldedcascode op amp of figure 14.
Steady State
Ad Gm2Gm4(GmlO + Gmg)/
(Gm(Gm 4 + Gm2)(GOg + Go lO ))
CMRR Gm6Gm2Gm12Gm.<GmlO + Gmg)/
GmlO  Gmg)(Gm6Gm2Gm4G012 + GoGm2Gm12Gm4
Gm4Go2Gm6Gml2 + G04Gm6Gm2Gm12 + Gm6GoGm2Gm4))
nPSRR Gm4Gm2Gml2Gm6(GmlO + Gmg)/
(GmI2Gm6GmGoIOGm4 + Gm12Gm6GmGoIOGm2  Gm.Gm2GmgGm4Go
Gm12Go4Gm6GmgGm2  Gm 12 Gm 2GmgGm 4Go + Gm.Gm2Gm4GoGmlO
+ Gm12Gm2Gm4GoGmlO + GmI2Gm2Go4Gm.GmlO)
pPSRR Gm.Gm.2Gm4Gm,(GmlO + Gmg)/
(GmGog(Go g + GOIO)(Gm2 + Gm 4)(Gm. + Gm12))
Poles
Ad (Go lO + Gog)/Cl
Gm/C
CMRR
nPSRR (Gmg + GmlolGm4Gm2/Gm4 + Gm2)GOlOC)
pPSRR (GOg + GolO)/CI
Gm/C
Abstract. This paper presents an approach suitable for the symbolic analysis of largescale active networks. The
method depends on the partitioning of the network into smaller networks which are then symbolically analyzed
noniteratively using the Mason's signal flowgraph models of each partition. The resulting solutions, which are
reduced signal flowgraphs (transfer functions) for the subnetworks are then hierarchically combined to produce
the final solution or solutions (transfer functions) for the entire system. The advantage of such an approach is
the reduction in the number of symbolic terms compared to the conventional approaches, and the ability to analyze
hybrid systems consisting of electrical and nonelectrical parts. The result of the analysis is a series of equations
that have an upward hierarchical dependency on each other.
4. Selfloop reduction (figure 6)
WI nz Wz W\WZ A selfloop adjusts the weights of all branches enter
n I _I.~_ _I.~_ n 3 ~ n I _I.~_". n 3
ing the node. The feedback branch is then deleted.
Fig. 3. Series suppression of node nz.
5~ Suppression of a node with no outgoing branches
This corresponds to an I/O variable not requested
by the analysis. The suppression is done by simply
WI + Wz deleting the node.
~ n,. .nz
structures. The reduced nodes and old branches data Each branch and node (figure 2) is described as follows,
structures are then removed and rather than their mem respectively:
ory deallocated from the program, they are stored in a
linked list of deleted elements. This list is then reused b = next branch n = next node
for new structures that need to be created by the pro
num num
gram. So MASSAP has a form of local memory man
agement in order to reduce the execution time due to Wb Tn
costly system memory allocation and deallocation calls.
Operations are performed in the order stated above bnl Fn
because parallel and selfloop reductions are computa bn2
tionally less expensive than series reductions. The ex
ternal nodes are then revisited to reduce any selfloops Being an external node is determined by a direct check
created by the deletion of internal flowgraph nodes. in the list of tearing nodes TN. TN is defined as
The main variables of the algorithm are defined as
follows:
Ni = set of signal flowgraph nodes (variables) in
partition i
Bi = set of signal flowgraph branches in partition i If node n does exist in TN, then the node is not to be
ENi = set of signal flowgraph external nodes suppressed. If, however, the node is not in TN, the node
(variables) in partition i is scheduled to be suppressed.
IN; = set of signal flowgraph internal nodes The program concludes execution by recombining
(variables) in partitioned circuit i the solutions for the partitions into an overall system
TN = set of signal flowgraph tearing nodes solution. The algorithm is recursive, highly paralleliz
(variables) able, and suitable for implementation on multiprocessor
V = set of signal flowgraph input and output machines. Each partition can be analyzed independent
nodes (variables) of the other partitions and is only visited once (non
Wb = weight associated with branch b iterative). This reduces to a minimum any interproc
Tn = set of braches entering signal flowgraph essor communication, and in turn the large overhead
node n usually associated with the use of multiprocessor
Fn = set of branches exiting signal flowgraph machines.
node n The general algorithm can be illustrated as follows:
main {
MSFG_analyze (Network);
suppress (Network); /* Delete any internal nodes left */
} /* End of main procedure */
MSGF_analyze (Network) { /* Binary partition into P 1eft & Pright and perform
the analysis */
partition (Network); /* Partitions P 1eft & Pright */
if is a leaf cell)
(P1eft
suppress (P1e0; /* Suppress internal nodes for this terminal block */
else MSGF_analyze (Pleft); /* Recursively call MSGF_analyze */
if is a leaf cell)
(Pright
suppress (Pright); /* Suppress internal nodes for this terminal block */
else MSGF_analyze (P1eft); /* Recursively call MSGF_analyze */
combine (Pleft,Pright); /* Produce merged MSGF by concatenating the reduced
MSFGs and generate the new Network */
return (Network);
} /* End of MSGF analysis */
34 Hassoun and McCarville
}
}
/* A series and general suppression (figures 3 and 5) */
foreach (bin E T,,) {
foreach (bout E F n) {
create new branch b;
Wbnew = Wbin * Wbout;
}
}
delete all branches attached to node n;
delete(node n);
} /* End of variable suppression for this partition */
} /* End of suppression for this partition */
3.2. The Input Deck cumbersome expression it represents. The resulting out
put contains one branch for each inputoutput node
MASSAP requires a SPICElike input deck with ad combination (figure 1).
ditional partitioning statements. A flowgraph branch
is input exactly as a circuit branch is using SPICE. The
3.4. Special Considerations
direction of flow is taken from the first node given to
the second. An ".output" statement outlines the in
1. It is better to reduce feedback paths before all the
put and the output nodes. Currently a graphics inter
nodes in the forward path of the loop are deleted. This
face is being built onto the package which includes
is not a requirement for the success of the algorithm,
menu driven options in addition to schematic capture
however, it will have a significant impact on the resul
capabilities.
tant sequence of expressions. Example 3 and table 2
illustrate the impact of the reduction node ordering on
3.3. The Output File the sequence of expressions.
It is possible to guarantee that all nodes in a feed
The program output is a sequence of hierarchically back paths are reduced first by one of two ways:
dependent expressions in the form of an evaluatable pro a. Implementing a check before eliminating each
gramming module. The program gives an option of node. A search for any path from that node to itself
choosing a C function or a FORTRAN subroutine as is sufficient to identify a feedback loop. If such a path
an output. As each internal node is deleted, a sequence is found, the processing of that node is assigned a lowest
of expressions term is created from the weights of the priority position in the reduction queue.
reduced branches and assigned a new symbol. The new b. Listing all feedback paths first in the input deck.
symbol is then used in the analysis rather than the This will guarantee that all feedback nodes are placed
Symbolic Analysis of LargeScale Networks Using a Hierarchical Signal Flowgraph Approach 35
/
G7
_ V4 Y2 G9
H S4 (3) 6
Vs
~11
Y4 7
Parte
G4
H I4 = V4 = YI(Y2 + Y4) (4)
VI Y4(YI + Y3) 2 G2
~ r~ ... 5
4~
8 Gs
V
n I n] G]
1 2 3
I;
G3 Part A Part B 1~6
J+
Since this algorithm seeks to deal with real prob
lems, a perfectly valid assumption is that a real net 2
F(n) = F [ n 3 k n (15)
work has an upper bound on the number of branches
2 2 P
incident and leaving each node (excluding the reference
nodes). A general survey of practical (real) circuits MASSAP uses a binary partitioning algoritm to decom
showed that an average of six branches are connected pose the input network or flowgraph [4]. The complex
to a given circuit node. Therefore, for this discussion, ity of the partitioning algorithm however, it not included
the average number of branches connected to a node in the current complexity analysis. The reason is that
is assumed to be a constant. Alternatively, this assump most circuits are already prepartitioned due to the fact
tion states that each vertex in the flowgraph has an that they are composed of building blocks during their
average of k branches connected to it, k/2 entering and design phase. These building blocks are considered
k/2 leaving. Since each branch has two nodes, this gives natural partitions and eliminate the need for applying
rise to the equation the partitioning function.
Symbolic Analysis of LargeScale Networks Using a Hierarchical Signal Flowgraph Approach 37
The function suppress ( ) is initiated when the size (I and 12) and one output node (5), the resultant signal
of each partition (subcircuit) reaches nip nodes. Since flowgraph consists of 2 branches representing the
the internal nodes ni are suppressed the number of transfer functions H(12, 5) and H(1, 5).
nodes processed at the next function cell level is 2(nlp
 nJ which is the number of tearing variables (exter Example 4.2. (Dualbiquad). Consider the dualbiquad
nal) to the subcircuits. It is expected that ni > nip. amplifier example shown in figure 10 [10]. The out
This actually is a necessity for the efficient execution of put sequence of expressions is
the algorithm. Also for practical circuit building blocks, wI g4/(gl  sCI)
the number of 1/0 variables will always be less than w2 = g2/sC2
the number of internal nodes. Therefore, on the average, w3 g5/g6
the number of nodes that suppress ( ) will handle will w4 = g4/g3
always be a constant proportional to 2(nlp  ni)' w5 = g8/g11
Another feature of real circuits is the fact that nand w6 = g7/glO
p are directly proportional to each other, that is a big w7 = g9/glO
ger circuit will always have more partitions to it HOEI(I,6) = wI *w2
(building blocks). Also, automatic partitioners usual HOE2(1,8) = wI *w5
ly continue until a maximum p or a minimum nip is HOE3(1,1l) = wI *w6
met. Hence the final average asymptotic time complex H0E4(1O,6) = w4*w2
ity of the algorithm is given by solving the reoccurence HOE5(10,8) = w4*w5
equation (15). The result is HOE6(10,1l) = w4*w6
HOE7(1,10) = HOEI(I,6)*w3
O(n log n) (16)
HOE8(10,1O) = H0E4(10,6)*w3
To study the quality of the results that the algorithm HOE9(1,IO) = HOE7(1, 10)/(1 HOE8(10, 10))
produces, a close inspection of the above analysis will HOEIO(I,8) = HOE9(1,IO)*HOE5(10,8)
yield a direct correspondence between the number of HOEll(l,ll) = HOE9(l,IO)*HOE6(10,1l)
operations that need to be performed in every reduc HOEI2(1,8) = HOE2(1,8)+HOEI0(1,8)
tion and the number of operations resulting in the se HOE13(I,ll) = HOE3(1,1l)+HOEll(1,1l)+w7
quence of expressions. In general terms each parallel,
series or selfloop reduction at a node will produce Example 4.3. (Bandpass filter). Figure 14 is a full im
plementation of a bandpass filter [3]. Figure 15 shows
o multiplications and kl2 additions the hierarchical partitioning and analysis tree model and
for parallel reduction (17)
figures 7, 12, and 13 show the subcircuits of the parti
2
k /2 multiplications and 0 additions tioned network. By using partitioning, the computa
for general reduction (18) tional efficiency of the flowgraph is improved. Table
I shows the results of the analysis and table 2 shows
kl2 multiplications and I addition
a comparison for this example with SCAPP [2] and with
for selfloop reduction (19)
the Coates Graph hierarchical analysis method pre
Equations (17), (18), and (19) show that the number sented in [3]. The results are shown with and without
of operations that will result in the sequence of expres network partitioning. The table also illustrates the ef
sions will exhibit only a quadratic growth with respect fect of the node reduction order on the complexity of
to the size of the circuit measured by the number of the output expressions.
nodes in it.
Example 4.4. (Ladder network). Examples 4a and 4b
show comparisons for ladder networks of 10 and 20
4. Examples nodes, respectively. The results of the signal flowgraph
analysis and comparisons with other methods are
Example 4.1. (Bandpass filter terminal block). Exam presented in table 3. The computational count increases
ple I (figure 8) is the analysis of a subcircuit which linearly with the number of circuit elements. The flow
is a building block of example 3. The ideal operational graph method multiplication and addition counts are
amplifiers have been reduced to flowgraph form as comparable to those from the network approach [2].
shown in figure 9. Since the block has 2 input nodes Although there is not a onetoone mapping from circuit
38 Hassoun and McCarville
3 Gs
6
SCI R I sCz Rn
I~
v~ ~Vn+l
SCI RI sC n
Yin
"I
G40
30
BLOCK
5
Fig. 13. Block 5 of the bandpass filter (Example 4.3.).
5. General Discussion
The reduction processes of a Mason's signal flowgraph Fig. 14. Bandpass filter of example 3 [31.
using the above suppression procedures has been con
sidered a complex process for a digital computer [1,
11]. The main problem is the growth in the number
of terms involved when the reduction is applied in order
to get a compact signal flowgraph. This problem is
solved here by using several aids:
1. There is no advantage to attempting to produce a
single expression for the final symbolic transfer
function for large network. No possible insight
could be gained from inspecting a transfer function
with hundreds of terms in the numerator and denom
inator. The only possible insight is through numer
ical evaluation of the function and a plot of the
transfer characteristics. Using a hierarchically
dependent sequence of expression [2, 3] rather than
a single expression to represent the transfer func Fig. 15. Hierarchical model for bandpass filter (Example 4.3).
tion eliminates the handicap.
2. Computer memory requirement for analysis oflarge 3. The use of network partitioning or graph partition
scale networks can be reduced drastically by using ing to reduce the overall complexity of the algorithm
a sequence of expressions method. needed to analyze largescale networks.
40 Hassoun and McCarville
Table 1. Symbolic analysis results of Example 4.3. Table 2. Comparison of bandpass filter with other methods. a
figure 15. Parts A, Band C, are simply the blocks lems and the need for normalization during the
already analyzed in figure 7 (part A, which is a sum numerical evaluation process of the sequence of ex
mer is slightly different with an extra input terminal). pressions. This is also the case in the network ap
Table 3 also illustrates comparisons with the hier proach [2] but is not the case in the Coates f1ow
archical network approach used in SCAPP for all the graph approach [3].
examples presented in this paper. 7. The number of terms in the f10wgraph analysis of
active networks is lower than that for general net
works due to the onetoone correspondence between
7. Conclusions the actual circuit nodes and the nodes of its f1ow
graph model.
The advantages of the Mason's f10wgraph method im In general this method works very well for circuits
plemented in MASSAP and presented herein are: with standard building blocks, active or passive. The
1. The simplicity of its reduction rules in order to obtain fact that these building blocks can be considered as
the I/O transfer function sequence of expressions. natural partitions to the circuit and their analysis results
2. The number of operations and expressions resulting loaded into the analysis directly eliminates the overhead
are comparable to the other methods proposed for associated with building the signal f10wgraph for the
the analysis of largescale networks. This is due to network.
(a) the use of a sequence of expressions which ex
hibits only a quadratic growth rate for general cir References
cuits and sometimes a linear growth rate (ladder net
works) in the number of terms as the network size I. P.M. Lin, "A survey of applications of symbolic network func
increases, and (b) the use of network partitioning tions," IEEE Trans. Circuit Theory, Vol. CT20, pp. 732737,
which reduces the overall complexity of the analysis 1973.
2. M.M. Hassoun and P.M. Lin, "An efficient network approach
algorithm. to symbolic simulation of largescale circuits;' in Proc. IEEE
3. Symbolic libraries can be built for common sub Int. Symp. Circuits Sys., pp. 806809, 1989.
systems with a reduced f10wgraph already produced. 3. J.A. Starzyk and A. Konczykowska, "Flowgraph analysis of large
4. The ability to include any current or voltage variable electronic networks," IEEE Trans. Circuit Sys., Vol. CAS33,
as part of the analysis without any extra or special pp. 302315, 1986.
4. M.M. Hassoun, and P.M. Lin, "An efficient partitioning
considerations [Lin76]. algorithm for largescale circuits," in Proc. IEEE Int. Symp. Cir
5. Another major advantage of this hierarachical f1ow cuits Sys., pp. 24052408, 1990.
graph approach is the ability to simulate integrated 5. G. Gielen, H. Walscharts, and W. Sansen, "ISSAC: A symbolic
systems. That is, systems with electrical and non simulator for analog integrated circuits," IEEE J. SolidState Cir
electrical components. The only requirements on the cuits, Vol. SC24, pp. 15871597, 1989.
6. F.Y. Fernandez, A. RodriguezVazquez, and J.L. Huertas, "An
components of the system is that they be represent advanced symbolic analyzer for the automatic generation of
able in f10wgraph format. Mechanical and chemical analog circuit design equations," in Proc. IEEE Int. Symp. Cir
systems are commonly represented by a Mason's cuits Sys., Singapore, pp. 810813, 1991.
f10wgraph and interconnections of such components 7. G. Di Domenico and S.l Seda et. aI., "BRAINS: a symbolic
with electrical networks can be simulated using the solver for electronic circuits;' Int. Workshop Symb. Methods Appl.
Circuit Design, 1991.
method herein. 8. R. Sommer, "EASYan experimental analog design system
6. The existence of division in the sequence of expres framework," Int. Ubrkshop Sym. Methods Appl. Circuit Design,
sion. This eliminates underflow and overflow prob 1991.
42 Hassoun and McCarville
Abstract. This paper addresses the topic of reducing the complexity of formulae resulting from the symbolic analysis
of analog integrated circuits, covering both flat and hierarchical symbolic analysis approaches. Previously reported
criteria for flat analysis are first briefly reviewed and their limitations illustrated via examples of practical analog
circuits. In all of these criteria simplifications are performed by estimating the numerical values of the symbolic
terms at a single point of the parameter space, corresponding to the expected typical values for symbols. Conse
quent quantitative as well as qualitative inaccuracies resulting from this approach are identified. A new simplifica
tion strategy for flat symbolic approaches is then presented in which insignificant terms are deleted taking into
account expected ranges of variation in the symbol values. Examples are used to show that this new criterion over
comes the drawbacks encountered in previous ones. Finally, an algorithm to simplify hierarchical formulae is
presented which includes consideration of the potential ranges of variation in the symbolic parameter values. This
algorithm is also applied to practical analog integrated circuits.
level, where formulae containing a huge amount of the ninetransistor folded cascode OTA of figure Ib:
terms are obtained even for elementary building blocks. using the model of figure le, the formula representing
Because of these difficulties, the development of ap the voltage gain of this op amp contains 97,953!! dif
propriate, powerful formula postprocessing tools is in ferent terms [9]. A similar number of terms are ob
dispensable to ease, or even enable, the interpretation tained for other specs that must be taken into account
of the primary results provided by symbolic analyzers. in the design procedure, e.g., CMRR, PSRR, noise,
Formula postprocessing comprises a wide variety input capacitance, etc. A much larger number of terms
of tasks, such as parametric graphical representations will result for advanced CMOS or BJT op amp building
[9], sensitivity calculation [15], pole/zero extraction [9], blocks, typically containing about 30 transistors. Try
etc. Formula simplification is an issue of outstanding ing to create models including all the characteristics
importance among the different postprocessing tasks. needed for the ac design of these building blocks, and
Simplifying a symbolic formula implies reducing its using exact symbolic expressions, will probably be
complexity (measured as the number of terms) by beyond the capabilities of many compilers. Even if com
eliminating insignificant terms, determined by a pilation were possible, the computation time required
numerical estimate using typical values of the symbolic for the iterative design procedure would be extremely
parameters. The convenience of formula simplification high. Hence, this application also demonstrates the need
is shown when considering calculation of the output for simplifications.
impedance of the cascode current mirror of figure la, Previous approaches to symbolic formula approx
using the MOS transistor model of figure le. The form imation focused only on fully expanded expressions
ula supplied by the symbolic analyzer ASAP [9] con resulting after applying flat symbolic analysis tech
tains 1384 different terms. This number is not par niques [79, 19]. In addition, these approaches only
ticularly astounding in itself, but suppose this formula consider a single point of the complete parameter space
is used for educational purposes to gain insight into to estimate the relative size of the symbolic terms. Sec
the circuit operation. It is obvious that a more com tion 2 introduces the concept of symbolic formula ap
pact expression containing a few dominant terms would proximation, and the drawbacks of previously reported
be more appropriate for this purpose. In fact, the ex simplification criteria are shown by examples of prac
pressions found in advanced analog circuit textbooks tical analog integrated circuits. Section 3 presents a
for these characteristics contain less than 10 terms completely different simplification approach, where
[1618]. numerical estimate is not made at a single point of the
parameter space but inside a region, defined by taking
into account typical ranges of variation of the symbols.
It is shown that this approach overcomes the problems
found in previous ones. Section 4 focuses on the sim
plification of formulae resulting from hierarchical sym
bolic analysis procedures [20]. An algorithm is given
(al for this type of expressions and demonstrated for prac
tical analog integrated circuits. Finally, a brief discus
sion of results is made in Section 5.
0.1
~02
term 'enn
hf"hfe2R3RLR, +hf" (R2 +RiJ(R3+r,2)R\ +(R2 +RiJ(R3+r,2)(R, +r,,)+(R3+r,2)rr,R, Fig. 3. Percentage distribution profLles for the different symbolic terms
(1) in (I): (a) numerator, (b) denominator.
~1=I,plhkl(Xo)1 <
I~1=1,,.hkl(Xo) I
"~~ro ~1=I,plhkl(Xo)1
(*)
M, M2 ~l=l TIhkl(X o) I
(e) V" We will try now to compare the criteria in (*) refer
(b)
ring to their performance at the nominal point as well
Fig. 4. Benchmark circuits for illustration of flat simplification criteria:
as other points of the parameter space located inside
(a) positive feedback orA; (b) Miller orA; (c) active CMOS cur a region around X O ' This latter situation deserves con
rent mirror. sideration since the design point in symbolic analysis
is not usually known beforehand, and its value is defined
Four different criteria have been proposed for ex
as a heuristic guess. Furthermore, even if the exact
panded format expressions. Three require sorting terms
design point were known a priori, in practice, dis
in hk(x) according to their magnitude at the nominal
placements due to the influence of unavoidable device
point XO ' The P smallest magnitude terms are then
mismatches would be observed around it.
eliminated, P being the largest integer for which the
The three criteria in (*) yield identical results if all
accumulated error is below M' The criteria differ
the terms of each coefficient hk(x) have the same sign
among themselves in the expression used to estimate
at xo ' and provided that this sign remains the same in
this accumulated error; these three alternatives are
side the region considered. This is the case if each co
shown in (*). In the three cases, each hk(xo) is trun
efficient fulfills the following:
cated to a value a0k(Xo) , where ak depends upon M'
For functions containing a large number of terms inside sign{hkl(xo + LlX)} = a VI, LlX E R (8)
Formula Approximation for Flat and Hierarchical Symbolic Analysis 47
where a is either I or 1. However, for many analog formulae would be obtained. Thus, this criterion is not
circuits this is not the case and, consequently, different used in modern tools [6, 9].
results can be expected for each criterion in (*).
2.2.3. Unsigned Reference Unsigned Object Criterion.
2.2.1. Signed Reference Signed Object Criterion. This This is the criterion in the right equation of (*). It is
is the criterion in the left equation of (*). Note that less accurate at the nominal point than the signed
terms are added with their signs so that eventual con reference signed object criterion: however, unlike the
tributions from opposite signed terms mutually cancel
former, the likelihood of additional inaccuracies due
themselves. Thus, if (8) were not fulfilled, this criterion
to displacements around X o is smaller. Actually, this
gives the most accurate results at xO ' However, impor criterion is the most commonly used in modern sym
tant errors may result when the simplified formulae are bolic analyzers [6, 9]. Unfortunately, there are many
evaluated at points other than X o in case these circuits where its use may yield large errors, as shown
simplified formulae result from the cancellation of large
in the following.
magnitude opposite sign terms.
Let us consider calculating the dc voltage gain of
the orA of figure 4a, given as the coefficient ratio ".
\~,
foCx)/go(x). Assume these coefficients are simplified ""
for EM = 0.25. After simplification errors measured at ",.,
the nominal point are the same for fo(x) and go(x):
"", .
\ _._._~~.~~~._._._._._._._._.
24.9%, which is very close to the userspecified " E M=O.10
?
I
sistors. Corresponding maximum deviations for .~
"0
I
I
f
matched transistors are 1.1 dB at 100 kHz and 5.1 ~
deg at 2.8 MHz, in both cases for EM = 0.2. As s: / cM=O.05
:5 cM=O.lO/
,i"
formula calculated at the nominal point is applied at
:i'\ ,./
points located nearby. ,.
I
"
J06 J08
(b)
2.2.2. Signed Reference Unsigned Object Criterion. Frequency (Hz)
V'lZl Zz P 3 P1PZ Z3
,J 0 ~r.....,r':::JT"""""_r__
1:"': ... . _.. . ._.. . _.'......_...r._......_......._...,_...... ._r"......,~..='r.rrT"o
~ 1 _ _ . _ _ _ _ _ _ _  _,
, I
I I
I
I . :
I':
J
t
o u''''''.1J1iL...L'_''_J..I..._.L'_''__':''~''_::_';:_L......J
o 10 5 0 5 10
Re(s) (log)
Zz Z 3
V'l .....P...;..............__rrrr.Z~I!..rP~3'r.........__rrr.P~zr.__r,
~O
w
5 o 5 10
Im(s) (log)
Fig. 7. Root loci for the current gain of the active current mirror as a function of M: (a) real part of the roots; (b) imaginary part.
totally or partially unsized circuits. That is, in symbolic figure Ie yields a 64dimension space), this approach
analysis the exact numerical value of some or all the does not seem computationally feasible.
parameters is not known beforehand. Hence, approx A different algorithm is presented in this section
imating symbolic expressions by considering only a where each symbolic parameter is assigned a range of
single point of the parameter space does not seem con variation and simplifications are achieved by perform
sistent with the very nature of symbolic analysis pro ing operations among the parameter ranges.
cedure. Even when symbolic analysis is used to study
critical parameter variations in sized schematics, 3.1. Concept and Basic Operators
simplification using only information about the nominal
point may lead to important inaccuracies, as shown To perform the simplification procedure, we will
previously for the PSRR of the Miller afA. assume that each symbol 6 may take any value inside
It is common in analog integrated circuits that a given range of variation.
parameter variations be comprised inside a limited
Yi E [YiL, YiH] (11)
region of the parameter space. For instance, it is not
realistic in standard CMOS technologies for capacitor where YiL and YiH are real numbers and YiL ~ YiH'
values to be smaller than 0.1 pF or larger than 100 pF. Bear in mind that simplifications are made by
Similar restrictions exist for most parameters. Thus, eliminating addends in each symbolic coefficient; the
accurate approximate formulae could be obtained by general coefficient expression is (4), repeated here for
applying the criteria in the left equation of (*) to each convenience sake,
point located inside a limited region of the parameter
space.s However, considering that parameter space + hkrtX) = ~ hkl(X)
dimensions for typical analog circuits are very large 1=I.T
(for instance, the afA of figure Ib with the model of (12)
50 Fernandez, RodriguezVazquez, Martin and Huertas
where the addends are products of symbols. As dis 3.1.2. Addition of Ranges. Consider the general case
cussed in Section 2, conventional simplification ap of two symbols, denoted Yi and Yj respectively, for
proaches calculate the values of the different hklx) at which the corresponding ranges are known. Let us
the nominal point xo , and compare these values to that assume that a new symbol is defined as the sum of Yi
of hk(xo); insignificant terms are then eliminated. and Yj' The range for this new symbol is computed by
When a range criterion is applied, the ranges of the adding the corresponding extrema of the addends.
different hklx) must be calculated and compared to the
(Yi + Y) E [(YiL + YjL) , (YiH + YjH)] (15)
range of hk(x). Hence, operations among ranges must
be defined; in particular, those that allow calculating This operator allows evaluating ranges of either hk(x)
the range for a product of symbols (product of ranges or subsets of addends in (12).
operator) and the range for a sum of symbols (addi
tion of ranges operator) from the component ranges. 3.1.3. Modulus of Ranges. For a given symbol, prod
Additionally, two more operators must be defined: the uct of symbols, or sum of products for which a range
modulus ofranges operator and upper and lower range (YiL, YiH) is defined or calculated, the modulus of
operators. These operators allow calculating the relative ranges operator yields another range defined from the
range values required to determine which terms must previous one by taking the modulus of the extrema in
be eliminated from a given coefficient. an appropriate order,
l[YiL, YiH]1 = [min (IYiLI, !YiHI), max (IYiLI, IYiHI))
3.1.1. Product of Ranges. Assume a new symbol is (16)
formed by multiplying two symbolic factors, Yi and Yj'
The extrema (Yi Y)L and (Yi Y)H of the range of this 3.1.4. Upper and Lower Operator. These two operators
new symbol can be calculated from the extrema of the return the extrema of the range for a given symbol Yi'
factors as follows: respectively,
2. Ranges ofcoefficients hk(x). Calculate the range of their maximum values for one term while simultane
the coefficient [SL, SH] using previously calculated ously taking the minimum in the other. This may be
ranges and the addition of ranges operator. accounted for by factorizing the sum of the terms
3. Grouping of terms. Determine pairs of terms Yi, Yj
(23)
with opposite sign and similar magnitude and con
sider the sum of these terms. which yields a real maximum range of [1.74E18,
1.74E18]. When this range is taken into account, it can
(Yi + Y) E [(YiL + YjL) , (YiH + YjH)] (19)
be concluded that both terms may be grouped together,
Then evaluate the following inequalities: thus increasing accuracy in the simplification.
It is worth noting that the pruning based on (18)
CU(I [(YiL + YjL) , (YiH + YjH)] I) < (1 [YiL> YiH] I) upperlower criterionmay yield very conservative
cu(1 [(YiL + YjL) , (YiH + YjH)] I) < (1 [YjL, YjH] \) formula due to the fact that there may be terms with
(20) their maximum value added to the accumulated sum
(numerator in (18)) and the minimum value to the total
If they are simultaneously fulfilled, the pair of terms
sum (denominator in (18)). For that reason, a slightly
is grouped and a new range defined by (19) is
modified criterion has been developedupper
associated to it; otherwise the terms are not grouped.
mediumwhere terms added with their maximum
Note that these groupings allow proper handling of
magnitude in the numerator are added likewise in the
the mismatch problem. Thus, pairs of terms cor
denominator. This implies modification of the
responding to mismatched parameters can be
denominator in (18) for each term added to the ac
eliminated (in spite of their large magnitude), if their
cumulated sum, and though it requires a little extra
maximum difference is small enough.
computation it obtains less conservative results.
4. Ordering ofterms. Arrange the terms in an ordered
Another alternative range criterion has been
array using the modulus and upper operator for the
developed where the sum of symbolic terms is factor
range comparison. Assume two arbitrary terms, Yi
ized prior to computing [SL, SH] and [A cL ' AcH]' This
and Yj; Yj is considered less significant than Yi, if
obtains more reduced ranges and, hence, less conser
it fulfills the following:
vative results than the upperlower criterion. Our ex
(21) perience with this criterion does not show clear advan
tages when compared to the uppermedium criterion;
5. Elimination of terms. Beginning with the least however, from the computational point of view it is
significant term determined in the previous sorting, much more costly. Consequently, it does not seem very
the range of each new term is added to the ac convenient for simplification of flat expressions. This
cumulated sum range and the terms are pruned one criterion's greatest utility is found in the hierarchical
by one until (18) is no longer fulfilled. simplification procedure presented in Section 4, where
The grouping of terms described in step 3 of this the range reduction is very convenient.
algorithm can be refined with a little extra computa
tion, by the factorization of both terms. For illustra
tion's sake, consider the symbolic expression for the 3. 3. Practical Results
PSRR + of the Miller OTA. The ranges for two of the
terms corresponding to nominally matched transistors Validity of the proposed range simplification criteria
are, has been tested on a wide variety of analog integrated
circuits: both analog building blocks described at a
[2.36XIO 18 , 5.27xIO 18] device level, as well as larger complexity circuits
[5.27XI0 18 , 2.36XIO18 ] described at a macromodel level. Accurate results
(within userspecified error margins) have been ob
(22)
served in all the cases, and a significant reduction in
where a mismatching of 10% is assumed between formula complexity. Actually, based on our experience,
MOST transconductances. The range for the sum of the criteria allow very flexible accuracy versus com
these terms can be calculated as [ 2. 91E18, 2.91E18]. plexity tradeoffs. Thus, the complexity is greatly
At first glance, these terms would not be grouped decreased for noncritical circuits, and increased to the
together, however it is unlikely that Gm5 and Gm6 have level required to ensure accuracy in critical circuits.
52 Fernandez, RodriguezVazquez, Martin and Huertas
1
Frequency (Hz)
It~
~ 0 I++I+t+t''I+'i=';~".',"
t :! ~
H
__ ~~~=O20 ;:
I~
.G \~ '.
\'. , (
" I
\ '. 1/
\ ~ II
\ '/'
I I
I I
... EM=O.lO\
...'
:
I
,
9
\
L_
(a) "]~~~~l~ 106 lOR
Frequency (Hz) o
I
8
106
II
I I (b) ] 10
Frequency (Hz)
cM=O.lO: ~
: /'\ Fig. 10. Parametric Bode plots for the voltage gain of the positive
"'
I \ feedback OTA using uppermedium range simplification criterion:
"
/i
Ii
(.
t (a) magnitude; (b) phase.
, r ~
II t
Ii" I1 As a final example, figure 12 presents the locus for
==I.;8:_
o F=~'='=_c___O=~... I i
'i \
the real part of the roots of the active current mirror,
","'''''' . ,._ff ~ resulting after applying the uppermedium range cri
~=O.20
,
,
I
terion. As shown, the range criterion overcomes the
'. I
qualitative misinterpretation problems emerging from
(b) ] 106 lOR
Frequency (Hz) conventional simplification criteria. Furthermore,
quantitative root displacements are minimal for margin
Fig. 8. Illustrating performance of the uppermedium range criterion
for the PSRR of the Miller OTA: (a) parametric magnitude error errors up to 50 %. On the other hand, complexity of the
curves; (b) corresponding phase error curves. simplified formula is similar to that for the conventional
Formula Approximation for Flat and Hierarchical Symbolic Analysis 53
~
called expanded format expressions. This format is ap
propriate for low and medium complexity circuits, as
demonstrated in previous examples, but not for larger
circuits. Hierarchical symbolic analysis must be used
(c)
for large circuits, e.g., highspeed and fully differential
op amps, active filters, etc. [20]. Since nested instead
Fig. 13. Example of hierarchical circuit: (a) voltage amplifier based
of expanded format expressions result when applying on transconductors; (b) transconductance amplifier ac conceptual
these approaches, and due to the huge computational model; (c) transconductance amplifier architecture and related build
cost of expanding large nested formulae (if it were ing block models.
54 Fernandez, RodriguezVazquez, Martin and Huertas
Routine hierarchical analysis allows us to obtain the where GNk(s, x) and GDk(s, x) are symbolic polynomi
following nested expression for the voltage gain of fig als in s and the circuit parameters x. Our interest lies
ure 13a: in determining how GNk(S, x) and GDk(s, x) contribute
to the numerator and the denominator of the root ex
H(s)
pression H(s, x), if this root expression is transformed
and given as a ratio of two s polynomials. These con
(YiC1 + Yopl){(YOC) + YodCl'ic2 + Y op2 ) + 2Fc2 Gp2 } tributions can be seen from the following formula:
(24)
H(s, x) == HN(s, x)
where the numerical subscripts correspond to the HD(s, x)
amplifier numbers in figure 13a and, for simplicity, the
GNk(S, X)CNNk(S, x) + GDk(s, X)CNDk(S, x) + RN(s, x)
dependency of the different subexpressions on the com
plex frequency s is not explicitly shown.
GNk(S, X)CDNk(S, x) + GDk(S, X)CDDk(S, x) + RD(s, x)
(26)
Subexpression hierarchy in a nested formula can be
conceptualized as an inverted tree, like that shown in where the polynomials CNNk , CDNb CNDb CDDk repre
figure 14, for (24). Each node in an inverted tree con sent the contribution factors of G Nk and G Dk to the
tains an associated expression. The lowest nodes of the total transfer function H('); Rn (') and RD (') denote the
hierarchy (the tree leaves) corresponds to expanded for parts of the numerator and denominator polynomials
mat expressions. Expressions at the top node (the root of H(') not contributed by gk' This concept of contri
node), and at the intermediate nodes are determined bution from the leaf nodes to the root node, as well
by lower level nodes connected to them. The expres as the associated mathematical treatment, can be ex
sions (equivalently the nodes) referenced by either the tended to intermediate hierarchy nodes.
root or any intermediate node are the children of that To ensure accuracy in the simplification, contribu
node. Similarly, for any node ni but the root, the set tion factors for the different subexpressions are calcu
of nodes at the subsequent hierarchy level whose ex lated, together with the coefficients of the different s
pressions are contributed by ni are its parents. As powers in H('), prior to pruning terms in the sUbexpres
illustrated by figure 14, following the inverted tree struc sions. Thus, we may determine beforehand how much
ture for a given circuit enables seeing how single ex those simplifications will affect the total. In our tech
pressions join together hierarchically to yield the root nique, contribution factors and system function coeffi
expression. cients are computed numerically, taking into account
the ranges of the coefficients appearing in the system
functions at the leaf nodes. Symbolic expansion at the
high hierarchy levels is not required for the algorithm.
It must be emphasized that the use of typical values,
instead of ranges, to compute contribution factors is un
sure as some expressions may be very sensitive to small
changes in the symbols; however, this fact is not dis
covered until reaching higher levels in the hierarchy.
Fig. 14. Inverted tree structure for the voltage gain of figure 13a.
In the proposed algorithm, simplifications are not 4.2. Overview of the Algorithm
applied to local expressions. Instead, contributions to
the root expression made by expressions at intermediate 4.2.1. Calculation of the Contribution Factors. In the
nodes and at leaves are assessed prior to reducing the following, contributions to the root expression from a
complexity of intermediate and leaf expressions. This given leaf node are denoted using uppercase subscripts;
is done using the contribution factor concept. This con lowercase subscripts denote contributions to the corre
cept is applied in the following to the particular case sponding parent. Since a node may be referenced in
of expressions at the tree leaves. more than one expression, the contribution to each
Assume the system function at a generic leaf node parent is denoted with a superscript. Thus, CDNi repre
sents the contribution to the denominator of the root
expression due to the numerator of the expression asso
(25)
ciated to the ith node. Likewise C~di represents the
Formula Approximation for Flat and Hierarchical Symbolic Analysis 55
contribution of the expression denominator of i th node, 4.2.2. Calculating Simplification Percentages. Once
to the numerator of the expression at kth node. To the contribution of each leaf node to the root is known,
simplify notation, the complex frequency, s, and the a matrix equation may be written expressing the error
symbolic parameters, x, will be omitted when denoting of the coefficients in the root node, as a function of
system functions and contribution factors. the error in the coefficients of the leaf nodes. The struc
The algorithm aims to store the leaves' contribution ture of this equation is
]
factors to the tree's root within the leaves themselves.
This is achieved in two steps: in the first one, the tree . ..
is traversed from the leaves to the root. The value of ...
each nonleaf node is computed together with the con
tributions of its children to it. Children are computed
before parents so that the latter have the information
to be computed. As a simple example, let us assume
we have a node with three children whose values have
already been computed or are leaf nodes:
,
Exact :>..,
,
The developed algorithm was applied to the OTAC ,,
bandpass filter structure of figure 15a [25]. The trans ~
I
,,
,
conductances and output impedances of the OTAs (de
(a) 1:~~1";;02':::104'~~1076~::J108
scribed at the transistor levels as shown in figure 15b) Frequency (Hz)
were considered to calculate the global transfer func
,
tion. The expanded formula would have hundreds of ,,, ,,,
millions terms and, consequently, none of the criteria ,, '
reviewed in Sections 2 and 3 is applicable to this case. ,,,
The criterion discussed in this section was applied to ,,,
this example to evaluate the relative importance of each Exact: Simplified
,
coefficient at the leaf nodes in the total function. This ,,,
enables applying higher margin errors at those leaf sym ,,
bolic expressions of less relative importance. Hence, .,
g ,,,
,,
a good tradeoff between accuracy and simplification
level is achieved.
, :
(b) 1 106 108
A smooth error function was applied to the coeffi Frequency (Hz)
parameters and addressing the problem of simplifica 8. G. Gielen, H. Walsharts, and W. Sansen, "ISAAC: A symbolic
tion for hierarchical symbolic procedures. Results simulator for analog integrated circuits," IEEE J. SolidState Cir
reported in the paper prove the suitability of the tech cuits, Vol. 24, pp. 15871597, 1989.
9. EY. Fernandez, A. RodriguezVazquez, and J.L. Huertas, "Inter
niques proposed. active AC modeling and characterization of analog circuits via
symbolic analysis," Analog Integrated Circuit Signal Process. ,
Vol. I, pp. 183208, 1991.
Acknowledgment
10. L.P. Huelsman, "Personal computer symbolic analysis programs
for undergraduate engineering courses," in Proc. 1989 IEEE Int.
The authors would like to acknowledge Professor Symp. Circuits and Systems, pp. 798801, Portland, 1989.
Lawrence P. Huelsman for encouraging them to submit 11. A. Konczykowska and M. Bon, "Automated design software for
this material. switchedcapacitor IC's with symbolic simulator SCYMBAL:'
in Proc. 25th Design Automation Corif., pp. 363368, 1988.
12. G.E. Gielen, H. Walsharts, and W. Sansen, "Analog circuit design
Notes optimization based on symbolic simulation and simulated anneal
ing," IEEE J. SolidState Circuits, Vol. 25, pp. 707713, 1990.
1. Most of the results in this paper have been obtained with a 4Mips 13. F.Y. Fernandez, A. RodriguezVazquez, and J.L. Huertas,
and 8Mbyte physical memory SUN3/260 workstation. "Design and applications of symbolic analysis tools for analog
2. In the rest of the paper the concept ofjormula complexity denotes integrated circuits," in Proc. First Int. Workshop Symbolic
the number of symbolic terms contained in a formula. Each addend Methods, Paris, 1991.
in (4) is considered as a term to this purpose. 14. A. Liberatore, S. Manetti, and M. Piccirilli, "A symbolic
3. For instance, simplification of the voltage gain for the folded cas approach to the timedomain analysis of nonlinear or switched
code aTA of figure 1b, with a maximum error margin of 60% networks," in Proc. Int. Workshop Symbolic Methods, Paris, 1991.
(M = 0.6), yields a dc gain deviation of 1.6% [9]. 15. A. Liberatore and S. Manetti, "Network sensitivity analysis via
4. An analog schematic is said to be sized when a numerical value symbolic formulation," in Proc. 1989 IEEE 1nt. Symp. Circuits
has been assigned to each circuit element and model parameter. and Systems, pp. 705708, Portland, 1989.
5. In practice a sufficiently fine grid should be defined inside that 16. R. Gregorian and G.c. Ternes, Analog MOS Integrated Circuits
region. jor Signal Processing, Wiley: New York, 1986.
6. Here, "symbol" is generally applied, in the sense that it may either 17. P. Allen and D. Holdberg, CMOS Analog Circuit Design, Holt,
denote a parameter space variable, a product of variables, or a Rinehart, and Winston: New York, 1987.
sum of products. 18. R. Unbehauen and A. Cichocki, MOS SWitchedCapacitor and
7. The models used in this example are intended only as an illustra ContinuousTime Integrated Circuits and Systems, Springer: New
tion. Hence, they do not include all the issues required for prac York, 1989.
tical transconductance amplifier applications. 19. Sspice User Manual, Version 1.0, Michigan State University, 1991.
20. M.M. Hassoun and P.M. Lin, "A new network approach to sym
bolic simulation of largescale networks," in Proc. 1989 IEEE
References Int. Symp. Circuits and Systems, pp. 806809, Portland, 1989.
21. G.A. Watson, Approximation Theory and Numerical Methods,
I. P.M. Lin, Symbolic Network Analysis, Elsevier: New York, 1991. Wiley: New York, 1980.
2. T. Ozawa (ed.), Analog Methods jor ComputerAided Circuit 22. C. Laber and P. R. Gray, ''A positivefeedback transconductance
Analysis and Diagnosis, Marcel Dekker: New York, 1988. amplifier with applications to highfrequency, highQ CMOS
3. YP. Tsividis, "Analog MOS integrated circuits: Certain new switchedcapacitor filters," IEEE J. SolidState Circuits, Vol. 23,
ideas, trends, and obstacles," IEEE J. SolidState CirCUits, Vol. pp. 13701378, 1988.
22, pp. 317321, 1987. 23. D. Nairn and C. Salama, "Highresolution, currentmode AID
4. E. Vittoz, "Future of analog in the VLSI environment," in Proc. convertors using active current mirrors," Electron. Lett., Vol.
1990 IEEE Int. Symp. Circuits Syst., pp. 13721375, 1990. 24, pp. 13311332, 1988.
5. L.R. Carley and R. Rutenbar, "How to automate analog IC 24. G. Di Domenico, S. Seda, M.A. Khaifa et aI., "BRAINSI
designs," IEEE Spectrum, pp. 2630, 1988. SYNAP: A symbolic solver for analog circuits," in Proc. First
6. G. Gielen and W. Sansen, Symbolic Analysis jor Automated Int. Workshop Symbolic Methods, Paris, 1991.
Design oj Analog Integrated Circuits, Kluwer: Boston, 1991. 25. E. SanchezSinencio, R.L. Geiger, and H. NevarezLozano,
7. S. Seda, M. Degrauwe, and W. Fichtner, "A symbolic analysis "Generation of continuoustime two integrator loop aTA filter
tool for analog circuit design automation," in Proc. 1988 IEEE structures," IEEE Trans. Circuits Syst., Vol. 35, pp. 936946,
Int. Con! Computer Aided Design, pp. 488491, 1988. 1988.
58 Fernandez, RodriguezVazquez, Martin and Huertas
Francisco V. Fernandez received the Licenciado en Flsica degree Juan D. MartIn received the Licenciado en Flsica degree from the
in 1988 and the Ph.D. degree in 1992, both from the University of University of Seville, Spain, in 1988. He is currently working towards
Seville, Spain. In 1988 he joined the Department of Electronics and the Ph.D. degree in the field of analog design automation. Since 1988
Electromagnetism at the University of Seville, where he is a teaching he has been working at the Department of Analog Circuit Design
assistant. He is also at the Department of Analog Circuit Design of of the Centro Nacional de Microelectronica. His research interests
the Centro Nacionale de Microelectronica. His research interests in are in the field of computeraided design, programming techniques
clude design and modeling of analog integrated circuits and analog and analog design automation.
design automation.
Abstract. A new symbolic technique for the realization of simulators for nonlinear analog circuits is presented.
The generated simulators work with input/output in numerical form, but they are very efficient due to the use
of the symbolic approach. For nonlinear components a PWL (PieceWise Linearization) method is used. The pro
posed approach permits to obtain libraries of simulators which can be very useful in many application fields. In
particular we present a possible application to an expert system devoted to nonlinear circuit fault diagnosis. The
program package, realized for this application, is described from both algorithmic and functional points of view.
Some simple examples are presented in order to illustrate the main features of the program.
2. they are devoted to a given circuit structure; in parallel with a current source Ii can be associated
3. they are independent from both the component with each nonlinear component: for every linearity
values and input values, which must be indicated region, Gi corresponds to the slope of the segment and
only at runtime, before numerical simulation. Ii to the zerovoltage current of the segment, as shown
Another novel aspect of the presented approach is in figure 1 for a diode.
constituted by the fact that the generated symbolic
simulators produce timedomain simulations and are
able to work on nonlinear circuits. To this end the 2.2. Transient Analysis Modelsfor Reactive Components
following methods have been used:
a. nonlinear components are replaced by suitable PWL The reactive components are made time independent by
models; using the backward difference algorithm and the corre
b. reactive elements are simulated by their backward sponding circuit models are constituted by a conductance
difference models; in parallel with a current source. In figure 2 the model
c. a Katznelson type algorithm is used for timedomain of a capacitor is shown as an example: the conductance
response calculation. value is a function of the sampling time T and the
In the following these three points are examined in capacitance value, while the current value depends on
detail. the sampling time T, the capacitance value and the volt
age value at the previous time step. In this way neither
the Laplace variable nor integrodifferential operations
2.1. PWL Models are used and the circuit becomes, from the symbolic
analysis point of view, without memory, and, from the
With the PWL technique [28] the voltagecurrent numerical simulation point of view, time discrete.
characteristic of any nonlinear electronic device is
replaced by piecewise linear segments obtained by
means of the individuation of one or more comer points 2.3. The Katznelson Type Algorithm
on the characteristic. The so obtained piecewise linear
characteristic describes approximately the element The Katznelson algorithm is an iterative process, which
behavior in the different operating regions in which it allows one to determine the dc solution of a PWL cir
can work. It is evident that the increase of the corner cuit. In its standard form this algorithm can be sum
points number and, consequently, of the linearity marized as follows [28, 29].
regions number allows to obtain a higher precision in The starting system is of the following kind:
the simulation of the real component; obviously, in this
(1)
way, the corresponding model becomes more complex.
It is worth pointing out that the symbolic analysis is where TI is the characteristic matrix of the circuit and
completely independent from the number of the PWL the subscript I denotes the region in which the network
characteristics corner points; in fact, from a symbolic operates. The righthandside vectors denote the
analysis point of view, each nonlinear component of equivalent sources due to linearization (WI) and the in
a PWL model is represented by a single symbol. How dependent sources (w) and they are written separately
ever, the increase of the number of corner points in for clarity. Since at the beginning the regions are
fluences computational time in the numerical simula unknown, the node voltages and the currents of current
tion phase, so a tradeoff between a small number of controlled elements are arbitrarily selected in order to
corner points and requested accuracy must be realized determine all the operating regions of PWL elements.
for each model. Then all GI and II are known and the vector XI is so
In order to determine the circuit network functions determined.! This vector does not satisfy equation (1)
the MNA (Modified Nodal Analysis) [19] is used dur due to the arbitrary choice of node voltages and the cur
ing symbolic analysis. This method yields a solving rents of the current controlled elements. Thus an
system whose dimension increases with the number of iterative process of correction starts for which the
components which have impedance representation. For estimated vector XI represents the initial value. By
this reason, if possible, a characteristic I = G(V) has defining an error vector as:
to be considered for nonlinear components. In this way,
an equivalent circuit constituted by a conductance Gi (2)
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 61
+
~I
Gl I l
v
o
I 2
a) b)
Fig. 1. (a) Diode PWL model; (b) diode PWL characteristic.
B c
E CCC5
a) b)
esat
c)
Fig. 6.. (a) BJT transistor model; (b) PWL model; (c) nonlinear conductance characteristic.
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 65
G.ill
a)
c)
{\Vd
Vu
Va<Vd<Vb
Vv =
elsewhere
V max . ..... .
,
f:":x
Va
V d< Va
Vb +  Vf
VV =Vd V d> Vb
V mm
. Va < Vd < Vb
b)
Fig. 7. (a)Op amp; (b) inputoutput PWL characteristic; (c) PWL model.
OUT 0) 1
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Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 69
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t ";" o o ~ t_... ,_._ .."; ~ ~
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"It's funny how many of the best ideas are just an old idea backtofront."
Douglas Adams
Abstract. In this paper, two efficient approaches will be discussed that support linear network analysis: supernode
analysis (SNA) and reduced loop analysis (RLA). By means of some selected example networks, these methods
will be demonstrated and, thus, it will be shown that calculations can be dramatically simplified. In this way,
all network situations can be handled. There are obvious advantages to SNA as it combines the MNA and the
straightforward manual processing of the network. A very efficient solution strategy is obtained without source
shifting and other common, less directed methods being used. SNA/RLA and symbolic algebra fit extremely well
together. Thus an algorithm that supports the symbolic calculation of networks by means of supernodes which
has been conceptualized and implemented in the analog design expert system EASY will be presented in detail.
Above the educational aspect, it should be noted that the computer can now take a systematic approach to MNA
and network analysis in general.
Then, the Ui are expressed one by one in terms of loop DEFINITION. Supernodes are generalized cutsets2
currents, and finally, those intermediate results are rein enclosing independent and/or dependent voltage sources
serted in the above equation. This procedure is not actu [1] .
ally incorrect, but, it is contrary to all efforts that try These special cutsets will be used in a very efficient
to avoid the introduction of unnecessary variables and way as will be shown below.
equations.
To introduce unnecessary variables and equations
complicates the system of equations that need to be 3.1. Algorithm for Setting Up SNA Equations
solved. Furthermore, it obstructs any attempt towards
applying loop analysis to networks containing elements To set up the equations needed for SNA done by hand,
that have no impedance representation at all, such as follow these steps:
current sources and opencircuit branches. In a similar
1. Label each of the n nodes of the network, one of
way, everything mentioned here applies to the setting
which must be the reference node. Thus (n  1) node
up of node equations as well.
voltages have to be taken as independent variables.
There exist several approaches to the systematic for
2. Mark all supernodes by surrounding all the cutsets
mulation of network equations which either require the
of voltage sources (s is number, no matter whether
network to contain certain types of elements only or
dependent or independent) by a closed line.
which yield a larger number of equations but can handle
3. Set up all forced conditions for each supernode. Use
all types of elements. A wellknown example for the
the forced conditions to eliminate s node voltages.
latter is modified nodal analysis (MNA). Regrettably,
Take one reference node voltage of each supernode
MNA introduces additional equations although there
as the independent variable.
should be no need to set up more than n  1 equations
4. Set up the remaining (n  s  1) generalized cut
if there are n nodes in the network. Likewise, I loops
set equations. (Set up one equation for each super
should not yield more than I equations for any given
node as well as for every remaining regular node.)
network. Actually, there is no reason at all why current
sources should not appear in networks to be analyzed
Remark. Controlling currents have to be expressed in
with loop analysis (LA). For example, if a source cur
terms of node voltages and element relations. This
rent i could be identified with one independent loop
might require additional node equations.
current jb the loop equation to obtain jk would not
even need to be set up, as jk is equal to i. The same
applies to nodal analysis (NA). If a voltage source is
3.2. Algorithm for Setting Up RLA Equations
considered as a forced potential difference of u between
its two terminal nodes (A) and (B), then one potential
The setup of the equations for RLA can be divided into
would be immediately known if either of the potentials
the following steps:
VB or VA were known. It turns out that every current
source sets a forced condition for LA much in the same 1. Remove all current sources (s in number, dependent
way that every voltage source does for NA. Conse or independent) from the network.
quently, each forced condition reduces the degree of 2. Introduce (l  s) loop currents for the remaining
freedom of the independent equations by one. These (I  s) independent closed loops.
approaches will be called supernode analysis (SNA) 3. Reinsert the current sources step by step and assign
and reduced loop analysis (RLA). only one loop current to a closed loop laid across
this source in each step.
4. Identify all loop currents flowing through the current
3. Manual Equation Setup and Motivating Examples sources with the source currents themselves.
5. Set up all remaining loop equations. Express all volt
Before some examples can be calculated to illustrate ages in these loops in terms of loop currents, the con
the backtofront idea underlying these approaches, a straint equations from step 4, and element relations.
clear definition of what supernodes are must be made 6. If there are voltage controlled sources, additional
before they are used. equations have to be set up.
More Efficient Algorithms for Symbolic Network Analysis 75
Another procedure to obtain an optimized set of Now the steps for the supemode method are applied:
loops is to generate a tree from the network in which
I. All nodes are labeled by VI, ... , Vs respectively.
the current sources are located within the interconnec
2. Two supemodes are found and marked (see above).
tion branches. This tree approach can also be used to
3. The forced conditions are set up (reference voltage
prove the correctness of RLA. Furthermore, it should
of supemode SNI is VI): The additional equation
be relevant to support the implementation of RLA on
for the CCVS is V3  VI = rG4 (V1  Vs); this
a computer, because there are several methods to find
directly applied results in
exactly those trees by making use of the nodal incidence
matrix A [3]. V2 = VI + UOI (fl)
The following examples will hopefully put aside any
difficulties.
V4 VI + U02 (f2)
Vs U03 (f3)
Fig. 1. Example to demonstrate MNA and SNA. Fig. 2. Example for RLA.
76 Sommer, Ammermann and Hennig
2. The loop current jl is assigned to this loop. overall number (zero is a trivial case), is the approach
3. Reinserting 10 closes the loop L2 (identified with which will require the sources to be shifted in that direc
loop current h), then the VCCS is inserted, thus tion. If SNA is the preferred method, then current
completing loop L3 (identified with loop currenth). sources have to be created. This may require more than
4. The loop currentsh andh are identified withh = one shift (see preceeding example). On the other hand,
10 and h = gU" where U I = Rlh if RLA is the preferred method, then voltage sources
5. By directly inserting these relations the loop equa have to be created through source shifting.
tion LI is set up: The circuit (figure 3) is another example for using
SNA. On the other hand, when using RLA, six loops
RIUI) + Rz(h  gRljl) + R3UI  10) = 0
are found, and two forced conditions are set by current
This equation could be solved with ease. sources. As a result, source shifting or RLA would
The network on the righthand side is a little more result in four equations. Applying the steps of SNA to
complicated as the currenth through the VCCS flows the network in figure 3:
in the controlling branch (R4 ) , too. For this reason,
one more equation has to be considered: Steps 1 and 2 1. All nodes are labeled by VI, ... , V4 respectively.
are the same as above, but in step 3 the voltage U4 2. Two supernodes are found and marked (see above).
across R4 has to be expressed in terms of loop currents
and element relations:
R4/ 0
3. U4 = R4(gU4 + 10) ~ U4 = 1 + gR
4
Now the loop equation (L1) to derive !..I 3is set up:
4. LI: . IC J I
JW 1
+ Rz (J I
l:..  g 1 ~/OR
+g 4
J
+ R3(!..1  10) =0
0,,;/(::1_+.:g;:..R..;,4,,)_+~R",3L,"0
~!..I _R_=ZR=4,""g::/
1/jwC + R + R I z 3
Fig. 3. Network, supemodes marked.
V,Uo, VI g(UO,+UOI  vd
r ...!:.... VIUOI
R. R3 R, R.
I
U021
'"
1
Fig. 5. Transformation to Norton equivalent circuit.
More Efficient Algorithms for Symbolic Network Analysis 77
V3 = U02 (fl) I
V4 = VI  Uo, (f2)
+ Gs(V,  UOI)  10 = 0
4. All remaining node equations are set up. There is
which is one equation with V, as unknown. no equation needed for SNo because it is the refer
ence node. Moreover, no equations are necessary
for nodes 1, 2, 3, and 6, since they belong to SNo.
4. Applying SNA to Nullor Networks This leaves only nodes 4 and 5 to supply the missing
two independent equations. By immediately insert
Since there already exist other approaches that make ing the constraints from step 3, the following equa
nullors fit into the concept of nodal analysis, it would tions are obtained.
be interesting to know if the same object could be
accomplished with SNA. In fact, only the following N4: G'(UI  V3 ) + G(U,
two rules have to be observed to achieve the goal. N5: GUz + Gz(Uz  V6 )
1. A norator must be considered as a voltage source These equations can easily be solved for V3 and V6
with an unknown output voltage.4 Therefore, norators It becomes apparent from this example and other
are treated like all other voltage sources as far as research, that SNA is a truly universal and powerful
their inclusion in a supernode is concerned. How tool for handling all imaginable network elements and
ever, since their output voltage is arbitrary, they do configurations.
not furnish any constraint equations. This is logical
as each norator causes the rank of the admittance
matrix to be reduced by one. 5. An RLA Approach to Nullor Networks
2. Nullators must not be incorporated into a supernode.
Each nullator forces the potentials at its two terminal The following example demonstrates that RLA is also
nodes to be equal, thus eliminating one node voltage able to handle nullors very well.
from the system of equations. Figure 7 shows the network that will be analyzed
To demonstrate the application of SNA to nullor net below. In fact, it is almost the same network on which
works, the example network in figure 6 will be ana
R
lyzed. The task shall be to compute the node voltages
V3 and V6 .
1. All nodes are given individual labels/variables:
VI>' .. ,V6
2. All supernodes are marked. In this case, there exists
only one supernode, which consists of the two volt
age sources U, and Uz, and both norators. Fig. 7. Gyrator equivalent circuit.
78 Sommer, Ammermann and Hennig
an SNA was already performed in Section 4. The task Sorting the equations and variables results in the follow
supposed here is to compute the output current of the ing 3x3 system that must be solved for the norator out
norator on the righthand side. Since the unknown value put current 17.
is a current, it is best to apply RLA. Thus, one loop
current has to be defined for each of the seven indepen
dent loops as was shown when RLA was introduced.
R_~l R,
o
R ~ R2]
R2
[!:]
17
As far as the nullors are concerned, a few additional
rules must be observed. = [Rl\  (2~2 + R)12 ]
type of mathematics needed to solve the system of equa the other potential is well defined (in terms of the first),
tions. In the following sections, this aspect will be in and is no longer an equation in the system that needs
vestigated in detail. Furthermore, an algorithm already to be solved. The number of unknowns has been re
implemented in EASY [4, 5], will be presented and duced from three to one. For example, Vq can be ex
discussed. pressed as Vq = Vp  Uo. Exactly this elimination is
The MNA is a well known and commonly imple recognizable in the filling pattern of the MNA matrix
mented method for the analysis and calculation of net (see figure 9). It is possible to add row p to row q. One
works: for example, SPICE. At this moment, only the of the original two rows may then be deleted. In this
results of the theory behind the MNA are needed, so manner, the variable i k can be eliminated, so that this
that the matrix can be filled appropriately for each ele column may be deleted as well. This seems to be the
ment. The nodebased equations (KCL) represent each RMNA approach sometimes referenced in the litera
row of the aforementioned matrix. ture [6].
i. q
~q I, .I
This degree of freedom can be immediately reduced
Nullator fillin Norator fillin
by applying the forced condition (*). Consequently, one
of the two potentials remains as an unknown, whereas Fig. 10. Fillin patterns of a nullator and a norator.
80 Sommer, Ammermann and Hennig
1. Each of the nullator and norator introduce only one Explanation (4b). The inclusion of the row k' to
new row or column, but not both. Consequently, the the supernode k, k' still allows access to the origi
matrix is no longer square, and the system of equa nal node(s), and thereby does not hinder the collec
tions is singular. tion of several nodes into a supernode.
2. A nullor (a nullator and a norator) eliminates one Note. If k or k' is the reference node (ground)
row and one column from the matrix. This is equiva then step 4a is not performed. In place of step 4b,
lent to constructing a supernode around the norator. the computer generates supernode SNo labeled with
Mathematically, row r is summed to row s, resulting 0, k.
in row r being removed from the matrix. In this way, Explanation. The reference node row is linearly
the norator current is eliminated from the list of un dependent on the other nodal rows. It may be deleted
knowns. A nullator equates Vp to Vq . This collec because it has been incorporated into SNo. The
tion of unknowns means that column p is added to voltage reference is remembered.
column q, and columnp can be removed. Likewise, 5. For all shortcircuits between node j and node j':
Vp is removed from the list of unknowns. a. Add column j to column j'.
b. Delete column j which is redundant.
c. Remove row m + 1 which is a zero row. (Row
8. Algorithm Implemented in EASY m + 1 denotes the row belonging to the short
circuit.)
EASY [4, 5] is an experimental analog design expert Explanation (5a). A shortcircuit means Vj = vr,
system developed at the Institute of Network Theory and therefore, the columns are combined.
at the Technical University of Braunschweig. The Explanation (5b). Row m + 1 informs that Vj =
following algorithm was conceptualized and imple vr' This is the forced condition.
mented in EASY. The algorithm supports the symbolic 6. Fixing of desired voltages:
calculation of networks by means of supernodes. It a. Output of all remaining nodal voltages.
offers the possibility to express the results in the b. User input of desired voltages in terms of node
Belevitch form, which is needed to support the calcu voltage differences.
lation of networks containing nonlinear elements via c. Apply the following scheme for the substitution
a piecewise linear representation. This will be re of nodal voltages by branch voltages:
ferred to as the PWL Tool, and is described in more (i) Potentials not needed for the description of
detail in [9]. the desired voltages must remain.
The algorithm contains the following steps: (ii) Of the r branch voltages that exist, as many
(if not all) as possible are to be used to
1. Read in network/netlists (to calculate currents, a replace the node voltages (s) being their
short circuit branch must be identified). number). For this reason, the rank of the
2. Set up standard matrix for MNA. matrix V must be r, otherwise the voltages
3. Create lists needed for the evaluation. are linearly dependent on each other.
a. Create list of all control currents (L)).
100
b. Create list of all generated currents in the MNA
010
(Lz)
001
c. Deduce list of desired currents (~).
d. Generate the union list/set of L 1 and ~ (Lunion)'
4. For all currents from node k to k', ik,k' rt: Lunion:
a. Add row k to row k'.
V,
b. Rename row k' to k, k'.
c. Delete row k and column h,k" i.e., the column 1 0 0 V" ..
belonging to the eliminated current. 1 I 0 V 2 , .
Explanation (4a). By the addition of row k and 0 1 1 V .. , ..
row k', a cutset of node k and k' is generated: the (1)
supernode. The internal currents through the voltage
sources and the shortcircuits will be eliminated in
this way. Vs
More Efficient Algorithms for Symbolic Network Analysis 81
By using GaussSeidel elimination tech dents have often commented that the above listed ideas
niques, the matrix will be restructured to ap have been juggled in a haphazard somewhat nonpredict
pear in the form: able way resulting in a poor understanding of circuit
analysis. Consequently, many may now be able to inter
vJ, .. pret several of the SNA equations as one or the other
V2 , .
of the above listed "magical tricks."
0 0 v .. ,..
[1 1 0
1 1
...
] V4
V ..
10. Conclusions
The resulting amount of work is much less in compari 3. L.O. Chua and P. M. Lin, ComputerAided Analysis ofElectronic
son to sparse tableau or MNA approaches. Above the Circuit Analysis, Prentice Hall: Englewood Cliffs, 1975.
4. R. Sommer, R. Kamitz, and E.H. Horneber, "Qualitative reason
educational aspect, it should be noted that the computer
ing in the analog design expert system EASY," in Proc.
can now take a systematic approach to MNA and net ECCTD'9I, Copenhagen, 1991.
work analysis in general. The fact that the current 5. R. Sommer and E.H. Horneber, "EASYan experimental
centered representation has proven so fruitful may result analog design system framework," in Proc. Int. Workshop Sym
in more research in this area. bolic Methods and Applications to Circuit Design, Paris/Bagneux,
1991.
6. K. Lee and S. Park, "Reduced modified nodal approach to cir
Acknowledgments cuit analysis," IEEE CAS32, No. 10, 1985.
7. W. Sansen and G. Gielen, "ISAAC: A symbolic simulator for
analog integrated circuits," IEEE J. SolidState Circuits, Vol. 24,
The authors would like to acknowledge the students C. No.6, pp. 15871597, 1989.
Beckmann, H. Trispel, and G. Weinerth for their con 8. G. Gielen and W. Sansen, Symbolic Analysis for Automated
tributions toward the project. We would especially like Design of Analog Integrated Circuits, Kluwer: Boston, 1991.
to thank A. Reibiger, Technical University Dresden, 9. R. Sommer, D. Ammermann, and E.H. Horneber, "Qualitative
reasoning and nonlinear effects in analog design expert system
for profound discussions and for providing the theoreti
EASY," in Proc. ICM'9I, Kairo, 1991.
cal background, and H. Ziemann for his invaluable help 10. Symbolics MACSYMA Reference Manual, Version 13, 1988.
during the translation of this paper. 11. W. Sansen and G. Gielen, in Proc. Summer Course in Systematic
Analogue Design, Katholiek Universiteit Leuven, 1990.
Notes
Eckhard Hennig was born in Westerstede, Germany, on January 14, Dirk Ammermann was born in Bremen, Germany, on March 16,
1969. He is a graduate student in electrical engineering at the Technical 1967. He started studying electrical engineering at the Technical
University of Braunschweig. University of Braunschweig in 1987. In 199192, he attended Georgia
Institute of Technology, where he received his M.S. in electrical
engineering.
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