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SYMBOLIC ANALYSIS OF

ANALOG CIRCUITS:
TECHNIQUES AND APPLlCATIONS
edited by

Lawrence P. Huelsman
University of Arizona, Tuscon
and
Georges G.E. Gielen
Katholieke Universiteit Leuven Belgium

A Special Issue of
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

Reprinted from ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING


Val. 3, No. 1 (1993)

SPRINGER SCIENCE+BUSINESS MEDIA, LLC


THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSING

Consulting Editor

Mohammed Ismail
Ohio State University

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INTRODUCTION TO THE DESIGN OF TRANSCONDUCTOR-CAPACITOR
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MICROWAVE CIRCUITS, Kenneth S. Kundert, Jacob White, Alberto
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Contents

Special Issue on Symbolic Analysis of Analog Circuits:


Techniques and Applications
Guest Editors: Lawrence P. Huelsman and Georges G.. Gielen

Editorial Mohammed Ismail. David G. Haigh and Nobuo Fuji 5

Guest Editors Introduction Lawrence P. Huelsman and Georges G. E. Gielen 7

Symbolic Analysis of Simplified Transfer Functions .


Marco Amadori, Roberto Guerrieri and Enrico Malavasi 9

Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach .....
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Marwan M. Hassoun and Kevin S. McCarville 31

Formula Approximation for Flat and Hierarchical Symbolic Analysis .


. . . . . . . . . . . . . . . . . . . . . . . .. FV Fernandez. A. ROdriguez-Vazquez, J.D. Martin and J.L. Huertas 43

Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits .


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S. Manetti and M.e. Piccirilli 59

More Efficient Algorithms for Symbolic Network Analysis: Supernodes and Reduced Loop Analysis
Ralf Sommer, Dirk Ammermann and Eckhard He mig 73
Llbrary of Congrcss Cataloging-in-Publication Data

Symbolic analysis of analog circuits : techniques and applications I


edited by Lawrence P. Huelsman, Georges G. E. Gielen.
p. cm. -- (The Kluwer international series in engineering and
computer science : SECS 219. Analog circuits and signal processing)
Issued also as a special issue of Analog integrated circuils and
signal processing, volume 3, no. 1, January 1993.
ISBN 978-1-4613-6424-5 ISBN 978-1-4615-3240-8 (eBook)
DOI 10.1007/978-1-4615-3240-8
1. Electric circuits, Linear. 2. Symbolic circuit analysis.
3. Electronic circuit design-oData processing. 1. Huelsman,
Lawrence P. II. Gielen, Georges. III. Series: Kluwer international
series in engineering and computer science ; SECS 219. IV. Series:
Kluwer international ser ies in engineering and computer science.
Analog circuits and signal processing.
TK454 . 15 . LS6S96 1993
621 . 3815--dc20 92-40211
CIP

Copyright 1993 by Springer Science+Business Media New York


Originally published by Kluwer Academic Publishers in 1993
Softcover reprint ofthe hardcover Ist edition 1993
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, record ing,
or otherwise, without the prior written permission of the publisher, Springer Science+
Business Media, LLC.

Printed on acid-free paper.


Analog Integrated Circuits and Signal Processing 3, 5 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Editorial

We are pleased to announce that starting with this issue of Analog Integrated Circuits and Signal Processing (Volume
3, 1993), the Journal will appear six times a years instead of four. This increase in issues per year is intended
to keep up with the increased number of high quality papers being submitted for publication.
We are also very pleased to welcome as members of the Editorial Board, Drs. John Choma, Jr., Johan Huijsing,
Edgar Sanchez-Sinencio, Trond Srether and Gabor Ternes, and we look forward to the valuable contributions they
will make to our Journal.

Mohammed Ismail
David G. Haigh
Nobuo Fujii
Editors-in-Chief
Analog Integrated Circuits and Signal Processing 3, 7 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Guest Editorial

This Special Issue is dedicated to the techniques and applications of symbolic analysis for analog circuits. The
general topic of analog circuit analysis may be divided into two main categories. The first of these is usually called
numeric analysis. In this, numeric values of ohms, henries, farads, gain, and so forth, are assigned to the appropri-
ate circuit elements. The interconnection of the elements in the circuit is specified by topological information,
typically given as node numbers. The goal of the analysis is the generation of numeric information giving sinusoidal
steady-state or time-domain response information, which is presented either in tabular form or, more usually, as
plotted information. Examples of numeric analysis are readily seen as the output from the SPICE program or
its PC counterpart PSpice. The second general category of analog circuit analysis is the one addressed in this Special
Issue, namely symbolic analysis. In this, literal names (symbolic values) are assigned to the elements of the circuit.
These literal names represent the symbolic (nonnumeric) values of the ohms, henries, farads, gain, and so forth
of the circuit elements. These names, together with the topological interconnection information, are used to create
a network function in the complex variable s or z which gives a description of the relation between the transformed
output and input variables of the circuit. In such a network function, the coefficients of various powers of s or
z appear as explicit functions of the literal names of the circuit elements.
Symbolic analysis and the computer techniques for automated symbolic analysis, i.e., the automatic generation
of analytic equations describing a circuit's electrical behavior, have reattracted much attention in recent years.
They represent a natural way of analyzing a circuit, a way taught in all basic engineering courses and practiced
by real-life designers. Symbolic analysis is far more general than numeric analysis, since if offers complete freedom
in the choice of applications, and includes sinusoidal steady-state and time-domain studies as special cases. Numeric
simulators such as SPICE have become much more popular than symbolic ones as design supporting CAD tools,
because they can rapidly and accurately simulate a circuit's behavior, including its transient response. They are
also able to simulate larger-size circuits. In contrast, however, symbolic analyses can provide many results which
are simply not available from numeric simulation methods. Most importantly, they can provide explicit insight
into the dominant behavior and properties of a circuit. Among the useful applications of this insight are the deter-
mination of derivatives of the network function with respect to one or more elements. Such literal information
provides direct application to sensitivity determination. Another application of the insight obtained from symbolic
analysis is the development of the equations which are required in the use of optimization techniques to provide
solutions to specific design specifications. With SPICE-like numerical simulators, the same insight can only be
obtained after combining and often extrapolating the results of numerous simulation runs. In addition, symbolic
analysis can also be used in many other applications, such as in compiled-code evaluation for statistical analysis,
and automated synthesis or failure diagnosis of analog circuits, much the same way as symbolic Boolean analysis
is used for synthesis and verification of logic circuits.
For a long time, symbolic circuit analysis has been regarded as an academic topic. It is true that it has computa-
tional complexity limits which have prevented it from being feasible for large-size circuits. In recent years however,
enormous progress has been made in developing more advanced techniques and algorithms for symbolic circuit
analysis. This has resulted in an extension of the functionality of symbolic simulators, including for instance the
automatic generation of simplified symbolic expressions or the automatic generation of symbolic distortion for-
mulas. At the same time, the capabilities of symbolic analysis have been extended toward larger circuits by the
introduction of hierarchical methods. All these advancements have resulted in the recent development of several
successful symbolic simulators such as ISAAC, ASAP, SC, and SSPICE. As a result, symbolic analysis is finally
becoming an attractive tool to assist designers in real-life circuit design.
This Special Issue contains five selected papers that present recent developments in the field of symbolic analysis
for analog circuits. The first paper, by Amadori et aI., presents original algorithms for the direct generation 0;'
simplified symbolic transfer functions based on the relative magnitudes of the circuit elements. These simplified
expressions, which show the dominant contributions only, provide a good approximation for the overall circuit
behavior. Also, an algorithm for the simplified symbolic computation of the poles and zeroes of the transfer func-
tions is described. Hassoun and McCarville, in the second paper, describe an approach to the symbolic analysis
8 Huelsman and Gielen

of large-scale networks based on hierarchical decomposition. The total network is recursively decomposed into
smaller subblocks, which are analyzed separately. The expression for the total network is then obained by combin-
ing bottom-up the expressions for the subblocks. This tremendously reduces the CPU time and the number of
symbolic terms for large circuits. In the third paper, Fernandez et al. describe new criteria and algorithms for
the generation of simplified expressions, both for flat and hierarchical symbolic analysis. A major difference between
this approach and that given by the first paper, is that the simplification is carried out taking into account a range
of element values instead of a single nominal value for the magnitude of each circuit element. The technique of
simplification is also extended to the hierarchical formulas, which would be the result of the decomposition method
of the second paper. This combination opens new perspectives for the fast generation of both exact and simplified
symbolic expressions for large circuits. In the fourth paper, Manetti and Piccirilli show how dedicated simulators
based on compiled symbolic formulas can boost the efficiency of applications requiring repetitive circuit evaluation.
Nonlinear circuits are handled with piecewise linear approximation. The application of the method to nonlinear
circuit fault diagnosis is presented, in which the actual element values and hence also faulty components are extracted
by fitting the simulated to the measured response. Finally, in the short paper by Sommer et al., two alternative
network equation formulations are highlighted: supernode and reduced loop analysis. Compared to the classical
node, loop, and MNA formulations, the described variants result in simpler equations. This is advantageous both
for manual analysis as well as for computerized symbolic analysis.
The editors would like to thank all the authors who submitted papers, all the reviewers who participated in
the final selection of the papers, and the Kluwer Editorial Staff for their efforts in creating this Special Issue.
We hope that this Issue will provide you, the reader, with a useful introduction to the potential and power of the
use of symbolic analysis techniques in analog design.

Lawrence P. Huelsman
Georges G.E. Gielen

Lawrence P. Huelsman received the BSEE degree from Case Institute of Technology and the MSEE and Ph.D.
degrees from the University of California at Berkeley. He is a Fellow of the Institute of Electrical and Electronic
Engineers. He currently holds an appointment as Professor Emeritus of Electrical and Computer Engineering at
the University of Arizona.
Dr. Huelsman is the author or coauthor of sixteen books including: Basic Circuit Theory-3rd Ed. published
by Prentice-Hall, Inc.; and Operational Amplifiers: Design and Applications. Introduction to Operational Amplifier
Theory and Applications, and Introduction to the Theory and Design of Active Filters, published by the McGraw-
Hill Book Company. Japanese, German, Spanish and Russian translations have been made of several of his books.
He has also published many papers in the area of active circuit theory.
He has served as Associate Editor of the IEEE Transactions on Circuit and System Theory and the IEEE Trans-
actions on Education and was technical chairman of the IEEE Region Six Annual Conference. He is a member
of the steering committee for the Midwest Symposium on Circuits and Systems. He is a member of several scien-
tific, engineering, and honorary societies, including Tau Beta Pi, Phi Beta Kappa, Eta Kappa Nu, and Sigma Xi. He has received the Anderson
Prize of the College of Engineering and Mines of the University of Arizona for his contributions to education.

Georges G.E. Gielen was born in Heist-op-den-Berg, Belgium, on August 25, 1963. He received the E.E. and
Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1986 and
1990, respectively. From 1986 until 1990, he was appointed by the Belgian National Fund of Scientific Research
as a Research Assistant at the ESAT laboratory of the Katholieke Universiteit Leuven, working on symbolic analysis
and analog design automation. From 1990 until 1991, he was connected to the University of California, Berkeley,
as a Visiting Lecturer and Visiting Research Engineer, working on behavioral models for analog integrated circuits.
In October 1991, he was again appointed by the Belgian National Fund of Scientific Research as a Senior Research
Assistant at the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven, Heverlee, Belgium, where he is
currently heading the analog design automation group. His research interests are in the design of analog and mixed
analog-digital integrated circuits and in analog design automation (modeling and simulation, synthesis, optimiza-
tion, layout and testing). He has authored or co-authored more than 30 papers, including several chapters for edited
books. In 1991, he also published a book on symbolic analysis and design automation of analog integrated circuits.
Analog Integrated Circuits and Signal Processing 3, 9-29 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Symbolic Analysis of Simplified Transfer Functions

MARCO AMADORI, ROBERlO GUERRIERI, AND ENRICO MALAVASI


Dipartimento di Elettronica, Informatica e Sistemistica, Universita di Bologna, viale Risorgimento, 2-40/36 Bologna, Italy

Abstract. This contribution presents new algorithms for the automatic simplified computation of symbolic transfer
functions of linear circuits. The problem of symbolic simplification of transfer functions is defined and a set of
algorithms able to cope with this problem and the simplified computation of poles and zeroes is developed and
discussed. Results are reported with examples of circuits analyzed by our algorithms, showing good accuracy in
their approximation, when compared to the corresponding SPICE simulations. Our technique merges the simplifica-
tion procedure and the evaluation of the transfer functions, thus achieving significant improvements in terms of
CPU time, compared with direct evaluation of the functions themselves.

1. Introduction methodology have been presented in [10], [11], and


[13]. The goal ofthis approach is twofold. Firstly, the
The present trend in the realization of complex systems, availability of simple expressions provides a better
where analog and digital parts often coexist on the same understanding of the behavior of the circuit and of the
chip, requires CAD tools to automate the various design relative importance of each parameter, avoiding at the
phases. Although the design of the digital circuitry is same time a tedious and error-prone manual elabora-
extensively carried out by automatic tools, it is not easy tion. Secondly, compact analytic expressions simplify
to find appropriate CAD tools for the analog synthesis; the work of numeric optimizers used for circuit synthe-
therefore a significant effort is required by expert sis, since the problem is considerably reduced in its
designers to implement the analog parts by hand. This complexity as well as in the number of parameters [14].
introduces delay and cost into the chip design process. This feature would allow the use of circuit synthesis
A phase requiring much time and effort is the com- tools such as IDAC [15] and OPASYN [16] for arbitrary
putation of the transfer functions that describe the cir- architecture cells. In [10], simplification is achieved by
cuit behavior. The research in the automatic derivation exploiting the knowledge of the circuit structure. The
of symbolic transfer functions of electronic circuits was retrieval of peculiar components and architectures in
developed during the seventies [1-3]. Due to the com- the schematic (such as differential pairs and current
plexity of the symbolic expressions and the difficulty mirrors) and the recognition of nonsignificant capaci-
of dealing with nonlinear problems, this field was later tances allow the tool to simplify the circuit neglecting
abandoned, although it had produced several interesting nonrelevant parameters. In ISAAC [13] a heuristic ap-
contributions, such as efficient algorithms for the com- proach based on the order of magnitude of circuit
putation of transfer functions [4-6] and accurate estima- parameters is described. This allows the tool to neglect
tions of the computational complexity of these problems the parameters which provide small contributions to the
[7, 8]. In the following years, numerical simulation of overall transfer function.
linear and nonlinear circuits [9] received a much Unfortunately, neither approach addresses the prob-
stronger emphasis since it removed the above limitations. lem of formal definition of simplification. Both use
In recent times, the symbolic analysis approach has heuristics when dealing with the reduction of computa-
gained new interest [10-12], aiming at the achievement tion and, finally, do not analyze the stability properties
of automatic computation of simplified transfer func- of the simplified expressions, when working in the fre-
tions. A broad overview of the techniques for symbolic quency domain.
analysis can be found in [13], while applications of this In this paper we propose a novel approach to the
This work has been partially supported by the National Council of simplification of transfer functions. Four original algo-
Research (CNR) under Progetto Finalizzato MADESS and by a grant rithms are presented. The first reduces the full rational
of SGS-Thomson, Agrate Brianza. expression of a transfer function by means of a global
10 Amadori, Guerrieri and Malavasi

strategy based on the orders of magnitude of each of r

its terms. It can be applied to the fully expanded expres- P = 2..: ai si (1)
sion of the transfer function. The second and third i=oO
algorithms perform the simplification during the com-
where r, maximum degree in s of the polynomial,
putation of the determinant of the admittance matrix
depends upon the number of circut capacitors and the
at zero frequency and in the frequency domain respec-
topology of the network.
tively. The fourth algorithm finds the locations of poles
and zeroes of a transfer function by exploiting the pole
PROPERTY 2. If the circu it is stable, polynomial (I) is
splitting and pole clustering hypotheses. All these algo-
complete, that is,
rithms are proved to fulfill a consistent definition of
optimal symbolic simplification. The problems raised ai ~ 0, i = 0, ... , r
by symmetric and antisymmetric architectures, due to
the fact that their transfer functions are not in minimal Furthermore all its coefficients have the same sign.
form, are investigated and suitable approaches are sug-
gested. The required parameter classification does not PROPERTY 3. The coefficients ai are given by
rely on the user's expertise but is automatic and based Ki
on simulation. a I = L..J
""" A I
k
(2)
The organization of this paper is as follows. In Sec- k=l
tion 2 the basic properties of the admittance matrix are
recalled and the symbolic structure of a transfer func- where K i indicates the number of monomials in ai and
tion is described. In Section 3 two algorithms for the At is the monomial given by the product of n factors
automatic simplification of a transfer function at zero of the form
frequency are illustrated. Their extension to the general k
Aik = (g\k ... gn-i
k )(CI ' .. Ck)
i (3)
case in the frequency domain is described in Section
4. In Section 5 the implementation of the algorithms where gf are conductances or transconductances and
is illustrated and results showing the suitability of our Cf are capacitances. If i = 0,
symbolic simplification are reported. Finally, in Section
n
6 some conclusions are drawn.
A~ = II (gt) (4)
i=l

2. Basic Definitions and Properties is the product of exactly n conductances.

The transfer functions of an n-port linear circuit are Unfortunately the symbolic computation of the above
given by the ratios of determinants derived from the polynomials leads to very complex expressions even
nodal definite admittance matrix (DAM) of the circuit. in simple cases [7, 8]. Such expressions are difficult
In what follows we will recall some properties of the to evaluate and to use for design purposes. Consider,
DAM. Proofs of these properties can be found in [17, for instance, the two-stage operational amplifier shown
pp. 197 ff], along with a comprehensive survey of this in figure 1, whose equivalent circuit is shown in figure
subject. For sake of simplicity and since our emphasis 2. Its admittance matrix is of the fifth order and, even
is on problems stemming from the linearization of cir- keeping the differential-stage transistor matching into
cuits implemented in integrated technology, the only account, it contains 14 different parameters: the exact
circuit elements we consider are conductances, capaci- expression of its differential gain has 390 monomials,
tances and voltage-controlled current sources. 48 in the numerator, and 342 in the denominator.
Giv~n a linear circuit with n + 1 distinct nodes, the Since even for small networks the computed expres-
DAM Yassociated with it is an invertible square matrix sions are very complex, it is essential to simplify the
of size n, with the following properties. above polynomials, removing some monomials so as
to minimize the perturbation induced into the function.
PROPERTY 1. The polynomial P given by P = det(Y) The simplification procedure is based on the following
can be expressed as definitions.
Symbolic Analysis of Simplified Transfer Functions 11

Vdd

M6

Vin 1 ~ M1
I4-__ _ _-.--_ __ --t-.l
M2
~ Vi n2 '--_~ Cc
Out

Cl

M5
Vbias - - l . - - - - H...._:..:..:,
M7

I
Vss
Fig. 1. Schematic of a two-stage operational amplifier.

Gm4 v3

,f',.---=":"----l 1-----1---,--- Out


Viol -

Gm2 ( Viol .. v5 ) .. v5

C1

Go?

Fig. 2. Small-signal circuit for the two-stage op amp.


12 Amadori, Guerrieri and Malavasi

DEFINITION 1. Let :71 be the set of all the monomials can be partitioned into two or more groups depending
of the coefficients of polynomial P: on their relative magnitudes. For instance, for an MaS
transistor in saturation we can assume:
:71 = {A;k; i = 0, ... , r; k = 1, ... , KJ.
Gm ~ Go (7)
We define the cardinality of P to be the cardinality of
the set :71 associated with it, namely the number of ele- where Gm is the transconductance and Go is the output
ments in :71: conductance. Based on the above consideration we in-
troduce the following definition.
r

card(P) = ~ K j
;=1 DEFINITION 3. An equivalence class C is the set of
circuit parameters {Ck } satisfying the following
In what follows the notation P j will denote a polyno- conditions:
mial P whose cardinality is i.
1. They are dimensionally homogeneous;
DEFINITION 2. Given a polynomial PM and an integer 2. Let Ct , Cs be two classes such that Is I ~ Il I, "Is
m ~ M, the optimal simplified polynomial ofcardinal- E Cs , vl E Ct. Then
ity m is the polynomial p~l whose coefficients are ISII + IS2\ ~ \ll, vlECt, VS"s2ECs (8)
composed of terms drawn from :71 and satisfying the
following condition: 1(l l11 - Il21)1 ~ lsI,
c
"Is E s ' "Ill> l2 E Cj, l1 l2 (9)
The first condition is required to avoid meaningless
where 1111 indicates a suitable norm. comparisons between symbols. The second condition
allows us to consider the equivalence class as a group
Given M and m, the number of different polynomials with respect to the operation of algebraic summation.
Pm simplifying PM is given by all the combinations of Equivalence classes are based on the observation that
M terms m by m without repetitions, that is, in practical circuits most parameters are clustered in
two or more widely spaced groups. However, it is easy
[~J = (M _M~)!m! (6) to define circuits whose parameters do not satisfy the
last condition. In this case it is necessary to perform
When m is far apart from 1 and M, the number of poly- a parameter transformation. If (8) does not hold for two
nomials is very high and the computational cost of an given parameters Sl, S2 E Cs whose sum appears in the
exhaustive search of p;:r is unfeasible. In fact, neglect- polynomial to be simplified, then both parameters will
ing the case m :::: M because of the complexity of the be transferred into the class of larger parameters Ct.
expressions, we have that the case m :::: 1 is not rele- As a consequence, they will be treated as nonnegligible
vant for applications, since there are minimum require- in a number of simplification steps. The simplified ex-
ments on accuracy. On the other hand, the accuracy pression will be more accurate although more compli-
improves with m, since a larger number of terms makes cated. If (9) does not hold for the parameters ll' l2 E
the simplified polynomial closer to the exact one. There- Ct , we introduce an additional symbol III = l2 - II
fore a trade-off is needed between the simplification in the class Cs of the small elements and we substitute
accuracy and the complexity of the final expression. all occurrences of l2 with II + Ill. If III = 0, we
simply associate the same symboll to the two different
parameters l I> l2'
3. Simplification of Transfer Functions at
As an example consider the circuit in figure 2 with
Zero Frequency
two classes of conductances:
The transfer functions for a nonlinear circuit are deter- 1. Lg = large conductances
mined by its small-signal parameters. Considerations 2. Sg = small conductances
on the relative relevance of these parameters have to
and two classes of capacitances:
be drawn in order to ensure a correct simplification.
For a given working point, it is possible to determine 1. Lc = large capacitances
the order of magnitude of each of the parameters. They 2. Sc = small capacitances
Symbolic Analysis of Simplified Transfer Functions 13

If the differential pair is matched, the parameters of exactly a terms from L g Based on this expression, the
the two input transistors are represented by the same following algorithm computes a simplified expression
symbols. When the mismatch is considered, condition for the numerator and the denominator of Ho.
(9) is satisfied if the difference between the transcon-
ductances of the input pair is large compared with the ALGORITHM 1. Let Po be a polynomial in the form
output conductances of the same circuit. The classes
are then composed as follows:
1. Sg = {Go 2, Go4, Go 5 , Go6, Go?}
2. Lg = {Gm2' Gm4, Gm6, GOg} where A5
is expressed as in (11) for some integer
3. Se = {Cw , Ci } a E [0, n]. Algorithm 1 is as follows:
4. L e = {CI , CJ
set
where Cw accounts for the capacitance associated with Po = 0
the sources of the differential pair and Ci is the para- a=n
sitic capacitance associated with the high-impedance do while (a ~ 0)
node. When the mismatch of the input pair t:.Gm = Add to Po all the monomials A5 with exactly a
G~ - Gm\ is small, we explicitly introduce the addi- ele!!1ents from L g
tional symbol t:.Gm and associate it with the class of if Po ;r= 0 then
small conductances. The class composition becomes a max = a
the following: m(a max ) = card(Po)
exit
1. Sg = {t:.Gm , Go2, Go4, Go5 , Go6, Go?}
endif
2. L g = {Gm2, Gm4, Gm6, GOg}
a = a-I
3. Se = {Cw , Ci }
end do
4. L e = {CI , Ce }
At the end of the algorithm, Po is the optimal simpli-
3.1. Transfer Function Simplification fied polyomial of cardinality m(a max ) of Po according
to definition (5). In fact for this polynomial the follow-
The zero-frequency analysis of a linear circuit is par- ing properties hold:
ticularly simple because the transfer functions are given 1. m(a max ) :S M = cardinality of the complete poly-
by the ratio of tWo polynomials of degree 0 in s: nomial Po.
- Ek,Aok' 2. The monomials appearing in Po are a subset of
H.0 - --k-" (10) those appearing in Po.
Ek"A o
where Ar Ar
and indicate monomials as in (4). No
3. Given the m(a max ) provided by Algorithm 1, defini-
tion (5) is satisfied since the neglected monomials
capacitances appear in (10). Hence two equivalence are the smallest ones and their algebraic sum is
classes can be defined as follows: negligible compared with Po, by condition (9).
1. L g = the class of large conductances The simplification of the transfer function (10) can be
2. Sg = the class of small conductances carried out by applying Algorithm 1 to its numerator
Since monomials A5 contain n conductances each, and denominator respectively. The fulfillment of con-
they can be rewritten in the form: dition (5) for the numerator and denominator does not
imply an optimality condition for the approximation
ex
n-(X
Ho of the transfer function Ho expressed by their ratio.
A5 = II g~ II gff (11)
However, it limits the maximum range of the relative
i=\ i=\
error. In fact, let Pm Pd be respectively the numerator
where g~ are conductances in Sg, gff are in Lg, and a and denominator of Ho. Let Pn and Pd be their optimal
is an integer in [0, n]. For a given polynomial Po ap- simplified polynomials computed with Algorithm 1 and
pearing at the numerator or denominator of Ho, we t:.Pm t:.Pd the respective errors Pn - Pm Pd - Pd' The
denote by mea) the number of monomials in Po with relative error on Ho is
14 Amadori, Guerrieri and Malavasi

IHo ~o H o I = I~: [~: - ~:J I


where Gm, "'" Gm2 ~ Gmb ~ Go,. If Gmb is put in
EHo = Sg, the simplified expression provided by Algorithm

:;1 ;:I[I ~~n I+ I~~d IJ


I is

Ii - Gm, + Gm2
o - Gm3 + Gm4
Since in general PdlPd "'" 1, the maximum error in the
transfer function is the sum of the relative errors in its and the error is given by
numerator and denominator respectively, both of which G b
are minimal, because Pn and Pd are optimal simplified EHo "'" I Gml : Gm21
polynomials.
As an example, consider the transfer function If Gmb is put in Lg , the simplified expression becomes

H - Go, + G0 2 + Gm, + Gm2 it - Gm, + Gm2 + Gmb


o- Gm3 + Gm4 o- Gm3 + Gm4
In this case, the error expression is the same as (12).
where

3.2. The Simplified Computation of Determinants at


Zero Frequency
The simplification provided by Algorithm I yields
Algorithm 1 operates on the numerator and on the
Gm, + Gm2
Ho = -::::-.:..!..---::::-~ denominator of a transfer function in explicit rational
Gm3 + Gm4 form. However, as pointed out in Section 2, the cost
The error is of the calculation of this explicit expression can be pro-
hibitively high. The problem is substantially reduced
~Pn I IGo, + G0Go,2 ++ Gml
G0 2 by introducing simplification in the algorithm for the
EHo =
I Pn + computation of determinants.
The approach we propose starts from a circuit
"'" I Go, + G0 2 1 (12) description based on the n Xn admittance matrix Y. We
Gm, + Gm2 define two equivalence classes Lg and Sg correspond-
If Gmj "'" - Gm2, there would be a violation of con- ing to th~ large and small conductances respectively.
dition (9). In case of perfect matching the value of Ho Matrix Y can be written as
would be set to zero, thus giving a serious error. As = = =
Y = L + S, (13)
shown before in this section, this can be avoided by in- -- --
troducing ~GII1 = Gm, + Gm2, belonging to class S~. where S contains only the small conductances and L
Hence Algorithm I would yield contains only the large ones. These two matrices can
be used to determine the simplified determinant by
il _ Go, + G0 2 + ~Gm means of the following algorithm.
o- Gm3 + Gm4

In case of perfect matching ~Gm = and ALGORITHM 2.


I. if det(L) :;t. =0 then STOP: the simplified determi-
Ii - GO l + G02
o - Gm3 + Gm4 nant is det(L).
2. Set j to I. _
which is the correct solution.
. -
3. Generate matnces L b (k = I, ... , q = (j
N
,
ob-
Finally, notice that Definition 3 does not require that tain~d replacing every possible combina~on ofj rows
the elements within one class be of the same order of of L with the corresponding ones of S.
magnitude. For instance, suppose we modify the trans- 4. If d = [%=1 det(ik) :;t. 0, then STOP: the simpli-
fer function of the previous example as follows: fied determinant is d.
5. else increment j and go to step 3.
H - Gm, + Gm} + GO l + Gmh
o - Gm] + Gm4 This algorithm is based on the following property.
Symbolic Analysis of Simplified Transfer Functions 15

PROPERTY 4. Given the nXn matrix M, if every element (3). The generalization of the procedure described for
of its ith row can be written in the form the zero-frequency case is based on the application of
Algorithm 1 to each coefficient of the polynomials. In
M(i; j) =mil + mil Vj = I, ... , n
general, a simplification corresponds to introducing a
then perturbation in the coefficients of the polynomials. Its
-- -- effects can be studied using the theory of sensitivity
det(M) det(M') + det(M")
of transfer functions [2, Chap. IS] to the variations of
- - -
where matrices M' and M" can be obtained from M coefficients. The error introduced by the simplification
splitting the ith row: is analyzed below under some hypotheses on the loca-
tion of the zeroes of the polynomial.
M'(i, j) = mil Vj = I, ... , n
Since capacitances and conductances are not dimen-
M"(i, j) = m'!
IJ Vj = I, .. -, n sionally homogeneous, we cannot safely compare the
= = = respective values of these quantities, unless we use the
M(k, j) = M'(k, j) = M"(k, j)
operating frequency as normalization factor. If we want
vk ~ i, Vj I, ... , n to derive simplified equations which are not related to
the specific operating frequency, it is necessary to oper-
Proof It can be found in [18, p. 161]. ate separately on capacitances and conductances, keep-
ing the dominant elements of both parameter types. The
By using this property, in step 3 we can define a set of trade-off between precision and number of monomials
matrices, whose determinants are expressed each by a is therefore unbalanced and the optimality achieved in
sum of monomials, all having the same number of lalge the zero-frequency case cannot be fully obtained in
and small conductances. By introducingj rows of Sin this case.
matrix L, we evaluate all the monomials with n - j A further precaution is required when the transfer
large conductances andj small conductances, until the function is not in minimal form. In this case coinciding
determinant is different from zero. This algorithm is zeroes and poles may occur and the final degree of the
most efficient when few substitutions of small terms exact transfer function is decreased by the correspond-
allow us to find the simplified determinant. Note that ing cancellations. This is the case, in particular, of sym-
an efficient implementation of this algorithm is achieved metrical and anti symmetrical circuits (see figure 3).
observing that when in step 3 j is incremented, most Therefore it is important to distinguish between alge-
minors evaluated at step j - 1 can be used if properly braic and symbolic simplification. While the latter is
stored. the process of selection of the most important terms
Finally, the results provided by Algorithms I and 2 of the coefficients of the polynomials, the former is the
are the same. In fact any further increase in the number cancellation of coinciding poles and zeroes.
of small terms in Algorithm 2 once condition 4 is ful-
filled yields monomials which would be discarded by
Algorithm 1. At the same time, the monomials evalu-
ated in step 4 when the condition is satisfied have all
the same (minimum) number of small terms and for
this reason they would be retained by Algorithm 1.

4. Simplification of Transfer Functions in the


Frequency Domain Fig. 3. (a) Symmetric circuit; (b) antisymmetric circuit.

The approach shown for the zero-frequency case can PROPERTY 5. Algebraic simplification and symbolic
be extended to the frequency analysis of transfer func- simplification do not commute.
tions. Since in the frequency domain capacitances have
to be accounted for, a transfer function becomes a ratio Proof The demonstration is carried out by construct-
of polynomials in s, whose coefficients are of the form ing an example. Let us consider the polynomials
16 Amadori, Guerrieri and Malavasi

p\ = Gal + Gm2 + SCI determinants cannot be used with nonminimal systems,


otherwise the symbolic simplification would be carried
P2 Gm2Gol + sC\Gm\ + s2C\C2 out before the algebraic simplification, thus introduc-
ing errors.
P3 Gm2Gm\ + S(Gm2C2 + Go\C\) + S2C\C2
In order to perform the analysis with the algorithms
whose parameters can be classified to the following described above on symmetric and antisymmetric cir-
classes: cuits, the symmetry of the system must be explicitly
taken into account. An effective way to reduce a sym-
Lg {Gmb Gm2} metric circuit (see figure 3a) to minimal form is pro-
vided by the
Sg {God
Lc = {Cb C2 } (BARTLETT'S) BISECfION THEOREM. A symmetric circuit
can be split into two parts across its symmetry axis.
Sc = c/> If the inputs are in common mode, that is,

and the following transfer function, composed of the V\ = V2


previous polynomials: the circuit behavior is unchanged if the edges linking
the two parts of the network are open circuits, namely if
Ij = 0 Vi = 1, ... , n
By applying algebraic simplification to H(s) we obtain If the inputs are in differential mode, that is,
V\ = -V2
H'(s)
= Pp\3 the circuit behavior is unchanged if the edges linking
the two parts of the network are virtual grounds,
namely:
Gm2Gm\ + S(Gm2C2 + Go\C1) + s2C\C2
loj = 0 Vi = 1, ... , n
which can symbolically be simplified to
Proof It can be found in [19, pp. 196-200].

The Bisection Theorem can be extended to antisym-


If we directly simplify the product of the polynomials metric circuits by the following:
in the numerator and denominator without accounting
for the algebraic simplification, we obtain LEMMA 1. An antisymmetric circuit (see figure 3b) can
be split into two parts across its symmetry axis. The
H'(s) =
circuit behavior is unchanged if we impose boundary
conditions on each of the two parts as follows. Let a,
b be two symmetric nodes in the circuit. If the inputs
which cannot be further reduced. Therefore are in common mode, that is,

H*(s) ~ H(s).
then
As a further remark, notice that even the degrees of
the polynomials in H(s) and H*(s) are different. The Va = Vb
problem is due to small and otherwise negligible terms,
If its inputs are in differential mode, then
needed for the polynomial factorization of numerator
and denominator, which would disappear in the simpli- Va = -Vb
fied computation of determinants. Correct results are
obtained only if the algebraic simplification is per- Proof Each part of the circuit shown in figure 3b is
formed before the symbolic simplification. As a conse- described by the same admittance matrix, which im-
quence, Algorithm 2 for the computation of simplified plies that
Symbolic Analysis of Simplified Transfer Functions 17

Ia = Yll Va + y 12 Vb + Y13 V I all significant. The algorithm for the simplified compu-
{
Ib = Y21 Va + Y22 Vb + Y23 V l tation of determinants in the frequency domain follows.
II = Y31 Va + Y32 Vb + Y33 V I
ALGORITHM 3.
I~ = YIIV~ + YI2 Vt + Y13 V2
{ Ith = = Y2IV~
Y3IV~
+ Y22 Vt + Y23 V2
+ Y32 Vt + Y33 V2
1. Apply Algorithm 2 to matrices Land S. The number
k of iterations executed by this algorithm is also the
number of rows of L Denoting by r the degree in
where the symbols with the prime refer to the right part
s of the determinant, in the simplified expression
of the circuit. The following constraints, imposed by
the antisymmetry of the circuit, r

A = 2.: ai si
1=0

imply that
all the coefficients ai, i = r - k, ... , r have been
(Yll + Y22) Va + (Y12 + Y22) Vb + (Y13 VI + Y23 V2) = 0 defined, provided the zero-degree coefficient is non-
zero. In fact after the substitution of k rows they are
(Y12 + Y21)Va + (Yll + Y22)Vb + (Y23 V I + Y13 V2) = 0 given by all the possible combinations of n - r + k
If VI = V2 (inputs in common mode), then conductances and r - k capacitances as in (3).
2. For each of the remaining coefficients aj, j = 1,
(YI1 + Y22 - (YI2 + Y21)Va ... , r - k - 1:
+ (YI2 + Y21 - (YI1 + Y22)Vb = 0 If aj r! 0 it coincides with its best approximated
expressio,!, since the substitution of any further
and, consequently,
rows of S would only decrease the order of
Va = Vb magnitude of the conductance component of the
monomials.
If the inputs are in differential mode (V2 = -VI), then
If aj = 0, its approximated expression is given by
(Yll + Y22 + YI2 + Y22) Va n n
+ (YI2 + Y22 + Yll + Y22)Vb = 0 aj = 2.: 2.: (Ci,.I, C i2 ,!2 ... Cij,l)
i" .. ij=l II> . . ,lj=l \.. y I
and, consequently,
j terms

Va = -Vb .1.. ..1 d,1 2"'!j


_ 1,12 . . Ij 1,1 2 ,,, .Ij "~2" .Ij
By using the Bisection Theorem and Lemma 1 it
where G contaiQs the conductances and C the
is always possible to reduce a symmetric or antisym-
capacitances of Y so that
metric system to minimal form. Since symmetric and
= = =
antisymmetric circuits are the most common situation Y = G +C
for this kind of problem, in what follows we will assume
that the systems we consider are all in minimal form.
is the minor obtained bvJ
G,I',1 2 . ",Ij
12'" J
removing the G
ilth, i2th, ... , ijth rows and the 11th, 12th, ... ,
ljth columns and
4.1. The Simplified Computation ofDeterminants in the
0 when at least two of its
Frequency Domain
.1 b = arguments are equal
a ... c { 1 otherwise
The simplified computation of determinants in the fre-
quency domain can be performed by generalizing the 3. Simplify the coefficients of the polynomials by
algorithms described in the zero-frequency case. Expres- applying Algorithm 1 to each aj computed so far,
sion (13) can still be used to de~ompose the admittance taking into account the order of magnitude of the
matrix. However, now matrix i must contain_the large capacitances.
conductances and all the capacitances, while oS contains
the small conductances. All the capacitances are in L The efficiency of this technique is related to the
In fact, since the highest-degree coefficient in its deter- specific structure of the polynomial under examination.
minant contains all the existing capacitances, they are In fact, it provides the maximum advantage when the
18 Amadori, Guerrieri and Malavasi

iterations required in steps 1-3 are few compared to begin


the matrix size n. On the other hand, if the system under Factorize P as
analysis were not stable, some coefficient of the poly-
q
momials could be equal to zero (see Property 2), thus
requiring the evaluation of the determinant specified P = II Pi'
i=l
in step 3 of the algorithm.
A simple property of the simplified coefficients where q E [1, r], using the polynomial factorization rule.
which is used later on follows.
/* The coefficients of the polynomials Pi are integer
PROPERTY 6. If ai, i = 1, r are the coefficients of the rational functions of the coefficients of P. */
original polynomial and ai' i = 1, r are those of the Solve the polynomials Pi whose degree is one.
siimplified one, then
set
sign(ai) = sign(a;), i = 1, r i = 1 Error Flag =0
where the function sign( ) has the following definition: do while (i ::5 q)
P= = bki Sk

{b
p.I I;Ki
k=O
if x > 0 if (Ki > 1) then
sign(x) = if x = 0 set} = 1
-1 if x < 0 do while U < K;)
/* Pole-splitting procedure [20J */
Proof. By construction, each ai has been obtained by Sj = -bj_l/bj
discarding only the small terms from ai' Since these Sj+1 = -b/bj+1
terms must fulfill the requirements of Definition 3, they if (Sj ~ Sj+l) then
cannot change the sign of the expression determined accept(sj)
by the largest terms. if U = K i - 1) accept(sj+l)
else
/* Pole-clustering procedure */
4.2. Computation of the Zeroes of Polynomials Solve bj +1S2 + bjs + bj - 1 = 0
/* .. . using the resolving formula for second order
Poles and zeroes of a simplified transfer function are equations */
the zeroes of its denominator and numerator respec- if U + 2 = K;) then
tively, which are polynomials in the form (1). Focusing accept(sj' Sj+l)
on stable polynomials only, zeroes are computed with }=}+2
the following algorithm. else
Sj+2 = -bj+2/bj+1
ALGORITHM 4. Let P = I;~=I aisi be the polynomial if (Sj+2 ~ m[Sj], m[Sj+1]) then
whose zeroes have to be determined. This algorithm /* Operator mreturns the real part of a number */
is divided in three phases. In the first phase an attempt accept(sj' Sj+l)
is made to determine the zeroes of P by using poly- } =} + 2
nomial factorization. As a result, some of the zeroes else
are found, the others are expressed as zeroes of smaller ErrorFlag
order polynomials. In the second phase, the pole- Exit
splitting hypothesis is assumed to compute the zeroes end if
of the reduced polynomials. The values of the zeroes end if
found are checked against the pole-splitting hypothesis, end if
to ensure that their orders of magnitude are widely end do
separated. Finally, the polynomials to which the pole end if
splitting hypothesis cannot be applied are reduced by i = i + 1
means of the pole-clustering hypothesis, which assumes end do
that the polynomial zeroes are clustered in small groups. end
Symbolic Analysis of Simplified Transfer Functions 19

During the pole-clustering procedure, the size of the 5. Implementation and Results
cluster which can be solved analytically could be ex-
tended. However, the resolving formulae for third Algorithms 1-4 have been implemented using a sym-
degree equations are too complex to be useful in this bolic manipulator called Maple [21], with about 3500
context. For this reason, it is easy to define a transfer lines of code written in a high-level Pascal-like lan-
function which cannot be solved using this algorithm. guage. The structure of the program is illustrated in
However, for most practical circuits the algorithm works figure 4. The input format is a SPICE netlist with anno-
successfully, providing an accurate estimation of poles tations specifying the analysis required. Numerical sim-
and zeroes of the transfer function. As an example, let ulation with SPICE provides a large-signal de analysis,
us consider the standard two-stage operational amplifier which is used to automatically determine the order of
of figure 1. In open loop, the assumption of pole split- magnitude of all the parameters in the circuit. Hence
ting is acceptable for the dominant poles. When the all the circuit parameters are assigned to the corre-
same circuit is connected as a follower, then the first sponding equivalence classes. The number of signifi-
two poles may become very close to each other, thus cant capacitances is critical and must be minimized.
producing a double pole or a pair of complex conjugate In fact they determine the degree of the transfer func-
solutions which are far apart from the third parasitic tion and, to a large extent, its computational cost. For
pole. In this case, the splitting hypothesis is valid for this reason, an automatic procedure tries to allocate the
a cluster of poles, which can correctly be evaluated by minimum number of capacitances required to model the
the algorithm. circuit in a proper way. This is accomplished by com-
An important property of Algorithms 3-4 follows. puting the conductance of each node toward ground.
The task is carried out very cheaply by using Algorithm
PROPERTY 7. If algorithms 3 and 4 are applied to a stable 2. Nodes are then sorted according to their impedance:
circuit and do not terminate with an error flag in Algo- while external capacitances are always accounted for
rithm 4, the simplified zeroes are associated with a in the analysis, the procedure includes only parasitic
stable system. and intrinsic capacitances to ground for high-impedance
nodes which are not yet connected to ground by other
Proof A successful application of Algorithm 4 requires capacitors. Figure 2 shows an example of a small-signal
that the zeroes of the original polynomial P can be eval- circuit automatically derived with this procedure.
uated by Algorithm 4 using the pole-splitting or pole-
clustering method. If the pole-splitting can be applied, USER INPUT FILE
then zero Sj of the original polynomial is Sj = -aj_1laj'
Since by Property 6 the sign of the coefficients cannot
change because of the simplification, then sign(sj) =
sign(Sj), where Sj is the jth simplified zero.
A similar argument holds for the pole-clustering
technique. Since the solution of a second-order equa-

Jl -
tion is

_ aj_1 [_
Sj,j-l - 2 1
4aj aj _2
2
J
aj aj _ 1

and from Property 6 and Property 2

J l- 2J
sign [ a.a. = J_/-
sign [a.a. 2J
aj _ 1 aJ-l
Symbolic analysis of the
then required transfer function

sign(ffi[sj.j_Il) = sign(ffi[Sj,j_Il).
It must be noted that this algorithm does not prevent
a pair of real zeroes to become a pair of complex con-
jugate zeroes after simplification. Fig. 4. Structure of the program.
20 Amadori, Guerrieri and Malavasi

The results shown in this section have been pro- derived by our procedure for the differential gain in
duced by the described algorithms implemented on a open-loop. Observe that when the PSRR is evaluated,
VAXStation-3l00 in Unix environment. Comparisons two different parasitic capacitances to the positive and
with SPICE simulations have been carried out by con- negative supply are considered. Also, the parasitic
veniently sizing the devices and computing the simpli- capacitance associated with the source of the differen-
fied transfer function with the same parameter values tial pair was taken into account. Since the automatic
used by SPICE. More specifically, our procedure com- procedure deriving the equivalent circuit does not ex-
putes the approximate poles and zeroes of the transfer ploit the symmetry of the inputs when the differential
function, which are then used for comparison, while gain is computed, this capacitance is included even
the numerical simulator takes into account the complete though it does not contribute to this analysis.
small-signal circuit. In figures 5 and 6 comparisons with SPICE simula-
tions are shown. The two curves, plotting the module
(figure 5) and the phase (figure 6) of the differential
5.1. Two-Stage CMOS Operational Amplifier gain, are very close to the results of simulation for all
frequencies below about 10 MHz. Beyond this frequency
The two-stage CMOS operational amplifier of figure the curves diverge, due to the presence of further poles
1 has been analyzed extensively as a simple test case corresponding to parasitic capacitances not accounted
which shows the potentiality of the algorithms. In table for in the analysis. However, divergence occurs in a
1, the differential gain (Ad), the common mode rejec- range well beyond the unity-gain frequency. In this ex-
tion ratio (CMRR), and the negative and positive power ample, the pole-splitting approximation proved to be
supply rejection ratio (nPSRR, pPSRR) are shown. The adequate for pole-zero calculation. In figure 7 the auto-
same expressions can be found in the literature [22, matically derived small-signal circuit of the same opera-
20], but all of them have been extracted by applying tional amplifier in closed loop is shown. Now the high-
the described algorithms. In these equations, the small- impedance nodes are different from those chosen for
signal circuit shown in figure 2 has been automatically the open-loop configuration. In fact the impedance at

Table 1. Differential gain (Ad), common mode rejection ratio (CMRR), and nega-
tive and positive power supply rejection ratio (nPSRR, pPSRR) for the two-stage
CMOS op amp of figure 1.

Steady State

Ad Gm6Gm2/Go6 + G0 7)(G0 2 + Go.)


CMRR 2Gm2Gm.t(GoS(Go2 + Go.))
nPSRR 2Gm6Gm2Gm./2Go7Gm. - Gm6GoS)(Go2 + Go.
pPSRR Gm2Gm6/(Go6(GO. + Go 2)

Zeroes Poles

Ad -GoSGm6/ (Go 7 + Go6)(G0 2 + Go.)!


CC(Gm6 - GOg) Gm6Cc

- Gm 6/ CI
-Gos/Ci
CMRR -2Gm 2/Cw -Gos/Cw
nPSRR - Gm6GOg -(2Go 7Gm. - Gm6Go,)(Go2 + Go.)/
Gm 6 - Gog)Cc) (2Gm.(-Gm6Ci + CcGo 7

-Gos(-Gm6Ci + CcGo 7)/


(CcCi(Go s - Gm6)
pPSRR -Gm6GoS/ -Go 6(Go. + Go 2)/
(CC(Gm6 - Go s) (Gm 6 Cc)

- Gm 6/ Ci
Symbolic Analysis of Simplified Transfer Functions 21

Two-Stage CMOS Op-Amp


80 r------r-------r---.----~--......,....--___,,----....__--_,

60

-I::
.;0
40

o 20
~
::;
I::
QJ
r... o
........
QJ

Slmplltled results
Q
-20 SPICE simulation

-40 L - - - - - - ' - L -_ _--'-_ _----l - ' -_ _----L ~_ _ _ l

1.0E+00 1.0E+02 1.0E+04 1.0E+06 1.0E+08

Frequency ( Hz )

Fig. 5. Amplitude of thedifferential gain of the two-stage op amp.

Two-Stage CMOS Op-Amp


0r----"""""=-----r----..---,---..-----,r----.------,

- QJ
QJ
r...

-
~ -45
~

-90
-- ...........
"' "'
"'"'
"' \
\
-135 Slmpllfled results \
\
\
SPICE simulation
"'
-180 L _ _-'--_ _-L-_ _- L . ._ _---l._ _--'- L -_ _- ' - - _ ~

1.0E+00 1.0E+02 1.0E+04 1.0E+06 1.0E+08

Frequency ( Hz )

Fig. 6. Phase of the differential gain of the two-stage op amp.


22 Amadori, Guerrieri and Malavasi

C3 Gm4 v3 Gm6 v4 Go6

Vout

T'
- Vin2 Go8 CC

Gm2 ( Vout - v5 ) Gm2 ( Vin2 - v5 )

Go?

Fig. 7. Small-signal circuit of the two-stage operational amplifier connected as a follower.

node 4 in figure 2 is divided by the differential gain of L g = {Gm2' Gm4, Gm6' Gmg)
the op amp. Moreover, now the biasing of the input dif- Sg = {Gm2, Go4, Go6, GOg, Go9 , Go lO }
ferential pair has a slight asymmetry due to the presence L c = {CLl
of a finite differential gain in the feedback path. This Sc = {CIO , Cw }
asymmetry has been modeled by introducing an addi-
In this case, the automatic procedure correctly finds
tional symbol t.Gm, which was included in the class of
out that this is a single-pole circuit. Since the output
small conductances (see Section 3). The curves shown
node is already connected to ground by the load capaci-
in figures 8 and 9 represent the behavior of the approx-
tance, no further additional circuit elements would be
imate transfer function for three different situations
required. The user can include other capacitances
compared with SPICE simulations. The curves indi-
beyond those associated with the highest-impedance
cated by a refer to the case of a double pole located at a
nodes. In this case elements C lO and Cw are chosen by
frequency of J7 MHz. The curves indicated by b corre-
the procedure, as the second most relevant capacitances.
spond to a situation where the two dominant poles are
Results are reported in table 2. Comparison with SPICE
widely spaced in the frequency domain (S2/S1 > 30).
simulation for the differential gain is shown in figures
The curves indicated by c refer to the case of two com-
12 and 13. The two curves match up to 100 MHz, where
plex conjugate poles, whose real part is located at
this architecture is not used anymore.
3.7 MHz. The third pole is always far apart from the
two other poles. Curves band c have been computed
5.3. Fully Differential Op Amp in Class AB
using the pole-clustering technique. These examples
show that the error introduced by the simplification is
The circuit shown in figure 14 is a fairly more complex
influenced by the location of the poles, especially for
example than the previous ones. The left half of the
"resonant" circuits.
small-signal circuit for this op amp is shown in figure
15. In this case, parameters have been organized using
5.2. Folded-Cascode OTA
the following classes:
Figure 10 shows an operational transconductance ampli- L g = {Gm2' Gm4, Gmg, GmlO' Gm12, Gm}
fier (orA). In figure 11 its small-signal equivalent Sg = {Go 2, Go4, Go s , GOg, Go 10, GO I2 , Go}
circuit is displayed, with the following parameter Lc = {Cl}
classification: Sc = {C}
Symbolic Analysis of Simplified Transfer Functions 23

Two-Stage in follower connection


6,-- .-- ---,

,,"
"
\
\

4
,,
,,
\

,
2 ,,
~~/
~~~

o r--=====----===~~
-2
....c
CIl
t' -4

-6
Simplified results
-8
SPICE Simulation
-10 L.- .L- -'- -----'

1.0E+05 1.0E+06 1.0E+07

Frequency ( Hz )

Fig. 8. Amplitude of the transfer function of the two-stage op amp used as a follower with different values for capacitance Cc-

The approximate expressions for some transfer func- of the input transistors was also considered. The fully
tions are reported in table 3. For some of them, such expanded expressions of the transfer functions exceeded
as the PSRRs, we are aware of no known expressions the storage capability of any available workstation. By
in the literature. means of Algorithms 3 and 4, the simplified expression
was computed in a reasonable time (see table 4). Al-
though our approach does not reduce the asymptotic
5.4. Computational Efficiency computational complexity of the problem, the exten-
sion of the range of applicability of symbolic analysis
Some considerations about the efficiency of the pro- is particularly evident with this example. We expect to
posed technique can be drawn from table 4. Computa- be able to cope with even more complex cases with
tion times are reported in column 1 for the computation the systematic use of automatic circuit partitioning
of poles and zeroes using Algorithms 3 and 4, while techniques.
column 2 gives the times required to achieve the same
goal without the matrix simplification detailed in Algo-
rithm 3. The first example shows that the higher com- 6. Conclusions
plexity of the technique causes an increase of CPU time
for a very simple circuit such as the two-stage opera- In this paper we have shown algorithms useful to deter-
tional amplifier of figure 1. However, the second example mine the simplified transfer functions associated with
shows that the performance of the algorithm improves a linear circuit with a special emphasis on techniques
with a more complex circuit such as the folded cascode suitable to reduce the computational cost of the process.
op amp. The computation of the CMRR is still less effi- The task of polynomial simplification has been formally
cient since several iterations of steps 1 and 2 of Algo- defmed and new algorithms for the evaluation of simpli-
rithm 3 are required before the significant terms are fied expressions proposed. They can be applied to zero-
found. In the case of the class AB op amp the mismatch frequency as well as to frequency domain problems.
24 Amadori, Guerrieri and Malavasi

Two-Stage in follower connection


0r-----------,-------------,

-Q)
Q)
s..
~

-
Q)
~ -45
Q)
tI'l
Cll
~
p..

Simplified results

SPICE simulation

-90 '-- .L.-_--'-'- ---..:.---J

1.0E+05 1.0E+06 1.0E+07

Frequency ( Hz )

Fig. 9. Phase of the transfer function of the two-stage op amp used as a follower, with different values for capacitance C - c.

Vdd

MlG Mll Vbias2


Vbias 1 ---t-----'

M7 M8

-1 ~-M-l-_.,_-_M-2--.f ~
Out
Vin 1 Vin2
M5 M6

Vbias3 -1 M9 M3 M4

Vss

Fig. 10. Schematic of a folded-cascode mA.


Symbolic Analysis of Simplified Transfer Functions 25

Qn2 ( Vln2 - v5 )
Gmt ( Vinl - vS ) G08 G08

GmS vJ

Out
u6
u8 )

Qn6 Go6

.1
v8

Qn4
Gm4 v8 Go4

Fig. 11. Small-signal circuit of the folded-cascode OTA.

Table 2. Differential gain (Ad), common mode rejection ratio (CMRR), and negative and positive power supply re-
jection ratio (nPSRR, pPSRR) for the CYrA of figure 10.

Steady State

Ad -Gm.Gm6Gm 2/
(Gm.Go 6Go 4 + G02Gm6Go. + Go IO GO.Gm6)
CMRR

nPSRR - 2Gm.Gm2Gm6Gm4/
(2Gm6Go.Go2Gm4 + 2Gm.Go 6Go4Gm 4 + Gm.Gm6Go9Go4 + 2Go.Gm6GoIOGm4)

pPSRR - Gm4Gm2/(Go4GoIO)

Zeroes Poles

Ad ( - Gm.Go 6Go4 + Go 2 Gm 6Go. + Go IO GO.Gm6)/


(Gm. Gm6CI )

CMRR -2Gm 2/Cw -Gm.Gm6Go4/


(CIO(Gm6Go4 + Gm 4Go. + Gm6Go.))

nPSRR -2Gm2/Cw -(2Gm6Go.Go2Gm4 + 2Gm.Go 6Go 4Gm 4


+ Gm.Gm 6Go 9Go 4 + 2Go.Gm6GoIOGm4)/
(Gm.Gm6Go4Cw)

pPSRR

- Gm.Gm6Go4/
(CIO(Gm6Go4 + Gm 4Go. + Gm6Go.
26 Amadori, Guerrieri and MaLavasi

Folded Cascade
90. r - - - - - - - . - - - - - - - , - - - - - , - - - - - , - - - - - - - ,

70.

50.

30.

10.

-10.

-30.

-50.

-70. Simplified results

-90. SPICE Simulation





-11 O. '-- ----' ----'- ----L. ~ ~

1.0E+00 1.0E+02 1.0E+04 1.0E+06 1.0E+08 1.0E+ 10

Frequency ( Hz )

Fig. 12. Amplitude of the differential gain of the folded-cascode aTA.

Folded Cascade
O. r----=~----,_----r_---__r-----l

-45.

(l) -90.
VJ
to
...c:
0...
c:
to
'-' -135. Simplified results
\
\
_ _ _ SPICE simulalion \
\

,
\
\

-180. L..- ----'- -'- L- --'---=_..._-...;;:-=-_~


' ...
1.0E+00 1.0E+02 1.0E+04 1.0E+06 1.0E+08 1.0E+I0

Frequency ( Hz )

Fig. 13. Phase of the differential gain of the folded-cascode aTA.


Symbolic Analysis of Simplified Transfer Functions 27

I
I
Vdd

Me M7

Outl 1------, Out2

MIO M9

,
Vss

Fig. 14. Class AB op amp.

Gal2 Go8 GmS v5


Gm Gml2 C Vinl - v9 )

- Vinl

Go2
Gm2 ( Vinl - v3 I

Gm6
Out

lei
v4

Go4
Gm4 (vll-v41

Go

Gm GolO GmlO v1

Fig. 15. Small-signal circuit for the class AB op amp (right halt).
28 Amadori, Guerrieri and Malavasi

Table 3. Differential gain (Ad), common mode rejection ratio (CMRR), and negative and positive
power supply rejection ratio (nPSRR, pPSRR) for the folded-cascode op amp of figure 14.

Steady State

Ad Gm2Gm4(GmlO + Gmg)/
(Gm(Gm 4 + Gm2)(GOg + Go lO ))
CMRR -Gm6Gm2Gm12Gm.<GmlO + Gmg)/
GmlO - Gmg)(Gm6Gm2Gm4G012 + GoGm2Gm12Gm4
-Gm4Go2Gm6Gml2 + G04Gm6Gm2Gm12 + Gm6GoGm2Gm4))
nPSRR Gm4Gm2Gml2Gm6(GmlO + Gmg)/
(GmI2Gm6GmGoIOGm4 + Gm12Gm6GmGoIOGm2 - Gm.Gm2GmgGm4Go
Gm12Go4Gm6GmgGm2 - Gm 12 Gm 2GmgGm 4Go + Gm.Gm2Gm4GoGmlO
+ Gm12Gm2Gm4GoGmlO + GmI2Gm2Go4Gm.GmlO)
pPSRR Gm.Gm.2Gm4Gm,(GmlO + Gmg)/
(GmGog(Go g + GOIO)(Gm2 + Gm 4)(Gm. + Gm12))

Poles

Ad -(Go lO + Gog)/Cl
-Gm/C
CMRR
nPSRR -(Gmg + GmlolGm4Gm2/Gm4 + Gm2)GOlOC)
pPSRR -(GOg + GolO)/CI
-Gm/C

Table 4. Pole-zero computation times with (column I) and without References


(column 2) the determinant simplification algorithm (Algorithm 3).
These data refer to a VAXstation 3100. I. P.M. Lin, "A survey of applications of symbolic network func-
tions," IEEE Trans. Circuit Theory, Vol. CT-20, pp. 732-737, 1973.
Time (sec) Time (sec) 2. L.O. Chua and Pen-Min Lin, Computer Aided Analysis ofElec-
Required with Required without tronic Circuits: Algorithms and Computational Techniques,
Determinant Determinant
Prentice Hall: Englewood Cliffs, NJ, 1975.
Simplification Simplification 3. J. Vlach and K. Singhal, Computer Methodsfor Circuit Analysis
and Design, Van Nostrand Reinhold: New York, 1983.
Two-stage Ad 35.1 31.2
4. K. Singhal and J. Vlach, "Symbolic analysis of analog and digital
op amp CMRR 22.1 15.0
circuits;' IEEE Trans. Circuits Syst., Vol. CAS-24, No. 11, pp.
nPSRR 30.8 23.9
598-609, 1977.
pPSRR 28.8 21.8
5. J.K. Fidler and J.1. Sewell, "Symbolic analysis for computer-
Folded Ad 190.8 547.9 aided circuit design. The interpolative approach;' IEEE Trans.
cascode CMRR 267.3 164.3 Circuit Theory, Vol. CT-20, No.6, pp. 738-741, 1973.
nPSRR 189.2 298.4 6. P. Sannuti and N.N. Puri, "Symbolic network analysis-an alge-
pPSRR 336.4 357.9 braic formulation;' IEEE Trans. Circuits Syst., Vol. CAS-27, pp.
679-687, 1980.
AB class AD 1224.5 7. W. M. Gentleman and S.c. Johnson, "Analysis of algorithms, a
op amp CMRR 1457.4 case study: Determinants of matrices with polynomial entries,"
nPSRR 1256.9 ACM Trans. Math. Software, Vol. 2, No.3, pp. 232-241, 1976.
pPSRR 1305.4 8. E. Horowitz and S. Sahni, "On computing the exact determinant
of matrices with polynomial entries," J. ACM, Vol. 22, No. I,
In the frequency domain, it has been proved that the pp. 38-50, 1975.
proposed methodology preserves the stability of the 9. A. Vladimirescu, A.R. Newton, and D.o. Pederson, SPICE Ikrsion
2G.I User's Guide, Department of Electrical Engineering and
original system. For these reasons, these techniques are
Computer Sciences, University of California, Berkeley, CA, 1980.
suitable to extend the range of applicability of simplified 10. SJ. Seda, M.G.R. Degrauwe, and W. Fichtner, ':.\ symbolic anal-
symbolic analysis to larger circuits, still preserving their ysis tool for analog circuit design automation," in Proc. IEEE
accuracy. ICCAD, pp. 488-491, 1988.
Symbolic Analysis of Simplified Transfer Functions 29

11. G.G.E. Gielen, H.C.C. Walscharts, and W.M.C. Sansen, "ISAAC:


A symbolic simulator for analog integrated circuits;' IEEE JSSC,
Vol. 24, pp. 1587-1597, 1989.
12. P. Wambacq, G. Gielen, and W. Sanse, "Symbolic simulation
of harmonic distortion in analog integrated circuits with weak
nonlinearities;' in Proc. ISCAS, 1990.
13. G. Gielen and W. Sansen, Symbolic Analysis for Automated
Design of Analog Integrated Circuits, Kluwer: Boston, 1991.
14. G. Gielen, H. Walscharts, and W. Sansen, "Analog circuit design
optimization based on symbolic simulation and simulated anneal-
ing," in Proc. ESSCIRC, pp. 252-255, 1989.
15. M. Degrauwe et aI., "lDAC: An interactive design tool for analog
CMOS circuits;' IEEEJSSC, Vol. SC-22, No.6, pp. 1106-1116, Roberto Guerrieri received the Dr. Eng. degree from the University
1987. of Bologna, Italy, in 1980. From 1980 to 1986, he was with the Depart-
16. H.Y. Koh, C.H. Sequin, and P.R. Gray, "OPASYN: A compiler ment of Electrical Engineering of the same University where he
for CMOS operational amplifiers;' IEEE Trans. CAD, Vol. 9, received the Ph. D. degree in electrical engineering for his research
pp. 113-126, 1990. on the numerical simulation of semiconductor devices. From 1986
17. G.S. Moschytz, Linear Integrated Networks: Fundamentals, Van to 1988 he was with the Department of Electrical Engineering and
Nostrand Reinhold: New York, 1974. Computer Sciences, University of California, Berkeley as visiting
18. B. Noble and lW. Daniel, Applied Linear Algebra, 3rd ed., researcher. In 1987 he spent the winter semester at MIT, Boston,
Prentice Hall: Englewood Cliffs, Nl, 1988. as visiting scientist. In 1989 he joined the University of Bologna where
19. E.A. Guillemin, Synthesis of Passive Networks, Wiley: New he is currently Associate Professor and where he is in charge of the
York, 1957. Laboratory for VLSI design. His research interests are in various
20. P.R. Gray and R.G. Meyer, Analysis and Design ofAnalog Inte- aspects of IC design, process and device simulation, and parallel proc-
grated Circuits, Wiley: New York, 1977. essing. In 1986 he received a NATO fellowship and in 1989 a fellow-
21. B.W. Char, GJ. Fee, K.O. Geddes, G.H. Gonnet, and M.B. ship for young researchers provided by Consiglio Nazionale delle
Monagan, ''A tutorial introduction to maple;' J. Symbolic Compo , Ricerche, Italy.
Vol. 2, pp. 179-200, 1986.
22. R. Gregorian and G.c. Ternes, Analog MOS I.e for Analog Proc-
essing, Wiley: New York, 1986.

Enrico Malavasi graduated in Electrical Engineering from the Uni-


versity of Bologna, Italy, on December 12, 1984. Between 1986 and
1989 he worked at the Department of Electrical Engineering and Com-
Marco Amadori was born in Cesena, Italy, on October 4, 1963. He puter Science (DEIS) of the University of Bologna on research topics
received the engineering degree in Electronics from the University related to CAD for analog circuits. In 1989 he joined the Department
of Bologna in 1987. From the autumn of 1987 until spring 1991 he of Electrical Engineering and Computer Science of the University
worked at the Department of Electrical Engineering and Computer of Padova, Italy, as assistant professor. Between 1990 and 1992 he
Science of the University of Bologna on symbolic analysis techniques collaborated with the CAD group of the Department of EECS of the
for integrated circuits. In 1991 he worked at Central CAD of Sgs- University of California at Berkeley, working on performance-driven
Thomson in Agrate Brianza on the optimization of analog circuits CAD methodologies for analog design. His research interests include
based on the RSM method. He is currently with TECHNOGYM S.r.I. several areas of analog design automation: layout, design methodol-
where he is involved in the design of circuits for biotech applications. ogies, optimization and circuit analysis.
Analog Integrated Circuits and Signal Processing 3, 3I-42 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal


Flowgraph Approach

MARWAN M. HASSOUN AND KEVIN S. McCARVILLE


Department of Electrical Engineering and Computer Engineering, Iowa State University, Ames, IA 50011

Abstract. This paper presents an approach suitable for the symbolic analysis of large-scale active networks. The
method depends on the partitioning of the network into smaller networks which are then symbolically analyzed
noniteratively using the Mason's signal flowgraph models of each partition. The resulting solutions, which are
reduced signal flowgraphs (transfer functions) for the subnetworks are then hierarchically combined to produce
the final solution or solutions (transfer functions) for the entire system. The advantage of such an approach is
the reduction in the number of symbolic terms compared to the conventional approaches, and the ability to analyze
hybrid systems consisting of electrical and nonelectrical parts. The result of the analysis is a series of equations
that have an upward hierarchical dependency on each other.

1. Introduction analyze large-scale networks. The method uses the


Mason's signal flowgraph (MSFG) as the engine for the
Symbolic analysis of linear networks involves finding analysis mainly because it is a more general method of
the relationship between an input and an output variable representing both electrical and nonelectrical systems
in the frequency domain in the form of a transfer versus the methods mentioned above that are more suit-
function: able for electrical networks. Further advantages of us-
ing the Mason's signal flowgraph are listed in Section 7.
N(s, X) The analysis process consists of the following parts:
H(s, X) (1)
D(s, X) 1. Partitioning ofthe network: This can be done on
one oftwo levels: on the network level by using circuit
where N(s, X) and D(s, X) are polynomials in sand partitioning algorithms like the ones described in [4]
the symbolic network variables X. The idea of sym- and used herein, or can be done on the signal flowgraph
bolic analysis of large-scale networks has had severe level. The second would require the creation of the sig-
limitations in the past. The algorithms have been limited nal flowgraph for the entire network and then attempt-
to small size networks in the range of 50 nodes or less ing the partitioning. Network partitioning is a natural
[1, 2]. The main reason for this limitation has been choice for large circuits since they are inherently com-
the exponential growth in the number of terms in equa- posed of hierarchically combined subcircuits. These
tion (1). Two recently proposed methods [2, 3] have subcircuits are natural partitions on the network level
overcome this limitation by replacing the conventional but not necessarily on a signal flow graph level. The
transfer function in equation (1) by an alternate evalua- discussion of a particular partitioning scheme is beyond
tion scheme called the sequence of expressions where the scope of this paper. Figure 15 shows a recursive
the growth in number of terms is reduced to a linear hierarchical partitioning model.
or quadratic rate [2]. Also introduced is the idea of par- 2. Analysis ofthe partitions: By using Mason's signal
titioning, signal flowgraph partitioning in [3] and direct flowgraph to symbolically analyze the partitions. The
network partitioning in [2, 4]. Although other symbolic goal here is to produce a representation of the partition
analysis programs exist (e.g., ISSAC [5], ASAP [6], in terms of its inputs and outputs only. The inputs and
BRAINS [7], EASY [8]) comparisons in this paper are outputs of a partition are defined as its tearing nodes,
only made to the two methods mentioned earlier in addition to the input and output variables of the en-
because they are hierarchical methods which utilize par- tire network. So, for a network with two inputs and two
titioning and a sequence of expressions. outputs, the final reduced signal flowgraph will be as
This paper describes a method that makes use of illustrated in figure 1. All internal nodes of the MSGF
both partitioning and a sequence of expressions to have been suppressed using the MSGF reduction rules.
32 Hassoun and McCarville

branch exiting a node. A new branch is created from


node 1 to node 3 with a reduced weight.
2. Parallel reduction of branches (figure 4)
NETWORK Any parallel branches are reduced to one remain-
Viz
ing branch with a combined weight. A reduction of
this type is performed on parallel feedback loops
Fig. 1. Reduced signal flowgraph model.
if any exist.
3. General suppression of a node (figure 5)
A general suppression performs a series suppres-
Wb sion from every branch entering to every branch
n 1 .......----t~
. .- - n 2 leaving that node. Once all series suppressions for
a given node are complete, the node and its inci-
Fig. 2. Branch b. dent branches are removed.


4. Self-loop reduction (figure 6)
WI nz Wz W\WZ A self-loop adjusts the weights of all branches enter-
n I _-I.~_ _-I.~_ n 3 ~ n I _-I.~_". n 3
ing the node. The feedback branch is then deleted.
Fig. 3. Series suppression of node nz.
5~ Suppression of a node with no outgoing branches
This corresponds to an I/O variable not requested
by the analysis. The suppression is done by simply
WI + Wz deleting the node.
~ n,. .nz

Fig. 4. Parallel reduction of branches I and 2.


3. The Hierarchical Algorithm (MASSAP)

The implementation of the flowgraph analysis algorithm


was named MASSAP (Mason's symbolic analysis pro-
gram). MASSAP is part of a more general symbolic
analysis program called SCAPP (symbolic circuit
analysis program with partitioning) [2, 9]. SCAPP gives
the user the option of performing an automatic parti-
tioning on either the signal flowgraph level or the net-
Fig. 5. General suppression of node n3'
work level. It also accepts user defined partitions (sub-
circuits) and treats them as natural partitions for the
3. Hierarchical recombination of the solutions: A network. The package also gives a choice between two
new partition is created by combining two partitions methods of analysis: signal flowgraph analysis
with at least one common tearing node. Each common (MASSAP) or direct network analysis based on a
tearing node becomes an internal node of the new par- modified nodal approach [2, 9]. Section 6 illustrates
tition and is reduced using the MSGF reduction rules comparisons between the two methods.
(figure 1). The recombination process follows the par-
titioning model (figure 15) hierarchically and recur-
sively up the tree. 3.1. Program Operation

The operation of the program starts by parsing the input


2. MSGF Reduction Rules deck and creating the data structures to completely
describe the circuit. If requested, the circuit is parti-
The systematic node suppression rules utilized above tioned into subcircuits.
for a signal flowgraph can be achieved by using the Subcircuit analysis begins by visiting all the nodes
following four simple rules: included in the subcircuit. For all nodes in the subcir-
1. Series suppression of a node (figure 3) cuit, any parallel or feedback reductions are performed,
A series suppression is a specific case of the general and for all internal nodes any general reductions are
suppression with only one branch entering and one also performed. These operations produce new branch
Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach 33

structures. The reduced nodes and old branches data Each branch and node (figure 2) is described as follows,
structures are then removed and rather than their mem- respectively:
ory deallocated from the program, they are stored in a
linked list of deleted elements. This list is then reused b = next branch n = next node
for new structures that need to be created by the pro-
num num
gram. So MASSAP has a form of local memory man-
agement in order to reduce the execution time due to Wb Tn
costly system memory allocation and deallocation calls.
Operations are performed in the order stated above bnl Fn
because parallel and self-loop reductions are computa- bn2
tionally less expensive than series reductions. The ex-
ternal nodes are then revisited to reduce any self-loops Being an external node is determined by a direct check
created by the deletion of internal flowgraph nodes. in the list of tearing nodes TN. TN is defined as
The main variables of the algorithm are defined as
follows:
Ni = set of signal flowgraph nodes (variables) in
partition i
Bi = set of signal flowgraph branches in partition i If node n does exist in TN, then the node is not to be
ENi = set of signal flowgraph external nodes suppressed. If, however, the node is not in TN, the node
(variables) in partition i is scheduled to be suppressed.
IN; = set of signal flowgraph internal nodes The program concludes execution by recombining
(variables) in partitioned circuit i the solutions for the partitions into an overall system
TN = set of signal flowgraph tearing nodes solution. The algorithm is recursive, highly paralleliz-
(variables) able, and suitable for implementation on multiprocessor
V = set of signal flowgraph input and output machines. Each partition can be analyzed independent
nodes (variables) of the other partitions and is only visited once (non-
Wb = weight associated with branch b iterative). This reduces to a minimum any interproc-
Tn = set of braches entering signal flowgraph essor communication, and in turn the large overhead
node n usually associated with the use of multiprocessor
Fn = set of branches exiting signal flowgraph machines.
node n The general algorithm can be illustrated as follows:
main {
MSFG_analyze (Network);
suppress (Network); /* Delete any internal nodes left */
} /* End of main procedure */
MSGF_analyze (Network) { /* Binary partition into P 1eft & Pright and perform
the analysis */
partition (Network); /* Partitions P 1eft & Pright */
if is a leaf cell)
(P1eft
suppress (P1e0; /* Suppress internal nodes for this terminal block */
else MSGF_analyze (Pleft); /* Recursively call MSGF_analyze */
if is a leaf cell)
(Pright
suppress (Pright); /* Suppress internal nodes for this terminal block */
else MSGF_analyze (P1eft); /* Recursively call MSGF_analyze */
combine (Pleft,Pright); /* Produce merged MSGF by concatenating the reduced
MSFGs and generate the new Network */
return (Network);
} /* End of MSGF analysis */
34 Hassoun and McCarville

suppress (P,TN) { /* Suppress all internal nodes for a partition P */


foreach (n E N;) { /* All nodes */
/* A parallel suppression (figure 4) */
foreach (b l E Tn) { /* For all incoming branches */
foreach (b 2 E Tn && node1(b 1) = node2(b 2 )){ /* For all parallel branches */
Wbl = Wbl + Wb2; /* Wbl = weight of 1st parallel branch */
delete(b2 );
}
}
/* reduce all self loops (figure 6) */
foreach (b E Tn && node1(b) = nodel(b)){ /* A self-loop found */
foreach (bin E Tn && bin ;e b){ /* For all incoming branches */

}
}
/* A series and general suppression (figures 3 and 5) */
foreach (bin E T,,) {
foreach (bout E F n) {
create new branch b;
Wbnew = Wbin * Wbout;
}
}
delete all branches attached to node n;
delete(node n);
} /* End of variable suppression for this partition */
} /* End of suppression for this partition */

3.2. The Input Deck cumbersome expression it represents. The resulting out-
put contains one branch for each input-output node
MASSAP requires a SPICE-like input deck with ad- combination (figure 1).
ditional partitioning statements. A flowgraph branch
is input exactly as a circuit branch is using SPICE. The
3.4. Special Considerations
direction of flow is taken from the first node given to
the second. An ".output" statement outlines the in-
1. It is better to reduce feedback paths before all the
put and the output nodes. Currently a graphics inter-
nodes in the forward path of the loop are deleted. This
face is being built onto the package which includes
is not a requirement for the success of the algorithm,
menu driven options in addition to schematic capture
however, it will have a significant impact on the resul-
capabilities.
tant sequence of expressions. Example 3 and table 2
illustrate the impact of the reduction node ordering on
3.3. The Output File the sequence of expressions.
It is possible to guarantee that all nodes in a feed-
The program output is a sequence of hierarchically back paths are reduced first by one of two ways:
dependent expressions in the form of an evaluatable pro- a. Implementing a check before eliminating each
gramming module. The program gives an option of node. A search for any path from that node to itself
choosing a C function or a FORTRAN subroutine as is sufficient to identify a feedback loop. If such a path
an output. As each internal node is deleted, a sequence is found, the processing of that node is assigned a lowest
of expressions term is created from the weights of the priority position in the reduction queue.
reduced branches and assigned a new symbol. The new b. Listing all feedback paths first in the input deck.
symbol is then used in the analysis rather than the This will guarantee that all feedback nodes are placed
Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach 35

in a higher position in the reduction queue. This is


equivalent to labeling the feedback paths or the feedback Y4
nodes as such, which is another possible alternative.
2. Since Laplace transforms and signal flowgraphs
are only capable of characterizing and analyzing linear
networks, operational amplifiers circuits can be ana- 4
lyzed only if they are in a linear configuration. There-
fore, since there are only a few general forms of such
configurations (see figure 9 and equations (5)-(8,
it is best to include them in a macro library. Any oc-
currence of a linear operational amplifier network Op-amp
would be replaced by its approriate signal flowgraph exam Ie
model.
Ideal operational amplifier reduction rules are:
Recursively reduce all op amp feedback loops. The
recursiveness is necessary due to the fact that an op
amp circuit can exist in the feedback path of another
op amp configuration (figure 8). This would require
reducing op amp circuit A and replacing it by its
equivalent op amp model before continuing with the
reduction of op amp circuit B. Also, all linear opera-
tion amplifier configuration signal flowgraphs are
derived from a library rather than reanalyzing at every Fig. 7. Operational amplifier example.
op amp instance in the circuit. A general form for a
linear op amp circuit is shown in figure 7. The resulting BLOCKS ~~
signal flowgraph is also shown in figure 7, where 1,2,3 and 4 1'\

/
G7
_ V4 Y2 G9
H S4 (3) 6
Vs
~11
Y4 7
Parte
G4
H I4 = V4 = YI(Y2 + Y4) (4)
VI Y4(YI + Y3) 2 G2

~ r~ ... 5

4~
8 Gs

V
n I n] G]
1 2 3
I;
G3 Part A Part B 1~6

Fig. 8. Building block of the bandpass filter.


Fig. 6. General reduction of a self-loop.
Hl(5,3)
For each additional input Vi - connected to the
negative terminal of the op amp through an admittance
Yi-, the expression associated with it is given by
~

HWo, Vi-) =~ = - Yi- (5) ,ij,


Vi - Y/ 12
12

where Y/ is the feedback admittance from the op amp


output node to the negative input terminal. Also for
:
each additional input connected to the positive terminal
of the op amp through an admittance Yi+ the expres-
sion associated with it is given by Fig. 9. Signal flowgraph reduction process on Example 4.1.
36 Hassoun and McCarville

H(Va> Vi +) = Vo = Yi+(I:Yi- + Yf) (6) nk


b (10)
Vi + Yf(I:Yi+ + Yg) 2
where I:Yi- is the sum of all input admittances con- The function suppress(p, TN) is the heart of the
nected to the negative terminal of the op amp and y8 algorithm. The analysis is done by addressing the com-
is the admittance between the positive terminal and the ponents of this function:
low reference voltage. Usually in active filter design 1. Parallel reduction. Since a nested search through all
Yg is chosen such that branches entering the node is performed, the order
of complexity of this reduction is given by
Yg = I:Yi- + Yf - I:Yi+ (7)
k k k2
which makes equation (6) look like --n = -n => O(n) (11)
2 2 2
H(Vo' Vi +) = Vo = Yi+ (8) 2. General series reduction. Here a nested search
Vi + Yf through all the branches connected to this node is
and reduces the number of operations in the output ex- needed, hence the order of complexity of this reduc-
pressions needed to model the general linear op amp tion is derived from
circuit. However for the sake of generality, equations
k k k2
(5) and (6) are used in solving the examples in this - - n = - n => O(n) (12)
paper to produce the figures in tables 2 and 3. 2 2 2
3. Self-loop reduction. Self-loops results from feedback
paths in the signal flowgraph. For a given network,
3.5. Algorithm Complexity a constant number feedback paths, f, is assumed to
exist. The worst-case situation is when every node
There are two measures to the performance of the recur- develops a self-loop through the reduction of the
sive algorithm outlined above: (1) the program running feedback path. This gives rise to a complexity of
time complexity measured by the number of steps the
algorithm has to perform and (2) the quality of the -k -k f => O(f) => O(n) (worst case) (13)
results measured in terms of the number of operations 2 2
produced in the sequence of expressions (number of
The order of complexity of suppress ( ) is given by
additions, subtractions, multiplications, and divisions).
adding equations (11), (12), and (13) which yields the
First the program complexity is addressed using a
following figure for real networks
network with b branches, n nodes, and p partitions. An
average number of nodes per subcircuit is given by k2
3- n => O(n) (14)
n 2
np =- (9)
p The complexity of the whole algorithm can be ex-
pressed in terms of the following reoccurrence equation:

J+
Since this algorithm seeks to deal with real prob-
lems, a perfectly valid assumption is that a real net- 2
F(n) = F [ -n 3 -k -n (15)
work has an upper bound on the number of branches
2 2 P
incident and leaving each node (excluding the reference
nodes). A general survey of practical (real) circuits MASSAP uses a binary partitioning algoritm to decom-
showed that an average of six branches are connected pose the input network or flowgraph [4]. The complex-
to a given circuit node. Therefore, for this discussion, ity of the partitioning algorithm however, it not included
the average number of branches connected to a node in the current complexity analysis. The reason is that
is assumed to be a constant. Alternatively, this assump- most circuits are already prepartitioned due to the fact
tion states that each vertex in the flowgraph has an that they are composed of building blocks during their
average of k branches connected to it, k/2 entering and design phase. These building blocks are considered
k/2 leaving. Since each branch has two nodes, this gives natural partitions and eliminate the need for applying
rise to the equation the partitioning function.
Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach 37

The function suppress ( ) is initiated when the size (I and 12) and one output node (5), the resultant signal
of each partition (subcircuit) reaches nip nodes. Since flowgraph consists of 2 branches representing the
the internal nodes ni are suppressed the number of transfer functions H(12, 5) and H(1, 5).
nodes processed at the next function cell level is 2(nlp
- nJ which is the number of tearing variables (exter- Example 4.2. (Dual-biquad). Consider the dual-biquad
nal) to the subcircuits. It is expected that ni > nip. amplifier example shown in figure 10 [10]. The out-
This actually is a necessity for the efficient execution of put sequence of expressions is
the algorithm. Also for practical circuit building blocks, wI -g4/(gl - sCI)
the number of 1/0 variables will always be less than w2 = -g2/sC2
the number of internal nodes. Therefore, on the average, w3 -g5/g6
the number of nodes that suppress ( ) will handle will w4 = -g4/g3
always be a constant proportional to 2(nlp - ni)' w5 = -g8/g11
Another feature of real circuits is the fact that nand w6 = -g7/glO
p are directly proportional to each other, that is a big- w7 = -g9/glO
ger circuit will always have more partitions to it HOEI(I,6) = wI *w2
(building blocks). Also, automatic partitioners usual- HOE2(1,8) = wI *w5
ly continue until a maximum p or a minimum nip is HOE3(1,1l) = wI *w6
met. Hence the final average asymptotic time complex- H0E4(1O,6) = w4*w2
ity of the algorithm is given by solving the reoccurence HOE5(10,8) = w4*w5
equation (15). The result is HOE6(10,1l) = w4*w6
HOE7(1,10) = HOEI(I,6)*w3
O(n log n) (16)
HOE8(10,1O) = H0E4(10,6)*w3
To study the quality of the results that the algorithm HOE9(1,IO) = HOE7(1, 10)/(1- HOE8(10, 10))
produces, a close inspection of the above analysis will HOEIO(I,8) = HOE9(1,IO)*HOE5(10,8)
yield a direct correspondence between the number of HOEll(l,ll) = HOE9(l,IO)*HOE6(10,1l)
operations that need to be performed in every reduc- HOEI2(1,8) = HOE2(1,8)+HOEI0(1,8)
tion and the number of operations resulting in the se- HOE13(I,ll) = HOE3(1,1l)+HOEll(1,1l)+w7
quence of expressions. In general terms each parallel,
series or self-loop reduction at a node will produce Example 4.3. (Bandpass filter). Figure 14 is a full im-
plementation of a bandpass filter [3]. Figure 15 shows
o multiplications and kl2 additions the hierarchical partitioning and analysis tree model and
for parallel reduction (17)
figures 7, 12, and 13 show the subcircuits of the parti-
2
k /2 multiplications and 0 additions tioned network. By using partitioning, the computa-
for general reduction (18) tional efficiency of the flowgraph is improved. Table
I shows the results of the analysis and table 2 shows
kl2 multiplications and I addition
a comparison for this example with SCAPP [2] and with
for self-loop reduction (19)
the Coates Graph hierarchical analysis method pre-
Equations (17), (18), and (19) show that the number sented in [3]. The results are shown with and without
of operations that will result in the sequence of expres- network partitioning. The table also illustrates the ef-
sions will exhibit only a quadratic growth with respect fect of the node reduction order on the complexity of
to the size of the circuit measured by the number of the output expressions.
nodes in it.
Example 4.4. (Ladder network). Examples 4a and 4b
show comparisons for ladder networks of 10 and 20
4. Examples nodes, respectively. The results of the signal flowgraph
analysis and comparisons with other methods are
Example 4.1. (Bandpass filter terminal block). Exam- presented in table 3. The computational count increases
ple I (figure 8) is the analysis of a subcircuit which linearly with the number of circuit elements. The flow-
is a building block of example 3. The ideal operational graph method multiplication and addition counts are
amplifiers have been reduced to flowgraph form as comparable to those from the network approach [2].
shown in figure 9. Since the block has 2 input nodes Although there is not a one-to-one mapping from circuit
38 Hassoun and McCarville

3 Gs
6

Fig. 10. Dual-biquad amplifier for Example 4.2 [10].

~II 2 C]'3... ~]/n 0+\

.....- - - ~_: '.' ~


Number of Network nodes = n + 1
Numer of SFG branches = b = 20

-SCI R I -sCz Rn
I~
v~ ~Vn+l
SCI -RI sC n

Number of SFG nodes = 20 + I


Numer of SFC branches = 2b -I = 401

Fig. 11. Ladder network signal flowgraph model.


Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach 39

Yin
"I

Fig. 12. Interconnections of the partitioned bandpass filter.

G40

30

BLOCK
5
Fig. 13. Block 5 of the bandpass filter (Example 4.3.).

nodes to flowgraph vertices, for a ladder network with


n nodes and b branches the number of flowgraph ver-
tices is 2n + 1 and the number of flowgraph branches
is 4n - 1, the node reduction rules are simpler for the
flowgraph approach.

5. General Discussion

The reduction processes of a Mason's signal flowgraph Fig. 14. Bandpass filter of example 3 [31.
using the above suppression procedures has been con-
sidered a complex process for a digital computer [1,
11]. The main problem is the growth in the number
of terms involved when the reduction is applied in order
to get a compact signal flowgraph. This problem is
solved here by using several aids:
1. There is no advantage to attempting to produce a
single expression for the final symbolic transfer
function for large network. No possible insight
could be gained from inspecting a transfer function
with hundreds of terms in the numerator and denom-
inator. The only possible insight is through numer-
ical evaluation of the function and a plot of the
transfer characteristics. Using a hierarchically
dependent sequence of expression [2, 3] rather than
a single expression to represent the transfer func- Fig. 15. Hierarchical model for bandpass filter (Example 4.3).
tion eliminates the handicap.
2. Computer memory requirement for analysis oflarge- 3. The use of network partitioning or graph partition-
scale networks can be reduced drastically by using ing to reduce the overall complexity of the algorithm
a sequence of expressions method. needed to analyze large-scale networks.
40 Hassoun and McCarville

Table 1. Symbolic analysis results of Example 4.3. Table 2. Comparison of bandpass filter with other methods. a

New Value of Example 4.3.


Block Number Symbol New Symbol Bandpass [31
Partitioning
Terminal block I HI(I,3) gl(g2+g4)/g4(g1 +g3) Status Analysis Method Mults Adds Eqs
HI(12,2) -g/g4
HI(7,3) -g9/g4 With Coates (flowgraph) [31 63 30 25
partitioning SCAPP (network) [21 48 27 56
HI(3,5) - gS/(g6 + sC6)
H1(5,7) MASSAP (flowgraph) 70 29 60
-g7/scS
Reduce node 7 H1(5,3) H1(5,7) H1(7,3) No Coates (flowgraph) [31 b b b
Reduce node 3 H1(12,5) H1(12,3)H1(3,5) partitioning SCAPP (network) [21 79 35 88
H1(1,5) HI (I ,3)HI(3,5) MASSAP (flowgraph) 89 38 85
HI(5,5) HI(5,3)HI(3,5) (feedback nodes reduced first)
Reduce self-loop at H1(12,5) HI(12,5)/(1 - H1(5,5 MASSAP (flowgraph) 94 40 92
node 5 H1(1,5) H1(1,5)/(1-H1(5,5 (feedback nodes reduced last)
Terminal block 2 H2(5,1O) glQ(g11 + g13)/g13(glQ+ gn) aNumber of multiplications include divisions, and the number of ad-
H2(19,10) - gll/gl3 ditions include subtractions.
H2(14,1O) -gIS/gI3 bData is not available for the unpartitioned case.
H2(10,12) -gI4/(gI5+ sc lS)
H2(12,14) - gI6/ sc 17
Reduce node 14 H1(12,1O) H1(12, 14)H1(14, 10) 4. The use of symbolic solutions facilitates the use of
Reduce node 10 H1(19,12) HI(19, 10)HI(l0, 12)
HI(5,12) HI(5,IO)HI(lO,12)
noniterative hierarchical procedures for combining
HI(12,12) HI(l2, 1O)H1(10, 12) partitioned solutions into an overall system solution.
Reduce self-loop at H1(19,12) H1(19,12)/(I - HI(l2,12 This application is ideally suited for implementa-
node 12 HI(5,12) H1(5, 12)/(I-H1(12, 12
tion on parallel processor machines.
Terminal block 3 H3(12,17) gI9(g20+ gn)/g22(g19 + g21)
H3(26,17) -g201gn 5. Building standard symbolic signal flowgraph solu-
H3(21,17) - g27/gn tion librarires for commonly used cells. This would
H3(17,19) - g23/(g24 + sC24) eliminate the need for the repeated analysis of such
H3(19,21) -g2S/sc26
Reduce node 21 H1(19,17) HI(19,21)H1(21,17) cells. Even within one network, once a subnetwork
Reduce node 17 H1(26,19) H1(26, 17)HI(l7 ,19) that is instantiated more than once is analyzed, no
H1(12,19) H1(12, 17)HI(l7, 19) further analysis of the other instances is required.
H1(19,19) H1(19, 17)HI(17, 19)
Reduce self-loop at H1(26,19) H1(26,19)/(I-HI(l9,19
The reason the algorithm is suitable for active opera-
node 19 H1(12,19) HI(l2, 19)/(1- H1(19, 19 tional networks is the one-to-one correspondence be-
Terminal block 4 H4(19,24) g2S(g29 + g31)/g31(g2S+ g30) tween the circuit and its signal flowgraph representa-
H4(30,24) -g29/g31 tions. For a passive network, the number of nodes and
H4(28,24) - g36/g31
H4(24,26) - g32/(g33 + sC33) branches in the signal flowgraph is more than in the
H4(26,28) -g34/ sc35 original circuit (figure 11). This results in more sup-
Reduce node 28 HI(26,24) H1(26,28)HI(28,24) pression steps and thus more computational time.
Reduce node 24 HI(30,26) HI(30,24)H1(24,26)
H1(19,26) H1 (l9,24)HI (24,26) However the method works for both passive and ac-
HI(26,26) H1 (26,24)HI (24,26) tive networks and the comparisons in the next section
Reduce self-loop at Hl(30,26) H1(30,26)/(I- HI(26,26 shows its suitability to the task.
node 26 HI(19,26) HI (19 ,26)/(1- HI (26,26
Terminal block 5 H5(26,30) g37(g3S + g40)/g4Q(g37 + g39)
Middle block 6 H6(1,12) H1(1,5)H2(5,12)
6. Comparisons with Other Symbolic Methods
H6(12,12) H1(12,5)H2(5,12)
H6(1,12) H6(1, 12)/(1- H6(12, 12)
H6(19,12) H2(19, 12)/(1- H6(12, 12 Symbolic analysis has been performed on the bandpass
Middle block 7 ID(I,19) H6(1, 12)H3(12, 19) filter (figure 14 and example 3) using the two methods
ID(19,19) H6(19,12)H3(12,19)
ID(l,19) H7(I, 19)/(I-ID(19, 19 previously proposed for symbolic analysis of large-scale
ID(26,19) H3(26,19)/(l-H7(19,19 circuits [2, 3]. This particular filter has been chosen
Middle block 8 H8(1,26) H7(1,19)H4(19,26) because both hierarchical methods showed detailed
H8(26,26) H7(30,26)H4(19,26)
H8(1,26) H8(1,26)/(I-H8(26,26)
results of their analysis of the filter. The results of us-
H8(30,26) H4(30,26)/( 1- H8(26,26 ing the hierarchical Mason flowgraph approach pro-
Middle block 9 H9(1,30) H8(1,26)H5(26,30) posed in this paper are shown in table 1. The com-
(final) H9(30,30) H8(30,26)H5(26,30) parison with the other two methods is shown in table
H9(1,30) H9(1 ,30)/(1- H9(30,30)
3. The hierarchical model for the process is shown in
Symbolic Analysis of Large-Scale Networks Using a Hierarchical Signal Flowgraph Approach 41

Table 3. Examples 4.1,4.2, and 4.4 comparison with SCAPP".

Example 4.4 Example 4.4


Example 4.1 Example 4.2 Ladder Network Ladder Network
Basic Cell Biquad [l0] (10 nodes) (20 nodes
Analysis
Method Mults Adds Eqs Mults Adds Eqs Mults Adds Eqs Mults Adds Eqs

SCAPP [2] 16 7 23 16 6 22 48 34 54 102 70 107


MASSAP 13 5 II 16 5 18 67 33 67 100 49 100

"Number of multiplications include divisions, and number of additions include subtractions.

figure 15. Parts A, Band C, are simply the blocks lems and the need for normalization during the
already analyzed in figure 7 (part A, which is a sum- numerical evaluation process of the sequence of ex-
mer is slightly different with an extra input terminal). pressions. This is also the case in the network ap-
Table 3 also illustrates comparisons with the hier- proach [2] but is not the case in the Coates f1ow-
archical network approach used in SCAPP for all the graph approach [3].
examples presented in this paper. 7. The number of terms in the f10wgraph analysis of
active networks is lower than that for general net-
works due to the one-to-one correspondence between
7. Conclusions the actual circuit nodes and the nodes of its f1ow-
graph model.
The advantages of the Mason's f10wgraph method im- In general this method works very well for circuits
plemented in MASSAP and presented herein are: with standard building blocks, active or passive. The
1. The simplicity of its reduction rules in order to obtain fact that these building blocks can be considered as
the I/O transfer function sequence of expressions. natural partitions to the circuit and their analysis results
2. The number of operations and expressions resulting loaded into the analysis directly eliminates the overhead
are comparable to the other methods proposed for associated with building the signal f10wgraph for the
the analysis of large-scale networks. This is due to network.
(a) the use of a sequence of expressions which ex-
hibits only a quadratic growth rate for general cir- References
cuits and sometimes a linear growth rate (ladder net-
works) in the number of terms as the network size I. P.M. Lin, "A survey of applications of symbolic network func-
increases, and (b) the use of network partitioning tions," IEEE Trans. Circuit Theory, Vol. CT-20, pp. 732-737,
which reduces the overall complexity of the analysis 1973.
2. M.M. Hassoun and P.M. Lin, "An efficient network approach
algorithm. to symbolic simulation of large-scale circuits;' in Proc. IEEE
3. Symbolic libraries can be built for common sub- Int. Symp. Circuits Sys., pp. 806-809, 1989.
systems with a reduced f10wgraph already produced. 3. J.A. Starzyk and A. Konczykowska, "Flowgraph analysis of large
4. The ability to include any current or voltage variable electronic networks," IEEE Trans. Circuit Sys., Vol. CAS-33,
as part of the analysis without any extra or special pp. 302-315, 1986.
4. M.M. Hassoun, and P.M. Lin, "An efficient partitioning
considerations [Lin76]. algorithm for large-scale circuits," in Proc. IEEE Int. Symp. Cir-
5. Another major advantage of this hierarachical f1ow- cuits Sys., pp. 2405-2408, 1990.
graph approach is the ability to simulate integrated 5. G. Gielen, H. Walscharts, and W. Sansen, "ISSAC: A symbolic
systems. That is, systems with electrical and non- simulator for analog integrated circuits," IEEE J. Solid-State Cir-
electrical components. The only requirements on the cuits, Vol. SC-24, pp. 1587-1597, 1989.
6. F.Y. Fernandez, A. Rodriguez-Vazquez, and J.L. Huertas, "An
components of the system is that they be represent- advanced symbolic analyzer for the automatic generation of
able in f10wgraph format. Mechanical and chemical analog circuit design equations," in Proc. IEEE Int. Symp. Cir-
systems are commonly represented by a Mason's cuits Sys., Singapore, pp. 810-813, 1991.
f10wgraph and interconnections of such components 7. G. Di Domenico and S.l Seda et. aI., "BRAINS: a symbolic
with electrical networks can be simulated using the solver for electronic circuits;' Int. Workshop Symb. Methods Appl.
Circuit Design, 1991.
method herein. 8. R. Sommer, "EASY-an experimental analog design system
6. The existence of division in the sequence of expres- framework," Int. Ubrkshop Sym. Methods Appl. Circuit Design,
sion. This eliminates underflow and overflow prob- 1991.
42 Hassoun and McCarville

9. M. M. Hassoun, "Symbolic analysis of large-scale networks,"


Ph.D. dissertation, Purdue University Engineering Library, West
Lafayette, IN, 1988.
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tations, Wiley: New York, 1986.
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Circuits-Algorithms and Computational Techniques, Prentice-
Hall: Englewood Cliffs, NJ, 1975.
P.R. Adby, "Tree enumeration from the incidence matrix," Int.
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Design of Analog Integrated Circuits, Kluwer: Boston, 1991.
M. M. Hassoun, "Hierarchical symbolic analysis of large-scale Kevin McCarville was born in Stillwater, Minnesota on April 4,
systems using a Mason's signal flowgraph model," in Proc. IEEE 1968. He completed a B.S. degree at South Dakota State University
Int. Symp. on Circuits and Sys., pp. 802-805, 1991. in 1991 and is completing a M.S. Degree at Iowa State University
A. Konczykowska and M. Bon, "Symbolic simulation for effi- both in Electrical Engineering.
cient repetitive analysis and arti fidal intelligence techniques in He has been a research and teaching assistant since 1991 at Iowa
CAD," in ProcIEEE Int. Symp. Circuits Sys., pp. 802-805, 1989. State University. His research interests include symbolic circuit
P.-M. Lin, Symbolic Network Analysis, Elsevier: Amsterdam, simulation particularly in the area of active device modeling, VLSI
Netherlands, 1991. design, and electronic circuits.
SJ. Mason, "Feedback theory-some properties of signal
flowgraphs," Proc. IRE, Vol. 41, pp. 1144-1156, 1953.
SJ. Mason, "Feedback theory-further properties of signal
flowgraphs," in Proc. IRE, Vol. 44, pp. 920-926, 1956.
R.R. Mielke, "A new signal flowgraph formulation of sym-
bolic network functions," IEEE Trans. Circuits Sys., Vol.
CAS-25, pp. 334-340, 1978.
M. Sagawa and H. Kitazawa, "Symbolic network analysis of
linear networks using parameter extraction proc. ," Trans. IECE
Japan, Vol. E 60, No.8, Abs, p. 414, 1980.
K. Singhal and J. Vlach, "Generation of immetance functions
in symbolic form for lumped distributed active networks," IEEE
Trans. Circuits Sys., Vol. 21, pp. 57-67,1974. Marwan M. Nadim Bassoun received his B.S. degree in Electrical
K. Singhal and J. Vlach, "Symbolic analysis of analog and digital Engineering with high honors from South Dakota University in 1983
circuits," IEEE Trans. Circuits Sys., Vol. 24, pp. 598-609,1977. and the M.S. and Ph.D. degrees in Electrical Engineering from Purdue
R. Sommer, "EASY-an experimental analog design system University in 1984 and 1988. In 1985 he was a sofware development
framework;' Int. Workshop Sym. Methods Appl. Circuit Dseign, engineer with Hewlett-Packard Company in Santa Clara, Califor-
1991. nia. In 1988 he joined the department of Electrical Engineering and
lA. Starzyk and A. Konczykowska, "Flowgraph analysis oflarge Computer Engineering at Iowa State Unviersity. His current research
electronic networks," IEEE Trans. Circuits Sys., Vol. CAS-33, interests are in symbolic analysis of VLSI circuits and compuer-aided
pp. 302-315, 1986. design algorithms for VLSI.
Analog Integrated Circuits and Signal Processing 3, 43-58 (1993)
1993 K1uwer Academic Publishers, Boston. Manufactured in The Netherlands.

Formula Approximation for Flat and Hierarchical Symbolic Analysis

EY. FERNANDEZ, A. RODRIGUEZ-VAZQUEZ, 1.0. MARTIN, AND 1.L. HUERTAS


Department of Design of Analog Circuits, Centro Nacional de Microelectronica. Edificio CICA, Avda Reina Mercedes sin. 4/012
Sevilla. Spain

Abstract. This paper addresses the topic of reducing the complexity of formulae resulting from the symbolic analysis
of analog integrated circuits, covering both flat and hierarchical symbolic analysis approaches. Previously reported
criteria for flat analysis are first briefly reviewed and their limitations illustrated via examples of practical analog
circuits. In all of these criteria simplifications are performed by estimating the numerical values of the symbolic
terms at a single point of the parameter space, corresponding to the expected typical values for symbols. Conse-
quent quantitative as well as qualitative inaccuracies resulting from this approach are identified. A new simplifica-
tion strategy for flat symbolic approaches is then presented in which insignificant terms are deleted taking into
account expected ranges of variation in the symbol values. Examples are used to show that this new criterion over-
comes the drawbacks encountered in previous ones. Finally, an algorithm to simplify hierarchical formulae is
presented which includes consideration of the potential ranges of variation in the symbolic parameter values. This
algorithm is also applied to practical analog integrated circuits.

1. Introduction teaching and increasing designer insight [8-10]; auto-


matic generation of optimum circuit topologies [11];
Symbolic circuit analysis refers to the calculation of sys- interactive circuit improvement and automated design
tem functions for those networks consisting of the inter- space exploration [12, 13]; nonfixed topology analog
connection ofeither linear or incremental circuit models. synthesis tools [6]; fault diagnosis [14], etc.
As opposed to numerical circuit analysis, where model When running on standard workstation configura-
components (resistors, capacitors, controlled sources, tions l modern symbolic analyzers are capable of deal-
... ) are represented numerically, in symbolic analysis ing with typical analog building blocks (one- and two-
all or part of the model parameters remain symbols. stage op amps, transconductors, buffers, comparators,
A symbolic analyzer is a CAD tool intended for the etc.) described at the device level. More complex cir-
automation of symbolic analysis procedures. cuits (e.g., active RC filters, TA-C filters, etc.) can be
Symbolic analysis received strong attention during analyzed resorting to the use of macromodels. Hence,
the 1970s and early 1980s. Many computer-oriented manageable circuit complexity levels are large enough
analysis techniques were proposed and several analyzers to employ modern tools in connection with practical
evolved. Detailed presentations of these techniques and analog circuits. Efficiency in implemented algorithms
related programs are found in two recent books by Lin is also appropriate for this purpose. For instance, only
[1] and Ozawa [2]. Research in symbolic analysis has 10.8 sec CPU time on a 4-Mips workstation is required
increased significantly during the last few years. This to analyze a CMOS two-stage op amp using a high-
has been mainly due to the many potential applications frequency MOST model; or, to give another example,
of symbolic analysis in the design of analog integrated 1.2 sec is required for a Kerwin-Huelsman-Newcomb
circuits, being motivated by a renewed interest in analog biquad using a two-pole model for the op amps.
techniques [3, 4] and the need for improving efficiency However, in spite of its many applications and the
in modern analog and analog/digital ASIC design [5, availability of powerful tools, practical use of symbolic
6]. Several new symbolic analyzers have been devel- analysis may become seriously compromised due to the
oped whose features aim to meet the specific needs of difficulties encountered in the interpretation of the
present analog designers [7-9]. These tools have proven primary results provided by symbolic analyzers. This
to be very valuable for such diverse applications as, is specially true for circuits described at the device
44 Fernandez, Rodriguez-Vazquez, Martin and Huertas

level, where formulae containing a huge amount of the nine-transistor folded cascode OTA of figure Ib:
terms are obtained even for elementary building blocks. using the model of figure le, the formula representing
Because of these difficulties, the development of ap- the voltage gain of this op amp contains 97,953!! dif-
propriate, powerful formula postprocessing tools is in- ferent terms [9]. A similar number of terms are ob-
dispensable to ease, or even enable, the interpretation tained for other specs that must be taken into account
of the primary results provided by symbolic analyzers. in the design procedure, e.g., CMRR, PSRR, noise,
Formula postprocessing comprises a wide variety input capacitance, etc. A much larger number of terms
of tasks, such as parametric graphical representations will result for advanced CMOS or BJT op amp building
[9], sensitivity calculation [15], pole/zero extraction [9], blocks, typically containing about 30 transistors. Try-
etc. Formula simplification is an issue of outstanding ing to create models including all the characteristics
importance among the different postprocessing tasks. needed for the ac design of these building blocks, and
Simplifying a symbolic formula implies reducing its using exact symbolic expressions, will probably be
complexity (measured as the number of terms) by beyond the capabilities of many compilers. Even if com-
eliminating insignificant terms, determined by a pilation were possible, the computation time required
numerical estimate using typical values of the symbolic for the iterative design procedure would be extremely
parameters. The convenience of formula simplification high. Hence, this application also demonstrates the need
is shown when considering calculation of the output for simplifications.
impedance of the cascode current mirror of figure la, Previous approaches to symbolic formula approx-
using the MOS transistor model of figure le. The form- imation focused only on fully expanded expressions
ula supplied by the symbolic analyzer ASAP [9] con- resulting after applying flat symbolic analysis tech-
tains 1384 different terms. This number is not par- niques [7-9, 19]. In addition, these approaches only
ticularly astounding in itself, but suppose this formula consider a single point of the complete parameter space
is used for educational purposes to gain insight into to estimate the relative size of the symbolic terms. Sec-
the circuit operation. It is obvious that a more com- tion 2 introduces the concept of symbolic formula ap-
pact expression containing a few dominant terms would proximation, and the drawbacks of previously reported
be more appropriate for this purpose. In fact, the ex- simplification criteria are shown by examples of prac-
pressions found in advanced analog circuit textbooks tical analog integrated circuits. Section 3 presents a
for these characteristics contain less than 10 terms completely different simplification approach, where
[16-18]. numerical estimate is not made at a single point of the
parameter space but inside a region, defined by taking
into account typical ranges of variation of the symbols.
It is shown that this approach overcomes the problems
found in previous ones. Section 4 focuses on the sim-
plification of formulae resulting from hierarchical sym-
bolic analysis procedures [20]. An algorithm is given
(al for this type of expressions and demonstrated for prac-
tical analog integrated circuits. Finally, a brief discus-
sion of results is made in Section 5.

2. Simplification Techniques for Symbolic


Formulae: An Overview

2.1. The Concept ofSymbolic Formula Approximation


Fig. 1. (a) CMOS cascode current mirror; (b) folded cascode orA;
(c) high-frequency MOST model.
Reducing formula complexity by retaining only the
Applications involving repetitive formula evaluations most significant terms and pruning the insignificant
also impose the need for simplification. For instance, ones (according to a typical numerical estimate of the
consider the task of model compilation for automated parameter values) is common practice among expert
circuit dimensioning using statistical optimization [12]. designers in analog circuit analysis. The simplification
Assume a noncomplex CMOS building block, such as concept for general symbolic expressions is introduced
Formula Approximation for Flat and Hierarchical Symbolic Analysis 45

in the following example. Consider the circuit of figure 99.8'


2, showing an ac abstraction for a two-stage BJT feed-
back amplifier. The following symbolic voltage gain can
be found: 0.2 ~3

0.1

~02
term 'enn

hf"hfe2R3RLR, +hf" (R2 +RiJ(R3+r,2)R\ +(R2 +RiJ(R3+r,2)(R, +r,,)+(R3+r,2)rr,R, Fig. 3. Percentage distribution profLles for the different symbolic terms
(1) in (I): (a) numerator, (b) denominator.

where x T = {XI> X2, ... , xQ} is the vector of symbolic


parameters, and the coefficients of the s powers are
polynomials in x, generically,

hk(x) = h k1 (x) + hk2 (X) + ... + hkT(x) == ~ hk/(x)


/=I,T
- - - rn:l",rn:2",IOKO
hfel=hfc2E1OO (4)
R2=R 3"'RC"'IOKO
R]=IKn
where hk(x) represents either fi(x) or g/x) in (3) and
the terms hk/(x) being products of symbols.
Fig. 2. BIT feedback amplifier ac schematics.
Approximating a reference Junction, defined
Although this formula is obviously needed for fine analytically or as a set of data points, implies calculating
gain adjustment, it is a rather cumbersome expression an approximating Junction, typically made up of
from a more qualitative point of view, darkening the elementary functions with a predefined structure
operation of figure 2 as a feedback amplifier. In fact, (piecewise linear, polynomial, spline, etc.), which fits
if typical component values are used, (1) can be reduced the reference function for a given error inside a region
to of the variable's space [21]. This approximation con-
cept is not applicable to a function like (3). First, since
Va ::::; (R2 + R,)hje,hje2R3RL = R2 + R 1 (2) the coefficients are symbols there is no numerical in-
Vi hjethje2RtR3RL R1 formation available to perform the fitting. Besides, to
which displays the feedback effect, and provides the best of our knowledge, no general mathematical
guidelines for coarse voltage gain adjustment. theory has yet been developed to approximate symbolic
For convenience, the terms in (1) have been written functions. Second, since the function structure is
down sequentially, according to their magnitude for already known and easily computable, it is hardly worth
typical parameter values (see figure 2 for these values): searching for an alternative function structure.
the largest terms are on the left, and the magnitude The approximation of generic symbolic formulae pro-
decreases from left to right. Figure 3 shows the percent- ceeds as previously illustrated for the example of figure
age contributed by each term to the total numerator and 2. It does not aim to change the function structure, but
denominator typical magnitudes. As shown, the terms to reduce the number of symbolic terms included in
eliminated from (1) to achieve (2) total 0.18% and 4.3% the symbolic expression2 [6, 9]. This is achieved by the
of the original numerator and denominator, respectively. heuristic pruning of insignificant terms in each coeffi-
Taking this into account, we may state that (2) approx- cient hk(x) so that an approximate polynomial, hkA(x),
imates (1) with a maximum error of 4.3 %. is found for each coefficient. This approximate
Now, let us consider an expanded generic symbolic polynomial fits the original one for a user-specified
formula resulting after flat symbolic analysis, consisting maximum error parameter, EM, and inside a given
in a rational function in the complex frequency s, region R of the symbolic parameter space. In previously
reported criteria, this fitting is made only at a single
H(s, x) = fo(x) + sf,(x) + s2fz(x) + + I'ftl.. x ) point, xa , of the parameter space, called the nominal
go(x) + sg,(x) + S2 g2 (X) + + ~gM<x) point or the design point [6, 7, 9, 19]. These criteria
are reviewed below, separately considering symbolic
Ei=o,N s1;(x)
(3) expandedformat expressions, such as that shown in (3),
Ej=O,M sjg/x) and nested format expressions [7], like the following:
46 Fernandez, Rodrfguez-Vazquez, Martin and Huertas

[{(az + a3)a4 - as(a6 + a7)} + (as + ag)]al


(5)
each hk(x) , and provided that M is small enough,
[{b 1b zb 3 - b4} + b sb6b7(b s + bg)] similar truncation factors can be expected for the dif-
ferent coefficients and, consequently, errors in phase
where the different ai and bi are, in the most general and magnitude as well as in pole/zero locations much
case, functions of the complex frequency. smaller than M can be expected,3 yielding

2.2 Simplification Criteria for Expanded Symbolic (6)


Formulae
where aN "'" aD and hence HA(s, x o ) "'" H(s, x o ).
We will assume that the complex frequency remains Term sorting is not required in the fourth criterion
a symbolic parameter during simplification. This in- [19]: rather, the largest magnitude term for each hk(xo)
fers that simplification applies to the whole frequency is found and multiplied by M' Then, all the terms
range, and is the case typically covered in literature. whose magnitude is below the resulting value are
Performance of the different criteria will be illustrated eliminated. In other words, a term hkl(x) will be
using the circuits of figure 4, taken from different ap- eliminated from (4) if it fulfills the following:
plication contexts. Figure 4a is a positive feedback orA
used for high-Q SC filters [22]; figure 4b is a Miller Ihk/(xo) I< MCmax(lhk/xo)l for f = 1, 2, T
orA [17]; and figure 4c is an active current mirror used (7)
for current mode AID converters [23].
As long as term sorting is not required, this criterion
is faster than those presented in (*). However, since
the accumulated value of the deleted terms is not com-
pared to the total magnitude of the coefficient, non-
uniform truncation factor distributions are very likely
to occur and, consequently, large magnitude and phase
errors and large pole/zero displacements can be ex-
pected. Thus, this criterion deserves no further discus-
sion herein.

~1=I,plhkl(Xo)1 <
I~1=1,,.hkl(Xo) I
"~~ro ~1=I,plhkl(Xo)1
(*)
M, M2 ~l=l TIhkl(X o) I
(e) V" We will try now to compare the criteria in (*) refer-
(b)
ring to their performance at the nominal point as well
Fig. 4. Benchmark circuits for illustration of flat simplification criteria:
as other points of the parameter space located inside
(a) positive feedback orA; (b) Miller orA; (c) active CMOS cur- a region around X O ' This latter situation deserves con-
rent mirror. sideration since the design point in symbolic analysis
is not usually known beforehand, and its value is defined
Four different criteria have been proposed for ex-
as a heuristic guess. Furthermore, even if the exact
panded format expressions. Three require sorting terms
design point were known a priori, in practice, dis-
in hk(x) according to their magnitude at the nominal
placements due to the influence of unavoidable device
point XO ' The P smallest magnitude terms are then
mismatches would be observed around it.
eliminated, P being the largest integer for which the
The three criteria in (*) yield identical results if all
accumulated error is below M' The criteria differ
the terms of each coefficient hk(x) have the same sign
among themselves in the expression used to estimate
at xo ' and provided that this sign remains the same in-
this accumulated error; these three alternatives are
side the region considered. This is the case if each co-
shown in (*). In the three cases, each hk(xo) is trun-
efficient fulfills the following:
cated to a value a0k(Xo) , where ak depends upon M'
For functions containing a large number of terms inside sign{hkl(xo + LlX)} = a VI, LlX E R (8)
Formula Approximation for Flat and Hierarchical Symbolic Analysis 47

where a is either I or -1. However, for many analog formulae would be obtained. Thus, this criterion is not
circuits this is not the case and, consequently, different used in modern tools [6, 9].
results can be expected for each criterion in (*).
2.2.3. Unsigned Reference Unsigned Object Criterion.
2.2.1. Signed Reference Signed Object Criterion. This This is the criterion in the right equation of (*). It is
is the criterion in the left equation of (*). Note that less accurate at the nominal point than the signed
terms are added with their signs so that eventual con- reference signed object criterion: however, unlike the
tributions from opposite signed terms mutually cancel
former, the likelihood of additional inaccuracies due
themselves. Thus, if (8) were not fulfilled, this criterion
to displacements around X o is smaller. Actually, this
gives the most accurate results at xO ' However, impor- criterion is the most commonly used in modern sym-
tant errors may result when the simplified formulae are bolic analyzers [6, 9]. Unfortunately, there are many
evaluated at points other than X o in case these circuits where its use may yield large errors, as shown
simplified formulae result from the cancellation of large
in the following.
magnitude opposite sign terms.
Let us consider calculating the dc voltage gain of
the orA of figure 4a, given as the coefficient ratio ".
\~,
foCx)/go(x). Assume these coefficients are simplified ""
for EM = 0.25. After simplification errors measured at ",.,
the nominal point are the same for fo(x) and go(x):
"", .
\ _._._~~.~~~._._._._._._._._.-
24.9%, which is very close to the user-specified " E M=O.10

margin. However, when the simplified formulae are


evaluated with a mismatch of 0.1 % among amplifier
transconductances, the error in go(x) increases to
3170%!!, while not significantly changing for fo(x). '"I
Let us now consider calculating the PSRR + of the J06 J08
(a) Frequency (Hz)
Miller orA of figure 4b, using the MOST model of
figure le. Differences among exact and simplified ~ 0
to
,,.
magnitudes and phases, for different EM, are plotted in :Sc
,.
figure 5a and b for a mismatch of I% among MaS tran- .~ I

?
I
sistors. Corresponding maximum deviations for .~
"0
I
I
f
matched transistors are 1.1 dB at 100 kHz and -5.1 ~
deg at 2.8 MHz, in both cases for EM = 0.2. As s: / cM=O.05

:5 cM=O.lO/

shown, much larger inaccuracies appear when the I I

,i"
formula calculated at the nominal point is applied at
:i'\ ,./
points located nearby. ,.
I
"
J06 J08
(b)
2.2.2. Signed Reference Unsigned Object Criterion. Frequency (Hz)

Problems arising in previous criterion naturally lead


Fig. 5. Mismatch induced parametric error profiles for the PSRR of
to the alternative shown in the central equation of (*).
the Miller orA: (a) deviations in magnitude for different M: (b) cor-
In this new criterion, opposite sign terms are eliminated responding deviations in phase.
only when they are truly insignificant. However, since
terms in the denominator remain signed, the actual er- Consider the voltage gain of figure 4a using the
ror margin will be much smaller for those coefficients model of figure le. Figure 6 gives the exact and several
containing opposite sign terms than for those contain- simplified magnitude and phase plots for different EM'
ing only negative or positive terms. Consequently, large Very large errors can be observed, due to the fact that
disparities among the coefficient truncation factors are the independent coefficient as well as the coefficients
likely to appear, yielding large pole/zero displacements for the s and the s2 powers of the function denominator
at the nominal point. This problem could be overcome contain large opposite signed terms. Consequently, the
by forcing pole/zero displacements to remain bounded reference used for simplification (*) is large and many
as discussed in [9]. However, to compensate for the in- terms whose magnitude is comparable to that of the
herent lack of uniformity, excessively conservative coefficient
48 Fernandez, Rodriguez-Vazquez, Martin and Huertas

beyond a user-specified safety margin [9]. Unfortu-


~~ .. ~,,=O.15 nately, even though this guarantees a low error at the
]
c nominal point, it does not give confident results for a
'" .,.,
0

~ - different point of the parameter space.


,,=0.05 .
~ ------------------------~
Similar inaccuracies to those shown here for figure
4 can be found in many practical analog circuits, and
thus force the need to devise more advanced simplifica-
tion strategies. Section 3 presents new simplification
criteria, accounting for large variation ranges in the
(a) 0 1!---~--:-:10~2-~-----::IOT4-~-~1O-;r;--~~108 symbolic parameters. Prior to this, previously reported
Frequency (Hz)
techniques for simplification of nested formulae are
briefly reviewed in the next subsection.

2.3. Simplification Criteria for Nested Format Symbolic


Exact Formulae
,
,
Little has been done to simplify expressions in this for-
mat [7, 24]. The technique in [7] is based on pruning
insignificant subexpressions at the nested levels. This
is done without assessing how changes in the deleted
(b)
106 108 terms may affect the different s power coefficients of
Frequency (Hz)
the final expanded network function. Actually, large
Fig. 6 Exact and simplified Bode plots for the voltage gain of figure errors may appear if a pruned subexpression inhomo-
4a: (a) family of magnitude plots for different EM; (b) corresponding geneously influences the coefficients. The errors may
family of phase plots. be avoided using a partial fraction expansion to separate
(9) the different powers of the complex frequency; cancel-
ing the advantages of the nested symbolic format.
However, some problems may still appear even when
are eliminated. using this expansion:
This problem is further illustrated by calculating the
a. Significant terms may be pruned while insignificant
roots of the current gain of figure 4c at the nominal
ones are maintained. For instance, consider the
point xO ' Symbolic expressions for these roots are
nested expression
automatically calculated by the analyzer ASAP [9].
Three poles and three zeros result when using figure Ie (A + B) (C + D) + (E + F) (G + H) (10)
for the MOST and a resistive macromodel for the feed-
If A ~ B, C == D, E == F, G == H, in the expres-
back amplifier. Figures 7a and b show the loci for the
sion tree, B will be pruned even though it is possible
real and imaginary parts of the different roots, as a func-
that B(C + D) > E(G + H).
tion of EM' As shown, there are a pair of complex con-
b. Uncontrolled large errors caused by cancellations
jugate poles in the left half of the s-plane for some EM,
in the expression tree. This problem has been par-
and in the right half for others. Thus, the circuit may
tially solved using the lazy expansion technique
be considered either stable or unstable, depending on
given in [24], but only cancellations in consecutive
the formula used. It is obvious that this type of quali-
levels of the expression tree are detected.
tative errors are intolerable for practical use.
Different solutions have been proposed to overcome The need arises to devise better simplification
problems of this criterion. One possibility is to monitor strategies for nested expressions. A new criterion for
the magnitude of each term within each hk(x), to avoid this is presented in Section 4.
eliminating those whose magnitude is greater than
SD(see (9)) [6]. Another approach, providing better 3. Simplifications with Ranges of Variation
control of the accuracy of the simplified expression,
is to use an adaptive EM scheme so that simplifications Unlike numerical simulators, where analysis is made
can be stopped when pole/zero displacements are on sized schematics,4 symbolic analyzers focus on
Formula Approximation for Flat and Hierarchical Symbolic Analysis 49

V'lZl Zz P 3 P1PZ Z3
,J 0 ~r--.--....---,r--':::JT"""""-_r_-_-
1:"': ... . -_-.. . .-_-.. . -_-.-'......_-.-..r-._-.-....._-.-......_--.---..-,_.....-. -._r".-.....,~..-='--r--.--r---r-T"o
~ 1 _ _ . _ _ _ _ _ _ _ - _,

, I
I I
I
I . :
I':
J
t-
o u--'-----''---'----''--.1J1iL...--L----'-_-'----'-_J..--I..._.L----'-_'-----'-__':--'----'~--'-----'_::_';:_L......J
o -10 -5 0 5 10
Re(s) (log)
Zz Z 3
V'l .------.---...P...;..-......-.....---.-__r--r--r---r-.--Z~I!..rP~3'-r-----.-.......----.--__r--r--r---.-P~zr-.-__r--,
~O
w

-5 o 5 10
Im(s) (log)
Fig. 7. Root loci for the current gain of the active current mirror as a function of M: (a) real part of the roots; (b) imaginary part.

totally or partially unsized circuits. That is, in symbolic figure Ie yields a 64-dimension space), this approach
analysis the exact numerical value of some or all the does not seem computationally feasible.
parameters is not known beforehand. Hence, approx- A different algorithm is presented in this section
imating symbolic expressions by considering only a where each symbolic parameter is assigned a range of
single point of the parameter space does not seem con- variation and simplifications are achieved by perform-
sistent with the very nature of symbolic analysis pro- ing operations among the parameter ranges.
cedure. Even when symbolic analysis is used to study
critical parameter variations in sized schematics, 3.1. Concept and Basic Operators
simplification using only information about the nominal
point may lead to important inaccuracies, as shown To perform the simplification procedure, we will
previously for the PSRR of the Miller afA. assume that each symbol 6 may take any value inside
It is common in analog integrated circuits that a given range of variation.
parameter variations be comprised inside a limited
Yi E [YiL, YiH] (11)
region of the parameter space. For instance, it is not
realistic in standard CMOS technologies for capacitor where YiL and YiH are real numbers and YiL ~ YiH'
values to be smaller than 0.1 pF or larger than 100 pF. Bear in mind that simplifications are made by
Similar restrictions exist for most parameters. Thus, eliminating addends in each symbolic coefficient; the
accurate approximate formulae could be obtained by general coefficient expression is (4), repeated here for
applying the criteria in the left equation of (*) to each convenience sake,
point located inside a limited region of the parameter
space.s However, considering that parameter space + hkrtX) = ~ hkl(X)
dimensions for typical analog circuits are very large 1=I.T
(for instance, the afA of figure Ib with the model of (12)
50 Fernandez, Rodriguez-Vazquez, Martin and Huertas

where the addends are products of symbols. As dis- 3.1.2. Addition of Ranges. Consider the general case
cussed in Section 2, conventional simplification ap- of two symbols, denoted Yi and Yj respectively, for
proaches calculate the values of the different hklx) at which the corresponding ranges are known. Let us
the nominal point xo , and compare these values to that assume that a new symbol is defined as the sum of Yi
of hk(xo); insignificant terms are then eliminated. and Yj' The range for this new symbol is computed by
When a range criterion is applied, the ranges of the adding the corresponding extrema of the addends.
different hklx) must be calculated and compared to the
(Yi + Y) E [(YiL + YjL) , (YiH + YjH)] (15)
range of hk(x). Hence, operations among ranges must
be defined; in particular, those that allow calculating This operator allows evaluating ranges of either hk(x)
the range for a product of symbols (product of ranges or subsets of addends in (12).
operator) and the range for a sum of symbols (addi-
tion of ranges operator) from the component ranges. 3.1.3. Modulus of Ranges. For a given symbol, prod-
Additionally, two more operators must be defined: the uct of symbols, or sum of products for which a range
modulus ofranges operator and upper and lower range (YiL, YiH) is defined or calculated, the modulus of
operators. These operators allow calculating the relative ranges operator yields another range defined from the
range values required to determine which terms must previous one by taking the modulus of the extrema in
be eliminated from a given coefficient. an appropriate order,
l[YiL, YiH]1 = [min (IYiLI, !YiHI), max (IYiLI, IYiHI))
3.1.1. Product of Ranges. Assume a new symbol is (16)
formed by multiplying two symbolic factors, Yi and Yj'
The extrema (Yi Y)L and (Yi Y)H of the range of this 3.1.4. Upper and Lower Operator. These two operators
new symbol can be calculated from the extrema of the return the extrema of the range for a given symbol Yi'
factors as follows: respectively,

(YiY)L = min(YiLYjL, YiLYjH, YiHYjL, YiHYjH) "U([YiL, YiHD = YiH


(YiYj)H = max(YiLYjL, YiLYjH, YiHYjL, YiHYjH) (13) ([YiL, YiHD = YiL (17)
A particular case of this operator is that in which one The range simplification algorithms operate based
of the factors is a numerical coefficient. In this case, on previous range operators, as described in the next
the range of the product is obtained by scaling the range subsection.
of the symbolic factor. Another particularity arises
when the symbolic parameters do not change signs in- 3.2. Simplification Algorithm
side their corresponding definition intervals. In this
case, computations to calculate (Yi Y)L and (Yi Y)H can Like the conventional criteria of section 2, the purpose
be significantly simplified using the following equa- of range simplification criteria is to eliminate the P least
tions, instead of (13): significant terms in (12) for a given maximum error
margin EM' A conservative approach is to apply the
YiL > 0, YjL > 0 following formula:
YiL > 0, YjL < 0 "U(I[A cL ' AcH]I)
< EM (18)
(I[SL, SH]!)
YiL < 0, YjL > 0
where [SL' SH] represents the range of the sum of all
YiL < 0, YjL < 0 YiYj E [(YiHYjH) , (YiLYjL)) (14) the terms included in the coefficient being simplified,
For most practical analog circuits the product of ranges and [A cL ' AcH] (henceforth accumulated sum) denotes
operator can be handled using (14). However, some the range corresponding to the sum of terms to be
symbolic parameters may change sign inside their pruned, that is, the P least significant terms in this
definition interval in practical circuits, though this rarely coefficient.
occurs. Thus, (13) is also necessary. A practical situa- The simplification algorithm proceeds as follows.
tion of such a case is when mismatches are treated ex- For each coefficient polynomial hk(x):
plicitly as symbolic parameters; another case is the 1. Ranges of terms hkl(X). Calculate the range for
study of the local asymptotic stability properties of cir- each term inside the coefficient, using the product
cuits containing negative resistance devices. of ranges operator.
Formula Approximation for Flat and Hierarchical Symbolic Analysis 51

2. Ranges ofcoefficients hk(x). Calculate the range of their maximum values for one term while simultane-
the coefficient [SL, SH] using previously calculated ously taking the minimum in the other. This may be
ranges and the addition of ranges operator. accounted for by factorizing the sum of the terms
3. Grouping of terms. Determine pairs of terms Yi, Yj
(23)
with opposite sign and similar magnitude and con-
sider the sum of these terms. which yields a real maximum range of [-1.74E-18,
1.74E-18]. When this range is taken into account, it can
(Yi + Y) E [(YiL + YjL) , (YiH + YjH)] (19)
be concluded that both terms may be grouped together,
Then evaluate the following inequalities: thus increasing accuracy in the simplification.
It is worth noting that the pruning based on (18)-
CU(I [(YiL + YjL) , (YiH + YjH)] I) < (1 [YiL> YiH] I) upper-lower criterion-may yield very conservative
cu(1 [(YiL + YjL) , (YiH + YjH)] I) < (1 [YjL, YjH] \) formula due to the fact that there may be terms with
(20) their maximum value added to the accumulated sum
(numerator in (18)) and the minimum value to the total
If they are simultaneously fulfilled, the pair of terms
sum (denominator in (18)). For that reason, a slightly
is grouped and a new range defined by (19) is
modified criterion has been developed-upper-
associated to it; otherwise the terms are not grouped.
medium-where terms added with their maximum
Note that these groupings allow proper handling of
magnitude in the numerator are added likewise in the
the mismatch problem. Thus, pairs of terms cor-
denominator. This implies modification of the
responding to mismatched parameters can be
denominator in (18) for each term added to the ac-
eliminated (in spite of their large magnitude), if their
cumulated sum, and though it requires a little extra
maximum difference is small enough.
computation it obtains less conservative results.
4. Ordering ofterms. Arrange the terms in an ordered
Another alternative range criterion has been
array using the modulus and upper operator for the
developed where the sum of symbolic terms is factor-
range comparison. Assume two arbitrary terms, Yi
ized prior to computing [SL, SH] and [A cL ' AcH]' This
and Yj; Yj is considered less significant than Yi, if
obtains more reduced ranges and, hence, less conser-
it fulfills the following:
vative results than the upper-lower criterion. Our ex-
(21) perience with this criterion does not show clear advan-
tages when compared to the upper-medium criterion;
5. Elimination of terms. Beginning with the least however, from the computational point of view it is
significant term determined in the previous sorting, much more costly. Consequently, it does not seem very
the range of each new term is added to the ac- convenient for simplification of flat expressions. This
cumulated sum range and the terms are pruned one criterion's greatest utility is found in the hierarchical
by one until (18) is no longer fulfilled. simplification procedure presented in Section 4, where
The grouping of terms described in step 3 of this the range reduction is very convenient.
algorithm can be refined with a little extra computa-
tion, by the factorization of both terms. For illustra-
tion's sake, consider the symbolic expression for the 3. 3. Practical Results
PSRR + of the Miller OTA. The ranges for two of the
terms corresponding to nominally matched transistors Validity of the proposed range simplification criteria
are, has been tested on a wide variety of analog integrated
circuits: both analog building blocks described at a
[2.36XIO- 18 , 5.27xIO- 18] device level, as well as larger complexity circuits
[-5.27XI0- 18 , -2.36XIO-18 ] described at a macromodel level. Accurate results
(within user-specified error margins) have been ob-
(22)
served in all the cases, and a significant reduction in
where a mismatching of 10% is assumed between formula complexity. Actually, based on our experience,
MOST transconductances. The range for the sum of the criteria allow very flexible accuracy versus com-
these terms can be calculated as [- 2. 91E-18, 2.91E-18]. plexity trade-offs. Thus, the complexity is greatly
At first glance, these terms would not be grouped decreased for noncritical circuits, and increased to the
together, however it is unlikely that Gm5 and Gm6 have level required to ensure accuracy in critical circuits.
52 Fernandez, Rodriguez-Vazquez, Martin and Huertas

Figure 8 shows the differences in magnitude and


phase between the exact expression and different
simplifications for the Miller ffiA PSRR + using the
upper-medium range criterion for several EM values.
,
The same transistor mismatching was assumed as for ,,
figure 5. Note that the vertical scales in figures 5 and ,
,,
8 differ; maximum deviations are 0.4 dB and 2.5 deg
in figure 8, and 7 dB and 175 deg in figure 5. Conse- " ........ Upper-medium
-,
quently, accuracy is much better for the range criterion. Conventional
In addition, this significant increase in accuracy is ob-
tained without a significant increase in complexity, as
presented in figure 9, where the complexity versus EM
figures are shown for the two criteria. Fig. 9. Comparative complexity versus M curves for the PSRR of
This is further illustrated in figure 10, showing a the Miller OTA using conventional (signed) and upper-medium range
family of Bode plots for the voltage gain of the ffiA simplification criteria.
of figure 4a assuming different EM values for the
upper-medium range criterion. Like the Miller OTA, <o:r-------,.----------,------,-----~
much more accurate results are obtained than when us- :s
ing the conventional simplification criterion (see figure ~
'c
Exact - ,,=0.20

6). Also, and although complexity increases with ~


respect to that encountered for the conventional
criterion, a reduction of more than one order of
magnitude in complexity can be achieved with respect
to the exact expression for EM > 0.01, as shown in
figure 11.
O ' - - - - _ ~ _ _'~ __'_ ____L. .....J
<0: 2 4
106 108
:s (a) 1 10 10

1
Frequency (Hz)
It~
~ 0 I-----+--+---I---+---t---+----t---''I--+'i=';~".-',"
t :! ~
H-
----------------__ ~~~=O20 ;:
I~

.G \~ '.
\'. , (

" I
\ '. 1/
\ ~ II
\ '/'
I I
I I

... EM=O.lO\
...'
:
I
,
9
\

L_
(a) "-]-~--~----~~--l~- 106 lOR
Frequency (Hz) o
I
8
106
II
I I (b) ] 10
Frequency (Hz)
cM=O.lO: ~
: /'\ Fig. 10. Parametric Bode plots for the voltage gain of the positive
"'
I \ feedback OTA using upper-medium range simplification criterion:
"
/i
Ii
(.
t (a) magnitude; (b) phase.
, r ~
II t
Ii" I1 As a final example, figure 12 presents the locus for
=-=--I---.;8:_
o F=~---'='=_c-_-_-_O=~-... ----I -i-
'i \
the real part of the roots of the active current mirror,
","'''''' . ,._ff ~ resulting after applying the upper-medium range cri-
~=O.20
,
,
I
terion. As shown, the range criterion overcomes the
'. I
qualitative misinterpretation problems emerging from
(b) ] 106 lOR
Frequency (Hz) conventional simplification criteria. Furthermore,
quantitative root displacements are minimal for margin
Fig. 8. Illustrating performance of the upper-medium range criterion
for the PSRR of the Miller OTA: (a) parametric magnitude error errors up to 50 %. On the other hand, complexity of the
curves; (b) corresponding phase error curves. simplified formula is similar to that for the conventional
Formula Approximation for Flat and Hierarchical Symbolic Analysis 53

possible), the need to devise simplification techniques


that enable directly coping with this expression format
arises. However, dramatic problems may arise when
dealing with this type of expression, due to potential
cancellations at intermediate levels as previously cited
in Section 2.3. The simplification technique presented
Upper-medium here intends to overcome these problems by assessing
to what degree each function at a specific hierarchy
Conventional ------------------1 level influences functions at higher levels.

4.1. General Concepts


Fig. 11. Comparative complexity curves resulting from the applica-
tion of conventional and upper-medium range simplification criteria
to the positive feedback orA. Prior to presenting the proposed simplification tech-
nique, some general concepts and terms related to hier-
archical analysis will be introduced through an example.
Consider the circuit of figure 13a, where the active
device is a differential-input single-ended-output trans-
conductance amplifier. An ac model for this amplifier
is shown in figure 13b, containing two system functions:
one for the voltage to current gain, Gy{s), and the other
for output conductance Yoy{s).7 Assume the transcon-
ductance amplifier is composed ofa differential pair and
two current amplifiers, as conceptually shown in figure
13c, and that the building blocks are modeled as illus-
trated in the same figure (the model shown for the cur-
rent amplifier corresponds to that whose input is L;
:; Ll._...J1"-O~~~.lL-_-;-5 --~~..J.O~~--...JL,-~~~""""I~O.L.J the model of the other amplifier can be obtained from
Re(s) (log)
it by reversing the direction of the current in the CCCS).
Fig. 12. Real part root loci resulting from the simplification of the
active current mirror using upper-medium range criterion for differ-
ent fM values. +

criteria. For instance, for EM = 0.2, where conven-


tional criteria yield poles on the right half of the com-
(b)
plex frequency plane (figure 7), the number of terms
amounts to 25 for range criterion versus 17 for conven-
tional criterion.

4. Simplifications in Hierarchical Analysis 0-


+ ) \.---+i
So far we have discussed techniques to simplify the so-

~
called expanded format expressions. This format is ap-
propriate for low and medium complexity circuits, as
demonstrated in previous examples, but not for larger
circuits. Hierarchical symbolic analysis must be used
(c)
for large circuits, e.g., high-speed and fully differential
op amps, active filters, etc. [20]. Since nested instead
Fig. 13. Example of hierarchical circuit: (a) voltage amplifier based
of expanded format expressions result when applying on transconductors; (b) transconductance amplifier ac conceptual
these approaches, and due to the huge computational model; (c) transconductance amplifier architecture and related build-
cost of expanding large nested formulae (if it were ing block models.
54 Fernandez, Rodriguez-Vazquez, Martin and Huertas

Routine hierarchical analysis allows us to obtain the where GNk(s, x) and GDk(s, x) are symbolic polynomi-
following nested expression for the voltage gain of fig- als in s and the circuit parameters x. Our interest lies
ure 13a: in determining how GNk(S, x) and GDk(s, x) contribute
to the numerator and the denominator of the root ex-
H(s)
pression H(s, x), if this root expression is transformed
and given as a ratio of two s polynomials. These con-
(YiC1 + Yopl){(YOC) + YodCl'ic2 + Y op2 ) + 2Fc2 Gp2 } tributions can be seen from the following formula:
(24)
H(s, x) == HN(s, x)
where the numerical subscripts correspond to the HD(s, x)
amplifier numbers in figure 13a and, for simplicity, the
GNk(S, X)CNNk(S, x) + GDk(s, X)CNDk(S, x) + RN(s, x)
dependency of the different subexpressions on the com-
plex frequency s is not explicitly shown.
GNk(S, X)CDNk(S, x) + GDk(S, X)CDDk(S, x) + RD(s, x)
(26)
Subexpression hierarchy in a nested formula can be
conceptualized as an inverted tree, like that shown in where the polynomials CNNk , CDNb CNDb CDDk repre-
figure 14, for (24). Each node in an inverted tree con- sent the contribution factors of G Nk and G Dk to the
tains an associated expression. The lowest nodes of the total transfer function H('); Rn (') and RD (') denote the
hierarchy (the tree leaves) corresponds to expanded for- parts of the numerator and denominator polynomials
mat expressions. Expressions at the top node (the root of H(') not contributed by gk' This concept of contri-
node), and at the intermediate nodes are determined bution from the leaf nodes to the root node, as well
by lower level nodes connected to them. The expres- as the associated mathematical treatment, can be ex-
sions (equivalently the nodes) referenced by either the tended to intermediate hierarchy nodes.
root or any intermediate node are the children of that To ensure accuracy in the simplification, contribu-
node. Similarly, for any node ni but the root, the set tion factors for the different subexpressions are calcu-
of nodes at the subsequent hierarchy level whose ex- lated, together with the coefficients of the different s
pressions are contributed by ni are its parents. As powers in H('), prior to pruning terms in the sUbexpres-
illustrated by figure 14, following the inverted tree struc- sions. Thus, we may determine beforehand how much
ture for a given circuit enables seeing how single ex- those simplifications will affect the total. In our tech-
pressions join together hierarchically to yield the root nique, contribution factors and system function coeffi-
expression. cients are computed numerically, taking into account
the ranges of the coefficients appearing in the system
functions at the leaf nodes. Symbolic expansion at the
high hierarchy levels is not required for the algorithm.
It must be emphasized that the use of typical values,
instead of ranges, to compute contribution factors is un-
sure as some expressions may be very sensitive to small
changes in the symbols; however, this fact is not dis-
covered until reaching higher levels in the hierarchy.
Fig. 14. Inverted tree structure for the voltage gain of figure 13a.

In the proposed algorithm, simplifications are not 4.2. Overview of the Algorithm
applied to local expressions. Instead, contributions to
the root expression made by expressions at intermediate 4.2.1. Calculation of the Contribution Factors. In the
nodes and at leaves are assessed prior to reducing the following, contributions to the root expression from a
complexity of intermediate and leaf expressions. This given leaf node are denoted using uppercase subscripts;
is done using the contribution factor concept. This con- lowercase subscripts denote contributions to the corre-
cept is applied in the following to the particular case sponding parent. Since a node may be referenced in
of expressions at the tree leaves. more than one expression, the contribution to each
Assume the system function at a generic leaf node parent is denoted with a superscript. Thus, CDNi repre-
sents the contribution to the denominator of the root
expression due to the numerator of the expression asso-
(25)
ciated to the ith node. Likewise C~di represents the
Formula Approximation for Flat and Hierarchical Symbolic Analysis 55

contribution of the expression denominator of i th node, 4.2.2. Calculating Simplification Percentages. Once
to the numerator of the expression at kth node. To the contribution of each leaf node to the root is known,
simplify notation, the complex frequency, s, and the a matrix equation may be written expressing the error
symbolic parameters, x, will be omitted when denoting of the coefficients in the root node, as a function of
system functions and contribution factors. the error in the coefficients of the leaf nodes. The struc-
The algorithm aims to store the leaves' contribution ture of this equation is

]
factors to the tree's root within the leaves themselves.
This is achieved in two steps: in the first one, the tree . ..
is traversed from the leaves to the root. The value of ...
each nonleaf node is computed together with the con-
tributions of its children to it. Children are computed
before parents so that the latter have the information
to be computed. As a simple example, let us assume
we have a node with three children whose values have
already been computed or are leaf nodes:

(27) where submatrices M are built using the contributions


of leaf nodes; ENi and EDi represent the error in
and the parent node is numerator and denominator coefficients for the ith leaf
node; and EN and ED express the error in the total
g4 = gl + g2 = GN1 GD2Gm + GN2GD1Gm (28) function coefficients.
1 - g3 GD I GD2 Gm - GN3 GD I GD2
To define a similar equation for relative errors, the
The contribution factors of gl to its parent g4 are contribution matrix can be normalized multiplying each
C: n1 = GD2 Gm GN2 Gm
column by its respective coefficient of the leaf node,
and dividing each row by its respective coefficient of
Cdnl = 0 GD2 Gm - GN3 GD2 the total function.
(29) There are more variables than equations, which en-
able some degree of liberty to adjust the errors in the
In the second step, the tree is traversed from the root
total function. Computing the tolerated errors in the
to the leaves, assigning to each node its contribution
leaves requires some heuristic that takes into account
to the root. This has already been computed in the first
which factors are more significant. For instance, high
step for nodes which are direct children of the root.
powers of s may be irrelevant if we are not considering
For the remaining nodes, it may be calculated once the
very high frequencies. Thus, weak restrictions on those
contributions ofthe parents to the root are known. For
factors will not produce significant differences in the
the i node:
transfer function. An optimization algorithm is used to
CNNi = ~ (CNNkC~ni + CNDkCjnJ compute the tolerable errors in the leaves, based on the
k error specification in the total transfer function. Once
they are computed, the final result is obtained applying
CNDi = ~ (CNNkC~di + CNDkClJi) the simplification algorithm using the ranges of varia-
k
tion explained in Section 3.
CDNi = ~ (CDNkC~ni + CDDkCjnJ Note that this algorithm provides a natural mecha-
k nism to handle possible cancellations at intermediate
levels of the hierarchy. If a specific expression is going
CDDi = ~ (CDNkC~di + CDDkCjdi) (30) to be canceled at higher levels of the hierarchy its con-
k
tribution factor to the root node will be zero. An arbi-
where k comprises all nodes which are direct parents trary error value will be one solution of (31) for that
of the i node. expression and, hence, can be eliminated.
The proposed algorithm computes the values for Currently only leaf nodes are simplified because,
these factors prior to performing simplifications of each generally speaking, the tree is such that they are several
leaf node gk' Thus, we know beforehand the effect orders of magnitude more complex than the rest of the
those simplifications will have on the total. nodes. However, the same information used in the
56 Fernimdez, Rodriguez-Vazquez, Martin and Huertas

leaves is stored in nonleaf nodes. This retains the


possibility of "pruning" the tree by simplifying at
higher levels of the hierarchy.

4.3. Practical Results ~Simplified

,
Exact :>..,
,
The developed algorithm was applied to the OTA-C ,,
bandpass filter structure of figure 15a [25]. The trans- ~
I
,,
,
conductances and output impedances of the OTAs (de-
(a) 1:--~-~1-"-;;02'-------:::104'---~-~1076-~-----:-:J108
scribed at the transistor levels as shown in figure 15b) Frequency (Hz)
were considered to calculate the global transfer func-
,
tion. The expanded formula would have hundreds of ,,, ,,,
millions terms and, consequently, none of the criteria ,, '
reviewed in Sections 2 and 3 is applicable to this case. ,,,
The criterion discussed in this section was applied to ,,,
this example to evaluate the relative importance of each Exact: Simplified
,
coefficient at the leaf nodes in the total function. This ,,,
enables applying higher margin errors at those leaf sym- ,,
bolic expressions of less relative importance. Hence, .,
g ,,,
,,
a good trade-off between accuracy and simplification
level is achieved.
, :
(b) 1 106 108
A smooth error function was applied to the coeffi- Frequency (Hz)

cients of the total transfer function so that higher errors


Fig. 16. Exact and simplified Bode plots for the bandpass filter of
were tolerated at very high frequencies. The calculated figure 15: (a) magnitude plots; (b) phase plots.
contribution factors and margin errors, ENi and EDi ,
allowed reducing the number of terms at the leaf nodes
(transconductances and output impedances of the OTAs) 5. Conclusions
by two orders of magnitude. In spite of this great sim-
plification, the error in magnitude and phase in the Since parameter values are not known a priori, approx-
bandpass remains small, as shown in the plots for the imating symbolic expressions using numerical estimates
exact and simplified expression in figure 16. for a single point of the parameter space may result in
important inaccuracies when formulae are evaluated at
a different point. Although many problematic situations
Vi
can be traced to the existence of terms with opposite
signs in the symbolic coefficients, and solved by using
absolute values, this yields other problems and does
not ensure accurate results at other than the nominal
(al
point. Inaccuracies of previously reported approxima-
tion criteria are illustrated in the paper, and the results
showed that quantitative deviations larger than 200%
as well as qualitative errors can be obtained for basic
analog integrated circuits building blocks. However, the
need for formula simplification cannot be underesti-
mated if symbolic analysis is to be used in medium and
large complexity analog integrated circuits, where a
computationally intractable number of terms are very
(bl
likely to be obtained. The approaches reported in this
Fig. 15. (a) Gm-C bandpass filter to test the hierarchical simplifica- paper try to cope with this problem by introducing the
tion criterion; (b) orA transistor level schematics. approach of formula approximation for ranged symbolic
Formula Approximation for Flat and Hierarchical Symbolic Analysis 57

parameters and addressing the problem of simplifica- 8. G. Gielen, H. Walsharts, and W. Sansen, "ISAAC: A symbolic
tion for hierarchical symbolic procedures. Results simulator for analog integrated circuits," IEEE J. Solid-State Cir-
reported in the paper prove the suitability of the tech- cuits, Vol. 24, pp. 1587-1597, 1989.
9. EY. Fernandez, A. Rodriguez-Vazquez, and J.L. Huertas, "Inter-
niques proposed. active AC modeling and characterization of analog circuits via
symbolic analysis," Analog Integrated Circuit Signal Process. ,
Vol. I, pp. 183-208, 1991.
Acknowledgment
10. L.P. Huelsman, "Personal computer symbolic analysis programs
for undergraduate engineering courses," in Proc. 1989 IEEE Int.
The authors would like to acknowledge Professor Symp. Circuits and Systems, pp. 798-801, Portland, 1989.
Lawrence P. Huelsman for encouraging them to submit 11. A. Konczykowska and M. Bon, "Automated design software for
this material. switched-capacitor IC's with symbolic simulator SCYMBAL:'
in Proc. 25th Design Automation Corif., pp. 363-368, 1988.
12. G.E. Gielen, H. Walsharts, and W. Sansen, "Analog circuit design
Notes optimization based on symbolic simulation and simulated anneal-
ing," IEEE J. Solid-State Circuits, Vol. 25, pp. 707-713, 1990.
1. Most of the results in this paper have been obtained with a 4-Mips 13. F.Y. Fernandez, A. Rodriguez-Vazquez, and J.L. Huertas,
and 8-Mbyte physical memory SUN3/260 workstation. "Design and applications of symbolic analysis tools for analog
2. In the rest of the paper the concept ofjormula complexity denotes integrated circuits," in Proc. First Int. Workshop Symbolic
the number of symbolic terms contained in a formula. Each addend Methods, Paris, 1991.
in (4) is considered as a term to this purpose. 14. A. Liberatore, S. Manetti, and M. Piccirilli, "A symbolic
3. For instance, simplification of the voltage gain for the folded cas- approach to the time-domain analysis of nonlinear or switched
code aTA of figure 1b, with a maximum error margin of 60% networks," in Proc. Int. Workshop Symbolic Methods, Paris, 1991.
(M = 0.6), yields a dc gain deviation of 1.6% [9]. 15. A. Liberatore and S. Manetti, "Network sensitivity analysis via
4. An analog schematic is said to be sized when a numerical value symbolic formulation," in Proc. 1989 IEEE 1nt. Symp. Circuits
has been assigned to each circuit element and model parameter. and Systems, pp. 705-708, Portland, 1989.
5. In practice a sufficiently fine grid should be defined inside that 16. R. Gregorian and G.c. Ternes, Analog MOS Integrated Circuits
region. jor Signal Processing, Wiley: New York, 1986.
6. Here, "symbol" is generally applied, in the sense that it may either 17. P. Allen and D. Holdberg, CMOS Analog Circuit Design, Holt,
denote a parameter space variable, a product of variables, or a Rinehart, and Winston: New York, 1987.
sum of products. 18. R. Unbehauen and A. Cichocki, MOS SWitched-Capacitor and
7. The models used in this example are intended only as an illustra- Continuous-Time Integrated Circuits and Systems, Springer: New
tion. Hence, they do not include all the issues required for prac- York, 1989.
tical transconductance amplifier applications. 19. Sspice User Manual, Version 1.0, Michigan State University, 1991.
20. M.M. Hassoun and P.M. Lin, "A new network approach to sym-
bolic simulation of large-scale networks," in Proc. 1989 IEEE
References Int. Symp. Circuits and Systems, pp. 806-809, Portland, 1989.
21. G.A. Watson, Approximation Theory and Numerical Methods,
I. P.M. Lin, Symbolic Network Analysis, Elsevier: New York, 1991. Wiley: New York, 1980.
2. T. Ozawa (ed.), Analog Methods jor Computer-Aided Circuit 22. C. Laber and P. R. Gray, ''A positive-feedback transconductance
Analysis and Diagnosis, Marcel Dekker: New York, 1988. amplifier with applications to high-frequency, high-Q CMOS
3. YP. Tsividis, "Analog MOS integrated circuits: Certain new switched-capacitor filters," IEEE J. Solid-State Circuits, Vol. 23,
ideas, trends, and obstacles," IEEE J. Solid-State CirCUits, Vol. pp. 1370-1378, 1988.
22, pp. 317-321, 1987. 23. D. Nairn and C. Salama, "High-resolution, current-mode AID
4. E. Vittoz, "Future of analog in the VLSI environment," in Proc. convertors using active current mirrors," Electron. Lett., Vol.
1990 IEEE Int. Symp. Circuits Syst., pp. 1372-1375, 1990. 24, pp. 1331-1332, 1988.
5. L.R. Carley and R. Rutenbar, "How to automate analog IC 24. G. Di Domenico, S. Seda, M.A. Khaifa et aI., "BRAINSI
designs," IEEE Spectrum, pp. 26-30, 1988. SYNAP: A symbolic solver for analog circuits," in Proc. First
6. G. Gielen and W. Sansen, Symbolic Analysis jor Automated Int. Workshop Symbolic Methods, Paris, 1991.
Design oj Analog Integrated Circuits, Kluwer: Boston, 1991. 25. E. Sanchez-Sinencio, R.L. Geiger, and H. Nevarez-Lozano,
7. S. Seda, M. Degrauwe, and W. Fichtner, "A symbolic analysis "Generation of continuous-time two integrator loop aTA filter
tool for analog circuit design automation," in Proc. 1988 IEEE structures," IEEE Trans. Circuits Syst., Vol. 35, pp. 936-946,
Int. Con! Computer Aided Design, pp. 488-491, 1988. 1988.
58 Fernandez, Rodriguez-Vazquez, Martin and Huertas

Francisco V. Fernandez received the Licenciado en Flsica degree Juan D. MartIn received the Licenciado en Flsica degree from the
in 1988 and the Ph.D. degree in 1992, both from the University of University of Seville, Spain, in 1988. He is currently working towards
Seville, Spain. In 1988 he joined the Department of Electronics and the Ph.D. degree in the field of analog design automation. Since 1988
Electromagnetism at the University of Seville, where he is a teaching he has been working at the Department of Analog Circuit Design
assistant. He is also at the Department of Analog Circuit Design of of the Centro Nacional de Microelectronica. His research interests
the Centro Nacionale de Microelectronica. His research interests in- are in the field of computer-aided design, programming techniques
clude design and modeling of analog integrated circuits and analog and analog design automation.
design automation.

Jose L. Huertas received the Licenciado en Flsica degree in 1969


Angel Rodriguez-V3zquez (M'80) received the Licenciado en Flsica and the Doctor en Ciencias Flsicas degree in 1m, both from the
degree in 1'f77, and the Doctor en Ciencias Flsicas degree in 1983, University of Seville, Spain. From 1'f70 to 1'f71 he was with the Philips
both from the University of Seville, Spain. Since 1'f78 he has been Internationallnstitute, Eindhoven, The Netherlands, as a postgsraduate
with the Department of Electronics and Electromagnetism at the student. Since l'f7l he has been with the Department of Electronics
University of Seville where he is an associate professor. He is also and Electromagnetism at the University of Seville where he is a pro-
at the Department of Analog Circuit Design of the Centro Nacional fessor. He is also at the Department of Analog Circuit Design of
de Microelectronica. His research interest are in the fields of the Centro Nacional de Microelectronica. His research interests are
analog/digital integrated circuit design, analog integrated neural and in the fields of multi valued logic, sequential machines, analog cir-
nonlinear networks, and modeling of analog integrated circuits. cuits design, and nonlinear network analysis and synthesis.
Analog Integrated Circuits and Signal Processing 3, 59-72 (1993)
1993 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits

S. MANETTI AND M.e. PICCIRILLI


Department of Electronic Engineering, University of Florence, 50139 Firenze, Italy

Abstract. A new symbolic technique for the realization of simulators for nonlinear analog circuits is presented.
The generated simulators work with input/output in numerical form, but they are very efficient due to the use
of the symbolic approach. For nonlinear components a PWL (PieceWise Linearization) method is used. The pro-
posed approach permits to obtain libraries of simulators which can be very useful in many application fields. In
particular we present a possible application to an expert system devoted to nonlinear circuit fault diagnosis. The
program package, realized for this application, is described from both algorithmic and functional points of view.
Some simple examples are presented in order to illustrate the main features of the program.

1. Introduction The outlined approach can be used to generate


autonomous programs devoted to the topological cir-
The circuit symbolic simulation is a process which cuit analysis. Furthermore, for a complex circuit, these
yields network functions in which some or all of the simulators can be devoted to parts of the circuit in order
circuit elements, along with the complex frequency, are to obtain a simulator library.
represented by symbolic parameters. The above-mentioned application areas involve, very
This approach can be very useful in many situations often, nonlinear devices and the required simulations
[1-27], as for example in linear circuit design applica- are, prevalently, in time domain. Then it is mandatory
tions. In fact, numerical simulators give results in to extend the symbolic approach to this type of simula-
tabulated or plotted form, without any indication about tion, that is to nonlinear transient analysis.
which circuit element determines the observed perfor- In this paper a program package, developed by the
mance and without pointing out potential problems or authors is presented following the outlined approach.
suggesting possible solutions. On the contrary symbolic The program, named SAPDEC (Symbolic Analysis
simulators give, as a result, closed-form expressions, Program for Diagnosis of Electronic Circuits), is able
allowing the automate tedious hand calculations in order to produce devoted simulators for nonlinear analog cir-
to get real insight into the behavior of the circuit. Then cuits. The program was originally aimed at the applica-
they can be very useful for designers to check their own tion of expert systems for fault diagnosis, but it is also
intuitive knowledge, in particular for nonconventional suitable for the other applications which can exploit
circuit configurations. repeated simulations of the same circuit topology.
Another field in which the symbolic approach can
give noteworthy advantages with respect to the 2. Computer Generation of Devoted Simulators
numerical techniques is constituted by those applica-
tions which require the repetition of a high number of The technique proposed in this paper presents several
simulations performed on the same circuit topology novel aspects with respect to existing symbolic ap-
with the variation of component values and/or input proaches. First of all, the output of the realized pro-
signal values (circuit optimization, statistical analysis, gram package, SAPDEC, is an autonomous executable
design centering, tolerance analysis, fault diagnosis, and program, a simulator devoted to a given circuit struc-
so on). In this kind of applications the symbolic ap- ture, instead of a network function in symbolic form.
proach can be used to generate the requested network The generated simulators work with inputs and outputs
functions of the analyzed circuit in parametric form. in numerical form, nevertheless they are very efficient
In this way circuit analysis is performed only once and, because they strongly exploit the symbolic approach;
during the simulation phase, only a parameter substitu- in fact:
tion and an expression evaluation are required to ob- 1. they use, for numerical simulation, the closed sym-
tain numerical results. bolic form of the requested network functions;
60 Manetti and Piccirilli

2. they are devoted to a given circuit structure; in parallel with a current source Ii can be associated
3. they are independent from both the component with each nonlinear component: for every linearity
values and input values, which must be indicated region, Gi corresponds to the slope of the segment and
only at run-time, before numerical simulation. Ii to the zero-voltage current of the segment, as shown
Another novel aspect of the presented approach is in figure 1 for a diode.
constituted by the fact that the generated symbolic
simulators produce time-domain simulations and are
able to work on nonlinear circuits. To this end the 2.2. Transient Analysis Modelsfor Reactive Components
following methods have been used:
a. nonlinear components are replaced by suitable PWL The reactive components are made time independent by
models; using the backward difference algorithm and the corre-
b. reactive elements are simulated by their backward- sponding circuit models are constituted by a conductance
difference models; in parallel with a current source. In figure 2 the model
c. a Katznelson type algorithm is used for time-domain of a capacitor is shown as an example: the conductance
response calculation. value is a function of the sampling time T and the
In the following these three points are examined in capacitance value, while the current value depends on
detail. the sampling time T, the capacitance value and the volt-
age value at the previous time step. In this way neither
the Laplace variable nor integrodifferential operations
2.1. PWL Models are used and the circuit becomes, from the symbolic
analysis point of view, without memory, and, from the
With the PWL technique [28] the voltage-current numerical simulation point of view, time discrete.
characteristic of any nonlinear electronic device is
replaced by piecewise linear segments obtained by
means of the individuation of one or more comer points 2.3. The Katznelson Type Algorithm
on the characteristic. The so obtained piecewise linear
characteristic describes approximately the element The Katznelson algorithm is an iterative process, which
behavior in the different operating regions in which it allows one to determine the dc solution of a PWL cir-
can work. It is evident that the increase of the corner cuit. In its standard form this algorithm can be sum-
points number and, consequently, of the linearity marized as follows [28, 29].
regions number allows to obtain a higher precision in The starting system is of the following kind:
the simulation of the real component; obviously, in this
(1)
way, the corresponding model becomes more complex.
It is worth pointing out that the symbolic analysis is where TI is the characteristic matrix of the circuit and
completely independent from the number of the PWL the subscript I denotes the region in which the network
characteristics corner points; in fact, from a symbolic operates. The right-hand-side vectors denote the
analysis point of view, each nonlinear component of equivalent sources due to linearization (WI) and the in-
a PWL model is represented by a single symbol. How- dependent sources (w) and they are written separately
ever, the increase of the number of corner points in- for clarity. Since at the beginning the regions are
fluences computational time in the numerical simula- unknown, the node voltages and the currents of current-
tion phase, so a trade-off between a small number of controlled elements are arbitrarily selected in order to
corner points and requested accuracy must be realized determine all the operating regions of PWL elements.
for each model. Then all GI and II are known and the vector XI is so
In order to determine the circuit network functions determined.! This vector does not satisfy equation (1)
the MNA (Modified Nodal Analysis) [19] is used dur- due to the arbitrary choice of node voltages and the cur-
ing symbolic analysis. This method yields a solving rents of the current controlled elements. Thus an
system whose dimension increases with the number of iterative process of correction starts for which the
components which have impedance representation. For estimated vector XI represents the initial value. By
this reason, if possible, a characteristic I = G(V) has defining an error vector as:
to be considered for nonlinear components. In this way,
an equivalent circuit constituted by a conductance Gi (2)
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 61

+
~I

Gl I l
v

o
I 2
a) b)
Fig. 1. (a) Diode PWL model; (b) diode PWL characteristic.

It must be noted that, using a symbolic approach,


+
the time-domain simulation can be obtained with an
algorithm derived from that now described, but simpler.
By means of the symbolic MNA applied to the circuit
structure, all the needed network functions are avail-
V k+1 able for the algorithm in a symbolic form. Starting
C
I=- V k
from an arbitrary value for MNA unknown vector, the
T corresponding PWL elements values are determined
and introduced in the network functions together with
C
I k +1 = ( V k + 1- Vk ) the actual values of both inputs and linear components.
T The correction vector is, then, evaluated and the iter-
ative process starts until the final solution is achieved,
Fig. 2. Backward-difference model of a capacitor.
following the steps reported in figure 3. The differ-
where k indicates the kth iteration, the solution is reached ence with respect to the standard Katznelson algorithm
whenp is equal to zero. Once p has been evaluated, a consists, prevalently, in the fact that, with the symbolic
correction vector """il is determined by solving the fol- approach, the program works on the closed-form ex-
lowing system: pressions of the network functions and then, for each
If """il = - P (3) step of the algorithm, there is not a linear system solu-
tion, but only an expressions evaluation. This allows
The new solution is
to obtain a noteworthy gain in terms of computational
(4) times in the numerical simulation phase. In particular,
If equation (4) involves that none of the PWL elements referring to figure 3, A? can be computed simply
changes its own operating region with respect to the kth as the difference between the ? vector and the l'
iteration, ?+! is the desired final solution, otherwise vector obtained from the symbolic network functions,
the procedure starts again, replacing x- k by a new ?+!, in which the PWL component values have been re-
that is obtained from equation (4) by multiplying A? placed by the values corresponding to the ? con-
for a suitable corrective factor r/ [28]. sidered vector.
62 Manetti and Piccirilli

by means of suitable partitioning techniques. Then, for


Symbolic Network
each part, the following operations have to be carried
out:
I. representation of nonlinear components by means
of appropriate piecewise linear (PWL) models;
2. symbolic analysis of each part with the generation
of the required network functions as C language
evaluation of the statements;
parameters values
for PWL elements
3. generation of the devoted simulator by means of the
compilation of the produced functions and linking
evaluation of MNA with a standard module, in C language, which im-
vector X~from symbolic
'------------~ network functions
plements a PWL simulation technique by means of
a Katznelson type algorithm.
no PWL componelS The above-mentioned operations are performed, in
. - - - - - - - - - - - { operating regions
are changed J
an automatic and autonomous way, by the program
"'-k
XI are the yes SAPDEC.
desired outputs
k+1 "'I( k K
The expert system, in the fault localization phase,
= X + 6 6X
samp",s XI
should perform the following operations:
1. selection of potentially faulty parts by means of
heuristic methodologies, based on measurements
Fig. 3. Block diagram of the time response algorithm for a given performed during circuit testing;
time step.
for each part:
2. measurement and acquisition of both input and out-
3. A Circuit Fault Diagnosis Application put signals;
3. use of the simulator relative to the considered part,
Following the approach outlined in the previous sec- with the utilization of the nominal component values
tion, a program package, named SAPDEC (symbolic and actual measured input signals;
analysis program for diagnosis of electronic circuits), 4. qualitative and quantitative comparison between
has been developed by the authors. It is able to generate simulation results and measured output signals;
simulators devoted to any part of a suitably partitioned 5. if the comparison result is right, go to another part
circuit. (point 2);
The program can be used to realize a library of 6. otherwise: variation of component values in order
devoted simulators. Each simulator of the library is to obtain the measured output waveforms by the
devoted to a part of the circuit and can be directly used simulation; the variation should be made by the ex-
by an expert system for circuit fault diagnosis. The in- pert system on the base of both heuristic considera-
put signals for these simulators can be constituted by tions and statistical information.
the actual signals on the circuit under test, suitably An important characteristic ofthe proposed approach
measured and stored on a file. The circuit responses, is constituted by the fact that the input signals for the
produced by the simulators and stored in another file, simulators are constituted by the actual signals on the cir-
can be compared by means of qualitative and/or quanti- cuit under test, measured in fault conditions. In fact, usu-
tative methods with the actual responses measured on ally, for fault diagnosis, test signals are used instead of
the circuit under test. From this comparison the ex- actual input signals; this can be very difficult to do and
pert system will be able to test the correctness of the could not reflect the real behavior in many cases, as, for
behavior of the considered part. When a faulty part has example, in equipments with strong feedback and with
been located, the expert system can try to locate the internally generated signals, such as dc-dc converters.
fault at a component level. This last phase will require As regards the decomposition of the circuit under
repeated simulations with suitable variations of com- test, some considerations can be done. At present this
ponent values. partition is not performed automatically and has to be
The realization of the simulators library for a given done by the user that must try to obtain a trade-off
equipment requires a preliminary phase constituted by among several objectives. An important point is the
the decomposition of the circuit under test in small parts choice of the size of the blocks: they must be small,
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 63

not only to obtain faster simulators, but to have blocks SPICE-like


characterized by a high testability, in which it is pos- circuit description
sible to determine the faulty components starting from
the measurements performed on input/output nodes.
On the other hand very small blocks increase the
cost of the test because they complicate the phase of
location of the faulty block and, generally, they involve
a high number of input/output nodes (which, obviously,
must be accessible).
A possible way to follow is the iterative use of ex-
isting partitioning techniques [30-32] and of algorithms
for testability computation [16] applied to the obtained
C
parts, until a good trade-off is obtained.
We are studying the possibility of performing this
simulation
operation automatically.
algorithm

4. The SAPDEC Program devoted


simulator
In figure 4 the block diagram of SAPDEC is shown.
The program runs on MS-DOS personal computers and Fig. 4. Block diagram of SAPDEC operations.
requires an Ascn file describing the circuit under test.
The form of this file is, for many aspects, similar to The obtained simulator is able to produce a file con-
that required by the SPICE program. Each device of taining the output signal samples, result of the simula-
the circuit is represented in the input file by one line. tion, starting from the input samples file (containing
The allowed linear components are: conductor, induc- also the used sampling time) and from the components
tor, capacitor, independent voltage and current sources, values file. The nonlinear component values are in the
the four controlled sources, mutual inductance, ideal form of a list of parameters for semiconductor com-
transformer. The nonlinear components are the follow- ponents and for the operational amplifier (for exam-
ing: nonlinear conductor, diode, voltage controlled ple, hie' VbeM Vcesat' etc., for bipolar transistor), while,
switch, operational amplifier, bipolar and MOS tran- for nonlinear conductors and diodes, the slope (in form
sistor. Suitable commands, included in the input file, of conductance) and the corner voltage of each PWL
must be used to communicate to the program the out- characteristic linearity region are given. For these last
put nodes list and the names of the files containing the elements all the corner currents numerical values are
input signals samples and component values. automatically calculated by supposing the correspon-
Once the program has started, all the component ding characteristic crossing the point (0, 0); this
numerical values (both linear and nonlinear) are stored assumption makes univocal the corner points deter-
and both nonlinear and reactive components are auto- mination without loss of generality, because all the con-
matically replaced by the corresponding equivalent cir- sidered components have an I-V characteristic cross-
cuits. Then the symbolic evaluation of the requested ing the point (0, 0) (for example, photovoltaic com-
network functions is carried out by means of a program ponents have not been considered).
written in LISP. These network functions are generated In figure 5 the devoted simulator flow diagram is
in the form of C language statements and are automatic- shown. Once the simulator is realized, by changing only
ally assembled with the standard module, in C the files containing respectively the component values
language, which implements the Katznelson type and the input samples, repeated simulations can be ob-
simulation algorithm. Finally the compilation and link- tained in a very fast way.
ing of the obtained source program is automatically per- Suitable PWL models have been chosen by the
formed, so realizing the devoted simulator, which is authors for transistors and operational amplifiers in
independent of the component values, input sample such a way to realize a trade-off between a low num-
values, and sampling time. ber of components and simulation accuracy, taking
64 Manetti and Piccirilli

COMPONENT simplicity) reproduce the behavior in the three possible


INPUT
VALUES operating regions. The CCCS (Current Controlled Cur-
FILE
FILE rent Source) is controlled by the base current and is
linear (Ie = hfeh). The diode and the nonlinear con-
ductance play their own role in the cutoff and the satura-
tion regions. In the cutoff region the diode is off and,
DEVOTED then, also the CCCS current is off; in the saturation
SIMULATOR region the Vee is limited to the Vcesal value by the
nonlinar conductance, which is inactive in the other
regions. The program automatically adopts the right
model on the base of values of Vbe cutoff voltage and
OUTPUT \,
Gbe conduction conductance of the diode and of hfe
FILE
and Vcesal values, all specified by the user.
The model adopted for the real operational amplifier
Fig. 5. Devoted simulator operations flow diagram. is shown in figure 7 and takes into account the two
saturation regions. If the input voltage is between
into account the specific application requirements. For two fixed values Va and Vb, we have a linear be-
the transistor (MaS and bipolar) a model derived from havior, otherwise we have the saturation of op amp. Va
that of Ebers-Moll has been considered, while for the and Vb are automatically computed by the program by
operational amplifier a high input impedance and dividing Vmin and Vmax for the gain, where the mini-
suitable VCYS, (Voltage Controlled Voltage Source) mum output voltage Vmin , the maximum output volt-
reproducing the sigmoid-like input-output characteristic age Vmax' the gain and input conductance are specified
have been considered. by the user.
In particular for bipolar and MaS transistors the The representation used for switches is equivalent
model shown in figure 6 has been considered, in which to that of a nonlinear conductance, controlled by an ex-
the modifications with respect to the Ebers-Moll model ternal voltage. Then the equivalent circuit is similar to
have been necessary in order to reduce computational that of diode with the difference that the control voltage
time and memory requirements. The two parallel ele- is not the voltage of the component itself. Therefore,
ments between collector and emitter (only notations in the phase of circuit description, transistors used as
relevant to the BJT have been used for the sake of switches have their own representation.

B c
E CCC5
a) b)

..... ,.. ..... ", .


-v
",

esat
c)
Fig. 6.. (a) BJT transistor model; (b) PWL model; (c) nonlinear conductance characteristic.
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 65

G.ill

a)

c)

{\Vd
Vu
Va<Vd<Vb
Vv =
elsewhere
V max . ..... .
,

f:":x
Va
V d< Va
Vb + - Vf
V-V =Vd V d> Vb

V mm
. Va < Vd < Vb
b)
Fig. 7. (a)Op amp; (b) input-output PWL characteristic; (c) PWL model.

lt should be noted that the above presented models 8


are very simple, so the obtainable simulation accuracy
is not very high, but it is acceptable for fault diagnosis
+lQV
as well as for other application fields. Obviously the
use of more complex models permits to obtain more
Vout
accurate results.
Summarizing, the simulators produced by SAPDEC
have the following characteristics:
1. they are very compact (few tens of kbytes); 1 6
)1--_.....
2. they are very fast (few seconds to obtain 100 of out-
put samples on a medium-speed PC); Vin
3. the input signals samples are read from a file;
4. the output signals samples (the simulation result) are
stored in a file;
5. the component values are read from a file.
lt is worth pointing out that the files for input signals
and for output signals have the same structure. Then
it is also possible to use as input signals for a given Fig. 8. Schmitt trigger circuit.
block the simulated output signals of another block.
the input file, while in figure 10 and in figure 11 the
5. Illustrative Examples input and output signals respectively are reported. In
this case SAPDEC is used as a numerical simulator
For the first example, let us consider the simulation without taking maximum advantage of its symbolic
of the trigger circuit shown in figure 8. Figure 9 shows nature.
66 Manetti and Piccirilli

SCHMITT.CAP the measured output signal at node 5 is shown. In figure


(\TIN 1 0) 15 and in figure 16 the output signals at node 5 ob-
(BJT1 P 1 2 3 4 0.6 0.00045 tained by the devoted simulator, respectively for Gs =
200 0.2 0.8) 1/220 ohm- I (nominal value) and Gs = 1/82 ohm- I
(G1 8 4 1/2500) (fault value), are shown: as it can be noted, they are
(GE 3 0 0.01) very different. The comparison between the measured
(KCC 8 0 10) output signal in figure 14 and the waveform in fault
condition obtained by the simulator in figure 16 shows
(G2 8 7 0.001)
(GB 4 5 0.000051) that the program is able to produce output signals very
(BJT2 P 5 6 3 7 0.6 0.00045 similar both qualitatively and quantitatively to the ac-
200 0.2 0.8) tual measured output signals. The fact that the two
(.INP BJT.INP) waveforms do not fit perfectly is due to the very sim-
( . OUT 1 7) ple model adopted for the transistor and the backward
( . END) difference models used for reactive components. About
this second aspect, as well known, the sampling time
Fig. 9. Input file for the circuit in figure 8. plays its role: in order to reduce errors, it must be
chosen as small as possible, compatibly with arith-
For the second example, let us consider the circuit in metical errors. However, if the quantitative analysis is
figure 12, in which a fault condition has been simulated not exact, in the fault diagnosis field, a good qualitative
by changing the value of the conductance Gs from analysis can be satisfactory. Finally we note that in the
1/220 ohm - I to 1/82 ohm -I. The circuit constitutes second example the need of repeated simulations on
a part of a greater network that is connected to it by the same circuit, with different components values,
means of nodes 2, 3 and 4. In figure 13 the actual allows to take maximum advantage from the symbolic
measured input signals are reported, while in figure 14 nature of SAPDEC.

OUT 0) 1
._ ~. ~ ~._~ . ~-- _ ~ _.. ._ : : 1
. ..
.
. ... . .i
3.7<13 .......!
.
!. ~
.
~
.
!
.
~


: :
. .. : I

.-
I
. -
I
. . ......... _ .
. -.
.... .....
.

. _ - ........
1.243 ..- -
...
. .

............... _ .. . .. _.... .. .
... ....
-1.243
. .. . .. ....
.. . ., .
. .
-2."1,)~


. . . . " .
..................................................................................................
. ,
_.. __ ....
...
..
."
. ., ...

. .
-3.7-&3
f
.
~I
.
....--..1'zz:i.... 3"t-:ii:i-6Z7~ 0/-100

Fig. 10. Input signal for the circuit in figure 8.


Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 67

10 ,..---:----i
.: .
~ ..----:.._---:
OUT 0
;
<l
-;
"
...
.
,,r- _ 1.. ..- "
7.:5
................ _..;._ _ - .--.. - - .. - _-- 1-- .. _.. _- - -coo _
. ..
. . ...
.
.- _ ... --
.. _-_ -- ... -..
.
. . . .
..
..
..
..
. ..
.
.. .
. ,


.. ....
Z.:5 ... -: ..: . - "'.:.. - .
'"': .: :.. .
-:

~

. .
... . ..
I
. ..
... ..
..

_ .. .. . . ....
-2.5 ..................
... . ._. ~
.-
.. ~ ~

, ' "
. .
. ' " . , . .
, . . . . . . .. .-.
. -_
.. .
.... . .
.... .
..... ....
~

..
.. ..
. . .. ...
-7.:J

~ ..
... ... ...
ii.~. ..
....
~ii
.. ... ~.
...

~

.. ..
.
~

-10 .............'-i;i"" it :i" 3"..i :JO -6iC7::10'," -100

Fig. 11. Simulated output signal for the circuit in figure 8.

2 4 6. Conclusions

A new approach to the realization of symbolic


C1 G2 simulators for nonlinear analog circuits has been
1 10uF 1/4. 7K
O---j ~,........A...A/'-_---1::" G6 presented. To this end a new program package able to
1/47K generate symbolic simulators devoted to any part of a
G4 circuit, suitably partitioned, has been developed. The
1/680K program, named SAPDEC, runs on MS-DOS personal
3
computers and produces very compact and fast sim-
ulators. It can be used to realize a library of simulators
S
which can be of great utility in many application fields,
G8 CS GS
1/3.3k
as circuit optimization, fault diagnosis, tolerance
220uF 1/220
analysis, design centering and design verification. In
particular a possible application to fault diagnosis has
been presented.

Fig. 12. Circuit relative to the second example.


68 Manetti and Piccirilli

_
..... --- .. - ..
.
. .
_.. . _-_ .
.. .
-..
0.001l __
.. .... __ __ -
..
...
~

O.()()(,

0.00'1 _. -:--_
. _.- -:-
. --- -
.: .
--_.~--- -:
.
.
. . .
...
. ,
. ,
, .
. .
.
: : :
o.ooz ............
.
~
. ..
..:. :
.
u~

...
\--\---l--f---.+.'r---II---..l,+--+-+---Ir-+--J----4--\-1

-0.002 ............. -
. . -..
..
.
.
-o.OO~

-0.00G ..
( ~ ..;
. f ..

.
. .. . .. .
-0. 00lJ -5i;II:.ilt.uz-2:i-iii.i"3:a'i3ii;i-~0

(a)

. . . . . . .
1'.0 ~==i'1.~i-iY
... , ~ ~ ~

1.J:i

.
... . . t
. . :-,. . ,;.1.(
. . . . ."
. . .:;.

0.9
... . -:.._ _ :-. :. -:.
.. .
7~-_: ~

.
. . ..
..
.
. . ....
_ .. . . _. . . .
.............
.. ... .. .
. ,
. ..
..
...
.. ... .
...
.
..
. . "

..

...............;-
. .: :.
-o.~
..
. .
: :
,
-:
, .
.
....
.
. .
.
-: ~


. .
-0.9 ............. . _ .
.. -
. .. _ .
.
.-.
.
~-

-1.3:1 ., .
~II~-1"t1
.
. .. :..

-1.0 -5(;ii:z-16ii~fi:jliiir:a3'i;3'.iij-'1:10

(b)

Fig. 13. Measured input voltages, nodes 1 (a), 2 (b), 3 (c), and 4 (d).
Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 69

.. .
~~=r~
.
. .

..
. . .

..r..1....!..,...... +.. i..\.. ~


"
0.'

0.6 ............. -:- ; __ ; -;." __ .;.


_-_ ; ;. __ . . :.
: : : :
: :
. : .
.
: : :
.
0.3 ........ u -: ; ~ 1._ ~ l _.: .:
.... .... .
. .

-0.3

~~ . r11:1
.
-:

...
-0.6 ........- -t- .
t ";" o o ~ t_..--. ,_._ .."; ~ ~

~ ~ ~ ~ .
-0.9 _~ . ,.. f-~.;-i . f ~
; i :. ::
.
-1.2 ..:i6....i:I2.... 16ii.... ;2:.i'~ .....::;iiil.... -.--~3'i ...... ~<j3-.:4.:l0

(c)

2.0
---.. .--.-.-.- :--
.-.-.-..-..-t----- . - . . - --. . ---- -----. -.. -- --.-.;. -- --- .

~ -~ ~ -~. ~
.
., .
2.1

.......................... _- ...
1.4
...
.

0.7 .......... ...- .. . . .. .
.. ..
.

-0.7 ..............

-....-... -._--- ...----_.... _........


-1.'\.
. .
-2.1

-2.0
.
~(;--
.
..------i:I2.. ....J.6ii .... ---i:i"~ .. -:.iiil....-- .. 337...... sn------.. -'1.:10
(d)

Fig. 13. Continued.


70 Manetti and Piccirilli

S..:.Iu:::..:.ys-:::.ZSJ.:::7.ISJ
. . . . . . .
0.030'1

0.0200
V(.... \J
V~\~-'"' ~ V~

.............. :- .: -:. .::._ ;.
:. :
0.0.192 : ':._-_ :.: -- --_
:
::.
.
.. . ....
.
. ,
,
..
............. _
.
.
..
,
. . _. . . -...
0.()(y')6
.
..
...
.
1----. . j !
..
..
............... - .: .
: ,

-: -:- ,
..
: .: "':
-0.00'J6


.
..
. .
. ...
: : :

. ..,:.. .
-O.O~?2 ............. ...:,..- :
.
. .:
. - . .:
. .
:
, ~ .;
.
...
..
-0.0200 } j .. ii; ! j ~

. . . .
-0.000'1 .:.j'(;Iiiil6(j1i":i.:.iiji.. ~3'i393_"'':l0

Fig. 14. Measured output voltage at node 5.

O. ro367

.............
0.02&83

~

.:.. ...
..
~

..
-: --:-
.
...
..
..
:
... ... ~ ~

.... . . . .

............. _ . .
..
..
. .
.
, . .. ...
.
. ..
....
0.013'12
.. ,
.. ~

. .. .. ....
.
.. . .

............... .: :. -:,
.
-:-. .:. -: -::
... ..
-O.0~34.2

~

, .
. . . ...\ .
.
..
. . ..
"

.... .
.............. ...:,. _.. : :._._ ..:. .. : :
.. ..;
..
-0.026tJ3 ..: -

... .....
. . . . .
-.... ~ ..t- .. t~----:--- . It .-:

-0.~367 3(;ii:i].i:o:Ei:i-iii.l.. :ia'i393-Co

Fig. 15. Node 5 voltage, simulated for the Gs nominal value.


Symbolic Simulators for the Fault Diagnosis of Nonlinear Analog Circuits 71

0.0361Z

0.026j')

0.01')06 6 _
...
.. .... .... ... ... ... ..
..
...
0.OO9j31 ................ _ ..
..
..
..
.
..
.
_..
..
..
.. ...
. . ,..
.....
. .. . . .
. ..
.
'" ..
.
....
'"
. .
.

............. .. _ . ."
' " -.. ... ....
-O.00?~31

..
..
...
..
.. .
. .
.
.
.
. ..,..
... ..
. ... .
" " " .
..
-O.Ol'J06
...
................ ..;. :.-
..
:
..
.:.. .. ..:. ; ~
.. ..:
.
.
....
.
' ".... .
-O.020:S9
.

.
. .
.. :- ..,.. t
.
~
.
.. .... .,. .. , .. ~ .. 1.. :

-0.03612 "56-i:i:2..16u..;;t:l":,.. -iO.1'..337393_,,:l0

Fig. 16. Node 5 voltage, simulated for the Gs fault value.

Notes 9. G. Gielen, H. Walscharts, and W. Sansen, "ISAAC: A symbolic


simulator for analog integrated circuits;' IEEE JSSC, Vol. SC-24,
1. We are supposing that all the nonlinear elements are represented No.6, pp. 1587-1597, 1989.
by a characteristic of the kind 1 = G(V). 10. W. Sansen, G. Gielen, and H. Walscharts, "A symbolic simulator
for analog circuits," in Proc. ISSCC, pp. 204-205, 1989.
11. M. Hassoun and P. Lin, "A new network approach to symbolic
References simulation oflarge-scale networks;' in Proc. IEEE ISCAS 1989,
Portland, OR, pp. 806-809, 1989.
1. A. Liberatore and S. Manetti, "SAPEC-a personal computer 12. G. Gielen, H. Walscharts, and W. Sensen, "Analog circuit design
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ISCAS 1988, Helsinki: Finland, pp. 897-900. 1988. nealing;' IEEE JSSC, Vol. SC-25, NO.3, pp. 707-713, 1990.
2. S. Seda, M. Degrauwe, and W. Fichtner, "A symbolic analysis 13. P. Wambacq, G. Gielen, and W. Sansen, "Symbolic simulation
tool for analog circuit design automation," in Proc. ICCAD. pp. of harmonic distortion in analog integrated circuits with weak
488-491, 1988. nonlinearities," in Proc. IEEE ISCAS 1990, New Orleans, pp.
3. A. Konczykowska and M. Bon, "Automated design software for 536-539, 1990.
switched-capacitor Ie's with symbolic simulator SCYMBAL," 14. S. Manetti, M.e. Piccirilli, and A. Liberatore, "Automatic test
Proc. 25th DAC. Anaheim. pp. 363-368, 1988. point selection for linear analog network fault diagnosis;' in Proc.
4. A. Konczykowska, 1 Mulawka, and M. Bon, "An exaustive IEEE ISCAS 1990. New Orleans. pp. 25-28, 1990.
generation of switched-capacitor circuits: a symbolic simulation 15. A. Liberatore, S. Manetti, and M.C. Piccirilli, "Techniche di
and artificial intelligence approach," in Proc. IEEE ISCAS 1988, intelligenza artificiale applicate alia determinazione della
Espoo, pp. 1733-1736, 1988. testabilitit e alia scelta dei punti di prova in circuiti lineari
5. A. Liberatore and S. Manetti, "Network sensitivity analysis via analogici," Alta Frequenza, Vol. 3, No.2, pp. 137-145, 1991.
symbolic fonnulation;' in Proc. IEEE ISCAS 1989, Portland, OR, 16. R. Carmassi, M. Catelani, G. Iuculano, A. Liberatore, S.
pp. 705-708, 1989. Manetti, and M. Marini, "Analog network testability measure-
6. A. Konczykowska and M. Bon, "Symbolic simulation for effi- ment: a symbolic formulation approach," IEEE Trans. Instr.
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CAD;' Proc. IEEE ISCAS 1989, Portland, OR, pp. 802-805, 17. A Liberatore, S. Manetti, M.e. Piccirilli, and A. Reatti, ':A, new
1989. symbolic approach to the analysis of switch power converters,"
7. H. Walscharts, G. Gielen. and W. Sansen, "Symbolic simula- in Proc. EPE 1991, Florence, pp. 489-494, 1991.
tion of analog circuits in s- and z-domain;' in Proc. IEEE ISCAS 18. A. Liberatore. S. Manetti, and M.e. Piccirilli, ':A, symbolic
1989, Portland, OR, pp. 814-817, 1989. approach to the time-domain analysis of nonlinear or switched
8. lA. Starzyk and E. Sliwa, "Tolerances in symbolic network anal- networks," Int. Workshop in Symbolic Methods and Applications
ysis," inProc.lEEEISCAS 1989, Portland, OR, pp. 810-813.1989. to Circuit Design, Bagneaux, France, 1991.
72 Manetti and Piccirilli

19. S. Manetti, "New approach to automatic symbolic analysis of


electric circuits," lEE Proc-G, Vol. 138, No. I, pp. 22-28, 1991.
20. A. Konczykowska and M. Bon, "Analog design optimization
using symbolic approach;' in Proc. IEEE ISCAS 1991, Singapore,
pp. 786-789,1991.
2 I. G. Gielen, P. Wambacq, and W. Sansen, "Symbolic approxima-
tion strategies and the symbolic analysis of large and nonlinear
circuits;' in Proc. IEEE ISCAS 1991, Singapore, pp. 806-809,
1991.
22. EY. Fernandez, A. Rodriguez-Vazquez, and J.L. Huertas, "An
advanced symbolic analyzer for the automatic generation of
analog circuit design equations;' Proc. IEEE ISCAS 1991,
Singapore, pp. 810-813, 1991. Stefano Manetti was born in Florence, Italy, in 195 I. He received
23. L.P. Huelsman and D.G. Dalton, "A computational approach to the degree in electronic engineering from the University of Florence
the development and reduction of large symbolic expressions," in 1977. From 1977 to 1979 he had a research fellowship on the
in Proc. IEEE ISCAS 1991, Singapore, pp. 790-793, 1991. engineering faculty of Florence University. From 1980 to 1983 he
24. M.M. Hassoun, "Hierarchical symbolic analysis of large-scale was assistant professor of applied electronics at the Accadernia Navale
systems using a Mason's signal flow graph model;' in Proc. IEEE of Livorno. From 1983 he has been a researcher at the Electronics
ISCAS 1991, Singapore, pp. 802-805, 1991. Department of Florence University. Since May 1987 he has been
25. T. Matzumoto, N. Nakayama, and K. Tsuji, "Symbolic analysis associate professor of network theory at the same university. His
for large networks and systems including both numerical and sym- research interests are in circuit theory, neural networks, and fault
bolic parameters by using hybrid decomposition method;' in Proc. diagnosis of electronic circuits.
IEEE ISCAS 1991, Singapore, pp. 794-797, 1991.
26. Z.H. Arnautovic and P.M. Lin, "Symbolic analysis of mixed
continuous and sample-data system," Proc. IEEE ISCAS 1991,
Singapore, pp. 798-80 I, 199 I.
27. M.A. Styblinski, Xiao Sun, K.M. Opalska, and LJ. Opalski,
"An efficient symbolic approach to time delay optimization of
CMOS circuits," in Proc. IEEE ISCAS 1991, Singapore, pp.
814-817, 1991.
28. 1. Vlach and K. Singal, Computer Methods for Circuits Analysis
and Design, Van Nostrand-Reinhold: New York, 1983.
29. 1. Katznelson, "An algorithm for solving nonlinear resistor net-
works;' Bell Syst. Tech. 1., Vol. 44, pp. 1605-1620, 1965.
30. A. Konkzykowska and 1. Starzyk, "Computer analysis of large
signal flowgraphs by hierarchical decomposition method," in
Proc. ECCTD, pp. 408-413, 1980. Maria Cristina Piccirilli was born in Italy in 1959. She received
3 I. 1. Starzyk, "Signal-flow-graph analysis by decomposition the degree in electronic engineering from the University of Florence
method," IEEE Proc. Part G, Vol. 127, No.2, pp. 81-86, 1980. in 1987. From 1988 to 1990 she had a research fellowship from the
32. 1. Starzyk and A. Konczykowska, "F1owgraph analysis of large University of Pisa. From 1990 she has been a researcher at the Elec-
electronic networks," 1EEE Trans. Circuits Syst., Vol. CAS-33, tronics Department of the University of Florence, where she works
No.3, pp. 302-315, 1986. in the area of circuit theory and fault diagnosis of electronic circuits.
Analog Integrated Circuits and Signal Processing 3, 73-83 (1993)
1993 K1uwer Academic Publishers, Boston. Manufactured in The Netherlands.

More Efficient Algorithms for Symbolic Network Analysis:


Supernodes and Reduced Loop Analysis

RALF SOMMER, DIRK AMMERMANN, AND ECKHARD HENNIG


Institut fUr Netzwerktheorie und Schaltungstechnik, Technische Universitiit Braunschweig, FRG

"It's funny how many of the best ideas are just an old idea back-to-front."
Douglas Adams

Abstract. In this paper, two efficient approaches will be discussed that support linear network analysis: supernode
analysis (SNA) and reduced loop analysis (RLA). By means of some selected example networks, these methods
will be demonstrated and, thus, it will be shown that calculations can be dramatically simplified. In this way,
all network situations can be handled. There are obvious advantages to SNA as it combines the MNA and the
straightforward manual processing of the network. A very efficient solution strategy is obtained without source
shifting and other common, less directed methods being used. SNA/RLA and symbolic algebra fit extremely well
together. Thus an algorithm that supports the symbolic calculation of networks by means of supernodes which
has been conceptualized and implemented in the analog design expert system EASY will be presented in detail.
Above the educational aspect, it should be noted that the computer can now take a systematic approach to MNA
and network analysis in general.

1. Introduction infinite gain and their nullator/norator equivalents. A


few additional rules are appended to SNA and RLA
In recent years, symbolic methods have become increas- which make these approaches cope with nullors. An
ingly important in the equation-based nonfixed topology example network containing nullors will then be ana-
approach to the automated design of analog circuits. lyzed with SNA and RLA to demonstrate the universal-
Contrary to numerical calculations, symbolic calcula- ity and efficiency of the methods in all conceivable
tions tend to be very complicated and time-consuming, situations. Finally, some ideas will be presented on how
especially if inversion of large matrices-typically gen- SNA can be implemented on a computer; it will be
erated-must be performed. Thus, in order to make shown how to automatically generate a smaller system
symbolic network analysis feasible, it is necessary to of equations in comparison to popular methods. This
reduce the amount of mathematical work the task re- can be achieved by using a set of general rules for each
quires, to an absolute minimum. This can be achieved type of network element combined with the topological
by first selecting an analysis method appropriate to the information supplied by the network.
task, and then, systematically taking advantage of forced
conditions implied by the network.
In this paper, two efficient approaches will be dis- 2. Basic Relations and Theory
cussed that support linear network analysis: supernode
analysis (SNA) and reduced loop analysis (RLA). By Before launching into the discussion of efficient network
means of some selected example networks, these meth- analysis techniques, a remark must be made on an old
ods will be demonstrated and, thus, it will be shown bad habit which can be traced back to the time of
that calculations can be dramatically simplified. Since Kirchhoff himself and has still not been rooted out.
the simplified linear modeling of amplifier circuits such Very often, in literature as well as in lectures, loop equa-
as OpAmps and transistors through controlled sources tions are set up as sums of branch voltages, giving
is becoming increasingly important, this aspect will also something like the following for each loop:
be covered by the paper. Special importance will be
attached to the treatment of controlled sources with
74 Sommer, Ammermann and Hennig

Then, the Ui are expressed one by one in terms of loop DEFINITION. Supernodes are generalized cut-sets2
currents, and finally, those intermediate results are rein- enclosing independent and/or dependent voltage sources
serted in the above equation. This procedure is not actu- [1] .
ally incorrect, but, it is contrary to all efforts that try These special cut-sets will be used in a very efficient
to avoid the introduction of unnecessary variables and way as will be shown below.
equations.
To introduce unnecessary variables and equations
complicates the system of equations that need to be 3.1. Algorithm for Setting Up SNA Equations
solved. Furthermore, it obstructs any attempt towards
applying loop analysis to networks containing elements To set up the equations needed for SNA done by hand,
that have no impedance representation at all, such as follow these steps:
current sources and open-circuit branches. In a similar
1. Label each of the n nodes of the network, one of
way, everything mentioned here applies to the setting
which must be the reference node. Thus (n - 1) node
up of node equations as well.
voltages have to be taken as independent variables.
There exist several approaches to the systematic for-
2. Mark all supernodes by surrounding all the cut-sets
mulation of network equations which either require the
of voltage sources (s is number, no matter whether
network to contain certain types of elements only or
dependent or independent) by a closed line.
which yield a larger number of equations but can handle
3. Set up all forced conditions for each supernode. Use
all types of elements. A well-known example for the
the forced conditions to eliminate s node voltages.
latter is modified nodal analysis (MNA). Regrettably,
Take one reference node voltage of each supernode
MNA introduces additional equations although there
as the independent variable.
should be no need to set up more than n - 1 equations
4. Set up the remaining (n - s - 1) generalized cut-
if there are n nodes in the network. Likewise, I loops
set equations. (Set up one equation for each super-
should not yield more than I equations for any given
node as well as for every remaining regular node.)
network. Actually, there is no reason at all why current
sources should not appear in networks to be analyzed
Remark. Controlling currents have to be expressed in
with loop analysis (LA). For example, if a source cur-
terms of node voltages and element relations. This
rent i could be identified with one independent loop
might require additional node equations.
current jb the loop equation to obtain jk would not
even need to be set up, as jk is equal to i. The same
applies to nodal analysis (NA). If a voltage source is
3.2. Algorithm for Setting Up RLA Equations
considered as a forced potential difference of u between
its two terminal nodes (A) and (B), then one potential
The setup of the equations for RLA can be divided into
would be immediately known if either of the potentials
the following steps:
VB or VA were known. It turns out that every current
source sets a forced condition for LA much in the same 1. Remove all current sources (s in number, dependent
way that every voltage source does for NA. Conse- or independent) from the network.
quently, each forced condition reduces the degree of 2. Introduce (l - s) loop currents for the remaining
freedom of the independent equations by one. These (I - s) independent closed loops.
approaches will be called supernode analysis (SNA) 3. Reinsert the current sources step by step and assign
and reduced loop analysis (RLA). only one loop current to a closed loop laid across
this source in each step.
4. Identify all loop currents flowing through the current
3. Manual Equation Setup and Motivating Examples sources with the source currents themselves.
5. Set up all remaining loop equations. Express all volt-
Before some examples can be calculated to illustrate ages in these loops in terms of loop currents, the con-
the back-to-front idea underlying these approaches, a straint equations from step 4, and element relations.
clear definition of what supernodes are must be made 6. If there are voltage controlled sources, additional
before they are used. equations have to be set up.
More Efficient Algorithms for Symbolic Network Analysis 75

Another procedure to obtain an optimized set of Now the steps for the supemode method are applied:
loops is to generate a tree from the network in which
I. All nodes are labeled by VI, ... , Vs respectively.
the current sources are located within the interconnec-
2. Two supemodes are found and marked (see above).
tion branches. This tree approach can also be used to
3. The forced conditions are set up (reference voltage
prove the correctness of RLA. Furthermore, it should
of supemode SNI is VI): The additional equation
be relevant to support the implementation of RLA on
for the CCVS is V3 - VI = rG4 (V1 - Vs); this
a computer, because there are several methods to find
directly applied results in
exactly those trees by making use of the nodal incidence
matrix A [3]. V2 = VI + UOI (fl)
The following examples will hopefully put aside any
difficulties.
V4 VI + U02 (f2)
Vs U03 (f3)

3.3. Example Demonstrating SNA


V3 VI + r(V1 - U03 )G4 (f4)
4. Now one supemode equation can be written down
In the network shown in figure 1, there are six loops straightforward, directly expressing node potentials
and two independent current sources: this yields 6 - 2 via (fl) to (f4) (SNo belongs to the reference node,
= 4 equations when RLA is applied. On the other so no extra node equation is needed):
hand, when using SNA, a total of one supemode (SNI )
equation and one element equation for the CCVS are
/02 + G3 VI + G4(VI - U03 )
needed. This result is arrived at by identifying five + GSVI + U02 ) - U03 ) - /01 =0
nodes, taking into account the four voltage sources, and
which is only one independent equation with VI as
deducing the one required supemode equation. The
unknown.
facts listed above favor the supemode approach to
reduce the work most efficiently.
3.4. Example Demonstrating RLA

Since the network shown in figure 2 contains no


voltage sources or short-cut branches, it seems to be
suited perfectly to standard nodal analysis. A 3 x 3
matrix would have to be set up and inverted, if this
method was used. By counting the number of loops and
subtracting the number of current sources it turns out,
that only equation remains to be solved if RLA is
applied.
Following the strategy for the network on the left-
hand side results in the steps listed below:
I. Removing the current sources leaves only one closed
loop.
c,

Fig. 1. Example to demonstrate MNA and SNA. Fig. 2. Example for RLA.
76 Sommer, Ammermann and Hennig

2. The loop current jl is assigned to this loop. overall number (zero is a trivial case), is the approach
3. Reinserting 10 closes the loop L2 (identified with which will require the sources to be shifted in that direc-
loop current h), then the VCCS is inserted, thus tion. If SNA is the preferred method, then current
completing loop L3 (identified with loop currenth). sources have to be created. This may require more than
4. The loop currentsh andh are identified withh = one shift (see preceeding example). On the other hand,
10 and h = gU" where U I = Rlh- if RLA is the preferred method, then voltage sources
5. By directly inserting these relations the loop equa- have to be created through source shifting.
tion LI is set up: The circuit (figure 3) is another example for using
SNA. On the other hand, when using RLA, six loops
RIUI) + Rz(h - gRljl) + R3UI - 10) = 0
are found, and two forced conditions are set by current
This equation could be solved with ease. sources. As a result, source shifting or RLA would
The network on the right-hand side is a little more result in four equations. Applying the steps of SNA to
complicated as the currenth through the VCCS flows the network in figure 3:
in the controlling branch (R4 ) , too. For this reason,
one more equation has to be considered: Steps 1 and 2 1. All nodes are labeled by VI, ... , V4 respectively.
are the same as above, but in step 3 the voltage U4 2. Two supernodes are found and marked (see above).
across R4 has to be expressed in terms of loop currents
and element relations:
R4/ 0
3. U4 = R4(-gU4 + 10) ~ U4 = 1 + gR
4
Now the loop equation (L1) to derive !..I 3is set up:

4. LI: . IC J I
JW 1-
+ Rz (J I
l:.. - g 1 ~/OR
+g 4
J
+ R3(!..1 - 10) =0
0,,-;/(::-1_+---.:g;:..R..;,4,,-)_+~R-",3L-,"0
~!..I -_R_=-ZR-=4,""g:--:/
1/jwC + R + R I z 3
Fig. 3. Network, supemodes marked.

3.5. SNA in Comparison to Source Shifting

There is an interesting relation between the equations


which result from the SNA and RLA approach and
those obtained from standard methods by means of
source shifting. The crux of the problem is the question
of where to shift which sources? This question is quite
simple to answer now: for both methods (SNA and
RLA), the number of equations minus the forced condi-
tions is to be determined. The method with the smaller Fig. 4. Network, voltage source shifting.

V,-Uo, VI g(UO,+UOI - vd
r ...!:.... VI-UOI
R. R3 R, R.
I
U021
'"
1
Fig. 5. Transformation to Norton equivalent circuit.
More Efficient Algorithms for Symbolic Network Analysis 77

3. The forced conditions are set up (first independent


voltage sources, then controlled sources; reference
voltage of supernode SN, is V,): u,

V3 = U02 (fl) I
V4 = VI - Uo, (f2)

Vz = rGsV4 = rGs(V, - Uo,) (f3)


Fig. 6. Example nullor network for SNA.
4. Now one supernode equation can be written down
immediately, directly expressing node potentials via 3. The constraint equations are written down. The volt-
(fl) to (f3) (SNo belongs to the reference node, so age sources in SNo demand
no extra node equation is needed):

Gz(V, - rGs(V, - UOI)) + G,(V, - Uoz)


The nullator conditions demand
+ G4 V, - Uo,) - Uoz) - g(Uoz - (V, - UOI))

+ Gs(V, - UOI) - 10 = 0
4. All remaining node equations are set up. There is
which is one equation with V, as unknown. no equation needed for SNo because it is the refer-
ence node. Moreover, no equations are necessary
for nodes 1, 2, 3, and 6, since they belong to SNo.
4. Applying SNA to Nullor Networks This leaves only nodes 4 and 5 to supply the missing
two independent equations. By immediately insert-
Since there already exist other approaches that make ing the constraints from step 3, the following equa-
nullors fit into the concept of nodal analysis, it would tions are obtained.
be interesting to know if the same object could be
accomplished with SNA. In fact, only the following N4: G'(UI - V3 ) + G(U,
two rules have to be observed to achieve the goal. N5: GUz + Gz(Uz - V6 )
1. A norator must be considered as a voltage source These equations can easily be solved for V3 and V6
with an unknown output voltage.4 Therefore, norators It becomes apparent from this example and other
are treated like all other voltage sources as far as research, that SNA is a truly universal and powerful
their inclusion in a supernode is concerned. How- tool for handling all imaginable network elements and
ever, since their output voltage is arbitrary, they do configurations.
not furnish any constraint equations. This is logical
as each norator causes the rank of the admittance
matrix to be reduced by one. 5. An RLA Approach to Nullor Networks
2. Nullators must not be incorporated into a supernode.
Each nullator forces the potentials at its two terminal The following example demonstrates that RLA is also
nodes to be equal, thus eliminating one node voltage able to handle nullors very well.
from the system of equations. Figure 7 shows the network that will be analyzed
To demonstrate the application of SNA to nullor net- below. In fact, it is almost the same network on which
works, the example network in figure 6 will be ana-
R
lyzed. The task shall be to compute the node voltages
V3 and V6 .
1. All nodes are given individual labels/variables:
VI>' .. ,V6
2. All supernodes are marked. In this case, there exists
only one supernode, which consists of the two volt-
age sources U, and Uz, and both norators. Fig. 7. Gyrator equivalent circuit.
78 Sommer, Ammermann and Hennig

an SNA was already performed in Section 4. The task Sorting the equations and variables results in the follow-
supposed here is to compute the output current of the ing 3x3 system that must be solved for the norator out-
norator on the right-hand side. Since the unknown value put current 17.
is a current, it is best to apply RLA. Thus, one loop
current has to be defined for each of the seven indepen-
dent loops as was shown when RLA was introduced.
-R_~l R,
o
R ~ R2]
-R2
[!:]
17
As far as the nullors are concerned, a few additional
rules must be observed. = [Rl\ - (2~2 + R)12 ]

1. A nullator is a special case of a current source.


2R212
Hence, only one single loop current may pass through
each nullator. Nullator loop equations are thus set up The unknown op amp output current17 can be obtained
like regular loop equations. The nullator loop current as 17 = 2/1 as a result of only a few mathematical
is forced to be equal to zero, and consequently, does steps. In this case, RLA proves to be even more effi-
not appear in the equation. In this way, a nullator cient than SNA because SNA would have required
loop furnishes two equations: one loop equation and another node equation to express the norator current
one constraint equation for the loop current. in terms of node voltages and element relations.
2. In spite of the fact that a norator may be traversed
by any number of loop currents, it is recommended,
6. Correlation of MNA and SNA
however, to let only one loop current flow through
each norator. The idea is that every norator reduces
6.I. Motivating Example: Supernodes for Use in
the rank of the impedance matrix by one, because
Computer-Aided Analysis
its voltage as well as its current are arbitrary. Thus,
there will be no need to set up the norator loop equa-
Independent of the network type and size, the super-
tion at all, because it is linearly dependent on the
node method is an important and extremely useful tool
other equations.
for circuit analysis. This method is usually done by
3. Otherwise, if for any reason, more than one loop
hand but can be easily adapted for use by computers
current must be laid across a norator, it is necessary
with symbolic network analysis programs. This is
to set up all norator loop equations with an unknown
especially relevant, as compact equations are much
norator voltage u that must first be eliminated from
more important for symbolic calculations as they would
all equations but one. Then this last equation which
be for numerical calculations. The cost benefit of pre-
still contains the unwanted unknown u may be
processing the equations, and thereby reducing them in
deleted because it is no longer needed.
number, is strongly noticed later in the much simplified
Thus, a nullator reduces the number of variable loop arithmetic that must be done. For example, the sym-
currents by one, whereas a norator saves one entire loop bolic solution present in figure 1 requires the setting
equation. up of one equation, which is also linear. The additional
From figure 7, the following four constraint equa- four equations are "forced conditions" which could,
tions are obtained: with the result of a single equation mentioned, be
simply solved. On the other hand, the use of MNA
would require the setting up of 10 equations with 10
Hence, only h, J4, and 17 are left as unknowns. Loop unknowns. The latter is obviously more difficult.
equations must be set up for loops 3, 5, and 6. There
are no equations needed for loops 4 and 7 because of 6. I. I. Supernode Approach. A supernode analysis of
the reasons mentioned in rule 2. this network has already been performed in Section
3.3, resulting in only one independent equation which
L3: RU3 - J4 - 1\) + R\U3 - J4) + R\J3 + Rh must be solved. This poses an interesting question: Is
+ R2U3 + 12) + R2U3 + 17 + 12) it possible to interpret and to derive the supernode
+ RU3 + 17 + 12) = 0 method from the MNA or the general system of equa-
tions? If this is possible, then the topological informa-
L5: R\U3 - J4) + RJi3 =0 tion contained in the supernode(s) could be used before
L6: R2U3 + 12) + R2U3 + 17 + h) = 0 (or in) the MNA, and thereby simplify the amount and
More Efficient Algorithms for Symbolic Network Analysis 79

type of mathematics needed to solve the system of equa- the other potential is well defined (in terms of the first),
tions. In the following sections, this aspect will be in- and is no longer an equation in the system that needs
vestigated in detail. Furthermore, an algorithm already to be solved. The number of unknowns has been re-
implemented in EASY [4, 5], will be presented and duced from three to one. For example, Vq can be ex-
discussed. pressed as Vq = Vp - Uo. Exactly this elimination is
The MNA is a well known and commonly imple- recognizable in the filling pattern of the MNA matrix
mented method for the analysis and calculation of net- (see figure 9). It is possible to add row p to row q. One
works: for example, SPICE. At this moment, only the of the original two rows may then be deleted. In this
results of the theory behind the MNA are needed, so manner, the variable i k can be eliminated, so that this
that the matrix can be filled appropriately for each ele- column may be deleted as well. This seems to be the
ment. The node-based equations (KCL) represent each RMNA approach sometimes referenced in the litera-
row of the aforementioned matrix. ture [6].

6.2. The Interpretation of a Supernode


Po
-0
Ua

i. q

Consider a simple supernode with an independent volt-


age source (figure 8). The unknowns needed for the Fig. 9. MNA fill-in patern of an independent voltage source.
usual approach are Vp , Vq , and the supporting current
i k The following two equations are then set up: It is possible to obtain another simplification by
using the row k as a forced condition to eliminate either
Node p: i1 + i2 + ik = 0
Vq or Vp Consequently another column has disap-
Node q: i3 + i4 - ik = 0 peared.s This latter step may not be suited for a numer-
ically based program as it is not able to perform simple
equation manipulation. On the other hand, a symbol-
ically based program is able to perform this extraction
of subexpressions in terms of one or more variables
quite simply. As a result, only one of three equations
remain to be solved, and there is only one as opposed
to three unknowns left to be solved for. If this were
Fig. 8. Independent voltage sourced as supernode. extrapolated onto a large system, the benefit would
become quite apparent [8, p. 125]. In the same way,
The currents iJ, i2 , i3 , and i4 are then soleley functions VCVS and CCVS can be handled.
of nodal potentials and element relations (e.g., Ohm's The description of the algorithm in Section 8 will
law). But, a new variable, i b has appeared, thus re- clarify any doubts that may exist.
quiring an additional equation:
(*)
7. Nullator, Norator, and Nullor
The construction of a supernode means that a cut-set
equation has to be set up, and this is nothing more than Nullators and norators can be easily incorporated into
the addition of the two node equations in nodes p, q. the analysis. A nullor consists of a norator and a
In this way, the current i k must eliminate itself as it is nullator. The schematic and matrix fill-in model are
present in a positive sense in one equation and negative presented in figure 10. Two properties are easily
in the other one. This results in only one cut-set equa- recognized.
tion, in which the potentials Vp and Vq are still present
as unknowns:
iI + i2 + i3 + i4 = 0 p q p [v v, :i;]
P

~q I, .-I
This degree of freedom can be immediately reduced
Nullator fill-in Norator fill-in
by applying the forced condition (*). Consequently, one
of the two potentials remains as an unknown, whereas Fig. 10. Fill-in patterns of a nullator and a norator.
80 Sommer, Ammermann and Hennig

1. Each of the nullator and norator introduce only one Explanation (4b). The inclusion of the row k' to
new row or column, but not both. Consequently, the the supernode k, k' still allows access to the origi-
matrix is no longer square, and the system of equa- nal node(s), and thereby does not hinder the collec-
tions is singular. tion of several nodes into a supernode.
2. A nullor (a nullator and a norator) eliminates one Note. If k or k' is the reference node (ground)
row and one column from the matrix. This is equiva- then step 4a is not performed. In place of step 4b,
lent to constructing a supernode around the norator. the computer generates supernode SNo labeled with
Mathematically, row r is summed to row s, resulting 0, k.
in row r being removed from the matrix. In this way, Explanation. The reference node row is linearly
the norator current is eliminated from the list of un- dependent on the other nodal rows. It may be deleted
knowns. A nullator equates Vp to Vq . This collec- because it has been incorporated into SNo. The
tion of unknowns means that column p is added to voltage reference is remembered.
column q, and columnp can be removed. Likewise, 5. For all short-circuits between node j and node j':
Vp is removed from the list of unknowns. a. Add column j to column j'.
b. Delete column j which is redundant.
c. Remove row m + 1 which is a zero row. (Row
8. Algorithm Implemented in EASY m + 1 denotes the row belonging to the short-
circuit.)
EASY [4, 5] is an experimental analog design expert Explanation (5a). A short-circuit means Vj = vr,
system developed at the Institute of Network Theory and therefore, the columns are combined.
at the Technical University of Braunschweig. The Explanation (5b). Row m + 1 informs that Vj =
following algorithm was conceptualized and imple- vr' This is the forced condition.
mented in EASY. The algorithm supports the symbolic 6. Fixing of desired voltages:
calculation of networks by means of supernodes. It a. Output of all remaining nodal voltages.
offers the possibility to express the results in the b. User input of desired voltages in terms of node
Belevitch form, which is needed to support the calcu- voltage differences.
lation of networks containing nonlinear elements via c. Apply the following scheme for the substitution
a piecewise linear representation. This will be re- of nodal voltages by branch voltages:
ferred to as the PWL Tool, and is described in more (i) Potentials not needed for the description of
detail in [9]. the desired voltages must remain.
The algorithm contains the following steps: (ii) Of the r branch voltages that exist, as many
(if not all) as possible are to be used to
1. Read in network/netlists (to calculate currents, a replace the node voltages (s) being their
short circuit branch must be identified). number). For this reason, the rank of the
2. Set up standard matrix for MNA. matrix V must be r, otherwise the voltages
3. Create lists needed for the evaluation. are linearly dependent on each other.
a. Create list of all control currents (L)).
100
b. Create list of all generated currents in the MNA
010
(Lz)
001
c. Deduce list of desired currents (~).
d. Generate the union list/set of L 1 and ~ (Lunion)'
4. For all currents from node k to k', ik,k' rt: Lunion:
a. Add row k to row k'.
V,
b. Rename row k' to k, k'.
c. Delete row k and column h,k" i.e., the column 1 0 0 V" ..
belonging to the eliminated current. 1 I 0 V 2 , .
Explanation (4a). By the addition of row k and 0 1 1 V .. , ..
row k', a cut-set of node k and k' is generated: the (1)
supernode. The internal currents through the voltage
sources and the short-circuits will be eliminated in
this way. Vs
More Efficient Algorithms for Symbolic Network Analysis 81

By using Gauss-Seidel elimination tech- dents have often commented that the above listed ideas
niques, the matrix will be restructured to ap- have been juggled in a haphazard somewhat nonpredict-
pear in the form: able way resulting in a poor understanding of circuit
analysis. Consequently, many may now be able to inter-
vJ, .. pret several of the SNA equations as one or the other
V2 , .
of the above listed "magical tricks."
0 0 v .. ,..

[1 1 0
1 1
...

] V4
V ..
10. Conclusions

The supemode method, when applied manually, allows


for a strongly reduced number of unknown voltages
and/or currents. By not calculating the currents with
(2) the aid of voltage sources and short circuits, it is possi-
ble to find efficient generalized cut-sets which consist
only of voltage sources (either dependent or indepen-
dent). These cut-sets are called supemodes. The de-
scriptive equations inside the supemodes are mostly
simplistic relationships. These should be used at a very
In this way the r node voltages are replaced
early stage to simplify the required linear algebra. In
by r desired branch voltages and s - r nodal
the case of current controlled sources, the currents
voltages.
should be expressed directly from the network by use
of element relations in terms of node potentials.
The methods encompassing nullors and their imple-
mentation into SNA/RLA have been made full use of
7. By means of Gauss-Seidel elimination, the poten-
in the development of these algorithms. Consequently,
tials of v ' are removed and a set of equations results
the use of nullors allows for the construction of simpli-
containing only the desired quantities.
fied networks and avoids complicated limit calculations.6
8. With user-input desired output format, the solution
In this way, all network situations can be handled. There
of the set of equations is constructed.
are obvious advantages to SNA as it combines the MNA
a. Explicit solution
and the straightforward manual processing of the net-
b. Belevitch form (n-port equations)
work. A very efficient solution strategy is obtained
These procedures written in MACSYMA [10] for without source shifting and other common, less directed
EASY [4, 5] directly correspond to the described algo- methods being used. SNA/RLA and symbolic algebra
rithm. In EASY, the results are used for fit extremely well together. As symbolic algebra is able
to identify and perform matrix row operations to reduce
fast simulation based on symbolic expressions to dis-
the degree of the system it strongly supports the ideas
play the results in oscilloscope-like icons that may
of SNA/RLA. Numerical methods, on the other hand,
be directly manipulated.
may be able to identify elementary matrix operations
piecewise linear tool, which needs a special preproc-
but cannot perform them on symbolic quantities.
essed Belevitch form [9].
So far, the scope of the independent node potentials
and loop currents has been underestimated. It has been
9. Cookbook Approaches, Educational Aspects the intention of this paper to look at the basic principles
behind loop currents and nodal voltages. In many ways,
In this section, the educational value of these ideas will this paper covers the very basics and may be considered
be discussed. It has been shown that source shifting, trivial, but it identifies some very simple ideas. These
Norton and Thevenin equivalent circuits, superposition- ideas have contributed more to circuit analysis than the
ing of sources, calculating op amp circuits, wise use various techniques and aids commonly known. It is
of approximations and simplifications in practical cir- hoped that the various aspects of circuit analysis have
cuits, and some aspects of circuit design are easy to been tied together in an algorithm which produces an
embed into the global concept of SNA and RLA. Stu- efficient and compact representation of the mathematics.
82 Sommer, Ammermann and Hennig

The resulting amount of work is much less in compari- 3. L.O. Chua and P. M. Lin, Computer-Aided Analysis ofElectronic
son to sparse tableau or MNA approaches. Above the Circuit Analysis, Prentice Hall: Englewood Cliffs, 1975.
4. R. Sommer, R. Kamitz, and E.-H. Horneber, "Qualitative reason-
educational aspect, it should be noted that the computer
ing in the analog design expert system EASY," in Proc.
can now take a systematic approach to MNA and net- ECCTD'9I, Copenhagen, 1991.
work analysis in general. The fact that the current 5. R. Sommer and E.-H. Horneber, "EASY-an experimental
centered representation has proven so fruitful may result analog design system framework," in Proc. Int. Workshop Sym-
in more research in this area. bolic Methods and Applications to Circuit Design, Paris/Bagneux,
1991.
6. K. Lee and S. Park, "Reduced modified nodal approach to cir-
Acknowledgments cuit analysis," IEEE CAS-32, No. 10, 1985.
7. W. Sansen and G. Gielen, "ISAAC: A symbolic simulator for
analog integrated circuits," IEEE J. Solid-State Circuits, Vol. 24,
The authors would like to acknowledge the students C. No.6, pp. 1587-1597, 1989.
Beckmann, H. Trispel, and G. Weinerth for their con- 8. G. Gielen and W. Sansen, Symbolic Analysis for Automated
tributions toward the project. We would especially like Design of Analog Integrated Circuits, Kluwer: Boston, 1991.
to thank A. Reibiger, Technical University Dresden, 9. R. Sommer, D. Ammermann, and E.-H. Horneber, "Qualitative
reasoning and nonlinear effects in analog design expert system
for profound discussions and for providing the theoreti-
EASY," in Proc. ICM'9I, Kairo, 1991.
cal background, and H. Ziemann for his invaluable help 10. Symbolics MACSYMA Reference Manual, Version 13, 1988.
during the translation of this paper. 11. W. Sansen and G. Gielen, in Proc. Summer Course in Systematic
Analogue Design, Katholiek Universiteit Leuven, 1990.

Notes

1. There exist some extreme situations in which these additional equa-


tions are needed to express controlling currents.
2. Generalized cut-sets are not necessarily minimal cut-sets [2]. This
means that the removal of a generalized cut-set may split the net-
work graph into more than only two components.
3. Remark: This notation means that the current is in the frequency
domain, commonly known as a phasor.
4. This intuitive explanation will be confirmed in Section 7.
5. These compactions are exactly the same as those applied by the
CMNA implemented in ISAAC [7, 8, II]. In fact, the CMNA
is isomorphic to the SNA.
6. Not subject of this paper.
Ralf Sommer was born in Reinbek, Germany, on October 17, 1961.
He received his degree in electrical engineering from the Technical
References University of Braunschweig in 1988. Since 1988 he has been a Ph.D.
candidate at the Institute of Network-Theory and Circuit-Design at
I. 1. David Irwin, Basic Engineering Circuit Analysis, Macmillan: TU-Braunschweig. His current researches are development of an ex-
New York, 1987. pert system for analog circuit design; topics of interest include net-
2. A. Reibiger, Private communication, Dresden, Braunschweig, work theory, symbolic computer algebra, and qualitative circuit
1991. analysis.
More Efficient Algorithms for Symbolic Network Analysis 83

Eckhard Hennig was born in Westerstede, Germany, on January 14, Dirk Ammermann was born in Bremen, Germany, on March 16,
1969. He is a graduate student in electrical engineering at the Technical 1967. He started studying electrical engineering at the Technical
University of Braunschweig. University of Braunschweig in 1987. In 1991-92, he attended Georgia
Institute of Technology, where he received his M.S. in electrical
engineering.