DLD GTU EXAM ASKED QUE.

PREPARED BY: MR.DARSHAK PANDYA

3RD COMP. DIV-C
Dt: 22/10/2012

Sr
CH Name
NO.
1-Binary function 1

5
6
 1
2-Boolean Algebra &
Logic Gates
2

5
6

8
9
10
11
12
 1
3-Simplification of
Boolean Function
2

1
4-Combinational Logic
2
3
4

5-Combinational Logic 1

With MSI And LSI

 2

3
4
5

6
7

8
9

6-Programmable Logic 1

Devices
2
3

7-Sequential Logic 1

Flip Flops
2

6
7

10
11
 12

1
8-Register Transfer
Logic
& Micro-operation
2
3

4
 1
9-Registers
2

10-Counters and 1

Memory Unit
2
3

11-Processor Logic 1

Design
2
3

4
12-Control Logic Design 1
2

3
 DLD GTU EXAM ASKED QUE.

DLD
DigitalLogicDesign
Date of
Questions Marks Exam
Convert the following numbers to decimal
(i) (10001.101)2 (ii) (101011.11101)2 (iii) (0.365)8 7 Dec-09
(iv) A3E5 (v) CDA4 (vi) (11101.001)2 (vii) B2D4
Perform the operation of subtractions with the following binary
numbers using 2 complement 7 Dec-09
(i) 10010 - 10011 (ii) 100 -110000 (iii) 11010 -10000
Define: Digital System.
Convert following Hexadecimal Number to Decimal :
B28, FFF, F28 7 Mar-10
Convert following Octal Number to Hexadecimal and Binary:
414, 574, 725.25
Convert the following Numbers as directed:
(1) (52)10 = ( )2
(2) (101001011)2 = ( )10 7 Dec-10
(3) (11101110) 2 = ( )8
(4) (68)10 = ( )16
convert decimal 8620 into BCD , excess-3 code and Gray code. 3 May-11
Convert decimal 225.225 to binary ,octal and hexadecimal 3 May-11
Demonstrate by means of truth tables the validity of the following
Theorems of Boolean algebra 7 Dec-09
(i) De Morgans theorems for three variables
(ii) The Distributive law of + over-
Implement the following Boolean functions
(i) F= A (B +CD) +BC with NOR gates 7 Dec-09
(ii) F= (A + B) (CD + E) with NAND gates
Draw the logic symbol and construct the truth table for each of the
following gates. 7 Mar-10
[1] Two input NAND gate [2] Three input OR gate
[3] Three input EX-NOR gate [4] NOT gate
Give classification of Logic Families and compare CMOS and TTL
7 Mar-10
families
Explain SOP and POS expression using suitable examples 7 Mar-10
Reduce the expression:
7 Dec-10
(1) A+B(AC+(B+C)D) (2) (A+(BC))(AB+ABC)
Explain with figures how NAND gate and NOR gate can be used as Universal
7 Dec-10
gate.
Draw symbol and construct the truth table for three input Ex-OR gate 2 May-11
Explain briefly: standard SOP and POS forms. 2 May-11
What are Minterms and Maxterms? 2 May-11
Explain NAND and NOR as an universal gates 4 May-11
Implement Boolean expression for Ex-OR gate using NAND gates only 4 May-11
Obtain the simplified expressions in sum of products for the
following Boolean functions: 7 Dec-09
(i) F(A,B,C,D,E) =(0,1,4,5,16,17,21,25,29)
(ii) ABCE + ABCD +BDE + BC D
Simplify the Boolean function:
(1)F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14) 7 Dec-10
(2)F(w,x,y) = (0,1,3,4,5,7)
Simplify the Boolean function:
(1) F = ABC+BCD+ABCD+ABC 7 Dec-10
(2) F =ABD+ACD+ABC
d=ABCD+ACD+ABD Where d indicates Dont care conditions
Simplify the following Boolean function using K-map
F( w,x,y,z) = ( 1 , 3 , 7 , 11 , 15 ) 4 May-11
with dont care conditions d( w,x,y,z ) = ( 0, 2 ,5 )

Design a combinational circuit that accepts a three bit binary

number and generates an output binary number equal to the square 7 Dec-09
of the input number.
With necessary sketch explain full adder in detail 7 Dec-09
Design a 4 bit binary to BCD code converter 7 Mar-10
Design a combinational circuit whose input is four bit binary number and
output is the 2s complement of the input binary number 7 May-11

Design a full-adder with two half-adders and an OR gate 7 May-11

Discuss 4-bit magnitude comparator in detail

7 Dec-09
Design a combinational circuit that generates the 9 complement of a 7 Dec-09
BCD digit,
Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI 7 Mar-10
Design a full adder circuit using decoder and multiplexer 7 Mar-10
Define: [1] Comparator [2] Encoder [3] Decoder
5 Mar-10
[4] Multiplexer [5] De-multiplexer
With logic diagram and truth table explain the working of 3 to 8 line decoder 7 Dec-10
With logic diagram and function table explain the operation of 4 to 1 line
multiplexer. 7 Dec-10

Design a BCD to decimal decoder 7 May-11

What is multiplexer? Implement the following function with a multiplexer:
F(A,B,C,D) = (0 , 1 , 3 , 4 , 8 , 9 ,15 ) 7 May-11

Write short note on EEPROM, EPROM and PROM

7 Mar-10

Write short note on : Read Only Memory (ROM) 7 May-11

A combinational circuit is defined by functions:

F1(A,B,C) = ( 3 , 5 , 6, 7 ) 7 May-11
F2(A,B,C) = ( 0 , 2 , 4, 7 )
Implement the circuit with PLA having three inputs ,four product term and
two outputs

Discuss D-type edge- triggered flip-flop in detail

7 Dec-09
Design a counter with the following binary sequence:0,4,2,1,6and 7 Dec-09
repeat (Use JK flip-flop)
Design a counter with the following binary sequence:0,1,3,7,6,4,and
7 Dec-09
repeat.(Use T flip-flop)
(i)With neat sketch explain the operation of clocked RS flip
7 Dec-09
(ii)Show the logic diagram of clocked D
Draw and explain the working of following flip-flops
7 Mar-10
[1] Clocked RS [2] JK
Convert SR flip-flop into JK flip-flop 7 Mar-10
With logic diagram and truth table explain the working JK Flipflop.Also obtain
its 7 Dec-10
characteristic equation. How JK flip-flop is the refinement of RS flip-flop?

Design a counter with the following binary sequence:

7 Dec-10
0, 4,2,1,6 and repeat. Use JK flip-flops
Draw logic diagram , graphical symbol , and
3 May-11
Characteristic table for clocked D flip-flop
What is race-around condition in JK flip-flop? 2 May-11
Explain working of master-slave JK flip-flop with necessary logic diagram
, state equation and state diagram 7 May-11
Design sequential counter as shown in the state diagram using JK flip flop
[clockwise direction to follow]

7 Mar-10

Discuss Interregister Transfer in detail

7 Dec-09

State and explain the features of register transfer logic 7 Mar-10

With respect to Register Transfer logic, explain Interregister Transfer with 7 Dec-10
necessary diagrams.
Prepare a detailed note on: Instruction Codes 7 Dec-10
With necessary sketch explain Bidirectional Shift Register with 7 Dec-09
parallel load.

What is the function of shift register? With the help of simple diagram explain
its 7 Dec-10
working. With block diagram and timing diagram explain the serial transfer of
information from register A to register B.

Draw the state diagram of BCD ripple counter, develop its logic 7 Dec-09
diagram, and explain its operation
Explain the working of 4 bit asynchronous counter 7 Mar-10
With logic diagram explain the operation of 4 bit binary ripple counter. Explain
the 7 Dec-10
count sequence. How up counter can be converted into down counter?
Give classification of counters and explain asynchronous 7 May-11

Explain memory unit

7 Mar-10

Explain the design of Arithmetic Logic Unit 7 Mar-10

What is scratchpad memory? With diagram explain the working of a processor
unit 7 Dec-10
employing a scratchpad memory
Draw the block diagram of a processor unit with control variables and explain
its 7 Dec-10
operation briefly
Explain Control Logic Design 7 Mar-10
Briefly explain control organization. With diagram explain control logic with
one 7 Dec-10
flip-flop per state
With simple diagram explain the working of control logic with sequence
register 7 Dec-10
and decoder