Department of Electrical and Computer Engineering

University of Waterloo

ECE 222
Digital Computers

Hiren Patel

Special thanks to Prof. Bill Bishop, Prof. Gord Agnew,

and Prof. Anwar Hasan. These slides heavily borrow
theirs.

NOTE:

Students enrolled in ECE 222 are permitted to print copies of

these lecture notes for their personal use in this course.
Department of Electrical and Computer Engineering
University of Waterloo

Basic Processing Unit

 Readings

HVZM6
Chapter 5

ECE 222 (Patel, H.): Basic Processing Unit 3

 Outline

Instruction Execution

Datapath design

Hardwired Control-path

RISC processor

ECE 222 (Patel, H.): Basic Processing Unit 4

 Fundamentals of Processor Design

The central processing unit consists of the following essential

components:
Control unit
Arithmetic and logic unit
Registers

The central processing unit performs the following steps to

execute a single instruction:
Instruction
1. Fetch the next instruction to be performed Fetch
Phase
2. Decode the instruction
3. Read operands (if necessary) Instruction
Execution
4. Perform the operation Phase
5. Store the result (if necessary)

ECE 222 (Patel, H.): Basic Processing Unit 5

 Instruction Execution into Five Parts

Let us split every instructions execution into five parts

1. Fetch the instruction and increment the PC
2. Decode the instruction to determine operation and read the source
operands
3. Execute the operation
4. Read from or write to the memory
5. Write back any data to the register file

We can implement all the major instruction types in these

five parts

Common terminology is to call them stages (five stages)

We have five stages that implement the entire ISA

ECE 222 (Patel, H.): Basic Processing Unit 6

 Necessary Datapath Components

The datapath of a processor encompasses the hardware

components needed to implement the ISA
1: Register file is a set 4: Instruction address
of registers. Source generator updates the
and destination contents of the PC
operands are read after every instruction. 1
from/stored to the PC [PC] + 4
register file.
5: Instruction register 5
2: ALU performs the (IR) holds the
arithmetic, and logical instruction.
operations. IR [[PC]]
2 4
3: Processor-memory
interface is used on
Loads and Stores to
read or write to the
main memory 3
(caches).

ECE 222 (Patel, H.): Basic Processing Unit 7

 Datapath and Control

Datapath
Functional units, registers, memory interfaces
Must be able to implement every instruction in the ISA

Control
Implements the decode stage of the instruction execution
Sets the appropriate inputs for the mux selectors, write enables, and so
on to regulate flow of data in the processor

ECE 222 (Patel, H.): Basic Processing Unit 8

 Datapath Design: Single Registers

Single registers are useful

PC: program counter
IR: instruction register

ECE 222 (Patel, H.): Basic Processing Unit 9

 Datapath Design: Register file
A register file is an
array of registers that
enable data to be read
from or written into 1
any register.

1: The maximum
number of registers
written to by the ISA is 3
one.
1
2: The maximum 2
number of registers
read by any instruction
in the ISA is two.

3: One must make

sure that the address 2
width of the signals A,
B, and C allows
addressing all the
registers. 32 registers
requires log2(32) bits.
ECE 222 (Patel, H.): Basic Processing Unit 10
 Datapath Design: Memory

Memory
Data Memory
Data
Memory Address

Clock
Read/Write

The memory interface interacts with the memory

Clock
Data input
Data output
Address
Read/Write
Memory operation done

ECE 222 (Patel, H.): Basic Processing Unit 11

 Datapath Design: RF + ALU
ALU performs arithmetic
and logic operations.
AND, OR, ADD, SUB,

1: Recall that all ALU 1

operations using generic
RISC occur on two
operands. 1
2: The two operands
(InA and InB) could be
of register-type 1 2 3

3: or one of the
operands could be of
immediate-type and the
other register-type. 3
2
4: The third destination
register is written back
to the register file.

ECE 222 (Patel, H.): Basic Processing Unit 12

 5-stage Implementation of a RISC
processor
1: Get the instruction To execute each stage in 1
pointed by the PC, and one cycle, we add inter- Fetch
store it into the IR. stage registers.

2: The instruction is 2
decoded and the source Decode
registers are read

3: The computation 3
specific for the Execute
instruction is performed.

4: If instruction is a 4
memory instruction then Memory
perform it in this stage.

5: The result of the 5

Write-
instructions operation is
back
stored in the destination
register.
ECE 222 (Patel, H.): Basic Processing Unit 13
Recall the Generic RISC Encoding

ECE 222 (Patel, H.): Basic Processing Unit 14

 Decode Stage

IR supplies addresses A and B

Address determined by Rsrc1 and
Rsrc2 bits in IR

Source registers are read and

their contents stored in RA
and RB

1: Inter-stage registers.

ECE 222 (Patel, H.): Basic Processing Unit 15

 Execute Stage

MuxB selects RB or
immediate field based on the
instruction in IR 1

R-type then 0
I-type then 1

Results of ALU stored in

register RZ

If Store instruction in IR,

then RB holds the data to be
written to memory. This is
transferred to RM

1: Inter-stage registers.
1

ECE 222 (Patel, H.): Basic Processing Unit 16

 Memory Stage

If non-memory operation
RZ holds computation result
1
MuxY puts RZ into RY

If Load
RZ holds effective address
MuxY selects memory data,
reads into RY

If Store
RZ holds effective address
1
RM holds data

MuxY input 2 used for 1: Inter-stage registers.

subroutine calls
We will see how this works
ECE 222 (Patel, H.): Basic Processing Unit 17
 Write-back Stage

Result of the instruction is

stored in the destination
register selected by address
C
Address C determined by dest
bits in IR (Rdst)

1: Inter-stage registers.

ECE 222 (Patel, H.): Basic Processing Unit 18

 Datapath of Generic RISC Processor
1: Assume that the 4: If instruction is non-
Fetch stage has fetched memory, then pass RZ to
an instruction pointed by RY.
the PC, and stored it in
the IR. If instruction uses
memory, then ALU
computes the effective 2 2
2: The source operands
are read from the address and stores it
register file in the into RZ. This is sent to
Decode stage and stored memory in the Memory
stage. 3
in registers RA and RB. 3
If Load then RZ is EA.
If Store then RZ is EA
3: RA provides input for and RB is moved to RM
InA of ALU. MuxB which holds the value.
provides either RB or 3.1
immediate value to InB Interrupt/Link uses 4
of ALU depending on Return address
instruction in IR.
5: RY written back to
4
register file.
3.1: Result from Execute 4
stage (ALU) is stored in
register RZ.
5

ECE 222 (Patel, H.): Basic Processing Unit 19

Recall the Generic RISC Encoding

ECE 222 (Patel, H.): Basic Processing Unit 20

 Instruction Execution: ADD R3,R4,R5

Fetch
1. Memory address [PC]
2. IR [[PC]] (Memory data)
3. PC [PC] 4

Decode (decode IR)

1. RA [R4] (IR31-27),
RB [R5] (IR26-22)

Execute
1. RZ [RA] [RB]

ECE 222 (Patel, H.): Basic Processing Unit 21

 Instruction Execution: ADD R3,R4,R5

Memory
1. RY [RZ]

Write-back
1. R3 [RY] (IR21-17)

ECE 222 (Patel, H.): Basic Processing Unit 22

 Instruction Execution: Load R5,X(R7)

Fetch
1. Memory address [PC]
2. IR [[PC]] (Memory data)
3. PC [PC] 4

Decode (decode IR)

1. RA [R7] (IR31-27)

Execute
1. RZ [RA] Immediate value
X

ECE 222 (Patel, H.): Basic Processing Unit 23

 Instruction Execution: Load R5,X(R7)

Memory
1. Memory address [RZ]
2. RY [[RZ]] (Memory data)

Write-back
1. R5 [RY] (IR26-22)

ECE 222 (Patel, H.): Basic Processing Unit 24

 Branch_if_[R5]=[R6] LOOP

Fetch Memory
1. Memory address [PC] 1. No action
2. IR [[PC]] (Memory data)
Write-back
3. PC [PC] 4
1. No action
Decode (decode IR)
1. RA [R5] (IR31-27),
RB [R6] (IR26-21)

Execute
1. Compare [RA] to [RB]
2. If [RA]=[RB] then
1. PC [PC] Branch offset
2. Branch offset is immediate operand
3. Separate adder needed
1. Both operations done in one cycle
2. Adder used from instruction
address generator

ECE 222 (Patel, H.): Basic Processing Unit 25

 Subroutine: Call_R R9

Fetch
1. Memory address [PC]
2. IR [[PC]] (Memory data)
3. PC [PC] 4

Decode (decode IR)

1. RA [R9] (IR31-27)

Execute
1. PC-Temp [PC], PC [RA]

Memory
1. RY [PC-Temp]

Write-back
1. Link_Reg [RY]
ECE 222 (Patel, H.): Basic Processing Unit 26
 Waiting for Memory

The processor-memory interface generates a signal called

Memory Function Completed (MFC)
Sometimes also called a stall signal

On a memory access
Hit in cache then MFC is set in the same clock cycle as request
Miss in cache then MFC stalls the execution of the instruction until
completion of request

Fetch and Memory stages must wait for MFC to be asserted

before continuing to the next stage
They both access the respective memory hierarchies

ECE 222 (Patel, H.): Basic Processing Unit 27

 Control Signals

Control circuitry generates control signals that orchestrate the

flow of data through the datapath components
Set multiplexor selection bits
Set the function performed by the ALU
Determine when data written to the PC, the IR, the register file and
memory

ECE 222 (Patel, H.): Basic Processing Unit 28

 Generating addresses for Memory
Accesses
Fetch
MuxMA selects PC for memory address
Address generator:
PC incremented after fetching an
instruction
Also generates branch and subroutine
addresses
RA for call to address in register
RY used to save link address

Memory stage
MuxMA selects RZ when Load or Store
memory operations (effective address)

ECE 222 (Patel, H.): Basic Processing Unit 29

 Instruction Fetch Stage

Adder
Increment PC by 4 for straight-
line execution
Compute new target address
for branch and subroutine calls

MuxINC
Selects between 4 and branch
offset
Branch offset extracted from IR
and sign-extended to 32-bits

MuxPC
Select next PC (result of adder)
Or address for subroutine
linkage

ECE 222 (Patel, H.): Basic Processing Unit 30

 Control: Instruction Address Generator

INC_select
0: +4
1: Branch offset

PC_select
0: RA (Subroutine)
1: Incremented PC
Needs PC_enable to be on

ECE 222 (Patel, H.): Basic Processing Unit 31

 Memory Accesses

Recall
Requested data in cache (hit) results in one clock cycle
Requested data NOT in cache (miss) requires multiple clock cycles
Control signal MFC is used to wait for response from memory

Fetch stage
Memory address [PC], Read memory, Wait for MFC,
IR Memory data, PC [PC] 4

Memory stage
Memory address [RZ], Read/write memory, Wait for MFC,
RY Memory data (if read)

ECE 222 (Patel, H.): Basic Processing Unit

 Control Signals: Memory and IR

MEM_read
To read from memory

MEM_write
To write to memory

IR_enable
Loads new insn into IR
Activated in Fetch, after
MFC is asserted

MA_select
RZ: Load and Store
address
PC: Fetch address

ECE 222 (Patel, H.): Basic Processing Unit 33

 Control: Register File Signals

RF_write C_select
When reading A and B, set to 0 R-type, dest is IR21-17
When writing C, set to 1
I-type, dest is IR26-22

ECE 222 (Patel, H.): Basic Processing Unit 34

 Control: ALU

B_select
0: RB
1: Immediate

ALU_op
k-bit control code
(AND, OR, ) encoded in k bits

Condition signals
Monitored by control circuitry
to ensure branching

ECE 222 (Patel, H.): Basic Processing Unit 35

 Control: Signal Generation

Two approaches to generating the control signals

Hardwired control
Microprogramming

Hardwired control
Implement circuitry (FSM) to govern the setting of control signals

Microprogrammed control
Set the control signals through software (microprogram)

ECE 222 (Patel, H.): Basic Processing Unit 36

 Hardwired Control

Decoder interprets Op-code

and address mode in IR

Step counter sets T# to

indicate which stage to
execute (mod 5 counter)

Control signal generator

Combinational circuit produces
control signals

ALU/Load/Call insn
RF_write = T5.
(ALUOp+LOADOp+CallOp)

Fetch/Branch
PC_enable = T1.MFC + T3.BROp
ECE 222 (Patel, H.): Basic Processing Unit 37
 Summary

Instruction Execution

Datapath design

Hardwired Control-path

Generic RISC processor

ECE 222 (Patel, H.): Basic Processing Unit 38