VeriloginterviewQuestions&answersforFPGA&ASIC.

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Veriloggatelevelexpectedquestions.

1)Tellsomethingaboutwhywedogatelevelsimulations?

a.Sincescanandotherteststructuresareaddedduringandaftersynthesis,theyarenotcheckedbythertl
simulationsandthereforeneedtobeverifiedbygatelevelsimulation.
b.Statictiminganalysistoolsdonotcheckasynchronousinterfaces,sogatelevelsimulationisrequiredtolookat
thetimingoftheseinterfaces.
c.Carelesswildcardsinthestatictimingconstraintssetfalsepathormutlicyclepathconstraintswheretheydon't
belong.
d.Designchanges,typos,ormisunderstandingofthedesigncanleadtoincorrectfalsepathsormulticyclepaths
inthestatictimingconstraints.
e.Usingcreate_clockinsteadofcreate_generated_clockleadstoincorrectstatictimingbetweenclockdomains.
f.Gatelevelsimulationcanbeusedtocollectswitchingfactordataforpowerestimation.
g.X'sinRTLsimulationcanbeoptimisticorpessimistic.Thebestwaytoverifythatthedesigndoesnothaveany
unintendeddependenceoninitialconditionsistorungatelevelsimulation.
f.It'sanice"warmfuzzy"thatthedesignhasbeenimplementedcorrectly.

2)SayifIperformFormalVerificationsayLogicalEquivalenceacrossGatelevelnetlists(Synthesisand
postroutednetlist).DoyoustillseeareasonbehindGLS.?

IfwehaveverifiedtheSynthesizednetlistfunctionalityiscorrectwhencomparedtoRTLandwhenwecompare
theSynthesizednetlistversusPostroutenetlistlogicalEquivalencethenIthinkwemaynotrequireGLSafterP&
R.ButhowdoweensureonTiming.TomyknowledgeFormalVerificationLogicalEquivalenceCheckdoesnot
performTimingchecksanddontensurethatthedesignwillworkontheoperatingfrequency,sostillIwouldgo
forGLSafterpostroutedatabase.

3)AnANDgateandORgatearegiveninputsX&1,whatisexpectedoutput?

ANDGateoutputwillbeX
ORGateoutputwillbe1.
 ORGateoutputwillbe1.

VerilogFAQ
4)WhatisdifferencebetweenNMOS&RNMOS?
SynthesisFAQ RNMOSisresistivenmosthatisinsimulationstrengthwilldecreasebyoneunit,pleaserefertobelowDiagram.

DigitalFAQ

TimingFAQ

ASICFAQ

CmosFAQ

MiscFAQ

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4)Tellsomethingaboutmodelingdelaysinverilog?

Verilogcanmodeldelaytypeswithinitsspecificationforgatesandbuffers.Parametersthatcanbemodelledare
T_rise,T_fallandT_turnoff.Toaddfurtherdetail,eachofthethreevaluescanhaveminimum,typicaland
maximumvalues

T_rise,t_fallandt_off

Delaymodellingsyntaxfollowsaspecificdiscipline
gate_type#(t_rise,t_fall,t_off)gate_name(paramters)
Whenspecifiyingthedelaysitisnotnecessarytohaveallofthedelayvaluesspecified.However,certainrules
arefollowed.

and#(3)gate1(out1,in1,in2)
Whenonly1delayisspecified,thevalueisusedtorepresentallofthedelaytypes,i.e.inthisexample,t_rise=
t_fall=t_off=3.

or#(2,3)gate2(out2,in3,in4)
Whentwodelaysarespecified,thefirstvaluerepresentstherisetime,thesecondvaluerepresentsthefalltime.
Turnofftimeispresumedtobe0.

buf#(1,2,3)gate3(out3,enable,in5)
Whenthreedelaysarespecified,thefirstvaluerepresentst_rise,thesecondvaluerepresentst_fallandthelast
valuetheturnofftime.

Min,typandmaxvalues

Thegeneralsyntaxformin,typandmaxdelaymodellingis
gate_type#(t_rise_min:t_ris_typ:t_rise_max,t_fall_min:t_fall_typ:t_fall_max,t_off_min:t_off_typ:t_off_max)
gate_name(paramteters)

Similarrulesapplyforthespecifyingorderasabove.Ifonlyonet_risevalueisspecifiedthenthisvalueisapplied
tomin,typandmax.Ifspecifyingmorethanonenumber,thenall3MUSTbescpecified.Itisincorrecttospecify
twovaluesasthecompilerdoesnotknowwhichoftheparametersthevaluerepresents.
Anexampleofspecifyingtwodelays
 Anexampleofspecifyingtwodelays
and#(1:2:3,4:5:6)gate1(out1,in1,in2)
Thisshowsallvaluesnecessaryforriseandfalltimesandgivesvaluesformin,typandmaxforbothdelaytypes.
VerilogFAQ
Anotheracceptablealternativewouldbe
or#(6:3:9,5)gate2(out2,in3,in4)
SynthesisFAQ Here,5representsmin,typandmaxforthefalltime.
DigitalFAQ N.B.T_offisonlyapplicabletotristatelogicdevices,itdoesnotapplytoprimitivelogicgatesbecausethey
cannotbeturnedoff.
TimingFAQ

ASICFAQ
5)Withaspecifyblockhowtodefiningpintopindelaysforthemodule?
CmosFAQ

MiscFAQ
moduleA(q,a,b,c,d)
Home inputa,b,c,d

outputq

wiree,f

//specifyblockcontainingdelaystatements

specify

(a=>q)=6//delayfromatoq

(b=>q)=7//delayfrombtoq

(c=>q)=7//delayformctoq

(d=>q)=6//delayfromdtoq

endspecify

//moduledefinition

oro1(e,a,b)

oro2(f,c,d)

exorex1(q,e,f)

endmodule

moduleA(q,a,b,c,d)
inputa,b,c,d
outputq
wiree,f
//specifyblockcontainingfullconnectionstatements
specify
(a,d*>q)=6//delayfromaanddtoq
(b,c*>q)=7//delayfrombandctoq
endspecify
//moduledefinition
oro1(e,a,b)
oro2(f,c,d)
exorex1(q,e,f)
endmodule

6)Whatareconditionalpathdelays?

Conditionalpathdelays,sometimescalledstatedependentpathdelays,areusedtomodeldelayswhichare
dependentonthevaluesofthesignalsinthecircuit.Thistypeofdelayisexpressedwithanifconditional
statement.Theoperandscanbescalarorvectormoduleinputorinoutports,locallydefinedregistersornets,
compiletimeconstants(constantnumbersorspecifyblockparameters),oranybitselectorpartselectofthese.
Theconditionalstatementcancontainanybitwise,logical,concatenation,conditional,orreductionoperator.The
 Theconditionalstatementcancontainanybitwise,logical,concatenation,conditional,orreductionoperator.The
elseconstructcannotbeused.

VerilogFAQ //Conditionalpathdelays
ModuleA(q,a,b,c,d)
SynthesisFAQ
outputq
DigitalFAQ
inputa,b,c,d
TimingFAQ wiree,f

ASICFAQ //specifyblockwithconditionaltimingstatements
specify
CmosFAQ
//differenttimingsetbylevelofinputa
MiscFAQ
if(a)(a=>q)=12
Home
if~(a)(a=>q)=14
//delayconditionalonbandc
//ifb&cistruethendelayis7elsedelayis9
if(b&c)(b=>q)=7
if(~(b&c))(b=>q)=9
//usingtheconcatenationoperatorandfullconnections
if({c,d}=2'b10)(c,d*>q)=15
if({c,d}!=2'b10)(c,d*>q)=12
endspecify
oro1(e,a,b)
oro2(f,c,d)
exorex1(q,e,f)
endmodule

6)TellsomethingaboutRise,fall,andturnoffdelays?

Timingdelaysbetweenpinscanbeexpressedingreaterdetailbyspecifyingrise,fall,andturnoffdelayvalues.
One,two,three,six,ortwelvedelayvaluescanbespecifiedforanypath.Theorderinwhichthedelayvaluesare
specifiedmustbestrictlyfollowed.

//Onedelayusedforalltransitions
specparamdelay=15
(a=>q)=delay
//Twodelaysgivesriseandfalltimes
specparamrise=10,fall=11
(a=>q)=(rise,fall)
//Threedelaysgivesrise,fallandturnoff
//riseisusedfor01,andz1,fallfor10,andz0,andturnofffor0z,and1z.
specparamrise=10,fall=11,toff=8
(a=>q)=(rise,fall,toff)
//Sixdelaysspecifiestransitions01,10,0z,z1,1z,z0
//strictlyinthatorder
specparamt01=8,t10=9,t0z=10,tz1=11,t1z=12,tz0=13
(a=>q)=(t01,t10,t0z,tz1,t1z,tz0)
//Twelvedelaysspecifiestransitions:
//01,10,0z,z1,1z,z0,0x,x1,1x,x0,xz,zx
//againstrictlyinthatorder
specparamt01=8,t10=9,t0z=10,tz1=11,t1z=12,tz0=13
specparamt0x=11,tx1=14,t1x=12,tx0=10,txz=8,tzx=9
 specparamt0x=11,tx1=14,t1x=12,tx0=10,txz=8,tzx=9
(a=>q)=(t01,t10,t0z,tz1,t1z,tz0,t0x,tx1,t1x,tx0,txz,tzx)
VerilogFAQ 7)TellmeaboutInverilogdelaymodeling?

SynthesisFAQ DistributedDelay
DigitalFAQ
Distributeddelayisdelayassignedtoeachgateinamodule.Anexamplecircuitisshownbelow.
TimingFAQ

ASICFAQ

CmosFAQ

MiscFAQ

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Figure1:Distributeddelay

AscanbeseenfromFigure1,eachoftheorgatesinthecircuitabovehasadelayassignedtoit:

gate1hasadelayof4

gate2hasadelayof6

gate3hasadelayof3

Whentheinputofanygatechange,theoutputofthegatechangesafterthedelayvaluespecified.

Thegatefunctionanddelay,forexampleforgate1,canbedescribedinthefollowingmanner:

or#4a1(e,a,b)

Adelayof4isassignedtotheorgate.Thismeansthattheoutputofthegate,e,isdelayedby4fromtheinputsa
andb.

ThemoduleexplainingFigure1canbeoftwoforms:

1)
Moduleor_circ(out,a,b,c,d)
outputout
inputa,b,c,d
wiree,f
//Delaydistributedtoeachgate
or#4a1(e,a,b)
or#6a2(f,c,d)
or#3a3(out,e,f)
endmodule
2)
Moduleor_circ(out,a,b,c,d)
outputout
inputa,b,c,d
wiree,f
//Delaydistributedtoeachexpression
assign#4e=a&b
assign#6e=c&d
assign#3e=e&f
endmodule
Version1modelsthecircuitbyassigningdelayvaluestoindividualgates,whileversion2usedelayvaluesin
 Version1modelsthecircuitbyassigningdelayvaluestoindividualgates,whileversion2usedelayvaluesin
individualassignstatements.(Anassignstatementallowsustodescribeacombinationallogicfunctionwithout
regardtoitsactualstructuralimplementation.Thismeansthattheassignstatementdoesnotcontainanymodules
VerilogFAQ withportconnections.)

Theaboveor_circmodulesresultsindelaysof(4+3)=7and(6+3)=9forthe4connectionspartfromtheinputto
SynthesisFAQ theoutputofthecircuit.
DigitalFAQ
TimingFAQ
LumpedDelay
ASICFAQ
Lumpeddelayisdelayassignedasasingledelayineachmodule,mostlytotheoutputgateofthemodule.The
cumulativedelayofallpathsislumpedatonelocation.Thefigurebelowisanexampleoflumpeddelay.This
CmosFAQ figureissimilarasthefigureofthedistributeddelay,butwiththesumdelayofthelongestpathassignedtothe
outputgate:(delayofgate2+delayofgate3)=9.
MiscFAQ

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Figure2:Lumpeddelay

AscanbeseenfromFigure2,gate3hasgotadelayof9.Whentheinputofthisgatechanges,theoutputofthe
gatechangesafterthedelayvaluespecified.

TheprogramcorrespondingtoFigure2,isverysimilartotheonefordistributeddelay.Thedifferenceisthatonly
orgate3hasgotadelayassignedtoit:

1)
Moduleor_circ(out,a,b,c,d)
outputout
inputa,b,c,d
wiree,f
ora1(e,a,b)
ora2(f,c,d)
or#9a3(out,e,f)//delayonlyontheoutputgate
endmodule

Thismodelcanbeusedifdelaybetweendifferentinputsisnotrequired.

PintoPinDelay

PintoPindelay,alsocalledpathdelay,isdelayassignedtopathsfromeachinputtoeachoutput.Anexample
circuitisshownbelow.

pathaeout,delay=7
pathbeout,delay=7
 pathbeout,delay=7
pathcfout,delay=9
pathdfout,delay=9
VerilogFAQ Figure3:PintoPindelay

Thetotaldelayfromeachinputtoeachoutputisgiven.Thesameexamplecircuitasforthedistributedand
SynthesisFAQ lumpeddelaymodelisused.Thismeansthatthesumdelayfromeachinputtoeachoutputisthesame.
DigitalFAQ Themodulefortheabovecircuitisshownbeneath:
TimingFAQ Moduleor_circ(out,a,b,c,d)
outputout
ASICFAQ inputa,b,c,d
wiree,f
CmosFAQ //Blocksspecifiedwithpathdelay
specify
MiscFAQ (a=>out)=7
(b=>out)=7
Home (c=>out)=9
(d=>out)=9
endspecify
//gatecalculations
ora1(e,a,b)
ora2(f,c,d)
ora3(out,e,f)
endmodule

Pathdelaysofamodulearespecifiedincideaspecifyblock,asseenfromtheexampleabove.Anexampleof
delayfromtheinput,a,totheoutput,out,iswrittenas(a=>out)=delay,wheredelaysetsthedelaybetweenthe
twoports.Thegatecalculationsaredoneafterthepathdelaysaredefined.

Forlargercircuits,thepintopindelaycanbeeasiertomodelthandistributeddelay.Thisisbecausethe
designerwritingdelaymodels,needstoknowonlytheinput/outputpinsofthemodule,ratherthantheinternals
ofthemodule.Thepathdelaysfordigitalcircuitscanbefoundthroughdifferentsimulationprograms,forinstance
SPICE.PintoPindelaysforstandardpartscanbefoundfromdatabooks.Byusingthepathdelaymodel,the
programspeedwillincrease.

8)Tellsomethingaboutdelaymodelingtimingchecks?

DelayModeling:TimingChecks.

Keywords:$setup,$hold,$width

Thissection,thefinalpartofthedelaymodelingchapter,discussessomeofthevarioussystemtasksthatexistfor
thepurposesoftimingchecks.Verilogcontainsmanytimingchecksystemtasks,butonlythethreemostcommon
tasksarediscussedhere:$setup,$holdand$width.Timingchecksareusedtoverifythattimingconstraintsare
upheld,andareespeciallyimportantinthesimulationofhighspeedsequentialcircuitssuchasmicroprocessors.
Alltimingchecksmustbecontainedwithinspecifyblocksasshownintheexamplebelow.

The$setupand$holdtasksareusedtomonitorthesetupandholdconstraintsduringthesimulationofa
sequentialcircuitelement.Intheexample,thesetuptimeistheminimumallowedtimebetweenachangeinthe
inputdandapositiveclockedge.Similarly,theholdtimeistheminimumallowedtimebetweenapositiveclock
edgeandachangeintheinputd.

The$widthtaskisusedtochecktheminimumwidthofapositiveornegativegoingpulse.Intheexample,thisis
thetimebetweenanegativetransitionandthetransitionbackto1.

Syntax:

NB:data_change,referenceandreference1mustbedeclaredwires.
$setup(data_change,reference,time_limit)
 $setup(data_change,reference,time_limit)

data_change:signalthatischeckedagainstthereference
VerilogFAQ
reference:signalusedasreference
SynthesisFAQ time_limit:minimumtimerequiredbetweenthetwoevents.

DigitalFAQ Violationif:TreferenceTdata_change<time_limit.

TimingFAQ
$hold(reference,data_change,time_limit)
ASICFAQ
reference:signalusedasreference
CmosFAQ data_change:signalthatischeckedagainstthereference
MiscFAQ time_limit:minimumtimerequiredbetweenthetwoevents.

Home Violationif:Tdata_changeTreference<time_limit

$width(reference1,time_limit)

reference1:firsttransitionofsignal

time_limit:minimumtimerequiredbetweentransition1andtransition2.

Violationif:Treference2Treference1<time_limit

Example:

moduled_type(q,clk,d)
outputq
inputclk,d

regq

always@(posedgeclk)
q=d

endmodule//d_type

modulestimulus

regclk,d
wireq,clk2,d2

d_typedt_test(q,clk,d)

assignd2=d
assignclk2=clk

initial
begin
$display("\t\tclockdq")
$display($time,"%b%b%b",clk,d,q)
clk=0
d=1
#7d=0
#7d=1//causessetupviolation
 #7d=1//causessetupviolation
#3d=0
VerilogFAQ #5d=1//causesholdviolation

SynthesisFAQ #2d=0
#1d=1//causeswidthviolation
DigitalFAQ
end//initialbegin
TimingFAQ

ASICFAQ initial

CmosFAQ #26$finish

MiscFAQ
always
Home
#3clk=~clk

always
#1$display($time,"%b%b%b",clk,d,q)

specify
$setup(d2,posedgeclk2,2)
$hold(posedgeclk2,d2,2)
$width(negedged2,2)
endspecify
endmodule//stimulus

Output:

clockdq
0xxx
101x
201x
311x
4111
5111
6011
7001
8001
9101
10100
11100
12000
13000
14010
15110

"timechecks.v",46:Timingviolationinstimulus
$setup(d2:14,posedgeclk2:15,2)

16111

17101
 18001
VerilogFAQ 19001

SynthesisFAQ 20001
21101
DigitalFAQ
22110
TimingFAQ

ASICFAQ
"timechecks.v",47:Timingviolationinstimulus

CmosFAQ $hold(posedgeclk2:21,d2:22,2)

MiscFAQ
23110
Home
24000
25010

"timechecks.v",48:Timingviolationinstimulus
$width(negedged2:24,:25,2)

9)Drawa2:1muxusingswitchesandverilogcodeforit?

1bit21Multiplexer

Thiscircuitassignstheoutputouttoeitherinputsin1orin2dependingontheloworhighvaluesofctrl
respectively.

//Switchleveldescriptionofa1bit21multiplexer
//ctrl=0,out=in1ctrl=1,out=in2

modulemux21_sw(out,ctrl,in1,in2)

outputout//muxoutput
inputctrl,in1,in2//muxinputs
wirew//internalwire

inv_swI1(w,ctrl)//instantiateinvertermodule

cmosC1(out,in1,w,ctrl)//instantiatecmosswitches

cmosC2(out,in2,ctrl,w)

VerilogFAQ endmodule

SynthesisFAQ Aninverterisrequiredinthemultiplexercircuit,whichisinstantiatedfromthepreviouslydefinedmodule.

DigitalFAQ Twotransmissiongates,ofinstancenamesC1andC2,areimplementedwiththecmosstatement,intheformat
cmos[instancename]([output],[input],[nmosgate],[pmosgate]).Again,theinstancenameisoptional.
TimingFAQ
10)Whatarethesynthesizablegatelevelconstructs?
ASICFAQ

CmosFAQ

MiscFAQ

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Theabovetablegivesallthegatelevelconstructsofonlytheconstructsinfirsttwocolumnsaresynthesizable.

VLSI&ASICDigitaldesigninterviewquestions