Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High

Temperature Stability for 32nm and Beyond

P. Sivasubramani, P. D. Kirsch, J. Huang, C. Park, Y. N. Tan, D. C. Gilmer, C. Young, K. Freeman,

M. M. Hussain, bR. Harris, S. C. Song, D. Heh, R. Choi, cp_ Majhi, G. Bersuker, P. Lysaght, B .H.
1 1 1
Lee, H.-H. Tseng, J. S. Jur, D. J. Lichtenwalner, A. I. Kingon, and aR. Jammy

SEMATECH 2706 Montopolis Drive, Austin, TX 78741, U.S.A., "IBM, b AMD, 0 lntel e-mail: paulkirsch ematech.org
1
Dept. of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina 27695

Abstract Experimental

We demonstrate an amorphous higher-k (k>20) and maintain acceptably thin interfacial SiOx=0.7nm realizing
HITiSiON gate dielectric for sub 32nm node capable of low a scaling benefit to EOT=0.84nm and an I n-I rr benefit. The
0 0

equivalent oxide thickness (EOT=0.84nm). For the first time, initial reliability results suggest equivalence to the HfSiON
we have addressed the thermodynamic instability of TiOr control. This result is significant because it may represent a
containing gate dielectrics achieving an acceptably thin SiOx material evolution extending EOT scaling beyond the current
interface (0.7nm) after 1070C. 3-lOx leakage current HfSiON or m-HfO2 whose maximum k-20.
reduction is achieved with HITiSiON vs. HfSiON due to a
higher-k TiO2 cap (k=40) on HfSiON. For the first time, an 8%
I n-I rr improvement of HITiSiON vs. HfSiON is
0 0

demonstrated. HITiSiON shows I n=l3 00 A/m at

0

l rr= lO0n A/m for Vdd=l.2V without stress engineering.

0

HITiSiON shows bias temperature instability (PBTI) and time

dependent dielectric breakdown (TDDB) similar to HfSiON.
This work is significant because it demonstrates higher-k
scaling benefit and extension of high-k beyond Hf-oxides for
sub-32nm technologies.

Introduction

Higher-k gate dielectrics (k>20) may be necessary for sub

32 nm node to continue equivalent oxide thickness (EOT)
scaling <0.9 nm (Fig.la). Higher-k materials should be
amorphous, stable with Si and have k 40 to justify complexity
and to achieve EOT<0.9nm. Thermodynamic stability of
higher-k materials, such as Ta2O5, is challenging because they
may release O to Si due to smaller IAH /mol O vs. SiO 2
(Fig. lb). This O release forms thick (2nm) bottom interface
SiOx that severely limits scaling. For TiO 2, no stable tie line
exists between Si and TiO2 (in contrast to Si-ZrO2) , suggesting
that a Si-TiO2 interface is unstable (Figs. 2a, b) [l].
Experiments on HITaO [2], HITiO [3-5] and HITaTiO [6]
confirm that interface SiOx grows uncontrollably as proven by
TEM and EOT (1.2-2.0nm). Low EOT results have been
reported with HITiO but only up to 900C [7], suggesting that
kinetics with TiO2 may be controlled. Although TiO 2 is of
questionable stability, it is a desirable higher-k due to
symmetric band offsets [8] and k-80 (Fig. 1, 3). For the first
time, we place HITiSiON into a flow including 1070C-spike

1-4244-0439-X/07/$25.00 2007 IEEE 1

 Hf-based dielectrics were formed by atomic layer
deposition (ALD) [9]. TiO2 caps were formed with molecular
beam deposition. Post treatments include plasma nitridation,
thermal nitridation and post anneals. ALD or physical vapor
deposition was used to form metal gates. nMOSFETs were
fabricated with a gate first process (1070C-spike dopant
17 3
activation) and channel doping - 6xl0 cm- . EOT is
extracted using the North Carolina State University CVC
model and mobility is extracted with the mob2d model.
Grazing angle Fourier transform infrared spectroscopy (FTIR)
using a Ge hemispherical attenuated total reflectance (ATR)
crystal is utilized to understand interface issues. Positive bias
instability measurements are done on 10x0.5m nFETs at
125C with a stress voltage of Vg=V 1+1.4V. Time dependent
dielectric breakdown (TDDB) is done on 10x0.3m nFETs
with a stress voltage of 3.8V.
Material Design and Low-k SiOx Interface Control
Fig. 4 illustrates the historical difficulty in controlling the
bottom SiOx thickness for TaOx or TiOx doped HfO2. Both
dielectrics in Fig. 4 are grown on similar surfaces and see
1000C-5s, but SiOx is clearly thicker with HITaTiO. To
1-4244-0439-X/07/$25.00 2007 IEEE
understand this SiOx formation, an FTIR study of HfSiON,
HITiSiON and HfLaSiON on Si was done with the
expectation that dopant type would influence SiOx thickness
and composition. Fig. 5 shows the following results: the O-Si
O phonon mode attenuates and shifts to lower wave number
because La consumes bottom SiOx forming La-Si-O.
Conversely, the O-Si-O phonon mode intensifies and shifts to
larger wave numbers because Ti doping speeds SiOx growth,
but does not form Ti-Si-O. Both Figs. 4 and 5 show that TiOx
doping increases the interfacial SiOx thickness in the absence
of special stack engineering. Therefore, HITiSiON
EOT=0.8nm will require careful interface and TiO2
processing.
Backside SIMS results (Fig. 6) show that TiO2 is placed
at the top surface of HfSiON keeping the unstable higher-k
remote from the Si channel. Therefore we benefit from higher
k TiO2 without the penalty of interfacial SiOx growth. Fig. 7
compares CV data for optimized vs. non-optimized HITiSiON
and shows that EOT improves significantly (-0.5nm) when
the bottom interface is controlled, leveraging the higher-k.
Evidence for the higher-k is shown in Fig. 8 where the k-value
of TiO2 cap is approximately 40. HRTEM for optimized and
2
non-optimized HITiSiON shows that significant improvement
can be made at the SiOx bottom interface (Fig. 9). These TEM
results explain, in part, the CV results in Fig. 7. The TEM
result shows that the interface thickness increases -0.6nm
closely matching the -0.5nm EOT increase observed
electrically in Fig. 7. Therefore, by optimizing the integration
of the TiO2, to control the low-k interface layer growth, the
benefit of a material of k-40 can be realized. Current density
data in Fig. 10 are consistent with k=40, reducing leakage
current 3-lOx vs. HfSiON. Unfortunately, the conduction band
offset of TiO2 is - leV (vs. l.5eV for HfO 2) [7,8] and may
limit the amount of leakage current reduction that is possible
even in a fully optimized stack. Nevertheless, this small
leakage current benefit may enable the sub 0.8nm EOT
necessary for 32nm node and beyond.
Device Results
Mobility data in Fig. 11 illustrate that similar mobility can often near 2 nm (TEM thickness); in the present work, we
be achieved with HITiSiON and HfSiON. For the most
aggressively scaled stack (EOT=0.84nm), 76% Univ. SiO 2
(@l MV/cm) is achieved, without the use of strain 1070C to achieve good scaling (EOT=0.84nm) and I n-I
HfTiSiON, it is still found to be amorphous as estimated by
TEM. Maintenance of the amorphous phase has been
correlated with improved PBTI [10].
Fig. 18 shows similar TDDB distributions for the
HfSiON control and TiO2 containing dielectric. The
HfTiSiON TDDB distribution may show small improvement
(narrower distribution) as a result of the TiO2 capping. This
difference may be attributed to the increased Tphys of
HfTiSiON vs. control HfSiON. From the TEM results shown
in Fig. 19, the HITiSiON has Tphys-2nm, whereas the control
HfSiON has Tphys-l.6nm. Table 1 summarizes relevant
parameters for higher-k dielectrics. The majority of attempts
to utilize the higher-k TaOx and TiOx dielectrics have not
yielded results below EOT= 1 nm with the exception of ref [7]
where a relaxed thermal budget (900C) was used. The
limiting factor for this aggressive scaling is likely the
formation of a thick low-k interface layer (SiOx) Table 1
shows that the low-k interface layer in previous reports is
have controlled the interface thickness to 0.7nm even after
0 0

engineering. As expected, HITiSiON Vt roll-off curves (Fig. rr results.

12) are similar to control HfSiON, suggesting any short
channel effects will be similar for both dielectrics. Both stacks Conclusions
shown in Fig. 12 include the same midgap metal gate
electrode and no attempt was made to tune the Vt as We demonstrate a higher-k HITiSiON gate dielectric
previously demonstrated in [12]. material for sub 32nm node capable of low equivalent oxide
The transistor output characteristics are shown in Figs. 13 thickness (EOT=0.84nm). For the first time, we have
and 14 for the 0.08m devices. I n - I rr improvement of 8%
is observed with HITiSiON vs. an HfSiON (EOT=0.9lnm) addressed the thermodynamic instability of TiOrcontaining
0 0

control (Fig. 15). Some of this drive current improvement can dielectrics and formed an acceptably thin interface SiOx
be attributed to EOT scaling to 0.84nm. Additionally, we (0.7nm) after 1070C. I n-I rr improvement of 8% is achieved
0 0

speculate that the physically thicker HITiSiON may mediate a with HITiSiON vs. HfSiON to I n=l3 00 A/m 0
scattering mechanism by placing the high-k/metal interface
further from the Si channel. Simulations have shown that at I rr= lO0n A/m for Vdd=l.2V without stress engineering.
0

mobility may depend on the proximity of the electrode to the This demonstration is significant because it illustrates EOT-
inversion layer for SiO2/PolySi gate stack [13]. Therefore a 0.8nm with a higher-k material (k-40). This material may
physically thicker dielectric may reduce the effect of that enable gate stack scaling beyond HfO 2 (k-20) for sub 32nm
mechanism. Fig. 16 compares charge pumping interface trap
density (Nit) for HfSiON and HITiSiON. The interface quality node high performance logic technologies.
can be tuned in such a way to achieve results similar to the
HfSiON control. All charge pumping Nit results are similar References
2
and near mid E10/cm
.

[l] G.D. Wilk, R. M. Wallace and J.M. Anthony J. Appl. Phys. 89, p. 5243
Reliability Results (2001).
[2] X. Yu, C. Zhu, M. Yu, M. F. Li, A. Chin, C. H. Tung, D. Gui, and D.-L.
KwongIEDMTechDig. p. 31 (2005).
Initial HITiSiON positive bias temperature instability [3] T. Ma et al. IEEE Trans. Electron Dev. 48, p. 2348 (2001).
(PBTI) and time dependent dielectric breakdown (TDDB) [4] M. Li, Z. Zhang, S. A. Campbell, W. L. Gladfelter, M. P. Agustin, D. 0.
results are shown in Fig. 17 and Fig. 18 respectively. In both Klenov, S. Stemmer J. Appl. Phys. 98 p. 054506 (2005).
[5] D. Triyoso et al. Proc. AVS-ALD (2005).
cases, the results are similar to HfSiON. PBTI results in Fig.[6] N. Lu, H.-J. Li, M. Gardner, S. Wickramanayaka, D.-L. Kwong IEEE
17 show that HfSiON and HfTiSiON can be identical (open Electron Dev. Lett. 26 p. 298 (2005).
circle vs. open triangle), suggesting that TiO2 inclusion is [7] S. J. Rhee et al. IEDM Tech Dig. p. 837 (2004).
unlikely to present an intrinsic bulk charge trapping issue. [8] J. Robertson J. Vac. Sci & Tech.B 18 p.1785 (2000).
Despite the increased physical thickness (Tphys) of the [9] P. D. Kirsch et al. J. Appl. Phys. 99 p. 023508 (2006).
[10] M.A. Quevedo et al. IEDM Tech Dig. p. 437 (2005).

3
[11] S. Datta et al. IEDM Tech Dig. p. 653 (2003). [12] H. A!Shareef et al. Symp. VLSI Tech. p. 10 (2006).
[13] J. Li and T.-P. MaJ. Appl. Phys. 62, p.4212 (1987).

4
 (a) high-k = (20) 40 0 6
4

AEC 3.5
> 2
-2:!. 1.2 .o.o 1.5
0>, 0.3 - 0.1 ito 1.0
...
C)
a,
1.1
1.2
wC: -2 3.0
2.3 1.1

AEv no2 to 2.2 3.4

SrTiO3 BaTiO3
EOT = (0.89) 0.69 4.4
-4
nm HfO

(b) Material s;o2 Ta20

2
-AH, Si 5
(a - Amorphous -6
K-value (KJ!mol of
c - Crystalline) Oxygen)
SiO2 3.9 455 Figure 3. Valence / conduction band offsets of
a-Hf0 2 -20 556.5 higher-k materials with respect to Si compared
to HfO2 and SiO2. TiO2 t.E, is more favorable
a-La2O3 -25 598
compared to BTO/STO/Ta 2O5. (from Ref. [7-8])
c-LaAIO3 -27 -
c-Ta2O5 -25-45 409.2 10-----------
o Hf
c-TiO2 -so 472 u 101 -:--:-Ti
Zr ZrSi ZrSi2 Si
c-SrTiO3 -300 -
c-BaTiO3 >300 -
Figure 2. Ternary phase diagram of Me-O-Si 3: -------MG
where Me=Ti in (a) and Me=Zr in (b). Hf-O-Si
-;; 102
phase diagram expected to be similar to ZrO 2. "I:
Stable tie line for TiO2-Si does not exist, as in the
case of ZrO2-Si. (Reused with permission from
5 10 3

4
G. 10
Figure 1. (a) Scaling limit of 2nm a-HfO 2 (k-20) is
-0.89 nm assuming SiOx interface layer. Higher-k
D. Wilk, Journal of Applied Physics, 89 5243 iii
with EOT<0.19 nm required for <32 nm node
(2001). Copyright 2001, American Institute of 105 +-- - - - - -
Physics.) 0 2 4 6 8 10 12 14
assuming same SiOx interface (EOT=0.5nm). (b)
Stability of higher-k with Si is questionable Depth (nm)
because lt.H,l/mol O is similar to SiO2. --+-- HfTiSiON + 1070C 10
HfLaSiON + 1070C
--D- (b) o Hf
1
--o- HfSiON + 1070C u 10 -+-Ti
0.06 Qj
U) ----- MG
-;; 102
"I:
u 0.04
Qj
5 103
..c 10-4
5
U)
0.02 iii
..c
<(

1200 1100 1000

105 4 6 8 10 12 14
0 2 Depth (nm)
1300 Wavenumber (per cm)

Figure 5. FTIR shows TiOx does not mix with

Figure 4. Historical issue with TaOx /TiOxon Si
- growth of thick interfacial SiO2 (BIL). 2nm
SiO2 under HfTaTiO (left) but just 1 nm under
conventional HfO2 (right). Both after 1000C-5s
processing.
BIL as for LaOx. Note difference in Me-O-Si
1
intensity 1100 cm1 . O-Si-O intensity/peak
position (-1240 cm- ) is largest for TiO2 case
suggesting growth of BIL in this unoptimized
stack. (LO = longitudinal-optical stretch)
Figure 6. Backside SIMS of TiO 2 capped
stacks indicates intermixing with HfSiON.
(a) thin TiO2 cap (b) thick TiO2 cap. MG =
metal gate.

3.5
HmSiON (EOT=0.84nm)
E 3.0
N
0 HfSiON (EOT=0.91nm)
-HmSiON (EOT=1.3nm)
10
.!:!
LL 2.5
2:
2.0
a,
u I- 9
C: 1.5 0
.l w x 1/(slope) -40
1.0 8 k=3.9
!
u NFET 20x20m
2
! 100kHz- 5 die 7
cuC . 0 5 10 15 20
c u 0.5
u
0.0
-1.5 -1.0 -0.5 0.0 0.5 1.0
Voltage (V) Nominal TiO2 TPh ys (A)
Figure 7. Good CVT and EOT=0.84 nm
 Fig ure k-value extraction indicates an Figure 9. Control of bottom interface layer
8.
obtained for optimized HfTiSiON. For approximate value of 40 for the TiOx cap, (BIL) has been achieved for HfTiSiON by
comparison, non-optimized HfTiSiON and suggesting that a scaling benefit can be expected. re-engineering stacks.
HfSiON are shown.

N 10
4 3 0.6 ------------
E

r+
"J
3
5

1
102
10 0
0.5
3 4' HfTiSiON EOT=0.84nm
0

0
HfTiSiON (EOT 0.84 nm) HfSiON (EOT 0.91 nm)

.-..
ii,
250 t:, HfTiSiON
0 (EOT 0.98 nm) 0 HfSiON EOT=0.91nm
10 1 +o,,z,.
i *SiONIPoly
-Universal Si0 2

J E
200
0.
4 -tr SiONIPolySi EOT=1.6nm
10

.
2

,0,
ii 100
C
..
1:
::- 10 HfTiSiON 150 0.3
HfSiON '
. ..a ,
0 Hf0 2
00
0

:!!: 0.2
10
u::::, 10
50
3

2 10 .. +- 0 W=10m
0.0 0.5 1.0 0.1+-- -- -- -
-- 1.5 ----.-'
, Electric Field 0 02 0.4 0 0 1
0.7 0.8 0.9 1.0 1.1 1.2 1.3 (MVlcm)
1.4 Gate Length (m)
EOT (nm) Figure 11. High field electron mobility for Figure 12. HfTiSiON V, roll-off for gate
HfTiSiON is similar to HfSiON. 76% high- lengths down to Lg=0.08m. For
field mobility (1 MVlcm) achieved for comparison, data for HfSiON and
Figure 10. Scaling relationship indicates HfTiSiON at EOT=0.84 nm. SiONIPoly from SiONln-PolySi is included.
a Ref. [11].
3 -10x J9 benefit for HfTiSiON higher-k stacks
compared to HfSiON trend. HfTiSiON (EOT 0.84 nm)
1800
6 HfTiSiON(EOT 0.98 nm)
HfTiSiON
1600(EOT 0.84 nm) o HfSiON (EOT 0.91 nm)
V 9- V, o HfSiON control
4
10 10
e
1400
NFET 10 x 0.08 m

..
3 Vdd= 1.2V

e CU>---
10 1.0V

-'
1200
<i:
E 10
2

-=-
i..:!, ;t 1000 0.75V 6 60
800
"'
1
M
10 +eo
+o
+eo Vds=0.05,1.2V
..:!,
_-c 600 0.5V _o

10
C: 10
1
+ eO L = 0.08 m
::::s +eo g
0
u 10 +o 4 o.ov
2
+ HfTiSiON (EOT = 0.84 nm) 0
0
0.1

- 10 o HfSiON (EOT = 0.91 nm)

2
C: ' 0
0

0
10-4 0.5 1.0 2. 2. 0 200 400 600 800 1000 1200
0
0.5 1.0 2. 0. 1.5 0 5
0.0 1.5 0 0 Ion (A/m)
Vd 5 (Volts)
Gate Voltage
(V)

Figure 14. Reasonable ld-Vd Figure 15. 100 - 10 ,r improves by - 8%

Figure 13. ld-V 9 for 10 x 0.08 m devices characteristics and Id enhancement for for - 0.1nm EOT scaling of HfTiSiON
indicates comparable subthreshold slope HfTiSiON short channel devices gatestack.
for relative to HfSiON control.
HfTiSiON vs. HfSiON control.

10 E 2
u 6
-0
HfTiSiON' (EOT=0.88 nm) HfTiSiON (EOT=0.98 nm)
4 HfSiON (EOT=0.91 nm)
8 X

z
 1
2
0
><l
HfTiSiO
N' 40
HfTiSiO 1 20
N 0
0
0
8 10 100
0 1000

>E
60
- PBTI Stress condition: V9-V,.= 1.4 V
Temp.= 125C
NMOSFET 10 m x 0.3 mo
Stress:V,-V"=31'8V j>
+

HfSiON + HfTiSiON (EOT 0.84 nm) 1 10 100

1000
EOT=0.86 nm
o HfSiON (EOT 0.91 nm) 80
Gate Stack t:, HfTiSiON (EOT 0.98 nm) [50
Time Time (sec)
00 ,
(sec) 0 0+

:i -2 EOT=0.84 nm
c,,o"'o

-")

+ + HfTiSiON

Higher-k EOT(nm) Max Temp. (C) Low-k )Interface Morphology Reference
Figure 16. Charge pumping N;, data for HfTiSiON Figure 17. PBTI of!,) c,, c,,
HfTiSiON is -3 (nm)
Figure
Tohvs o HfSiONdielectric
18. Time dependent
stacks is comparable to HfSiON control and less comparablec,,to( that
1',.
of HfSiON control
2
than 5E10 cm . HfTaO 1.6 after 1000s 1000,1050 breakdown-2 for HfTiSiONT"TT"rl
is
a similar to HfSiON
[2]
device (-30-40 mV) at
of -4+-
similar EOT. Fewer early fails for
125C.
Ti0 2 1.6 800 -
HfTiSiON may be due ale [3]
to physically thicker
HfTiO -1.5 (CET) 900 dielectric stack.
-1 - 2 C [5]
HfTaTiO 1.1 to2.1 700,900 1.6 ale [6]
Table 1. Summary
HfTiO -0.8of higher-k dielectric
900 parameters- a [7]
HfTiSiON -0.8 1070 0.7 a This work

Figure 19. HfTiSiON HRTEM after 1070C *a - amorphous, c - crystalline

showing successful control of 0.7nm SiOx
BIL and -2nm HfTiSiON.