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BUREAU DEUDE EN ELECTRONIQUE EMBARQUE

PLAN

PARTIEI : LES GPIO

*les registres

* interface des gpio

* exemple

PARTIEII : LES TIMERS

*les registres

* interface des TIMERS

* Etape de configuration des timers (ENABLE TIM, ENABLE CLOCK ETC..)

* exemple

PARTIE II.1 : APPLICATION DES TIMERS (LES PWMS)

PARTIE II.2 : ROTATION DE DEUX SERVO_MOTEURS

PARTIE VI : LES ADC

*les registres DES ADCS

* interface des ADC

* Etape de configuration des ADCS (ENABLE TIM, ENABLE CLOCK ETC..)

* exemple

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PARTIE VII : LUSART

*les registres DE lUSART

* interface de lUSART

* Etape de configuration des USART (ENABLE TIM, ENABLE CLOCK ETC..)

* exemple1 : Emission et rception

* exemple2 : Emission des valeurs des ADCS et rception

PROJET GLOBALE

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Typedef struct

{
Typedef struct
Typedef struct
uint32_t registre1;
{
{
uint16_t registre2;
uint32_t registre1; Typedef struct
uint32_t registre1;
uint16_t registre3;
uint16_t registre2; {
uint16_t registre2;
} I2S_struct_name
uint16_t registre3; uint32_t registre1;
uint16_t registre3;
} USART_struct_name uint16_t registre2;
} DAC_struct_name
I2S uint16_t registre3;

Typedef struct
USART GPIO uint32_t registre4;

{ DAC } GPIO_struct_name

uint32_t registre1;
Typedef struct
uint16_t registre2;
{
uint16_t registreN;
STM32F4
ADC I2C
uint32_t registre1;
} ADC_struct_name
uint16_t registre2;

Typedef struct uint16_t registre3;

} I2C_struct_name
{ SPI
uint32_t registre1;
TIMER CAN
Typedef struct
uint16_t registre2; Typedef struct {
uint16_t registreN;
{ uint32_t registre1;
} TIMER_struct_name
uint32_t registre1; uint16_t registre2;

uint16_t registre2; uint16_t registre3;

uint16_t registre3; } SPI_struct_name

} CAN_struct_name 5
Prenons titre dexemple la structure de configuration de lhorloge (The Clock Configuration Register : RCC)

typedef struct (LINE 729 line 759)


{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved, 0x3C */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
uint32_t RESERVED4; /*!< Reserved, 0x5C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
__IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
} RCC_TypeDef;

Remarque: Cette structure contient un ensemble de registres dont laccs direct se fait via un pointeur intitul RCC

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#define RCC ((RCC_TypeDef *) RCC_BASE) LINE 1186 (du fichier STM32F4xx.h)

Chaque registre est cod sur 4 octets (32 bits) ou sur 2 octets (16 bits ). Laccs direct chaque registre de la RAM se fait via un pointeur.
Chaque registre est considr comme un tableau 16 ou 32 cases mmoires (chaque bit est une case mmoire). Chaque registre est une srie de
4 ou 2 octets dont chaquun (octet) lui correspond une seule et unique adresse dans la RAM. Ladresse dun registre est ladresse du premier
octet de ce registre. Par exemple, le registre RCC_CR contient 4 octets ayant les adresses suivantes : 0X42003800, 0X42003801, 0X42003802,
0X42003803

Adresse du pointeur RCC

#define RCC ((RCC_TypeDef *) RCC_BASE) Chaque registre appartenant a la structure


est dfinie par une adresse dans la RAM du
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) microcontrleur
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)

#define PERIPH_BASE ((uint32_t)0x40000000)

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Chaque interface du microcontrleur est un circuit dont le fonctionnement dpendra de la position des switchers. Chaque switcher est pilot par
un bit appartenant un registre bien dtermin. Ces registres appartiennent la RAM du microcontrleur.

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Ce principe est le mme pour nimporte quelle interface du microcontrleur : ADC, DAC, TIMER, I2C,SPI, etc

Vcc

Register_clock_enable : bit_N Register for ADC_ON: bit_N

Clock

Enable ADC ADC_OUTPUT

PIN

Register for Alternate funtiion : bit_N


GND

Register for ADC_enable : bit_N

Opration logique :
BITWISE AND :

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BITWISE OR

BITWISE XOR

BITWISE NOT

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BIT SHIFT OPERATORS

Assignment Operators
x = x + 7 equivalent x += 7
x = x | 3 equivalent x |= 3
x = x & 7 equivalent x &= 7

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Programmation ARM
Prenons le cas dune structure contenant lensemble dun Convertisseur ADC. La manipulation de ses registres se fait via un pointeur intitul
pt_ADC. Parmi ces registres choisissons le registreSR et le registre DR.
If((pt_ADC->SR&0x02)==0)
{
Pt_ADC->DR=a;
}
Programmation classique
If(SR&0x02==0)
{
DR=a;
}

for(int i=0;i<20;i++)
{
Pt_ADC->DR+=1;
}
Programmation classique
for(int i=0;i<20;i++)
{
DR+=1;
}

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Ajouter dautre exemple while()

Corps dun programme


Dclarations Variable ;

Dclarations tableaux ;

Dfinitions des diffrentes fonctions de configuration


void Fonction_de_configuration1() ;
{
}
void Fonction_de_configuration2() ;
{
}
void Fonction_de_configuration3() ;
{
}

int main(void)
{

Fonction_de_configuration1() ;
Fonction_de_configuration2() ;
Fonction_de_configuration3() ;

While(1)
{
Droulement_systeme() ;
}

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STM32F407 Clocks
1. Introduction

Figure: Basic clock circuitry for the STM32F407 ARM processor.

The STM32F407 micro-controller is capable of interfacing to a large range of peripheral devices or sub-systems. These peripherals all have different
protocols and requirements. To satisfy the clock requirements for these peripheral devices the STM32F407 includes a very flexible clocking
arrangement.

Following reset the High Speed Internal Clock (HSI) will be selected. By default this clock will also be the clock to the AHB (Advanced High Speed
Bus), and the peripheral buses APBx (Advanced Peripheral Bus).

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In contrast to many microcontrollers that have peripherals or subsystems where the clock signals are continuously active, to conserve power the
STM32F407 does not. It will therefore be the responsibility of the programmer to enable the clock to those subsystems and if necessary generate the
appropriate bus frequencies. It will be necessary to understand the requirements of the chosen peripherals as part of configuring the micro-controller
clock circuitry.

This page will review :

Setting the system clock: That is select HSI, HSE or the PLL as the system clock.
Setting the prescalers to provide the required bus frequencies.

2. The system clock

The STM32F407 microcontroller system clock can come from one of three sources:

1. The high speed internal clock (HSI)


2. The high speed external clock(HSE)
3. The phase locked loop (PLL) clock.

The clock control register RCC_CR will be used to enable and select the clock source while the clock configuration register RCC_CFGR will be used to
determine the final bus frequencies

Conclusion:

RCC_CR register will be used to enable and select the clock source

RCC_CFGR register will be used to determine the final bus frequencies

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Notes:

The ARM also includes a low speed internal clock (LSI) and low speed external clock (LSE).
The LSI clock is used as part of the watch dog timer.
The LSE is used as a clock for the ARM real time clock (RTC)
The input to the PLL will be either HSI or HSE
For the STM32F407 used in the Discovery board HSI = 16MHz.
For the STM32F407 used in the Discovery board HSE = 8MHz.

Clock Control Register: RCC_CR

The clock source is determined by the registers RCC_CR and RCC_CFGR shown below. At reset for both the STM32F107 and STM32F407 the CR (Control
Register) is 0x0000 XX83. The "3" indicates the internal 16 MHz RC oscillator (HSI) is enabled and stable. The HSE and PLL are not enabled.

Figure: STM32F407xx clock control register RCC_CR

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The Clock Configuration Register: RCC_CFG

Following reset the CFGR (Configuration Register) is cleared indicating the HSI (Low Speed Internal Clock) is selected. ie RCC_CFGR:SW[1:0] = 00

SW= 00 HSI Clock selected (default value following reset). SW =01 HSE selected. SW = 10 PLL selected. SW=11 Not allowed.

3. Using the external clock HSE

After reset the internal clock (HSI) is enabled. To use the external clock it must be enabled using bit 16 in the control register and then the firmware must wait
until the hardware indicates it is ready (stable). Possible code will be:

Figure: Enabling HSE as the system clock

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Note: The SWS bits in the CFGR may be monitored to confirm which clock is being used.

4.Using the STM32F407 Phase Locked Loop

A simplified diagram of the PLL for the STM32F407 is given below.

Figure: Basic circuit of the PLL circuitry for the STM32F407

Note: The STM32F407 contains a second similar PLL for the I2S (PLLI2S)

The clock source for the PLL is set using the PLLSRC bit while the PLL frequency is set by programming the PLLM, PLLN and PLLP bits in the phase lock
loop configuration register (RCC_PLLCFGR). (Reset value: 0x2400 3010)

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This register is used to configure the PLL clock output according to the formulas:

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Notes:

Reserved bits must be kept at their entry value.


PLL bits can be written only if PLL is disabled.
VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
VCO output frequency must be in range 192 to 432 MHz.
The PLL clock must not exceed 168 MHz.

5. The STM32F407 bus clock prescalers.

As illustrated the three bus signals (AHB, APB1 and APB2) are derived from the system clock as illustrated (Figure repeated for convenience).

Figure: Basic clock circuitry for the ARM processor.

The frequencies are determined by programming the configuration register (RCC_CFGR). (Figure repeated for convenience)

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SW= 00 HSI Clock selected (default value following reset). SW =01 HSE selected. SW = 10 PLL selected. SW=11 Not allowed.

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STM32F407 Example: Assuming that the peripheral buses are to operate at their maximum frequency then with a system clock of 168 Mhz the APB1
pre-scaler must divide the clock output of the high performance bus (HCLK) by 4. The code will be:

RCC->CFGR |= 5<<10; // set APB1 = 42 MHz

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6. Peripheral Clocks for the STM Microcontrollers

With the STM devices the peripheral devices are associated with an internal buse. (APB1 and APB2). To use the the peripheral device it must be
enabled/attached to the appropriate bus. The user has the choice of setting the frequency of the individual buses. When using a peripheral device the user will
need to

1. enable the clock to the peripheral device


2. enable the clock to the GPIO that is used by the peripheral device (ie an Alternate Function (AF))

The basic clock circuitry for the ARM microcontroller is shown below.

Figure: Basic clock circuitry for the ARM microcontroller.

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6.1.STM32F407 Peripheral Clock Enables

With the STM32F407 as illustrated below the peripheral clock is associated with AHB1, APB1 or APB2. (Advanced High speed Bus 1, Advanced Peripheral
Bus 1 or Advanced Peripheral Bus 2):

Figure: STM32F407 AHB1 high speed bus clock enable register (RCC_AHB1ENR)

Figure: STM32F407 APB1 peripheral clock enable register (RCC_APB1ENR)

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Figure: STM32F407 APB2 peripheral clock enable register (RCC_APB2ENR)

6.2. Resetting the Peripheral Clock Enable Registers


The peripheral clock enabled is controlled using two registers

1. The enable register presented in the previous section. To enable a clock a bit in the enable register is set. Clearing the bit will not result in any
action.
2. The reset register where setting a bit will clear the chosen clock. The reset registers are a set of registers that correspond to the enable
registers. (RCC_AHB1RSTR, RCC_APB1RSTR and RCC_APB2RSTR)

The circuitry is illustrated in the diagram below. To enable a clock the corresponding bit in the enable register is set while to reset/disable the same bit in the
reset register is set.

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FIGURE: ARCHITECTURE OF THE STM32F407 CLOCK

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Figure: REGISTERS OF THE GLOBAL STM32F407 CLOCK

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LES GPIOS

I. Prsentation
Le microcontrleur STM32F407 dispose de 9 ports dentres/sorties (dnomms GPIOA GPIOI), partags avec dautres priphriques. A chaque port I/O
est associ quatre registres de configuration 32 bits (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR et GPIOx_PUPDR), deux registres de donnes
32bits (GPIOx_IDR and GPIOx_ODR), un register de 32bits set/reset (GPIOx_BSRR), un registre 32bits de verrouillage (GPIOx_LCKR) et deux registres 32
bits pour les fonctions secondaire (Alternate function) (GPIOx_AFRH and GPIOx_AFRL).

II. Basic structure of a 5V tolent I/O port bit

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III. Input floating/pull up/Pull down configurations

I/O port is programmed as Input:

the output buffer is disabled


the Schmitt trigger input is activated
the pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
A read access to the input data register provides the I/O State

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IV. OUTPUT CONFIGURATION

I/O port is programmed as output:

The output buffer is enabled:


o Open drain mode: A 0 in the Output register activates the N-MOS whereas a 1 in the Output register leaves the port in Hi-Z (the P-MOS is
never activated)
o Push-pull mode: A 0 in the Output register activates the N-MOS whereas a 1 in the Output register activates the P-MOS
o Open drain / Push-pull
The Schmitt trigger input is activated
The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
A read access to the input data register gets the I/O state
A read access to the output data register gets the last written value

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V. ALTERNATE FUNCTION CONFIGURATION

as alternate function:

The output buffer can be configured as open-drain or push-pull


The output buffer is driven by the signal coming from the peripheral (transmitter enable and data)
The Schmitt trigger input is activated
The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
A read access to the input data register gets the I/O state

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VI. ANALOG CONGIGURATION

as analog configuration:

The output buffer is disabled


The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is
forced to a constant value (0).
The weak pull-up and pull-down resistors are disabled
Read access to the input data register gets the value 0

Note: In the analog configuration, the I/O pins cannot be 5 Volt tolerant. - analog operating voltage (VDDA) max at 3.6V

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VII. GLOBAL GPIO CONFIGURATION (ALL CASES)

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LES REGISTRES DE CONFIGURATIONS DUN GPIO :

Les diffrents registres utiliss pour configurer un GPIO sont regroups dans la structure ci-dessous intitule GPIO_TypeDef
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;

Chacun des 9 GPIO ( GPIOA GPIOI) utilise la mme structure mais avec des pointeurs diffrents :
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

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LES REGISTRES

GPIO port mode register (GPIOx_MODER) (x = A..I)

MODERy[1:0]: Port x configuration bits (y = 0..15)


These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

GPIO port output type register (GPIOx_OTYPER) (x = A..I)

Bits 31:16 Reserved, must be kept at reset value.


Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the output type of the I/O port.
0: Output push-pull (reset state)
1: Output open-drain

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GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I)

OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)


These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed

GPIO port pull-up/pull-down register (GPIOx_PUPDR)(x = A..I)

PUPDRy[1:0]: Port x configuration bits (y = 0..15)


These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

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GPIO port input data register (GPIOx_IDR) (x = A..I)

Bits 31:16 Reserved, must be kept at reset value.


Bits 15:0 IDRy: Port input data (y = 0..15)
These bits are read-only . They contain the input value of the corresponding I/O port.

GPIO port output data register (GPIOx_ODR) (x = A..I)

Bits 31:16 Reserved, must be kept at reset value.


Bits 15:0 ODRy: Port output data (y = 0..15). These bits can be read and written by software.

GPIO port bit set/reset register (GPIOx_BSRR) (x = A..I)

Bits 31:16 BRy: Port x reset bit y (y = 0..15)


These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.

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0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only and can be accessed in word, half-word or byte mode. A read to
these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit

GPIO alternate function low register (GPIOx_AFRL) (x = A..I)

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Thus part of configuring GPIOD will be the code:

GPIOD->AFR[0] |= (7<< 20); //enable USART2 Tx to PD5


GPIOD->AFR[0] |= (7<< 24); //enable USART2 Rx to PD6

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Thus part of configuring GPIOB will be the code:

GPIOB->AFR[0] |= (4<< 24); //enable SCK to PB6


GPIOB->AFR[1] |= (4<< 4); //enable SDA to PB9

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Thus part of configuring GPIOA will be the code:

GPIOA->AFR[0] |= (5<< 20); //enable SPI CLK to PA5


GPIOA->AFR[0] |= (5<< 24); //enable MISO to PA6
GPIOA->AFR[0] |= (5<< 28); //enable MOSI to PA7

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PULL_UP /PULL_DOWN:

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APPLICATIONS

Application 1: Commande de 4 leds via un bouton poussoir

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#include "stm32f4xx.h"
void System_Init()
{
RCC->AHB1ENR = 0x00000001; //clock to GPIOA
RCC->AHB1ENR |= 1<<3; //Clocks for GPIOD

GPIOD->MODER = 0x55000000; //Bits 12..15 are output


GPIOD->PUPDR = 0x55555555; //ACTIVATE PULL_UP for PORTD

GPIOA->MODER = 0x00000000; //Bits 0..15 are input


GPIOA->PUPDR = 0x22222222; //ACTIVATE PULL_DOWN for PORTA

}
int main (void)
{
System_Init();

while (1)
{
if (GPIOA->IDR & 0x0001)
{
GPIOD->ODR = 0xF000; //turn LEDs on
}
else
{
GPIOD->ODR = 0; //LEDs off
}
}
}

Dboguer le programme ci-dessus et vrifier le contenu des registres suivants : AHB1ENR appartenant la structure RCC_TypeDef, (MODER ,PUPDR
ODR et IDR)appartenant la structure GPIO_TypeDef

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APPLICATION 2: Clignotement de 4 leds (PD12, PD13, PD14, PD15)

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#include "stm32f4xx.h"

void Delay(__IO uint32_t nCount)


{
while(nCount--)
{}
}
Void cofiguration()
{

RCC->AHB1ENR = 1<<3; //Clocks for GPIOD


GPIOD->MODER = 0x55<<24; //Bits 12..15 are output
GPIOD->PUPDR = 0x55555555; //ACTIVATE PULL_UP for PORTD

}
int main (void)
{
cofiguration();
while (1)
{
GPIOD->ODR = 0xF000; //4 LEDs (PD12 PD13 PD14 PD15) : on
Delay(0xFFFFF);
GPIOD->ODR = 0x0000; //4 LEDs (PD12 PD13 PD14 PD15) : off
Delay(0xFFFFF);
}
}

Dboguer le programme ci-dessus et vrifier le contenu des registres suivants : AHB1ENR appartenant la structure RCC_TypeDef, (MODER ,PUPDR
ODR)appartenant la structure GPIO_TypeDef

48
Application 3: Registre dcalage 8 bits

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#include "stm32f4xx.h"

__IO uint32_t i;
void Delay(__IO uint32_t nCount)
{
while(nCount--)
{}
}
void configuration()
{

RCC->AHB1ENR = 1<<3; //Clocks for GPIOD


GPIOD->MODER = 0x55555555; //PORTD: PINs 0 15 are configured as output
GPIOD->PUPDR = 0x55555555; //ACTIVATE PULL_UP for PORTD
}
int main (void)
{
configuration();
while (1)
{
for(i=0;i<256;i++)
{
GPIOD->ODR+=1;
Delay(0xFFFFF);
if(i==255)
{
i=0;
}
}
}
}

Dboguer le programme ci-dessus et vrifier le contenu des registres suivants : AHB1ENR appartenant la structure RCC_TypeDef, (MODER ,PUPDR
ODR)appartenant la structure GPIO_TypeDef

50
APPLICATION 4 : Dcalage droite et gauche progressif

But : Lclairage progressif des 7 leds (une fois droite et une fois gauche) par mise en uvre du BITSHIFT <<

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#include "stm32f4xx.h"

__IO uint32_t i;
void Delay(__IO uint32_t nCount)
{
while(nCount--)
{}
}
void configuration()
{

RCC->AHB1ENR = 1<<3; //Clocks for GPIOD


GPIOD->MODER = 0x55555555; //PORTD: PINs 0 15 are configured as output
GPIOD->PUPDR=0x55555555; //Actvate pull-up for each pin 0=> 15

}
int main (void)
{
configuration();
while (1)
{
for(i=0;i<8;i++)
{
GPIOD->ODR=1<<i;
Delay(0xFFFFF);
}

for(i=6;i>0;i--)
{
GPIOD->ODR=1<<i;
Delay(0xFFFFF);
}
}
}

Dboguer le programme ci-dessus et vrifier le contenu des registres suivants : AHB1ENR appartenant la structure RCC_TypeDef, (MODER ,PUPDR
ODR)appartenant la structure GPIO_TypeDef

52
Application 5: Principe de masquage
But :
Le but principal de cette application est la manipulation de toutes les oprations logiques en embarqu (BITWISE NOT, BIT SHIFT, BITWISE
AND, BITWISE OR, Assignment Operators)
Ralisation :
Soit le montage suivant

53
#include "stm32f4xx.h"

__IO uint32_t i;
void Delay(__IO uint32_t nCount)
{
while(nCount--);
}
void configuration()
{
RCC->AHB1ENR = 1<<3; //Clocks for GPIOD
GPIOD->MODER = 0x55555555; //PORTD: PINs 0 15 are configured as output
GPIOD->PUPDR=0x55555555; //Actvate pull-up for each pin 0=> 15
}

int main (void)


{
configuration();
while (1)
{
GPIOD->ODR=0x00000000;
Delay(0xFFFFF);
GPIOD->ODR|=0xF0;
Delay(0xFFFFF);
GPIOD->ODR&=0x00;
Delay(0xFFFFF);
GPIOD->ODR|=0x0F;
Delay(0xFFFFF);
GPIOD->ODR&=0x0E;
Delay(0xFFFFF);
GPIOD->ODR&=0x0C;
Delay(0xFFFFF);
GPIOD->ODR&=0x08;
Delay(0xFFFFF);
GPIOD->ODR&=0x0;
Delay(0xFFFFF);
GPIOD->ODR=~0x00000000;
Delay(0xFFFFF);
}
}

Dboguer le programme ci-dessus et vrifier le contenu des registres suivants : AHB1ENR appartenant la structure RCC_TypeDef, MODER
appartenant la structure GPIO_Typedef et PUPDR appartenant la structure GPIO_TypeDef

54
APPLICATION 6 : MISE EN UVRE DES RESISTANCES DE PULL-UP ET PULL-DOWN( INPUT)

Ralisation : Soit le montage suivant

Dans cette application, on va activer les rsistances internes PULL_DOWN correspondant au PORTC ainsi que les rsistances internes
PULL_UP correspondant au PORTD

55
#include "stm32f4xx.h"

__IO uint32_t i;
void Delay(__IO uint32_t nCount)
{
while(nCount--);
}
void configuration()
{
RCC->AHB1ENR = 1<<3; //Clocks for GPIOD
RCC->AHB1ENR|=0x4; // Clocks for GPIOC

GPIOD->MODER = 0x55555555; //PORTD: PINs 0 15 are configured as output


GPIOD->PUPDR=0x55555555; //Actvate pull-up for each pin 0=> 15
GPIOD->OSPEEDR=0xFFFFFFFF; //GPIOD:EACH PIN Very high speed (The register OSPEEDER is configured only when the PORT is
//configured as output

GPIOC->MODER = 0x00000000; //PORTC: PINs 0 15 are configured as input


GPIOC->PUPDR=0x22222222; // Activate pull-down for each pin 0=> 15

}
int main (void)
{
configuration();
while (1)
{

if((GPIOC->IDR&0x4)==0x4)
{
GPIOD->ODR=0xF000;
Delay(0xFFFFF);
}
else
{
GPIOD->ODR=0x000;
}

56
GPIOD->ODR=0x0000;
Delay(0xFFFFF);
GPIOD->ODR|=0xF0;
Delay(0xFFFFF);
GPIOD->ODR&=0x00;
Delay(0xFFFFF);
GPIOD->ODR|=0x0F;
Delay(0xFFFFF);
GPIOD->ODR&=0xE;
Delay(0xFFFFF);
GPIOD->ODR&=0xC;
Delay(0xFFFFF);
GPIOD->ODR&=0x8;
Delay(0xFFFFF);
GPIOD->ODR&=0x0;
Delay(0xFFFFF);
GPIOD->ODR=0x00FF;
Delay(0xFFFFF);

}
}

57
INTERRUPTION EXTERNE SUR LES GPIO

typedef struct
{
__IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
__IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;

#define EXTI ((EXTI_TypeDef *) EXTI_BASE)

typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
} SYSCFG_TypeDef;

#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

58
SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

59
SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

60
SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

61
SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

62
Interrupt mask register (EXTI_IMR)

63
Event mask register (EXTI_EMR)

64
Rising trigger selection register (EXTI_RTSR)

65
Falling trigger selection register (EXTI_FTSR)

66
Software interrupt event register (EXTI_SWIER)

67
Pending register (EXTI_PR)

68
69
LE TIMER (compteur)

Principe
*Le but principal dun TIMER est de raliser une temporisation. Un Compteur s'incrmente chaque front montant du signal qui lui est applique.

Lorsque le compteur dpasse la valeur maximale qu'il peut contenir (dborde) (par exemple : 256 pour un compteur 8 bits), un drapeau (flag en anglais) se
lve.

Ce drapeau a pour but d'indiquer au programme que le compteur a dbord (c'est a dire qu'il a fini de compter).
De la mme manire que pour la boite aux lettres, c'est au programme de rebaisser le drapeau pour recommencer un cycle de comptage (ca ne se fait pas tout
seul !).

* Un Timer doit pouvoir compter un temps dfini par le programme (par exemple 1ms, 10ms, 50ms, etc).
Pour cela, 2 paramtres peuvent tre modifies :
* La frquence du signal applique au compteur Le compteur s'incrmentera ainsi plus ou moins vite.
*Le nombre d'impulsions compter
Remarque : on peut donc faire dbuter le compteur d'une valeur non nulle pour rduire le temps de comptage.
La frquence du signal appliqu au compteur peut tre modifie via un pr-diviseur (prescaler en anglais) plac en amont du signal source

70
Exemple : pour compter 4 fois moins vite

Les TIMERs dun STM32F4 :


Un STM32F4 possde 14 TIMERS dont les caractristiques sont illustrs dans le tableau ci-dessous :

71
STM32F4 timers

72
Le timer est compos de :
- Contrleur de dclenchement
- Un prdivisuer (Prescaler : PSC)
- Un compteur 16 bits (CNT)
- Un registre dauto-rechargement (AutoReload Register :ARR)
- Un module capture/Comparaison
Le prdiviseur divise la frquence dentre par une valeur comprise entre 1 et 65536. Le compteur sincrmente jusquau continu du registre
ARR ; repasse zro et gnre un vnement de mise jour (Update Event : UEV) et positionne le bit UIF.

LES REGISTRES DE CONFIGURATIONS DUN TIMER :

Les diffrents registres utiliss pour configurer nimporte quel TIMER sont regroups dans la structure ci-dessous intitule TIM_TypeDef

typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */

73
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED11; /*!< Reserved, 0x46 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
uint16_t RESERVED13; /*!< Reserved, 0x4E */
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;

Chacun des 14 TIMERS ( TIM1 TIM14) utilise la mme structure mais avec des pointeurs diffrents :
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)

74
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)

Voice titre dexemple quelque registres utiliss par les TIMERS

TIMx_PSC : prescaler

TIMx_ARR : auto-reload register

TIMx_CR1 : control register 1

Bits 15:8 Reserved, must be kept at reset value.


Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.

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Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM: One-pulse mode


0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS: Update request source


This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS: Update disable


This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set
or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable


0: Counter disabled
1: Counter enabled
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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TIMx_SR: status register

Bits 15:1 Reserved, must be kept at reset value.


Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
and UDIS = 0 in the TIMx_CR1 register.

TIMx_EGR : event generation register

Bits 15:1 Reserved, must be kept at reset value.


Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.

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1: Re-initializes the timer counter and generates an update of the registers.

TIMx_CNT : counter

TIMx_DIER : DMA/Interrupt enable register ( en cas de vouloir configur une interruption)

Bits 15:9 Reserved, must be kept at reset value.


Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

78
La notion dinterruption
Pour simplifier la comprhension dune interruption jai choisi larchitecture adapte par un microcontrleur PIC

79
La lever automatique du drapeau peut tre exploit de 2 manires :

Soit on lexploite pour raliser une tache lintrieur du programme principal (main) (UIE=0 quivalent TIMx->DIER = 0x00000).

80
81
Soit on lexploite pour raliser une interruption lextrieur du programme principal (main) (UIE=1 quivalent TIMx->DIER = 0x0001).

Remarque : Quand le timer dborde ARR 0x00 le flag se met automatiquement 1 (UIF=1). Ce flag restera toujours 1 tant quil nest pas
remis 0 (softwarement parlant).

82
Count-up mode overflow if TIMx_CNT reaches TIMx_ARR
On overflow event, UIF flag is set and TIMx_CNT resets to 0.
If UIE= 1 (update interrupt enabled), interrupt signal is sent to NVIC

83
84
Application :
Dans ces applications on aura recours aux registres suivant :

RCC_AHB1ENR

GPIOx_MODER

MODERy[1:0]: Port x configuration bits (y = 0..15)


These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

85
RCC_APB1ENR

APPLICATION 1: INTERRUPTION REPETETIVE

#include "stm32f4xx.h"
#include "stm32f4xx_gpio.h"

#define PLL_M 8
#define PLL_N 336
#define PLL_P 2
#define PLL_Q 7

void Delay(__IO uint32_t nCount)


{
while(nCount--)
{}
}

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

86
}

void clock_config1()
{

// PLL (clocked by HSE) used as System clock source.


// Enable HSE and wait until it is read.
RCC->CR|=RCC_CR_HSEON;
while(!(RCC->CR&RCC_CR_HSERDY));

RCC->CFGR|=RCC_CFGR_HPRE_DIV1; // HCLK = SYSCLK / 1


RCC->CFGR|=RCC_CFGR_PPRE2_DIV2; // PCLK2 = HCLK / 2
RCC->CFGR|=RCC_CFGR_PPRE1_DIV4; // PCLK1 = HCLK / 4
// Configure the main PLL.
RCC->PLLCFGR=PLL_M|(PLL_N<<6)|(((PLL_P>>1)-1)<<16)|(RCC_PLLCFGR_PLLSRC_HSE);
// Enable the main PLL and wait until it is ready.
RCC->CR|=RCC_CR_PLLON;
while((RCC->CR&RCC_CR_PLLRDY)==0);
// Configure Flash prefetch, Instruction cache, Data cache and wait state
FLASH->ACR=FLASH_ACR_ICEN|FLASH_ACR_DCEN|FLASH_ACR_LATENCY_5WS;
// Select the main PLL as system clock source.

RCC->CFGR|=RCC_CFGR_SW_PLL;
// Wait until the main PLL is used as system clock source.
while((RCC->CFGR&RCC_CFGR_SWS)!=RCC_CFGR_SWS_PLL);
}

int main()
{

clock_config();
RCC->AHB1ENR |= 0x00000008; // Enable GPIOD clock
GPIOD->MODER |= 0x55<<24; //Bits 12..15 are output
RCC->APB1ENR |= 0x00000010; // Enable TIM6 clock
TIM6->PSC = 41999; // Set prescaler to 41999

87
TIM6->ARR = 5999; // Set auto-reload to 5999
TIM6->CR1 &=0x0000; // Multiple pulse mode TIM6->CR1 &=~TIM_CR1_OPM;
TIM6->EGR |= 0x01; // Force update
TIM6->SR &= 0x0000; // Clear the update flag
TIM6->DIER |= 0x0001; // Enable interrupt on update event
NVIC_EnableIRQ(TIM6_DAC_IRQn); // Enable TIM6 IRQ
TIM6->CR1 |= 0x0001; // Enable TIM6 counter
while(1)
{

GPIOD->ODR |= 0x7000; //turn LEDs on


Delay(0xFFFFF);
GPIOD->ODR &= ~0x7000; //LEDs off
Delay(0xFFFFF);

}
}

void TIM6_DAC_IRQHandler()
{
if((TIM6->SR & 0x0001) != 0)// If update flag is set
{
GPIOD->ODR |= 0x8000; // Set D15 high
Delay(0xFFFFF);
GPIOD->ODR &= 0x0;
}

TIM6->SR &= 0x0000; // Interrupt has been handled


}

APPLICATION2 : Clignotement dune LED par lusage dinterruption dun TIMER TIM6

#include "stm32f4xx.h"

int ncount1;

88
void Delay(__IO uint32_t nCount)
{
while(nCount--)
{}
}

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

int main()
{

clock_config();
RCC->AHB1ENR |= 0x00000008; // Enable GPIOD clock
GPIOD->MODER |= 0x55<<24; //Bits 12..15 are output
RCC->APB1ENR |= 0x00000010; // Enable TIM6 clock
TIM6->PSC = 41999; // Set prescaler to 41999
TIM6->ARR = 59; // Set auto-reload to 5999
TIM6->CR1 &=0x0000; // Multiple pulse mode TIM6->CR1 &=~TIM_CR1_OPM;
TIM6->EGR |= 0x01; // Force update
TIM6->SR = 0x0000; // Clear the update flag
TIM6->DIER |= 0x0001; // Enable interrupt on update event
NVIC_EnableIRQ(TIM6_DAC_IRQn); // Enable TIM6 IRQ
TIM6->CR1 |= 0x0001; // Enable TIM6 counter
while(1)
{

}
}

void TIM6_DAC_IRQHandler()
{

89
if((TIM6->SR & 0x0001) != 0)// If update flag is set
{
ncount1++;
if(ncount1==1)
{
GPIOD->ODR |= 0x8000; // Set D15 high
}
if(ncount1==2)
{
GPIOD->ODR &= 0x0; // Set D15 high
ncount1=0;
}
}

TIM6->SR &= 0x0000; // Interrupt has been handled


}

90
APPLICATION 3: Machine dtat avec mise en jeu dinterruption

91
#include "stm32f4xx.h"

int ncount1;

void Delay(__IO uint32_t nCount)


{
while(nCount--)
{}
}

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock

92
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready
}

int main()
{

clock_config(); // Frequence source est HSE

RCC->AHB1ENR |= 0x00000008; // Enable GPIOD clock


GPIOD->MODER |= 0x55<<24; // PD12 PD13 PD14 PD15 are output

RCC->APB1ENR |= 0x00000010; // Enable TIM6 clock

TIM6->CR1= 0x0001; // Enable TIM6 counter


TIM6->PSC = 41999; // Set prescaler to 41999 Freq_TIMER= Freq_HSE/41999
TIM6->ARR = 59; // Set auto-reload to 59 Periode_update_event= (1/Freq_TIMER) x ARR

TIM6->EGR |= 0x01; // Force update


TIM6->DIER |= 0x0001; // Enable interrupt on update event
TIM6->SR = 0x0000; // Clear the update flag (UIF=0)
NVIC_EnableIRQ(TIM6_DAC_IRQn); // Enable TIM6 IRQ

while(1)
{

}
}

void TIM6_DAC_IRQHandler()
{
if((TIM6->SR & 0x0001) != 0)// If update flag is set
{
ncount1++;
if(ncount1==1)
{
GPIOD->ODR |= 0x8000; // Set D15 high

93
}
if(ncount1==2)
{
GPIOD->ODR = 0x4000; // Set D14 high

}
if(ncount1==3)
{
GPIOD->ODR = 0x2000; // Set D13 high
}
if(ncount1==4)
{
GPIOD->ODR = 0x1000; // Set D12 high
}
if(ncount1==5)
{
GPIOD->ODR = 0x0000; // Set D15 high
ncount1=0;
}
}

TIM6->SR &= 0x0000; // Interrupt has been handled


}

94
APPLICATION4 : Machine dtat avec mise en jeu du FLAG (sans interruption)

95
#include "stm32f4xx.h"

int ncount1;

void Delay(__IO uint32_t nCount)


{
while(nCount--)
{}
}

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on

96
while (!(RCC->CR & (1<<17))); //wait until HSE ready

int main()
{

clock_config(); //Freq_source=HSE
RCC->AHB1ENR = 0x00000008; // Enable GPIOD clock
GPIOD->MODER = 0x55<<24; // PD12 PD13 PD14 PD15 are output
RCC->APB1ENR = 0x00000010; // Enable TIM6 clock
TIM6->PSC = 41999; // Set prescaler to 41999 Freq_TIMER=HSE/41999
TIM6->ARR = 59; // Set auto-reload to 59 Periode_TIMER= (1/Freq_TIMER)x59
TIM6->SR = 0x0000; // Clear the update flag (UIF=0)
TIM6->DIER = 0x0000; // Disable interrupt
TIM6->CR1= 0x0001; // Enable TIM6 counter
while(1)
{
if((TIM6->SR & 0x0001) != 0)// If update flag is set (UIF=1)
{
ncount1++;
if(ncount1==1)
{
GPIOD->ODR |= 0x8000; // Set D15 high
}
if(ncount1==2)
{
GPIOD->ODR = 0x4000; // Set D14 high

}
if(ncount1==3)
{
GPIOD->ODR = 0x2000; // Set D13 high
}
if(ncount1==4)
{
GPIOD->ODR = 0x1000; // Set D12 high

97
}
if(ncount1==5)
{
GPIOD->ODR = 0x0000; // Set D15 high
ncount1=0;
}
TIM6->SR &= 0x0000; // Interrupt has been handled (UIF=0)
}

}
}

Remarque: Le dclenchement du FLAG est en liaison directe avec UDIS, URS UG (par exemple si UDIS=1 UIF=0 meme si le compteur
dborde)

La table ci-dessous, montre lensemble des PINs quon peut attribuer chaque TIMER caractris aussi par 4 chaines aux choix . On peut
slectionner 3 pins aux grand maximun pour chaque chaine.

98
99
100
LA MODULATION LARGEUR IMPULSION

STM32F4 Timer Peripherals:

Advanced Control Timer


TIM1 and TIM8
Input capture, output compare, PWM, one pulse mode
16-bit auto-reload register
Additional control for driving motor or other devices

General Purpose Timer


TIM2 to TIM5
Input capture, output compare, PWM, one pulse mode
16-bit or 32-bit auto-reload register

General Purpose Timer


TIM9 to TIM14
Input capture, output compare, PWM, one pulse mode
Only 16-bit auto-reload register

Basic Timer (Simple timer)


TIM6 and TIM7
Can be generic counter and internally connected to DAC
16-bit auto reload register

Pour gnrer un signal PWM on pourra utiliser 12 TIMERS


Pour la gnration dun pwm on a opt au TIMER 3 caractris par la structure suivante :

typedef struct
{

101
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED11; /*!< Reserved, 0x46 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
uint16_t RESERVED13; /*!< Reserved, 0x4E */
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;

102
Cette structure contient lensemble des registres qui nous permettra de configurer ce TIMER. La manipulation de ces registres se fait via un
pointeur intitul TIM3 (#define TIM3 ((TIM_TypeDef *) TIM3_BASE)

Chaque PWM est engendr par un TIMER. En mode PWM, le priode est dfinie par le contenu du registre TIMx_ARR et le rapport cyclique
par le contenu du registre TIMx_CCR1. La sortie du comparateur OC1REF est mise au niveau haut lorsque le continu du compteur est infrieur
au continu du comparateur TIMx_CNT < TIMx_CCR1, et place au niveau bas dans le cas contraire

103
Applications de la MLI :
Dans ces applications on aura recours aux registres suivant :

RCC_AHB1ENR

RCC_APB1ENR

104
GPIOx_MODER

MODERy[1:0]: Port x configuration bits (y = 0..15)


These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

105
GPIO alternate function low register (GPIOx_AFRL) (x = A..I)

TIMx capture/compare mode register 1 (TIMx_CCMR1) : Pour les chaines 1 et 2


The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS
bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is
configured in output, ICxx describes its function when the channel is configured in input. Take care that the same bit can have a
different meaning for the input stage and for the output stage.

106
Output compare mode
Bit 15 OC2CE: Output compare 2 clear enable

Bits 14:12 OC2M[2:0]: Output compare 2 mode

Bit 11 OC2PE: Output compare 2 preload enable

Bit 10 OC2FE: Output compare 2 fast enable

Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection


This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

Bit 7 OC1CE: Output compare 1 clear enable


OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

Bits 6:4 OC1M: Output compare 1 mode


These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level
depends on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a
timing base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode
to PWM mode.

Bit 3 OC1PE: Output compare 1 preload enable


0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

107
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).
2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE: Output compare 1 fast enable


This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger
input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0 CC1S: Capture/Compare 1 selection


This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

Input capture mode


Bits 15:12 IC2F: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler

Bits 9:8 CC2S: Capture/compare 2 selection


This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:

0000: No filter, sampling is done at fDTS


0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8

108
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8

Bits 3:2 IC1PSC: Input capture 1 prescaler


This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events

Bits 1:0 CC1S: Capture/Compare 1 selection


This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

TIMx capture/compare mode register 2 (TIMx_CCMR2) : Pour les chaines 3 et 4

Output compare mode

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M: Output compare 4 mode

109
Bit 11 OC4PE: Output compare 4 preload enable

Bit 10 OC4FE: Output compare 4 fast enable

Bits 9:8 CC4S: Capture/Compare 4 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

Bit 7 OC3CE: Output compare 3 clear enable

Bits 6:4 OC3M: Output compare 3 mode

Bit 3 OC3PE: Output compare 3 preload enable

Bit 2 OC3FE: Output compare 3 fast enable

Bits 1:0 CC3S: Capture/Compare 3 selection

This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

Input capture mode


Bits 15:12 IC4F: Input capture 4 filter
Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).

110
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

TIMx capture/compare enable register (TIMx_CCER)

Bit 15 CC4NP: Capture/Compare 4 output Polarity.


Refer to CC1NP description

Bit 14 Reserved, must be kept at reset value.

Bit 13 CC4P: Capture/Compare 4 output Polarity.


refer to CC1P description

Bit 12 CC4E: Capture/Compare 4 output enable.


refer to CC1E description

Bit 11 CC3NP: Capture/Compare 3 output Polarity.


refer to CC1NP description

Bit 10 Reserved, must be kept at reset value.

Bit 9 CC3P: Capture/Compare 3 output Polarity.


refer to CC1P description

Bit 8 CC3E: Capture/Compare 3 output enable.


refer to CC1E description

Bit 7 CC2NP: Capture/Compare 2 output Polarity.


refer to CC1NP description

111
Bit 6 Reserved, must be kept at reset value.

Bit 5 CC2P: Capture/Compare 2 output Polarity.


refer to CC1P description

Bit 4 CC2E: Capture/Compare 2 output enable.


refer to CC1E description

Bit 3 CC1NP: Capture/Compare 1 output Polarity.


CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CC1P: Capture/Compare 1 output Polarity.


CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.

Bit 0 CC1E: Capture/Compare 1 output enable.


CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled

112
1: Capture enabled

TIMx capture/compare register 1 (TIMx_CCR1)

Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5).
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).

113
TIMx capture/compare register 2 (TIMx_CCR2)

Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5).
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

TIMx capture/compare register 3 (TIMx_CCR3)

Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register
when an update event occurs.

114
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3).

TIMx capture/compare register 4 (TIMx_CCR4)

Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5).
Bits 15:0 CCR4[15:0]: Low Capture/Compare value
1. if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output.
2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):CCR4 is the counter value transferred by the last input capture 4 event (IC4).

Application1 : Gnration dun signal PWM with HSI CLOCK 16MHz and TIMER3 TIM3 : PA6

#include <stm32f4xx.h>

void Config_PWM(void)
{

RCC->APB1ENR = 0x00000002; //clock enable for TIM3


RCC->AHB1ENR = 0x00000001; //clock enable GPIOA
GPIOA->MODER = 0x2000; //Alternative function mode PA6

TIM3->CCMR1 |= 0x60; //PWM mode 1 on TIM3 Channel 1


TIM3->PSC = 1000;
TIM3->ARR = 200;

115
TIM3->CCR1 = 0;
GPIOA->AFR[0] = 0x2000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x01;
TIM3->EGR|=0x02;
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
Config_PWM();
while(1)
{

TIM3->CCR1++;
if(TIM3->CCR1==TIM3->ARR)
{
TIM3->CCR1=0;
}

for(f=0; f<200000; f++);


}
}
******************************************************************************************

116
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).

117
Application 2 : Gnration dun seul signal PWM with HSE CLOCK 8MHz: PA6
#include <stm32f4xx.h>

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

void Config_PWM(void)
{ //port PA6

RCC->APB1ENR |= 0x2; //clock enable for TIM3


RCC->AHB1ENR |= 0x1; //clock enable GPIOA
GPIOA->MODER |= 0x2000; //Alternative function mode PA6

TIM3->CCMR1 |= 0x60; //PWM mode 1 on TIM3 Channel 1


TIM3->PSC = 1000;
TIM3->ARR = 200;
TIM3->CCR1 = 0;
GPIOA->AFR[0] |= 0x2000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x01;
TIM3->EGR|=0x02;
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
Config_PWM();
clock_config();
while(1)
{

118
TIM3->CCR1++;
if(TIM3->CCR1==TIM3->ARR)
{
TIM3->CCR1=0;
}
for(f=0; f<200000; f++);
}
}

*****************************************************************************************************************

Application3 :Gnration de deux signaux PWM signal with HSE CLOCK 8MHz and TIMER3 TIM3 : PA6 and PA7
#include <stm32f4xx.h>

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

void Config_PWM(void)
{

RCC->APB1ENR |= 0x2; //clock enable for TIM3


RCC->AHB1ENR |= 0x1; //clock enable GPIOA
GPIOA->MODER |= 0xA000; //Alternative function mode PA6 and PA7

TIM3->CCMR1 |= 0x7070; //PWM mode 1 on TIM3 Channel 1 & TIM3 Channel 2

TIM3->PSC = 1000;
TIM3->ARR = 200;
TIM3->CCR1 = 0;
TIM3->CCR2 = 0;

119
GPIOA->AFR[0] |= 0x22000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x11; //Enable Capture/Compare 1 output && Enable Capture/Compare 1 output
TIM3->EGR|=0x06; // Capture/compare 1 generation && Capture/compare 2 generation
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
Config_PWM();
clock_config();
while(1)
{

TIM3->CCR1++;
TIM3->CCR2++;
if(TIM3->CCR1==TIM3->ARR && TIM3->CCR2==TIM3->ARR)
{
TIM3->CCR1=0;
TIM3->CCR2=0;
}
for(f=0; f<100000; f++);
}
}

********************************************************************************

Application 4 : Gnration de deux signaux PWM signal with HSI CLOCK 16MHz and TIMER3 TIM3 : PA6 and PA7
#include <stm32f4xx.h>

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

120
}
void Config_PWM(void)
{

RCC->APB1ENR |= 0x2; //clock enable for TIM3


RCC->AHB1ENR |= 0x1; //clock enable GPIOA
GPIOA->MODER |= 0xA000; //Alternative function mode PA6 and PA7
TIM3->CCMR1 |= 0x7070; //PWM mode 1 on TIM3 Channel 1 & TIM3 Channel 2
TIM3->PSC = 1000;
TIM3->ARR = 200;
TIM3->CCR1 = 0;
TIM3->CCR2 = 0;
GPIOA->AFR[0] |= 0x22000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x11; //Enable Capture/Compare 1 output && Enable Capture/Compare 1 output
TIM3->EGR|=0x06; // Capture/compare 1 generation && Capture/compare 2 generation
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
Config_PWM();
//clock_config();
while(1)
{

TIM3->CCR1++;
TIM3->CCR2++;
if(TIM3->CCR1==TIM3->ARR && TIM3->CCR2==TIM3->ARR)
{
TIM3->CCR1=0;
TIM3->CCR2=0;
}
for(f=0; f<100000; f++);
}
}

121
******************************************************************************************

APPLICATION 5: Generation de 4 signaux PWM using HSE clock and TIMER4 TIM4 : PD12 PD13 PD14 PD15
#include "stm32f4xx.h"

void delay(void)
{
volatile uint32_t i;
for (i=1; i <= 0xFFFF; i++);
}
int main()
{
RCC->APB1ENR = 0x00000004; // CLOCK ENABLE FOR TIMER4
RCC->AHB1ENR = 0x00000008; //CLOCK ENABLE FOR GPIOD

GPIOD->MODER = 0xAA000000; // ALTERNATE FUNCTION FOR PD12 PD13 PD14 PD15


GPIOD->AFR[1] = 0x22220000; //ATTRIBUATE THE ALTERNATE TIM4 FUNCTION TO THE 4 PINS PD12 PD13 PD14 PD15

TIM4->CCER = 0x1111;
TIM4->CCMR1=0x6060;

TIM4->CCMR2=0x6060;

TIM4->CR1 = 0x0001;

TIM4->PSC = 1000;
TIM4->ARR = 200;
TIM4->CCR1 = 0;
TIM4->CCR2 = 0;
TIM4->CCR3 = 0;
TIM4->CCR4 = 0;

while(1)

{
volatile int i = 0;

122
for(i = 0; i <= 200 ; i++)
{

TIM4->CCR1 = i;
TIM4->CCR2 = i;
TIM4->CCR3 = i;
TIM4->CCR4 = i;
delay();
}
for(i = 200; i >= 0 ; i--)
{
TIM4->CCR1 = i;
TIM4->CCR2 = i;
TIM4->CCR3 = i;
TIM4->CCR4 = i;

delay();
}

**********************************************************************************************************************

APPLICATION 6: Gnration de 4 signaux PWM using HSE clock and TIMER4 TIM4 : PD12 PD13 PD14 PD15
#include "stm32f4xx.h" // Device header

void delay(void)
{
volatile uint32_t i;
for (i=1; i <= 0xFFFF; i++);
}

123
int main()
{
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN;

GPIOD->MODER = GPIO_MODER_MODER12_1 | GPIO_MODER_MODER13_1 | GPIO_MODER_MODER14_1 | GPIO_MODER_MODER15_1;


GPIOD->AFR[1] = 0x22220000;

TIM4->CCER |= 0x1111;
TIM4->CCMR1|=0x6060;
TIM4->CCMR2|=0x6060;
TIM4->CR1 |= TIM_CR1_CEN;
TIM4->PSC = 1000;
TIM4->ARR = 200;
TIM4->CCR1 = 0;
TIM4->CCR2 = 0;
TIM4->CCR3 = 0;
TIM4->CCR4 = 0;

while(1)

{
volatile int i = 0;
for(i = 0; i <= 200 ; i++)
{
TIM4->CCR1 = i;
TIM4->CCR2 = i;
TIM4->CCR3 = i;
TIM4->CCR4 = i;
delay();
}
for(i = 200; i >= 0 ; i--){
TIM4->CCR1 = i;
TIM4->CCR2 = i;
TIM4->CCR3 = i;
TIM4->CCR4 = i;

124
delay();
}

125
APPLICATION 7 : ROTATION SYNCHRONNE DE 2 SERVO MOTEUR DE -90-> 0 et de 0->90
#include <stm32f4xx.h>

void clock_config() //Si on veut que la source clock soit egale HSE
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

void Config_PWM(void)
{

RCC->APB1ENR |= 0x2; //clock enable for TIM3


RCC->AHB1ENR |= 0x1; //clock enable GPIOA
GPIOA->MODER |= 0xA000; //Alternative function mode PA6 and PA7

TIM3->CCMR1 |= 0x6060; //PWM mode 1 on TIM3 Channel 1 & TIM3 Channel 2

TIM3->PSC = 1000; //Le compteur est pilot par une horologe egale 16.000.000/1000=16000Hz (16KHz)
TIM3->ARR = 320; //la priode du signal PWM doit etre egale 50Hz T(PWM)=ARR x (Source_clk/PSC)=320x(16000000/1000)=50
TIM3->CCR1 = 0;
TIM3->CCR2 = 0;
GPIOA->AFR[0] |= 0x22000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x11; //Enable Capture/Compare 1 output && Enable Capture/Compare 1 output
TIM3->EGR|=0x06; // Capture/compare 1 generation && Capture/compare 2 generation
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
unsigned int i;
Config_PWM();
//clock_config(); //Clock source HSI 16MHz
while(1)

126
{

TIM3->CCR1=10;
TIM3->CCR2=10;
for(i=6;i<=40;i++) //rotation du servo de -90 jusqu 0
{
TIM3->CCR1=i;
TIM3->CCR2=i;
for(f=0; f<200000; f++);
}
for(i=40;i>=6;i--) //rotation du servo de 0 jusqu 90
{
TIM3->CCR1=i;
TIM3->CCR2=i;
for(f=0; f<200000; f++);
}

}
}

127
APPLICATION 8 : ROTATION ASYNCHRONNE DE 2 SERVO MOTEUR DE -90-> 0 et de 0->90

#include <stm32f4xx.h>

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready

void Config_PWM(void)
{

RCC->APB1ENR |= 0x2; //clock enable for TIM3


RCC->AHB1ENR |= 0x1; //clock enable GPIOA
GPIOA->MODER |= 0xA000; //Alternative function mode PA6 and PA7

TIM3->CCMR1 |= 0x6060; //PWM mode 1 on TIM3 Channel 1 & TIM3 Channel 2

TIM3->PSC = 1000;
TIM3->ARR = 320; //TO fix the period T=20ms (50Hz)
TIM3->CCR1 = 0;
TIM3->CCR2 = 0;
GPIOA->AFR[0] |= 0x22000000; //set GPIOA to AF2
TIM3->BDTR|=0xc000;
TIM3->CCER|=0x11; //Enable Capture/Compare 1 output && Enable Capture/Compare 1 output
TIM3->EGR|=0x06; // Capture/compare 1 generation && Capture/compare 2 generation
TIM3->CR1 |= 0x1; //enable timer 3
}

int main(void)
{
unsigned int f;
unsigned int i;
Config_PWM();

128
//clock_config();
while(1)
{

TIM3->CCR1=8;
TIM3->CCR2=8;
for(i=8;i<=40;i++)
{
TIM3->CCR1=i;
for(f=0; f<200000; f++);
}
for(i=40;i>=8;i--)
{
TIM3->CCR1=i;
for(f=0; f<200000; f++);
}

for(i=8;i<=40;i++)
{
TIM3->CCR2=i;
for(f=0; f<200000; f++);
}
for(i=40;i>=8;i--)
{
TIM3->CCR2=i;
for(f=0; f<200000; f++);
}

}
}

129
130
131
LCD STM32F4

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "stm32_ub_lcd_2x16.h"

132
int main(void)
{
__IO uint16_t ADCBuffer;
unsigned long j;
char text[60];
SystemInit();

// Init LC-Display
UB_LCD_2x16_Init();

// Text auf Zeile-1 ausgeben


UB_LCD_2x16_String(0,0,"LCD 2x16 STM32F4");

// Text auf Zeile-2 ausgeben


UB_LCD_2x16_String(1,1,"HELLO");

for(j=0;j<=40000000;j++);

UB_LCD_2x16_Clear();
while(1)
{

for(ADCBuffer=0;ADCBuffer<4096;ADCBuffer++)
{

sprintf (text,"%d",ADCBuffer);
UB_LCD_2x16_String(0,0,"TIMER:");
UB_LCD_2x16_String(7,0,text);
for(j=0;j<=4000000;j++);

}
UB_LCD_2x16_Clear();
}
}

133
ANALOGUE DIGITAL CONVERTER

Introduction
The STM32F4 has 3 ADCs built in. There are 16 multiplexed channels used to connect the ADCs to the processor. 8 of these are connected to
ADC3, while all 16 of the channels are connected to ADC2 and ADC1. Each ADC can convert with a maximum precision of 12bits, meaning
that the output of the ADC will range from 0 to 212-1 or, 0 to 4095. The rest of the article looks at how you can use 1 of these ADCs to read
analog signals from 2 or more channels

CHANNELS ADC1 ADC2 ADC3


IN0 PA0 PA0 PA0
IN1 PA1 PA1 PA1
IN2 PA2 PA2 PA2
IN3 PA3 PA3 PA3
IN4 PA4 PA4 xxxxxxx
IN5 PA5 PA5 xxxxxxx
IN6 PA6 PA6 xxxxxxx
IN7 PA7 PA7 xxxxxxx
IN8 PB0 PB0 xxxxxxx
IN9 PB1 PB1 xxxxxxx
IN10 PC0 PC0 PC0
IN11 PC1 PC1 PC1
IN12 PC2 PC2 PC2
IN13 PC3 PC3 PC3
IN14 PC4 PC4 xxxxxxx
IN15 PC5 PC5 xxxxxxx

134
Figure: ADC BLOCK DIAGRAM

135
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;

#define ADC1 ((ADC_TypeDef *) ADC1_BASE)


#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)

136
REGISTRES:

RCC APB2 peripheral clock enable register (RCC_APB2ENR)

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

137
ADC common control register (ADC_CCR)

ADC control register 2 (ADC_CR2)

138
ADC regular sequence register 3 (ADC_SQR3)

Different Step for conversion

139
APPLICATION: Affichage de lADC outpout sur un LCD( 2x16)

Le but principal consiste afficher sur LCD(2x16) les rsultats de conversions de 2 chaines (ADC1)

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "stm32f4xx.h"
#include "stm32_ub_lcd_2x16.h"

140
/* inputs are PA2 & PA3 -> must be enabled for analog, PA must have clock! */
int main ()
{
unsigned int j;
__IO uint16_t ADCBuffer[2];
char text[60];
SystemInit(); // Quarz Einstellungen aktivieren

/*-----------------------------------------------------------------------------*/
/* Software triggered, dual, simultaneous sampling */
/*-----------------------------------------------------------------------------*/

RCC->APB2ENR |= 0x00000100 + 0x00000200; // Enable clock for ADC1 & ADC2


RCC->AHB1ENR |= 0x00000001 + 0x00000002; // Enable clock for GPIOA & GPIOB
ADC->CCR = 0x00000006; // No DMA, Regular simultaneous mode only

ADC1->CR2 = 0x00000001; // Control Register 2: ADC1 ON


ADC1->SQR3 = 0x00000002; // regular SeQuence Register 3
ADC2->CR2 = 0x00000001; // Control Register 2: ADC2 ON
ADC2->SQR3 = 0x00000003; // regular SeQuence Register 3
GPIOA->MODER |= 0x000000f0; // MODE Register -> PA2, PA3 are analog inputs
UB_LCD_2x16_Init();

UB_LCD_2x16_String(0,0,"TEST ADC");
for (j = 0; j<10000000; j++);
UB_LCD_2x16_Clear();
while (1)
{
ADC1->CR2 |= ADC_CR2_SWSTART; // simultaneous Start Conversion
ADC2->CR2 |= ADC_CR2_SWSTART; // simultaneous Start Conversion
for (j = 0; j<100; j++){}; // wait for conversion to complete
ADCBuffer[0]=ADC1->DR;
ADCBuffer[1]=ADC2->DR;
sprintf (text,"%d %d",ADCBuffer[0],ADCBuffer[1]);
UB_LCD_2x16_String(0,0,text);
for (j = 0; j<1000000; j++);
UB_LCD_2x16_Clear();

141
};
}

USART
#include <stdio.h>
#include "STM32F4xx.h"

char character[30];
int i;

142
/****************************************TEMPO**********************************/
void Delay_TIME(__IO uint32_t nCount)
{
while(nCount--);
}

/*******************************Configuration clock system ********************/


void SystemInit_1()
{

RCC->CFGR |= 0x00009400; // AHB ve APB hizlarini max degerlere set edelim


RCC->CR |= 0x00010000; // HSE Xtal osc calismaya baslasin
while (!(RCC->CR & 0x00020000));// Xtal osc stabil hale gelsin
RCC->PLLCFGR = 0x07402A04; // PLL katsayilarini M=4, N=168, P=2 ve Q=7 yapalim 168 Mhz
RCC->CR |= 0x01000000; // PLL calismaya baslasin (Rehber Sayfa 95)
while(!(RCC->CR & 0x02000000)); // Pll hazir oluncaya kadar bekle
FLASH->ACR = 0x00000605; // Flash ROM icin 5 Wait state secelim ve ART yi aktif edelim (Rehber Sayfa 55)
RCC->CFGR |= 0x00000002; // Sistem Clk u PLL uzerinden besleyelim
while ((RCC->CFGR & 0x0000000F) != 0x0000000A); // Besleninceye kadar bekle

}
/******************GPIO configuration : PD12, PD13, PD14, PD15 USED FOR THE COMMAND**************/

void config_GPIO()
{
RCC->AHB1ENR |= 1<<3; //Clocks for GPIOD
GPIOD->MODER |= 0x55<<24; //Bits 12..15 are output
GPIOD->OSPEEDR= 0xFFFFFFFF; // GPIOD nin tum cikislari en yuksek hizda kullanacagiz
}

/*********************************************************************************
USART3 configuration :
*********************************************************************************/
void UsartInit()
{

RCC->AHB1ENR |= 0x00000002; // Enable clock for GPIOB

143
RCC->APB1ENR|=0x00040000; // Enable clock for USART3
GPIOB->AFR[1]=0x00007700; // //enable USART3_TX to PB10 and USART3_RX to PB11
GPIOB->MODER|=0x2AA00000; // configuring the USART3 ALTERNATE function to PB10 and PB11
USART3->BRR=0X1112; // 9600 Baud
//UART4->BRR = 0x0890; // 19200 baud
//UART4->BRR = 0x0450; // 38400 baud
//UART4->BRR = 0x02e0; // 57600 baud
//UART4->BRR = 0x016d; // 115200 baud
USART3->CR1|=0x0000202C; // USART3 enable
// NVIC->ISER[1]|=0x80; // NVIC da USART3 interrupta izin verelim
}
/************************************************************************************************
//To send data, we simply assign it to the DR register. Then we wait until the TXE (TX empty) flag
//in the SR register is set to be sure the data is transmitted. In the code it looks like this:
************************************************************************************************/

void SendChar(char Tx)


{
while((USART3->SR&0x80)==0); // On attend ce que TXBUFF soit vide (libere) ou (FLAG TXNE=1) ou Le caractere est envoy
USART3->DR=Tx;
}

void SendTxt(char *Adr)


{
while(*Adr)
{
SendChar(*Adr);
Adr++;
}
}

char receive_data()
{
char RXCH = USART3->DR;
return RXCH;
}

/*********************************************************************************

144
MESSAGE DACCEUIL
*********************************************************************************/

void MESSAGE_WELCOM()
{
SendTxt("TEST UART ");
SendTxt("\n");
SendTxt("WELCOM");
SendTxt("\n");
}

int main()
{

config_GPIO();
SystemInit_1();
UsartInit();
MESSAGE_WELCOM();

while(1)
{
for(i=0;i<20;i++)
{
sprintf (character,"%d",i);
SendTxt(character);
SendTxt("\n");
Delay_TIME(10000000);

// To read in received data, all we have to do is to wait until RXNE (RX not empty) bit is set in the status register SR
//of the USART1. As soon as we realized, this bit is set, we read out the data from the DR (data register) of the USART

if((USART3->SR & 0x0020)!=0) //if((USART3->SR & 0x0020)) FLAG RXNE=1 BUFFER_RX est plein est pret lire
{
char read_character=receive_data(); //lecture du caractere et Le flag RXNE reviend 0

/********************** CMD1***************************************************/
if(read_character=='A')
{

145
SendTxt("CMD1 VALIDE ");
SendTxt("\n");
GPIOD->ODR = 0xF000; //turn LEDs D12 D13 D14 D15 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = ~0xF000; //turn LEDs D12 D13 D14 D15 off
Delay_TIME(0xFFFFFF);
}

/********************** CMD2 ***************************************************/


if(read_character=='B')
{
SendTxt("CMD2 VALIDE ");
SendTxt("\n");
GPIOD->ODR = 0x5000; //turn LEDs D12 and D14 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = ~0x5000; //turn LEDs D13 and D15 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = 0x0; //LEDs off
}

i=0;
}
}

STM32F4 USING USART and ADC


#include <stdio.h>
#include "STM32F4xx.h"

146
__IO uint16_t ADCBuffer[2];
char text[60];
int i;
int j;
int ncount1,ncount2;

/****************************************TEMPO**********************************/
void Delay_TIME(__IO uint32_t nCount)
{
while(nCount--);
}

/*******************************Configuration clock system ********************/


void SystemInit_1()
{

RCC->CFGR |= 0x00009400; // AHB ve APB hizlarini max degerlere set edelim


RCC->CR |= 0x00010000; // HSE Xtal osc calismaya baslasin
while (!(RCC->CR & 0x00020000));// Xtal osc stabil hale gelsin

RCC->PLLCFGR = 0x07402A04; // PLL katsayilarini M=4, N=168, P=2 ve Q=7 yapalim 168 Mhz
RCC->CR |= 0x01000000; // PLL calismaya baslasin (Rehber Sayfa 95)
while(!(RCC->CR & 0x02000000)); // Pll hazir oluncaya kadar bekle

FLASH->ACR = 0x00000605; // Flash ROM icin 5 Wait state secelim ve ART yi aktif edelim (Rehber Sayfa 55)
RCC->CFGR |= 0x00000002; // Sistem Clk u PLL uzerinden besleyelim
while ((RCC->CFGR & 0x0000000F) != 0x0000000A); // Besleninceye kadar bekle

/******************GPIO configuration : PD12, PD13, PD14, PD15 USED FOR THE COMMAND**************/

void config_GPIO()
{
RCC->AHB1ENR |= 1<<3; //Clocks for GPIOD

147
GPIOD->MODER |= 0x55<<24; //Bits 12..15 are output
GPIOD->OSPEEDR= 0xFFFFFFFF; // GPIOD nin tum cikislari en yuksek hizda kullanacagiz
}

/*********************************************************************************
USART3 configuration :
*********************************************************************************/

void UsartInit()
{

RCC->AHB1ENR |= 0x00000002; // Enable clock for GPIOB


RCC->APB1ENR|=0x00040000; // Enable clock for USART3
GPIOB->AFR[1]=0x00007700; // //enable USART3_TX to PB10 and USART3_RX to PB11
GPIOB->MODER|=0x2AA00000; // configuring the USART3 ALTERNATE function to PB10 and PB11
USART3->BRR=0X1112; // 9600 Baud
//UART4->BRR = 0x0890; // 19200 baud
//UART4->BRR = 0x0450; // 38400 baud
//UART4->BRR = 0x02e0; // 57600 baud
//UART4->BRR = 0x016d; // 115200 baud
USART3->CR1|=0x0000202C; // USART3 enable
// NVIC->ISER[1]|=0x80; // NVIC da USART3 interrupta izin verelim
}

void configuration_ADC()
{
RCC->APB2ENR |= 0x00000100 + 0x00000200; // Enable clock for ADC1 & ADC2
RCC->AHB1ENR |= 0x00000001 + 0x00000002; // Enable clock for GPIOA & GPIOB
ADC->CCR = 0x00000006; // No DMA, Regular simultaneous mode only
ADC1->CR2 = 0x00000001; // Control Register 2: ADC1 ON
ADC1->SQR3 = 0x00000002; // regular SeQuence Register 3
ADC2->CR2 = 0x00000001; // Control Register 2: ADC2 ON
ADC2->SQR3 = 0x00000003; // regular SeQuence Register 3
GPIOA->MODER |= 0x000000f0; // MODE Register -> PA2, PA3 are analog inputs
}

/************************************************************************************************

148
//To send data, we simply assign it to the DR register. Then we wait until the TXE (TX empty) flag
//in the SR register is set to be sure the data is transmitted. In the code it looks like this:
************************************************************************************************/

void SendChar(char Tx)


{
while((USART3->SR&0x80)==0); // On attend ce que TXBUFF soit vide (libere) ou (FLAG TXNE=1) ou Le caractere est envoy
USART3->DR=Tx;
}

void SendTxt(char *Adr)


{
while(*Adr)
{
SendChar(*Adr);
Adr++;
}
}

char receive_data()
{
char RXCH = USART3->DR;
return RXCH;
}

void MESSAGE_WELCOM()
{

SendTxt("TEST UART ");


SendTxt("\n");
SendTxt("WELCOM");
SendTxt("\n");
}

int main()

149
{

config_GPIO();

SystemInit_1();

UsartInit();

configuration_ADC();

//MESSAGE_WELCOM();

while(1)
{
ADC1->CR2 |= ADC_CR2_SWSTART; // simultaneous Start Conversion
ADC2->CR2 |= ADC_CR2_SWSTART; // simultaneous Start Conversion
while((ADC1->SR & 0x2)==0); // wait for ADC2 conversion to complete
while((ADC2->SR & 0x2)==0); // wait for ADC2 conversion to complete

ADCBuffer[0]=ADC1->DR;
ADCBuffer[1]=ADC2->DR;

sprintf (text,"%d %d",ADCBuffer[0],ADCBuffer[1]);


SendTxt(text);
SendTxt("\n");
Delay_TIME(10000000);

// To read in received data, all we have to do is to wait until RXNE (RX not empty) bit is set in the status register
SR
//of the USART1. As soon as we realized, this bit is set, we read out the data from the DR (data register) of the
USART

if((USART3->SR & 0x0020)!=0) //if((USART3->SR & 0x0020)) FLAG RXNE=1 BUFFER_RX est plein est pret lire
{
char read_character=receive_data(); //lecture du caractere et Le flag RXNE reviend 0

150
/********************** CMD1***************************************************/
if(read_character=='A')
{

ncount2=0;
if(ncount1==1)
{
GPIOD->ODR = 0xF000; //turn LEDs D12 D13 D14 D15 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = ~0xF000; //turn LEDs D12 D13 D14 D15 off
Delay_TIME(0xFFFFFF);

}
ncount1++;
}

/********************** CMD2 ***************************************************/


if(read_character=='B')
{

ncount1=0;

if(ncount2==1)
{
GPIOD->ODR = 0x5000; //turn LEDs D12 and D14 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = ~0x5000; //turn LEDs D13 and D15 on
Delay_TIME(0xFFFFFF);
GPIOD->ODR = 0x0; //LEDs off
}
ncount2++;
}

}
else
{
ncount1=0;
ncount2=0;

151
}

}
}

INPUT CAPTURE (MESURE DE LA FREQUENCE DUN SIGNAL PERIODIQUE ET TRANSMISSION PAR


USART)
#include "stm32f4xx.h"

152
#include <stdio.h>

__IO uint16_t value_CCR1;


__IO uint16_t value_CCR2;
char text[30];

int N1,N2;

void Delay(__IO uint32_t nCount)


{
while(nCount--)
{}
}

void clock_config()
{
RCC->CFGR = 0x00000001; //select HSE as system clock
RCC->CR |= 1<<16; //HSE on
while (!(RCC->CR & (1<<17))); //wait until HSE ready on attend ce que HSERDY=1

void SystemInit_1()
{

RCC->CFGR |= 0x00009400; // Fixation of the AHB and APB prescaler : HPRE PPRE1 PPRE2
RCC->CR |= 0x00010000; // HSE ON
while (!(RCC->CR & 0x00020000));// wait until will be ready HSERDY=1

RCC->PLLCFGR = 0x07402A04; // PLL coefficients : M = 4, N = 168, P = 2 and Q = 7 ==> SYSCLK= HSE x(N/M*P)=8x
(168/4x2)=168MHz =>CLK_TIM2=SYSCLK/PPRE1=168/4=42MHz
RCC->CR |= 0x01000000; // PLL ON
while(!(RCC->CR & 0x02000000)); // wait until will be PLL ready PLLRDY=1

153
FLASH->ACR = 0x00000605; // Flash ROM is 5 Wait state
RCC->CFGR |= 0x00000002; // System PLL On
while ((RCC->CFGR & 0x0000000F) != 0x0000000A); // Wait Pll On

void UsartInit()
{

RCC->AHB1ENR |= 0x00000002; // Enable clock for GPIOB


RCC->APB1ENR|=0x00040000; // Enable clock for USART3
GPIOB->AFR[1]=0x00007700; // //enable USART3_TX to PB10 and USART3_RX to PB11
GPIOB->MODER|=0x2AA00000; // configuring the USART3 ALTERNATE function to PB10 and PB11
USART3->BRR=0X1120; // 9600 Baud
//USART3->BRR = 0x0890; // 19200 baud
//USART3->BRR = 0x0450; // 38400 baud
//USART3->BRR = 0x02e0; // 57600 baud
//USART3->BRR = 0x016d; // 115200 baud
USART3->CR1|=0x0000202C; // USART3 enable
// NVIC->ISER[1]|=0x80; // NVIC da USART3 interrupta izin verelim
}

void SendChar(char Tx)


{
while((USART3->SR&0x80)==0); // On attend ce que TXBUFF soit vide (libere) ou (FLAG TXNE=1) ou Le caractere est envoy
USART3->DR=Tx;
}

void SendTxt(char *Adr)


{
while(*Adr)
{
SendChar(*Adr);
Adr++;
}

154
}

/**********************************************************************************
//PA0 and PA1 used for CAPTURE SIGNAL
**********************************************************************************/
void GPIOA_CONGIGURATION()
{
// enable GPIOA clock
RCC->AHB1ENR = 0x00000001;
// Alternate Function
GPIOA->MODER =0x0000000A; // AF, TIM2_CH1 // AF, TIM2_CH2
// Alternate Function pins
GPIOA->AFR[0] =0x00000011;// TIM2_CH1, AF1 // TIM2_CH2, AF1
}

void GPIOD_CONGIGURATION()
{
RCC->AHB1ENR |= 1<<3; //Clocks for GPIOD
GPIOD->MODER |= 0x55500000; //Bits 12..15 are output
}

void TIM2_MODE_INPUT_CAPTURE()
{
// enable TIM2 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; //0x00000001
// configure TIM2_CH1 for input capture //////////////////////////////////
TIM2->CCMR1 = 0x0121;// set TIM2_CH1 for input mode // set the input filter to 4 samples
// select edge of the active transition
//enable input capture
TIM2->CCER = 0x0033;

// NVIC_EnableIRQ(TIM2_IRQn); // Enable TIM2 IRQ


// TIM2->DIER = 0x0006; //Enable interrupt for CC1 and CC2

TIM2->SR=0;

//TIM2->PSC = 2;

155
//enable TIM2
TIM2->CR1 = 0x0001;

void square_signal_1()
{
GPIOD->ODR = 0xF000;
Delay(0x600);
GPIOD->ODR =~0xF000;
Delay(0x600);
}
void square_signal_2()
{
GPIOD->ODR = 0x0F00;
Delay(0x700);
GPIOD->ODR =~0x0F00;
Delay(0x700);
}

void MESSAGE_WELCOM()
{
SendTxt("TEST UART ");
SendTxt("\n");
SendTxt("WELCOM");
SendTxt("\n");
}

int main(void)
{

SystemInit_1();
UsartInit();
GPIOA_CONGIGURATION();
GPIOD_CONGIGURATION();

156
TIM2_MODE_INPUT_CAPTURE();
MESSAGE_WELCOM();

while (1)
{

square_signal_1();
square_signal_2();

if((TIM2->SR&0x0002)) // CC1IF =1 ?
{
N1++;
if(N1==10000)
{
value_CCR1=TIM2->CCR1;
sprintf(text,"%d %d",value_CCR1,value_CCR2);
SendTxt(text);
SendTxt("\n");
N1=0;
}
TIM2->CNT=0;
TIM2->SR &=0; // CC1IF =0 the flag is clear
}

if((TIM2->SR&0x0004)) // CC1IF =1 ?
{
N2++;
if(N2==10000)
{
value_CCR2=TIM2->CCR2;
sprintf(text,"%d %d",value_CCR1,value_CCR2);
SendTxt(text);
SendTxt("\n");
N2=0;
}

TIM2->CNT=0;
TIM2->SR &=0; // CC1IF =0 the flag is clear

157
}

void TIM2_IRQHandler()
{

158
ANNEXE

La rpartition de la RAM

159
GPIO

I2C / SPI /USART

TIMER

ADC

DAC

CAN

SYSTEM CLOCK

I2S

LES PERIPHERIQUES

160
Chaque interface (priphrique: interface de communication(I2C,SPI,USB), TIMER, PORT(PORTA,PORTB,PORTC.) est dfinie par un
ensemble de registres qui sont regroupes dans une structure(ensemble de registre). La manipulation de ces registres se fait
via un pointeur pointu sur cette structure.

Exemple : #define TIM2 ((TIM_TypeDef *) TIM2_BASE) TIM2 est un pointeur sur la structure TIM_TypeDef

Exemple :

161
La structure TIM_TypeDef contient plusieurs registres permettant de configurer les timers (CR1, RESERVED0,
CR2,RESERVED1,SMCR.etc, RESERVED14)et elle est dfinie comme ceci :

typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
uint16_t RESERVED9; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED10; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED11; /*!< Reserved, 0x46 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED12; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */

162
uint16_t RESERVED13; /*!< Reserved, 0x4E */
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED14; /*!< Reserved, 0x52 */
} TIM_TypeDef;

Pointeurs sur structures


#define TIM2 ((TIM_TypeDef *) TIM2_BASE) TIM2 est un pointeur sur la structure TIM_TypeDef
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) TIM3 est un pointeur sur la structure TIM_TypeDef
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)

163
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

164
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
#define HASH ((HASH_TypeDef *) HASH_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

165
166
167
168
FSMC register map
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) (0xA0000000+ 0x0000= 0XA0000000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) (0xA0000000+ 0x0104= 0XA0000104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) (0xA0000000+ 0x0060= 0XA0000060)
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) (0xA0000000+ 0x0080= 0XA0000080)
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) (0xA0000000+ 0x00A0= 0XA00000A0)

169
170
FMSC REGISTER MAP (SUITE)

171
FMSC REGISTER MAP (SUITE)

172
RNG register map
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) (0x40000000 + 0x00010000 = 0x50000000)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) (0x50000000+ 0x60800 =0x50060800)

Donc: #define RNG_BASE ((uint32_t)0x50060800)

HASH register map


#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) (0x40000000 + 0x00010000 = 0x50000000)
#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) (0x50000000+ 0x60400 =0x50060400)

173
174
HASH REGISTER MAP AND RESET VALUES (SUITE)

CRYP register map


#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) (0x40000000 + 0x00010000 = 0x50000000)
#define CRYP_BASE (AHB2PERIPH_BASE + 0x60400) (0x50000000+ 0x60000 =0x50060000)

175
176
177
DCMI register map
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) (0x40000000 + 0x00010000 = 0x50000000)
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) (0x50000000+ 0x50000 =0x50050000)

Donc: #define DCMI_BASE ((uint32_t)0x50050000)

178
179
ETHERNET MAC register map
#define PERIPH_BASE ((uint32_t)0x40000000)
Rq : #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) (0x40000000 + 0x00020000= 0x40020000)
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) (0x40020000 + 0x8000= 0x40028000)
#define ETH_MAC_BASE (ETH_BASE) 0x40028000
#define ETH_MMC_BASE (ETH_BASE + 0x0100) 0x40028000 + 0x0100 =0x40028100
#define ETH_PTP_BASE (ETH_BASE + 0x0700) 0x40028000 + 0x0700 =0x40028700
#define ETH_DMA_BASE (ETH_BASE + 0x1000) 0x40028000 + 0x1000 =0x40029000

180
181
182
Dfinition des bits attribus quelques registres

/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION ((uint32_t)0x00000001)
#define RCC_CR_HSIRDY ((uint32_t)0x00000002)

#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)


#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */

#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */

#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)


#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */

#define RCC_CR_HSEON ((uint32_t)0x00010000)


#define RCC_CR_HSERDY ((uint32_t)0x00020000)
#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
#define RCC_CR_CSSON ((uint32_t)0x00080000)
#define RCC_CR_PLLON ((uint32_t)0x01000000)

183
#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)

Address offset: 0x00


Reset value: 0x0000 XX83 where X is undefined.

/******************** Bit definition for RCC_PLLCFGR register ***************/


#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)

#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)


#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)

184
#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)

#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)


#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)

#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)


#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)

Address offset: 0x04


Reset value: 0x2400 3010

/******************** Bit definition for RCC_CFGR register ******************/


/*!< SW configuration */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */

#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */


#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */

185
/*!< SWS configuration */
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */

#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */


#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */

/*!< HPRE configuration */


#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */

#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */


#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */

/*!< PPRE1 configuration */


#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */

#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */


#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */

186
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */

#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */


#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */

/*!< RTCPRE configuration */


#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)

/*!< MCO1 configuration */


#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)

#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)

#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)


#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)

#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)


#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)

#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)

187
#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)

Address offset: 0x08


Reset value: 0x0000 0000

/******************** Bit definition for RCC_CIR register *******************/


#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
#define RCC_CIR_CSSF ((uint32_t)0x00000080)
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
#define RCC_CIR_CSSC ((uint32_t)0x00800000)

188
Address offset: 0x0C
Reset value: 0x0000 0000

/******************** Bit definition for RCC_AHB1RSTR register **************/


#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)

189
Address offset: 0x10
Reset value: 0x0000 0000

/******************** Bit definition for RCC_AHB2RSTR register **************/


#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
#define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020)
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)

Address offset: 0x14


Reset value: 0x0000 0000

190
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)

Address offset: 0x18


Reset value: 0x0000 0000

/******************** Bit definition for RCC_APB1RSTR register **************/


#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)

191
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)

Address offset: 0x20


Reset value: 0x0000 0000

/******************** Bit definition for RCC_APB2RSTR register **************/


#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
/* Old SPI1RST bit definition, maintained for legacy purpose */
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST

192
Address offset: 0x24
Reset value: 0x0000 0000

/******************** Bit definition for RCC_AHB1ENR register ***************/


#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)

193
Address offset: 0x30
Reset value: 0x0010 0000

/******************** Bit definition for RCC_AHB2ENR register ***************/


#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)

Address offset: 0x34


Reset value: 0x0000 0000

194
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)

Address offset: 0x38


Reset value: 0x0000 0000

/******************** Bit definition for RCC_APB1ENR register ***************/


#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)

195
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)

Address offset: 0x40


Reset value: 0x0000 0000

/******************** Bit definition for RCC_APB2ENR register ***************/


#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)

196
Address offset: 0x44
Reset value: 0x0000 0000

/******************** Bit definition for RCC_AHB1LPENR register *************/


#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)

197
Address offset: 0x50
Reset value: 0x7E67 91FF

/******************** Bit definition for RCC_AHB2LPENR register *************/


#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)

Address offset: 0x54


Reset value: 0x0000 00F1

198
/******************** Bit definition for RCC_AHB3LPENR register *************/
#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)

Address offset: 0x58


Reset value: 0x0000 0001

/******************** Bit definition for RCC_APB1LPENR register *************/


#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)

199
#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)

Address offset: 0x60


Reset value: 0x36FE C9FF

/******************** Bit definition for RCC_APB2LPENR register *************/


#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)

200
Address offset: 0x64
Reset value: 0x0007 5F33

/******************** Bit definition for RCC_BDCR register ******************/


#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)

#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)


#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)

#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)


#define RCC_BDCR_BDRST ((uint32_t)0x00010000)

Address offset: 0x70


Reset value: 0x0000 0000

201
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001)
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
#define RCC_CSR_RMVF ((uint32_t)0x01000000)
#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)

Address offset: 0x74


Reset value: 0x0E00 0000

/******************** Bit definition for RCC_SSCGR register *****************/


#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)

202
#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)

Address offset: 0x80


Reset value: 0x0000 0000

/******************** Bit definition for RCC_PLLI2SCFGR register ************/


#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)

Address offset: 0x84


Reset value: 0x2000 3000

203
/******************************************************************************/

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TIMER_STM32F4

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