Digital Control of Single Phase UPS Inverters
Based on Discrete-Time State and Disturbance
Observer
Nguyen Manh Linh
Graduate School of Engineering and Science
Shibaura Institute of Technology
Saitama 337-8570, Japan
Email: nb15502@shibaura-it.ac.jp
AbstractThis paper proposes a new strategy to design the
discrete-time controller for an uninterruptible power supply
(UPS) inverter. First, by using a proportional integral observer
(PIOb) as a state and disturbance estimation, all the unknown
terms caused by the modeling errors and unmeasured load
current are estimated and employed in the control design.
Then, the inductor current controller is designed based on
the one step-ahead minimum prediction error technique. The
optimal reference value for this current loop is generated by
a current command generator which minimizes the output
voltage tracking error. This proposed control strategy is capable
of achieving high robustness against the parameters variation
and excellent voltage regulation, even under nonlinear loads.
Simulation studies based on Matlab-Simulink are conducted to
further validate the effectiveness of the proposed strategy.
Keywordssingle phase UPS inverter, state and disturbance
estimation, one step-ahead minimum prediction error
I. I NTRODUCTION
Single phase inverters have been widely used in UPS
systems which are capable of delivering emergent AC power
to critical loads such as medical equipments, data processing
and computer systems in case of a utility power failure. The
output voltage of a high performance UPS must be sinusoidal
with low total harmonic distortion (THD) satisfying IEEE-
1547 standard [1], even with nonlinear loads. Furthermore,
good voltage regulation and quick transient response with
sudden changes of loads are also needed.
In order to fulfill the above mentioned requirements, many
control strategies have been proposed in the literature [2]-
[11]. In [2], conventional cascade control schemes based
on inner inductor current loop or inner capacitor current
loop are investigated. These control schemes are capable
of achieving high voltage performance with low THD and
quick response if the parameters of the output filter com-
ponents are known precisely. In practice, these parameters
are normally inaccurate and may be varied with the working
condition, following that the performance of the UPS can
be degraded considerably. In [4], a proportional-integral (PI)
controller is designed in a synchronous reference frame,
Xinkai Chen
Department of Electronic and Information Systems
Shibaura Institute of Technology
Saitama 337-8570, Japan
Email: chen@shibaura-it.ac.jp
which rotates synchronously with the output voltage, to
regulate the voltage with zero steady-state error. However,
the design procedure of this method is complicated and
the computation time is increased since the trigonometric
functions are employed in the coordinate transformation. In
[5], the iterative learning control (ILC) has been used to
achieve low THD under nonlinear periodic loads. The slow
dynamics, large memory requirement and poor performance
under non-periodic disturbances are the major problems of
this technique. The self-tuned feed-forward with harmonic
feedback control strategy proposed in [6] can also reduced
the THD of the output voltage significantly. In practice,
this method is suffered from its complexity in implemen-
tation. To further enhance the robustness of the closed-loop
control system, the sliding mode control (SMC) with many
advantages such as insensitive to matched disturbances, quick
dynamic response and simplicity in implementation has also
been applied to UPS inverters [7]- [9]. The dynamic of the
system even can be made faster by using a time-varying
sliding gain in the sliding function [9]. Since these techniques
are designed in continuous-time domain, the UPS systems
are suffered from the variable switching frequency which
may increases the THD and power loss. To alleviate the
variable switching frequency problem, discrete-time sliding
mode control (DSMC) has been adopted in [10] with a dual-
loops scheme including an inductor current predictor and
an inductor current controller. Nevertheless, the chattering
is still inevitable. In [11], an extended Lyapunov function
based control strategy is proposed to achieve global stability,
fast dynamic response and almost zero steady-state error in
the output voltage. Since one voltage and two current sensors
are required, the cost of the system is an issue in practice.
In this paper, a new strategy is proposed to handle the
control problem of the UPS inverter. A PIOb is employed to
estimated the unknown disturbances caused by the modeling
error and the unmeasured load current first. The information
getting from the PIOb is then used in the control design which
consists of a current command generator and an inductor
current controller. The advantages of this strategy is that the
design procedure is simple and straightforward in tuning. where Ts is the sampling time, O(Ts2 ) is the small error
Furthermore, the closed-loop system is robust against the caused by the numerical approximation. The magnitude of a
modeling error and disturbances. Simulations implemented signal g is said to be g = O(Tsn ) if
by Matlab-Simulink are conducted to verify the effectiveness
lim gn 6= 0 and lim n1g
=0 (5)
of this proposed strategy. Ts 0 Ts Ts 0 Ts

in which n is an integer [3].

II. P ROBLEM F ORMULATION
The corresponding state-space variables and matrices of
the discrete-time system (4) are
 
Vo,k
Xk = Yk =
IL,k 
ATs 11 12
=e =
21 22
RTs A
  (6)

= e d B = A1 ( I2 )B = 11
0
21
RTs A
 
f1,k
fk = e d{(k + 1)Ts }d =
0
f2,k
where I2 is an unity (2 2) matrix.
Fig. 1: Single phase UPS inverter
In this design, the output voltage Vo,k and the inductor
current IL,k are chosen as the state variables and measured.
The load current Io,k is not measured and treated as a
A single-phase full-bridge inverter with the typical config- disturbance. This unknown term in combination with the
uration shown in Fig. 1 can be considered as a voltage source other uncertainties caused by the parameters variation may
if the switching frequency is high enough. Then, the dynamic significantly degrade the performance of the control system.
response of the inverter is mainly governed by the output To cope with the above problem, a discrete-time proportional-
inductance-capacitance (LC) filter. The state-space equations integral observer (dPIOb) is employed to estimate the dis-
describing the operation of the inverter in continuous time turbances first. Then, the information getting from the dis-
domain are turbance observer is included in the control design which
x(t)
=Ax(t) + Bu(t) + d(t) is based on the one step-ahead minimum prediction error
(1) technique. By using the proposed control strategy, the closed-
y(t) =Cx(t)
loop system not only has a quick transient response but also
where, robust against the parameters variation.
   dio (t) io (t)

vo (t) R c + d 1 (t) III. S TATE AND D ISTURBANCE E STIMATION
x(t) = y(t) = , d(t) = dt C
i (t) d2 (t)
 L  The observability matrix Oab and controllability matrix
Rc Rf
"R V #
Rc 1
Cf Lf
c d
 
A = L1f B = LVf , C = 1 0 Cab of the continuous-time system (1) are derived from (2)
Lf
R
Lff
d
Lf
0 1 as
Rc2 Vd
 
(2) Rc V d 1 Rc Rf Vd
L Lf2 + Cf Lf Lf
Cab = [B AB] = Vf Rc V d Rf V d

In (2), vo (t) is the output voltage, iL (t) and io (t) are the Lf
d
L 2 L 2
f f
inductor and the load current, Vd is the dc input voltage, (7)
Rf , Rc , Lf , Cf are the parameters of the output LC filter,  
 
d1 (t), d2 (t) represent for the modeling errors due to the fact C I
Oab = = 2 (8)
that all the parameters of the inverter may be varied during CA A
operation. The control input u(t) is defined by Since
u = 2D 1 (3) Vd2
|Cab | = 6= 0 (9)
Lf Cf
in which 0 < D < 1 is the duty ratio of the pulse with
1
modulation (PWM). |A| = 6= 0 (10)
Lf Cf
For control design purpose, a discrete time state-space
model derived from (1) is used in this paper: It can be concluded that Cab and Oab are not singular, which
means the state-space system (1) is completely observable-
Xk+1 = Xk + uk + fk + O(Ts2 ) controllable. Then, the state and disturbance estimation can
(4) be designed based on the following assumptions:
Yk = CXk
 Assumption 1: The sampling time Ts is small enough such As proved in [12], if Assumption 1 is satisfied, the pair of
that the controllability and the observability of the discrete- matrices (M, G) is alway observable. Which means the ma-
time system (4) are preserved which results in trix (M-LG) can be stabilized, i.e, by using pole-placement
  technique. Then, it follows that:
I2 I2
rank( )=4 (11)
C 0 X k Xk O(T 2 ) as k
(23)
fk fk O(T 2 ) as k
Assumption 2: The disturbance d(t) is smooth and the
sampling time Ts is small enough such that The above analysis shows that the dPIOb can restrict the
estimation error in the small region O(T 2 ). The estimated
fk+1 fk =O(Ts2 ) disturbances are then employed in the control design intro-
fk+1 2fk + fk1 =O(Ts3 ) (12) duced in the next section.

Define X k and fk as the estimation state and the estimation

k Xk and IV. C ONTROL D ESIGN
disturbance. The goal of the dPIOb is to force X

fk fk as k . The state-space equation of the dPIOb A. Current controller
is [12]
From (6), the state space model (4) can be rewritten in
X k+1 = X k + uk + L1 (Yk Yk ) + fk detail as follows,

fk+1 = fk + L2 (Yk Yk ) (13)
Vo,k+1 =11 Vo,k + 12 IL,k + 11 uk + f1,k (24)
Yk = CXk
IL,k+1 =21 Vo,k + 22 IL,k + 21 uk + f2,k (25)
where L1 and L2 are (2 2) designed matrices and
To force the inductor current IL,k of the inverter track a

Vc,k
 
desired current IL,k in the presence of the unknown term
Xk = Yk = (14) f2,k , the current controller is designed as following.
IL,k
Define the estimation errors as Define the one step-ahead current tracking error ei,k+1 as
k = Xk X k
X (15) ei,k+1 = IL,k+1 IL,k+1 (26)
Yk = Yk Yk (16)
The control signal uk which forces ei,k+1 to zero can be
fk = fk fk (17) obtained by solving the following equation
From (4) and (13), the dynamic of the state estimation error ei,k+1 = 0 (27)
is
X k+1 = ( L1 C)X k + fk + O(Ts2 ) (18) By substituting (25) into (27), a fundamental operation yields
The one step ahead disturbance estimation error can be obtain 1
I


uk = 21 Vo,k 22 IL,k f2,k (28)
from (13) and (17) as follows, 21 L,k+1
fk+1 =fk+1 fk+1 Since f2,k is unknown, its approximation is employed
=(fk+1 fk ) + (fk fk ) L2 CX
k
f2,k f2,k (29)
=fk L2 CX
k + (fk+1 fk ) (19)
Suppose that the pole-placement design for the dPIOb results
From (15) and (19), the state-space equations of the estima- in
tion errors can be reformulated as
 
 
L2 = 11 12 (30)
k+1 k 21 22
      
X L1 C I2 X O(Ts2 )
= +
fk+1 L2 C I2 fk fk+1 fk
From (13), (20) and (30), it gives

 
X
=(M LG) k + O(Ts2 ) (20) f2,k =f2,k1 + 21 Vo,k1 + 22 IL,k1 (31)
fk

   
X X Based on (28) and (29), the control action for the current
Yk = [C 0] k = G k (21)
fk fk loop is
where, 1  
uk = IL,k+1 21 Vo,k 22 IL,k f2,k (32)

I2

T 21
, L = LT1 LT2

M= , G = [C 0] (22)
0 I2 which results in ei,k+1 O(T 2 ) asymptotically.
B. Current Command Generator TABLE I: Parameters of Inverter
To keep the output voltage Vo,k follows a desired voltage Lf 0.7 mH

Vo,k , an appropriate reference inductor current IL,k+1 is Rf 0.195
needed for the current loop. Cf 120 F
Rc 0.1
Define the generalized voltage tracking error Ev,k as Vd 250 Vdc
Ts 100 s
Ev,k = ev,k + ev,k1 (33) fsw 10 kHz
Vo 100sin(250kTs )
where 0 < < 1 is a design parameter and ev,k is the RLoad 10
instantaneous voltage tracking error computed by CLoad 470 F

ev,k = Vo,k Vo,k (34)
V. S IMULATION R ESULTS AND D ISCUSSION
The one step-ahead generalized voltage tracking error is
To verify the effectiveness of the proposed control strat-
Ev,k+1 =ev,k+1 + ev,k egy, simulations based on Matlab-Simulink are conducted for
a 1-kVA single phase PWM inverter. The parameters of the
=Vo,k+1 Vo,k+1 + (Vo,k Vo,k ) (35)
inverter are provided in Table I.
By using (24), (32) and (35), a fundamental operation yields
The corresponding matrices of the discrete-time state
space system (4) are
 
11
Evk+1 =Vo,k+1 + Vo,k + 21 11 Vo,k

 
 12 0.9282 0.7972
 = (43)
11 11 0.1371 0.9151
+ 22 12 IL,k + f2,k
21 21 = [17.9577 34.2824]
T
(44)
11
f1,k I (36) By placing the poles of the augmented system (20) as
21 L,k+1

Based on (36), the current command IL,k+1 which forces p = [0.05 0.1 0.2 0.3] (45)
Ev+1 = 0 is
the corresponding gain matrices L1 and L2 of the PIOb are
 
21

21 
1.4282 0.7972

IL,k+1 = V + Vo,k + 22 12 IL,k L1 = (46)
11 o,k+1 11 0.1371 1.7651
 
21 21  
+ 21 (11 + ) Vo,k + f2,k f1,k (37) L2 =
0.5600 0.0000
(47)
11 11 0.0000 0.8550
Due to the fact that f1,k in (37) is unknown, its approximation
is used instead
f1,k f1,k (38)

where f1,k is also computed from (13), (20) and (30) as

f1,k =f1,k1 + 11 Vo,k1 + 12 IL,k1 (39)

with,

Vo,k1 = Vo,k1 Vo,k1 (40)

IL,k1 = IL,k1 IL,k1 (41)
Fig. 2: Block diagram of the inverter controller
Finally, from (37)-(39), the output of the current command
generator is
 
21

21
IL,k+1 = V + Vo,k + 22 12 IL,k The block diagram of the controller are shown in Fig. 2,
11 o,k+1 11 in which a S-Function Builder is employed to implement the
 
21 21 control algorithm written by C language. Two typical loads,
+ 21 (11 + ) Vo,k + f2,k f1,k (42) including linear resistive load in Fig. 3 and nonlinear rectifier
11 11
load in Fig. 4, are used to investigate the performance of the
which also results in Ev,k O(T 2 ) asymptotically. proposed control strategy.
 Signal Available signals

Selected signal: 7.5 cycles. FFT window (in red): 5 cycles

100 Refresh

Signal mag.
Name: Vok

0 Input: input 1

Signal number: 1

-100 Display: Signal

0 0.05 0.1 0.15 FFT window

FFT analysis Time (s) FFT settings

Fundamental (50Hz) = 99.85 , THD= 1.10% Start time (s): 0.05

Number of cycles: 5
0.8

Mag (% of Fundamental)
Fundamental frequency (Hz): 50

0.6 Max frequency (Hz): 1000

Max frequency for THD computation:

Nyquist frequency
0.4
Display style:

Bar (relative to fundamental)

0.2 Base value: 1.0

Frequency axis: Hertz

0
0 200 400 600 800 1000 Display Close

Frequency (Hz)

Fig. 3: Single phase UPS inverter with resistive load Fig. 6: THD of the output voltage with resistive load

completely fulfills the requirement of IEEE-1547 standard.

Load current(A)
50
100 Reference Voltage

Voltage(V)
Output Voltage 25
0 Load current 0
-25
-100 0.041 0.042 0.043 0.044
-50
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)

Inductor current(A)
20 Inductor current
Observed current
0

Fig. 4: Single phase UPS inverter with rectifier load -20

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s)

First, suppose that the system model is perfect. Then, Fig. 7: Simulation result with rectifier load and accurate
the simulations with rate resistive load are carried out. The model
response of the system with the change from no-load to full-
load condition is shown in Fig. 5 and the THD analysis result
is shown in Fig. 6. It can be observed that the output voltage Signal

Selected signal: 5 cycles. FFT window (in red): 5 cycles

Available signals

100 Refresh

is quickly recovered within a few sampling cycles when the

Signal mag.

Name: Vok

load is changed. The THD at the steady-state is 1.1%, which 0 Input:

Signal number:
input 1

is much lower than the restriction value 5% of the IEEE-1547 -100

0 0.02 0.04 0.06 0.08 0.1
Display: Signal

FFT window

standard. FFT analysis

Time (s)
Fundamental (50Hz) = 100.2 , THD= 1.87%
FFT settings

Start time (s): 0.0

Mag (% of Fundamental)

Number of cycles: 5

1 Fundamental frequency (Hz): 50

Load current(A)

20
100 Reference Voltage 0.8 Max frequency (Hz):
Voltage(V)

1000

Output Voltage 10 Max frequency for THD computation:

Load current 0.6

0 0 Nyquist frequency

100
-10 0.4 Display style:

Bar (relative to fundamental)

-100 0.043 0.044 0.045 0.046 0.047

0.2
-20 Base value: 1.0

0 0.05 0.1 0.15 Frequency axis: Hertz

Time(s) 0
0 200 400 600 800 1000 Display Close
Inductor current(A)

Frequency (Hz)
20 Inductor current
Observed current
Fig. 8: THD of the output voltage with nonlinear rectifier
0 load
-20
0 0.05 0.1 0.15
Time(s)

By using the proposed control strategy, the current trim-

Fig. 5: Simulation result with resistive load and accurate ming function which protects the inverter against the overload
model failure can easily be accomplished as demonstrated in Fig.
9.
Finally, the robustness of the closed-loop system against
The simulation result and THD analysis of the system the modeling errors is confirmed by simulations which all
with nonlinear rectifier load are shown in Fig. 7 and Fig. 8, the parameters of the inverter are different from the values
respectively. It can be seen that the output voltage is slightly used in Table I. In practice, the variations of the commercial
distorted in this case. However, the T HD = 1.87% still inductors and capacitors are less than 10% while the
 RL = 0.4, RC = 0.2, L = 7.7mH, C = 132F, Vd = 270V

Load current(A)

Load current(A)
50 50
100 Reference Voltage 100 Reference Voltage
Voltage(V)

Voltage(V)
Output Voltage 25 Output Voltage 25
0 Load current 0 0 Load current 0
-25 -25
-100 -100 0.0405 0.041 0.0415 0.042 0.0425 0.043
-50 -50
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s) Time(s)
Inductor current(A)

Inductor current(A)
20 Inductor current 20 Inductor current
Observed current Observed current
0 0

-20 -20

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time(s) Time(s)

Fig. 9: Simulation result with 15A current trimming Fig. 11: Simulation result with nonlinear load and increased
function L, C values

RL = 0.4, RC = 0.2, L = 0.63mH, C = 108F, Vd = 220V

Load current(A)
100
50 tuning procedure are also simple and straightforward. The
Voltage(V)

Reference Voltage
25
0
Output Voltage
Load current 0 effectiveness and the robustness of the closed-loop system
-100 0.0405 0.041 0.0415 0.042 0.0425 0.043
-25 are validated by simulation results implemented by Matlab-
-50
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Simulink.
Time(s)
Inductor current(A)

20
0 [1]
-20
0 0.01
Fig. 10: Simulation result with nonlinear load and reduced
L, C values
internal resistance of the LC filter may increase up to 200%
in comparison with the nominal values. Moreover, the dc
voltage source Vd may be also 10% changed. Hence,
simulation studies based on the above mentioned practical
situations are conducted. Figure 10 shows the simulation
result where the internal resistance of the LC filter are twice
their nominal values, the inductor Lf , the capacitor Cf
of the filter are 10% reduced. In contrast, Fig. 11 shows
the simulation result where Lf and Cf are 10% increased.
Besides, the dc voltage source is also 10% deviated from its
nominal value. It can be seen that in both cases, the closed-
loop system is stable and the response of the output voltage
are almost same as the case where an accurate model is used.
The only different which can be recognized is the ripple of
the inductor current and the output voltages since it depends
on the systems parameters.
In this paper, a new control strategy for the single
phase UPS inverter is proposed and designed in discrete-
time domain. By taking into account the influences of the
parameters variation, disturbances and using one step-ahead
minimum prediction error technique, the proposed method
is capable of achieving quick response, excellent voltage
regulation, low THD satisfying IEEE-1547 standard and high
robustness against the modeling error. The control design and
Inductor current
R EFERENCES
Observed current
IEEE Standard for Interconnecting Distributed Resources with Electric
Power Systems, in IEEE Std 1547-2003 , vol., no., pp.1-28, July 28
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 2003.
Time(s)
[2] M. J. Ryan, W. E. Brumsickle and R. D. Lorenz, Control topology
options for single-phase UPS inverters, in IEEE Transactions on
Industry Applications, vol. 33, no. 2, pp. 493-501, Mar/Apr 1997
[3] K. Abidi, J. X. Xu and Y. Xinghuo, On the Discrete-Time Integral
Sliding-Mode Control, in IEEE Transactions on Automatic Control,
vol. 52, no. 4, pp. 709-715, April 2007
[4] M. Monfared, S. Golestan and J. M. Guerrero, Analysis, Design, and
Experimental Verification of a Synchronous Reference Frame Voltage
Control for Single-Phase Inverters, in IEEE Transactions on Industrial
Electronics, vol. 61, no. 1, pp. 258-269, Jan. 2014.
[5] H. Deng, R. Oruganti and D. Srinivasan, Analysis and Design of
Iterative Learning Control Strategies for UPS Inverters, in IEEE
Transactions on Industrial Electronics, vol. 54, no. 3, pp. 1739-1751,
June 2007.
[6] L. Padmavathi and P. A. Janakiraman, Self-Tuned Feed-Forward
Compensation for Harmonic Reduction in Single-Phase Low-Voltage
Inverters, in IEEE Transactions on Industrial Electronics, vol. 58, no.
10, pp. 4753-4762, Oct. 2011.
[7] S. J. Chiang, T. L. Tai and T. S. Lee, Variable structure control of
UPS inverters, in IEE Proceedings - Electric Power Applications, vol.
145, no. 6, pp. 559-567, Nov 1998.
[8] O. Kukrer, H. Komurcugil and A. Doganalp, A Three-Level Hysteresis
Function Approach to the Sliding-Mode Control of Single-Phase UPS
Inverters, in IEEE Transactions on Industrial Electronics, vol. 56, no.
9, pp. 3477-3486, Sept. 2009.
[9] H. Komurcugil, Rotating-Sliding-Line-Based Sliding-Mode Control
for Single-Phase UPS Inverters, in IEEE Transactions on Industrial
VI. C ONCLUSION Electronics, vol. 59, no. 10, pp. 3719-3726, Oct. 2012.
[10] Tsang-Li Tai and Jian-Shiang Chen, UPS inverter design using
discrete-time sliding-mode control scheme, in IEEE Transactions on
Industrial Electronics, vol. 49, no. 1, pp. 67-75, Feb 2002.
[11] H. Komurcugil, N. Altin, S. Ozdemir and I. Sefa, An Extended
Lyapunov-Function-Based Control Strategy for Single-Phase UPS In-
verters, in IEEE Transactions on Power Electronics, vol. 30, no. 7,
pp. 3976-3983, July 2015.
[12] Jeang-Lin Chang, Applying discrete-time proportional integral ob-
servers for state and disturbance estimations, in IEEE Transactions
on Automatic Control, vol. 51, no. 5, pp. 814-818, May 2006.