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Conways Game Of Life On FPGA

Mojo V2 FPGA Development Board

Abstract various patterns throughout the

course of the game.
The main aim of this project was to
implement Conways game of life (a Conways game of life is a zero
cellular automata) on a grid of player game and is governed by
16x16 led matrices. This was later simple rules. The real challenge to
upgraded to work on a VGA display. us was implementation using FPGA.
We have used Mojo V2 FPGA FPGA (Field Programmable Gate
Development board; our design uses Arrays), unlike microcontrollers, do
its parallelization and is hence fast. nothing by themselves and the entire
hardware has to be coded. This also
We tried to make it interactive but it the power of FPGA
was not implemented due to
technical difficulties. The game of
life is much more interesting if its
Motivation behind the Project
FPGAs are capable of parallel
Introduction processing which means that they
The Game of Life is not just a can simultaneously perform several
typical computer game. It is a operations which otherwise have to
'cellular automaton'. Cellular be performed sequentially. We have
automata are discrete, abstract exploited this property of FPGA to
computational systems that have manipulate the next stage every cell
proved useful both as general in our game according to its
models of complexity and as more neighbourhood cells simultaneously.
specific representations of non- As clear from the description, the
linear dynamics in a variety of execution this way is considerably
scientific fields. faster than one-by-one method. This
factor will be noticeably significant
The Game of Life is a simulation of once the setup is scaled up. This
a collection of cells which, based on makes it ideal to study cellular
a few mathematical rules, can live, automata as the processes
die or multiply. Depending on the necessarily dont occur sequentially.
initial conditions, the cells form

8 general purpose LEDs
Background Theory 1 reset button
The game of life by John Conway 1 LED to show when the
runs on simple rules as follows: FPGA is correctly configured
1. A live cell with fewer than On board voltage regulation
two live neighbours dies, as if that can handle 4.8V - 12V
caused by under-population.
2. A live cell with two or three A microcontroller
live neighbours lives on to the (ATmega16U4) used for
next generation. configuring the FPGA, USB
3. A live cell with more than communications, and reading
three live neighbours dies, as the analog pins
if by overcrowding.
4. A dead cell with exactly three On board flash memory to
live neighbours becomes a store the FPGA configuration
live cell, as if by reproduction. file

A prerequisite for working on FPGA

was to learn a HDL-Hardware
Descriptive Language. For FPGA
one can code in Verilog or VHDL.
We learnt the former. Each set of
commands in Verilog is executed
simultaneously as mentioned earlier
for parallel processing.

Mojo V2 FPGA Development Board

Implementation Details
Source: embeddedmicro.com
The FPGA development board we For the first stage of implementation
used is Mojo V2. The Mojo i.e. simulation of the game of life on
features include a 16X16 LED matrix we used four
Spartan 6 XC6SLX9 FPGA 8X8 LED matrices shorted
appropriately to effectively work as
84 digital IO pins a 16X16. Each LED matrix we used
was a 26 pin matrix 10 pins of which
8 analog inputs

are not required for lighting it up. HS and VS (horizontal and
Following is the pin description of vertical synchronization)
the LED matrix used:
All we needed to do is get a monitor
for VGA display and a female VGA
connector and connect the 15 pins in
the following manner:

In order to light up an LED, the Source: fpga4fun.com/PongGame

column-pin(C) corresponding to it
has to be given high and the row-pin Pins 13 and 14 of the VGA
has to be grounded. For e.g.: for connector (HS and VS) are
LED(3, 4) we have to set R =0, digital signals so can be
C4=1and other row-pins have to be driven directly from two
1 and column-pins 0. FPGA pins.
Pins 1, 2 and 3 (R, G and B)
These pins have to be connected to
are 75 analog signals with
the I/O pins of the Mojo board.
nominal values of 0.7V. With
There are some pins which are by
3.3V FPGA outputs, use three
default connected to the elements
270 series resistors. The
like the Reset button and internal
resistors form voltage dividers
LEDs in the mojo board itself and
with the 75 resistors in the
this has to be taken care of.
monitor inputs so that 3.3V
For the second stage of the project become 3.3*75/
i.e. simulation of game of life using (270+75)=0.72V, which is
VGA display: A VGA monitor close to 0.7V
requires 5 digital signals to display a Pins 5, 6, 7, 8 and 10 are
picture: ground pins.
R, G and B (red, green and
blue signals). Software Platform:

We have used ISE(Integrated switches and lighting a single
Software Environment) design LED in the LED matrix.
suite 14.7 by XilinxXilinx
Following is the entire code
ISE(Integrated Software
used for this version of the
Environment) is a software tool
game of life:
produced by Xilinx for synthesis
and analysis of HDL designs, In the main module, in which all
enabling the developer to modules are instantiated and
synthesize their designs, perform from where input/outputs from
timing analysis, examine RTL external hardware of the set-up
diagrams, simulate a design's are taken, we have three modules
reaction to different stimuli, and instantiated, namely pin, copy
configure the target device with and light in the following
the programmer. One can manner:
simulate the hardware using pin p(
iSim. However the coding in
iSim does not work on FPGA.
Testbenches /Test-fixtures are .arr(arr),
meant for simulation part only. .next(next),
We descried small blocks of
hardware named modules. Inputs
and outputs of each module are copy c(
needed to be specified in the .rst(rst),
beginning and way it processes
the inputs and outputs are needed
to be specified after that. For .arr(arr),
more on syntax and rules see .next(next)
section on code. A module once );
created can be instantiated in any
other module keeping in mind the
hardware feasibility. light pov(
Code for Version 1:
Initially the team wrote small .C(C)
modules to light internal/ external
LEDs with internal/external

Here R and C are the arrays of i.e. the next state of our cellular
I/O pins in mojo board to which grid. The module copy assigns
row and column pins of the LED the values in next to
matrix (16X16) are connected. R corresponding cells in arr.
and C are defined as outputs from
The module light is for POV.
the mojo-top. We had to
Any state of the game of life is
configure these pins in the
being displayed using Persistence
mojo.ucf file; mojo.ucf is where
of Vision. This is the module
we configure the I/O pins of the
which sends output to R and C
mojo board with some pins
pins. This module takes as input a
configured by default to internal
256 bit array and depending on
elements of the board.
the state of each LED lights up
The default clock of the board each of them one by one at a
(clk) is a 50 MHz clock which is frequency of 50 MHz.
too fast to have a noticeable
The module pin takes as input
updating of present state of the
the array arr, i.e. the present state
cell to the next. C1 is a 1 Hz
of the LED matrix and its
clock which has been slowed
function is to give the next state
down using the following
of the matrix in form of output
next following the rules of the
module count (clk, b); game of life. In other words,
input clk; // synthesis according to the present state of
attribute PERIOD clk "50 MHz" the neighbouring cells of the cell
reg [25:0] count = 0; under consideration, it assigns
output reg b = 0; // one pulse per
the next state of the cell in the
second array next. For checking the
rules, we simply add the states
(1-live, 0-dead) of the neighbours
always @ (posedge clk) begin
and compare. For e.g. if arr[x] is
b <= (count == 50000000 - 2); live and the neighbours add upto
count <= b ? 0 : count + 1; 5, we assign next[x] to be a dead
endmodule The matrix is refreshed to its
initial seeding each time the reset
For reference to any LED in the button on the mojo board is
LED matrix we used a 256 bit pressed. As mentioned earlier, the
array. The LED (i, j) is referred updating of the state occurs at a
by arr[i*8+j]. The other 256 bit frequency of 1 Hz.
array, next is the updated state,

All these modules run parallel to CounterX <= CounterX + 1;
give fast execution. If always @(posedge clk)
summarized, the pin module if(CounterXmaxed)
initializes and updates the states.
CounterY <= CounterY + 1;
The light module implements
POV for displaying the current endmodule
state. The module copy copies Module vga:
the array next onto array arr.
module vga(input clk, input [9:0]
Code for Version 2: CounterX, input [9:0] CounterY, output
vga_HS, output vga_VS
This version of Conways game
of life gets displayed on a VGA
screen. This is not as elegantly reg vga_HS, vga_VS;

simple as version-1. always @(posedge clk)

The modules for the slowed begin

down 1Hz clock (module: timer) vga_HS <= (CounterX[9:4]==0); //
and for copying (module: copy) active for 96 clocks
remain the same. For horizontal vga_VS <= (CounterY==0); // active for
and vertical synchronization 2 clocks
pulse generator we are using two end
modules, namely counter and endmodule
VGA. CounterX counts 768
values (from 0 to 767) and
CounterY counts 512 values (0 to To define cells for the game we
511). The two modules are: have hardcoded the blocks in this
Module counter: way:
block[0] =
module counter(input clk, output
CounterX, output CounterY nterY>=200&&CounterY<220))
The entire pin module has been
reg [9:0] CounterX; shifted to mojo-top, so the
reg [9:0] CounterY; updating of the grid occurs at the
wire CounterXmaxed = (CounterX==767); same block of hardware as the
display output.

always @(posedge clk)

In order to make a color be
displayed in the block we
defined, we assign the block
CounterX <= 0; signal to the color signal output
else in this way: R = block[x];

Block Diagram:

16X16 LED

Mojo V2

Female VGA

Out to VGA

Limitations and Compromises There are several more
applications of FPGAs.
There are some limitations to the
One of the ideas we were
latest version of the project:
considering is making a
The code for initial seeding genetic algorithm solver
needs to be changed whenever using FPGAs.
a different initial seed is FPGAs can be used in bots
needed. making their execution
The code is not robust at faster due to parallel
present. For scaling up the processing.
display, the code has to be To emphasize on the scope
changed significantly, of FPGA: it can be used to
especially when it comes to design any circuit be it a
VGA display which mainly simple AND gate or a
involves hard coding. microprocessor.
We havent been able to
implement user interfacing to
the game till now. Once the References
game is set on, user can not
change the state of a desired
Future Prospects and Scope ch?v=pkJAWpkaiHg
User interfacing can be
added to the game. This
would mean the user can http://www.fpga4fun.com/Pon
set the initial seeding and
further user can access any
cell and change its state in
run-time of the game.
There can be more than
two states associated with
each cell corresponding to
growth and aging using a
color gradient instead of
just one color.
Another idea is to simulate
spread of diseases and
mutation at cellular level.
Team: E_Trix


Team Members: Arjun Bhasin

Avani Samdariya, Avi Singh (Mentor)

Krati Agrawal, Kevin Jose

Samyak Jain, and Piyush Awasthi

Sanjari Srivastava