8-2 CLOCK GENERATOR (8284A) 293

System
reset
I
FIGURE 8-4 The clock generator (8284A) and the 8086 and 8088 microprocessor illustrating
the connection for the clock and reset signals. A 15 MHz crystal provides the 5 MHz clock for
the microprocessor.

Operation of the Clock Section. The top half of the logic diagram represents the clock and reset
synchronization section of the 8284A clock gznerator. As the diagram shows, the crystal oscil-
lator has two inputs: X1 and X2. If a crystal is attached to X1 and X2, the oscillator generates a
square-wave signal at the same frequency as the crystal. The square-wave signal is fed to an
AND gate and also to an inverting buffer that provides the OSC o u t p ~ signal.
~t The OSC signal is
sometimes used as an EFI input to other 8284A circuits in a system.
An inspection of the AND gate reveals that when FIT is a logic 0, the oscillator oi~tputis
steered through to the divide-by-3 counter. If FIT is a logic 1, then EFI is steered through to the
counter.
The output of the divide-by-3 counter generates the timing for ready synchronization, a
signal for another counter (divide-by-2), and the CLK signal to the 808618088 microprocessors.
The CLK signal is also buffered before it leaves the clock generator. Notice that the output of the
first counter feeds the second. These two cascaded counters provide the divide-by-6 output at
PCLK, the peripheral clock output.
Figure 8 - 4 shows how an 8284A is connected to the 808618088. Notice (1) that F/? and
CSYNC are grounded to select the crystal oscillator and (2) that a 15 MHz crystal provides the
normal 5 MHz clock signal to the 808618088 as well as a 2.5 MHz peripheral clock signal.
Operation of the Reset Section. The reset section of the 8284A is very simple. It consists of a
Schmitt trigger buffer and a single D-type flip-flop circuit. The D-type flip-flop ensures that the
timing requirements of the 808618088 RESET input are met. This circuit applies the RESET
signal to the microprocessor on the negative edge (1-to-0 transition) of each clock. The
808618088 microprocessors sample RESET at the positive edge (0-to-1 transition) of the clocks;
therefore, this circuit meets the timing requirements of the 8086/8088.
Refer again to Figure 8-4. Notice that an RC circuit provides a logic 0 to the RES input pin
when power is first applied to the system. After a short time, the RES input becomes a logic 1 be-
cause the capacitor charges toward +5.0 V through the resistor. A push-button switch allows the
microprocessor to be reset by the operator. Correct reset timing requires the RESET input to
 CHAPTER 8 808618088 HARDWARE SPECIFICATIONS

become a logic 1 no later than four clocks after syslem power is applied and to be held high for
at least 5 0 ps. The flip-flop makes certain that RESET goes high in four clocks, and the RC time
constant ensures that it stays high for at least 50 ps.

8-3 BUS BUFFERING AND LATCHING

Before the 808618088 microprocessors can be used with memory or 110 interfaces, their multi-
plexed buses must be demultiplexed. This section provides the detail required to demultiplex the
buses and illustrates how the buses are buffered for very large systems. (Because the maximum
fan-out is 10, the system must be buffered if it contains more than 10 other Components.)

Demultiplexing the Buses

The addressldata bus on the 808618088 is multiplexed (shared) to reduce the number of pins re-
quired for the 808618088 integrated circuit. Unfortunately, this burdens the hardware designer
with the task of extracting or demultiplexing information from these multiplexed pins.
Why not leave the buses multiplexed? Memory and 110 require that the address remains
valid and stable throughout a read or write cycle. If the buses are multiplexed, the address
changes at the memory and 110, which causes them to read or write data in the wrong locations.
All computer systems have three buses: (1) an address bus that provides the memory and
110 with the memory address or the 110 port number, (2) a data bus that transfers data between
the microprocessor and the memory and 110 in the system, and (3) a control bus that provides
control signals to the memory and 110. These buses must be present in order to interface to
memory and 110.

Demultiplexing the 8088. Figure 8-5 illustrates the 8088 microprocessor and the components
required to demultiplex its buses. In this case, two 74LS373 transparent latches are used to de-
multiplex the addressldata bus connections AD7-AD, and the multiplexed addresslstatus con-
nections AldS6-A 16/S3.
These transparent latclles, which are like wires whenever the address latch enable pin
(ALE) becomes a logic 1, pass the inputs to the outputs. After a short time, ALE returns to its
logic 0 condition, which causes the latches to remember the inputs at the time of the change to a
logic 0. In this case, A,-A. are stored in the bottom latch and AI9-AI6 in the top latch. This
yields a separate address bus with connections A19-A,. These address connections allow the
8088 to address 1M byte of memory space. The fact that the data bus is separate allows it to be
connected to any 8-bit peripheral device or memory component.
Demultiplexing the 8086. Like the 8088, the 8086 system requires separate address, data, and
control buses. It differs primarily in the number of multiplexed pins. In the 8088, only AD,-AD,
and AldS6-AI6IS3 a ~ m u l t i p l e x e d .In the 8086, the multiplexed pins include ADI5-AD,,
AI9/SG-AI6/S3,and BHE/S,. All of these signals must be demultiplex
Figure 8-6 illustrates a demultiplexed
- -8086 with all three buses: address (Al9-A, and
m), data (Dl,-D,,). and control (M/IO, RD, and m).
T1.t circuit shown in Figure 8-6 is almost identical to the one pictured in Figure 8-5, ex-
-74LS373 latch has been added to demultiplex the addressldata bus pins
cept that an additional
ADl5-AD, and a BHE/S, input has been added to the top 74LS373 to select the high-order
memory bank in the 16-bit memory system of the 8086. Here the memory and 110 system see the
8086 as a device with a 20-bit address bus (Al9-A,), a 16-bit data bus (D15-DO),and a _?-line
m,
conlrol bus ( M I E , m).
and
8-4 BUS TIMING

Vcn
- TCLCL -TCHlCH2

CLK (8284 Outpull

R E A D CYCLE
(NOTE 1 ) .
(wA,m. v,,

FIGURE 8-11 Minimum mode 8088 bus timing for a read operation

Memory access time starts when the address appears on the memory address bus and
continues until the microprocessor samples the memory data at T3. Approximately three T
states elapse between these times. (Refer to Figure 8-12 for the following times.) The ad-
dress does not appear until TCLAVtime (1 10 ns if the clock is 5 MHz) after the start of T I .
This means that T,,, time must be subtracted from the three clocking states (600 ns) that
separate the appearance of the address (TI) and the sampling of the data (T3). One other time
must also be subtracted: the data setup time (TDVCL),which occurs before T3. Memory access
time is thus three clocking states minus the sum of T,,, and TDVCL. Because TDVCL is 30 ns
with a 5 MHz clock, the allowed memory access time is only 460 ns (access time = 600 ns
- 110 ns - 30 ns).
Actually, the memory devices chosen for connection to the 808618088 operated at 5 MHz
must be able to access data in less than 460 ns because of the time delay introduced by the ad-
dress decoders and buffers in the system. At least a 30 or 40 ns margin should exist for the oper-
ation of these circuits. Therefore, the memory speed should be no slower than about 420 ns to
operate correctly with the 808618088 microprocessors.
 CHAPTER 8 808618088 HARDWARE SPECIFICATIONS

8088 is operated with a 5 MHz clock. Hold time is often much less than this, and is in fact often
0 ns for memory devices. The width of !he WR strobe is T,,,, or 340 ns at a 5 MHz clock rate.
This rate, too, is compatible with most memory devices that have an access time of 400 ns or less.

8-5 READY AND THE WAIT STATE

As we mentioned earlier in this chapter, the READY input causes wait states for slower memory
and I/O components. A wait state (Tw) is an extra clocking period, inserted between T 2 and T3.
that lengthens the bus cycle. If one wait state is inserted, then the memory access time, normally
460 ns with a 5 MHz clock, is lengthened by one clocking period (200 ns) to 660 ns.
In this section, we discuss the READY synchronization circuitry inside the 8284A clock
generator, show how to insert one or more wait states selectively into the bus cycle. and examine
the READY input and the synchronization times it requires.

The READY Input

The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. If
READY is a logic 0 at the end of T2, then T3 is delayed and Tw is inserted between T2 and T3.
READY is next sampled at the middle of Tw to determine if the next state is Tw or T3. It is
tested for a logic 0 on the 1-to-0 transition of the clock at the end of T2 and for a 1 on the 0-to-1
transition of the clock in the middle of Tw.
The READY input to the 808618088 has some stringent timing requirements. The timing
diagram in Figure 8-14 shows READY causing one wait state (Tw) along with the required
setup and hold times from the system clock. The timing requirement for this operation is met by
the intemal READY synchronization circuitry of the 8284A clock generator. When the 8284A is
used for READY, the RDY (ready input to the 8284A) input occurs at the end of each T state.

RDY and the 8284A

RDY is the synchronized ready input to the 8284A clock generator. The timing diagram for this
input is provided in Figure 8-15. Although it differs from the timing for the READY input to the
808618088, the internal 8284A circuitry guarantees the accuracy of the READY synchronization
provided to the 808618088.
Figure 8-16 again depicts the internal structure of the 8284A. The bottom half of this dia-
gram is the READY synchronization circuitry. At the leftmost side, the RDYI and AEN1 inputs
are ANDed, as are the RDY2 and AEN2 inputs. The outputs of the AND gates are then ORed to
generate the input to the one or two stages of synchronization. In order to obtain a logic 1 at the
inputs to the flip-flops, RDY 1 ANDed with AENl must be active or RDY2 ANDed with AEN2
must be active.

cLK
READY

FIGURE 8-14
-'-'i{r$
808618088 READY input timing
9-1 MEMORY DEVICES 31 3

Memory Pin Connections

Pin connections common to all memory devices are the address inputs, data outputs or inpuvout-
puts, some type of selection input, and at least one control input used to select a read or write op-
eration. See Figure 9-1 for ROM and RAM generic-memory devices.
Address Connections. All memory devices have address inputs that select a memory location
within the memory device. Address inputs are almost always labeled from A,, the least signifi-
cant address input, to A,, where subscript ,can be any value but is always labeled as one less
than the total number of address pins. For example, a memory device that has 10 address pins has
its address pins labeled from A, to A,. The number of address pins found on a memorj device is
determined by the number of memory locations found within it.
Today, the more common memory devices have between 1K (1,024) to 16M (16,777,216)
memory locations, with 256M memory location devices on the horizon. A 1K memory device
has 10 address pins (A,-A,); therefore, 10 address inputs are required to select any of its 1,024
memory locations. It takes a 10-bit binary number (1,024 different combinations) to select any
single location on a 1,024-location device. If a memory device has 11 address connections
(A,-A,,), it has 2,048 (2K) internal memory locations. The number of memory locations can
thus be extrapolated from the number of address pins. For example, a 4K memory device has 12
address connections, an 8K device has 13, and so forth. A device that contains 1M locations re-
quires a 20-bit address (A,-A,,).
A 400H represents a 1K-byte section of the memory system. If a memory device is de-
coded to begin at memory address 10000H, and it is a 1K device, its last location is at address
103FFH-one location less than 400H. Another important hexadecimal number to remember is
a 1000H, because lOOOH is 4K. A memory device containing a starting address of 14000H that
is 4K bytes in size ends at location 14FFFH--one location less than 1000H. A third number is
64K or 10000H. A memory that starts at location 30000H and ends at location 3FFFFH is a 64K
byte memory. Finally, because l M of memory is not uncommon, a 1M memory contains
lOOOOOH memory locations.
Data Connections. All memory devices have a set of data outputs or input/outputs. The device
illustrated in Figure 9-1 has a common set of input/output (110) connections. Today, many
memory devices have bi-directional common VO pins.
The data connections are the points at which data are entered for storage or extracted for
reading. Data pins on memory devices are almost always labeled Do through D, for an 8-bit-wide

FIGURE 3-1 A pseudo-

memory component illustrat-
ing the address, data, and
control connections
Address
connection,

- -- --
Sclcct Krad
9-1 MEMORY DEVICES

UODE SELECTION

Vpp VcC OUTPUTS

(20) (21) (24) (9-11, 13-17]
,.
PIN CONFIGURATION
Read "IL 1 vIL I +5 1 +5 1 DOUT
ikselect I Don't care / VIH / +5 / +5 1 High Z I
Power Down

Program Verlfy +25 DOUT

Program Inhibit "IL VIH +25 +5 High Z

BLOCK DIAGRAM

"CC ~
GND
"PP
-
- - - - e
DATA OUTPUTS
01-1-07

W- CHIP SELECT,

=r~-i
PDIPGM --4 POWER DOWN, OUTPUT BUFFERS
PIN NAMES AND PROG. LOGIC

I An-Aqn I ADDRESSES 1 DECODER

PDIPGM POWER DOWNIPROGRAM Ao-A10

?% / CHIP SELECT
ADDRESS
INPUTS -
--4

1
-
X 16,384-BIT
DECODER CELLMATRIX

FIGURE 9-2 The pin-out of the 2716, 2K x 8 EPROM (Courtesy of Intel Corporation)

Still another, newer type of read-mostly memory (RMM) is called theflash memoly. The
flash memory1 is also often called an EEPROM (electrically erasable programmable ROM),
EAROM (electrically alter-able ROM), or a NOVRAM (nonvolatile RAM). These memory de-
vices are electrically erasable in the system, but require more time to erase than a normal RAM.
The flash memory device is used to store setup information for systems such as the video card in
the computer. It may also soon replace the EPROM in the computer for the BIOS memory. Some
systems contain a password stored in the flash memory device.
Figure 9-2 illustrates the 2716 EPROM, which is representative of most EPROMs. This de-
vice contains 11 address inputs and 8 data outputs. The 2716 is a 2K x 8 memory device. The
27XXX series of the EPROMs contains the following part numbers: 2704 (512 x 8), 2708 (1K x 8),
2716 (2K x 8), 2732 (4K x 8), 2764 (8K x 8), 27128 (16K x 8), 27256 (32K x 8), 27512 (64K x 8),
and 271024 (128K x 8). Each of these parts contains address pins, eight data connections, one or
more chip selection inputs (E), and an output enable pin (m).
Figure 9-3 illustrates the timing diagram for the 2716 EPROM. Data only appear on the
output connections after a logic 0 is placed on both the a
and ?%pin connections. 1f and a
are not both logic O's, the data output connections remain at their high-impedance or off states. Note
that the Vpppin must be placed at a logic 1 for data to be read from the EPROM. In some cases, the
Vpppin is in the same position as the %% pin on the SRAM. This can allow a single socket to hold
either an EPROM or an S U M . Examples are the 2716 EPROM and the 61 16 SRAM, both 2K x 8
devices that have the same pin-out, except for VPpon the EPROM and on the SRAM.
One important piece of information provided by the timing diagram and data sheet is the
memory access time-the time that it takes the memory to read information. As Figure 9-3 il-
lustrates, memory access time (TAcc) is measured from the appearance of the address at the

'Flash memory is a registered trademark of Intel Corporation

CHAPTER 9 MEMORY INTERFACE

A.C. Characteristics
T~ = O'C to 70C, ~ ~ ~ = 1+5V
' +5%.
1 vppI2' = VCCf0.6vi3'

I Symbol I Parameter
Min. I
Limits
1
~ y p . [ ~ ] Max.
1 1 Unit Test Conditions 1
tAccl Address to Output Delay 1 250 1 450 1 ns ( PDIPGM = %C = VIL

tAcc2 I PD/PGM to output Delay 1 280 1 450 1 ns 1 a =v,,

f co Chip Select to Output Delay 120 ns PDIPGM = VIL

~ P F PDIPGM to Output Float 0 100 ns s =vIL

~ D F Chip Deselect to Output Float 0 100 ns PDIPGM =VIL

to" Address to Output Hold 0 ns PDIPGM = = VIL

~ a ~ a c i t a n cTA
e~=~
25'c,
~ f = 1 MHZ A.C. Test Conditions:
Symbol I Parameter ] Typ. ] Max. I Unit I Conditions I Output Load: 1 TTL gate and CL = 100 pF
lnput Rise and Fall Times: <20 ns
CIN Input Capacitance 4 6 pF VIN =OV
lnput Pulse Levels: 0.8V to 2.2V
COuT Output Capacitance 8 12 pF VoUT = OV Timing Measurement Reference Level:
lnouts 1V and 2V
Outputs O.8V and 2V
WAVEFORMS
A. Read Mode
PDIPGM = VIL I
ADDRESS

YIG* 2
OUTPUT DATA OUT V I L l O

FIGURE 9-3 The timing diagram of AC c h a r a c t e r i s t i c s of the 2716 EPROM (Courtesy o f Intel
Corporation)

Also,
=
address inputs until the appearance of the data at the output connections. This is based on the as-
sunlption that the input goes low at the same time that the address inputs become stable.
must be a logic 0 for the output connections to become active. The basic speed of th
EPROM is 450 ns. (Recall from Chapter 7 that the 808618088 operated with a 5 MHz clock al-
lowed memory 460 ns to access data.) This type of inemory component requires wait states to
operate properly with the 8086/8088 microprocessors because of its rather long access time. If
wait states are not desired, higher speed versions of the EPROM are available at an additional
cost. Today, EPROM memory is available with access times of as little as 100 ns.

Static Ram (SRAM) Devices

Static RAM memory devices retain data for as long as DC power is applied. Because no special ac-
tion (except power) is required to retain stored data, these devices are called stutic memory. They
are also called volatile memoly because they will not retain data without power. The main differ-
ence between a ROM and a RAM is that a RAM is written under nonnal operation, while a ROM
is programmed outside the computer and is only normally read. The SRAM stores temporary data
9-1 MEMORY DEVICES

FiGURE 9-4 The pin-out TMS4016 . ..

NL PACKAGE
(TOP VIEW1
of the TMS4016, 2K x 8 static
RAM (SRAM). (Courtesy
of Texas Instruments
Incorporated.)

PIN NOMENCLATURE
A0 - A10 Addresses
DO1 - DO8 Data IniDara Out
E Output Enable
9 Chip Select
"cc + 5-v Supply
VSS Ground
w W r ~ r eEnable

and is used when the size of the readlwrite memory is relatively small. Today, a small memory is
one that is less than 1M byte.
Figure 9 4 illustrates the 4016 SRAM, which is a 2K x 8 readlwrite memory. This device
has 11 address inputs and 8 data input/output connections. This device is representative of all
SRAM devices.
The control inputs of this RAM are slightly different from those presented earlier. The
pin is labeled G, the CS pin 3, and the WE pin W.Despite the altered designations, the control
pins function exactly the same as those outlined previously. Other manufacturers make this pop-
ular SRAM under the part numbers 2016 and 6 116.
Figure 9-5 depicts the timing diagram for.the 4016 SRAM. As the read cycle timing re-
veals, the access time is ta (A). On the slowest version of the 4016, this time is 250 ns, which is
fast enough to connect to an 8088 or an 8086 operated at 5 MHz without wait states. Again, it is
important to remember that the access time must be checked to determine the compatibility of
memory components with the microprocessor.
Figure 9-6 illustrates the pin-out of the 62256, 32K x 8 static RAM. This device is pack-
aged in a 28-pin integrated circuit, and is available with access times of 120 ns or 150 ns. Other
common SRAM devices are available in 8K x 8 and 128K x 8 sizes with access times of as little
as 10 ns for SRAM used in computer cache memory systems.

Dynamic Ram (DRAM) Memory

About the largest static RAM available today is a 128K x 8. Dynamic RAMS, on the other hand,
are available in much lager sizes: up to 16M x 1. In all other respects, DRAM is essentially the
same as SRAM, except that it retains data for only 2 or 4 ms on an integrated capacitor. After 2
or 4 ms, the contents of the DRAM must be completely rewritten (rej5,eshed) because the capac-
itors, which store a logic 1 or logic 0, lose their charges.
Instead of requiring the almost impossible task of reading the contents of each memory
location with a program and then rewriting them, the manufacturer has internally constructed
the DRAM so that, in the 64K x 1 version, the entire contents of the memory is refreshed with
 9-1 MEMORY DEVICES

timing waveform of read cycle [see note 5)

I
ADDRESS

timing waveform of write cycle no. 1 (see note 6)

ADDRESS
I
I (see note 8)

p~

W
(see

timing waveform of write cycle no. 2 (see notes 6 and 11)

-t----------tc(wr)
ADDRESS

NOTES 5 W IS h ~ g hRead Cycle

6.W must be high dur~ngall address transltlons.
7. A wrlte occurs during the overlap of a low 5 and a l o w m
8 (,I is measured from the earlier of 5 o r W going high to the end of the wrlte cycle.
9. Dur~ngt h ~ speriod. 110 plns are in the output state so that the Input signals of opposlte phase to the outputs must not be appl~ed.
10 If the Slow transition occurs simultaneously with t h e m low trans~tlonsor after t h e m transltlon, output remalns In a hlgh ~mpedancestate
11 G IS continuously low (G = VIL).
12 If S is low dur~ngthis period. 110 plns are In the output state Data lnput sgnals of opposlte phase to the outputs must not be applied.
+
13, Translt~onIS measured 200 mV from steady-state voltage
14 If the 3 low transltlon occurs before the W low transition. then the data r p u t signals of opposlte phase to the outputs must not be applied
for the durat~onof tdlsiW, after t h e m low transition.

FIGURE 9-5 (continued)

9-1 MEMORY DEVICES

FIGURE 9-8 RAS, CAS, and address input timing for the TMS4464 DRAM (Courtesy of Texas
Instruments Incorporated)

TMS4464, which stores 256K bits of data. Notice that it contains only 8 address inputs where it
should contain 16-the number required to address 64K memory locations. The only way that
16 address bits can be forced into 8 address pins is in two-
8-bit increments. This operation
- re-
quires two special pins called column address strobe (CAS) and row address strobe -
(RAS).
First, Ao-A, are placed on the address pins and strobed into an internal row latch by RAS as the
row address. Next. the address bits A s - A d r e placed on the same eight address inputs and
strobed into an internal column latch by CAS as the column address (see Figure 9-8 for this
timing). The 16-bit address held in- these internal latches addresses the contents of one of the 4-
bit memory locations. Note that CAS also performs the function of the chip selection input to
the DRAM.
Figure 9-9 illustrates a set of multiplexers used to strobe the column
-
and row addresses
into the eight address inputs of a pair of TMS4464 DRAMs. Here the RAS not only strobes the
row address into the DRAMs, but it also changes the address applied to the address-inputs. This
is possible due to the long propagation delay time of the multiplexers. When - RAS is a logic 1,
the B inputs are connected to the Y outputs of the multiplexers; when the RAS input goes to a
logic 0, the A inputs connect to the Y outputs. Because the internal row address latch is edge-
triggered, it captures the row address before the address at the inputs change to the column ad-
dress. More detail on DRAM and DRAM interfacing is provided in Section 9-6.
As with the SRAM, the R m pin writes data to the DRAM when a logic 0, but there is no
pin labeled or enable. There also is no (select) input to the DRAM. As mentioned, the CAS
input selects the DRAM. If selected, the DRAM is written if R/W = 0 and read if RTW = 1.
Figure 9-10 shows the pinout of the 41256 dynamic RAM. This device is organized as a
256K x 1 memory requiring as little as 70 ns to access data.
More recently. larger DRAMs have become available that are organized as a 1M x 1
memory, 4M x 1, and 16M x 1. On the horizon is the 256M x 1 memory, which is in the plan-
ning stages. Because DRAM memory is usually placed on small circuit boards called SIMMs,
Figure 9-1 1 shows the pin-outs of the two most common SIMMs (Single In-line Memory Mod-
ules). The 30-pin SIMM is organized most often as 1 M x 8 or 1M x 9 and 4M x 8 or 4M x 9.
 9-2 ADDRESS DECODING

DATE 6/6/96
CHIP DECODE31 PALl6L8

;pins1 2 3 4 5 6 7 8 9 1 0
A19 .A18 A17 A16 Ai5 .A14 A13 NC NC GND

;pins 11 12 13 14 i5 i6 3.7 18 i9 20
NC 08 07 05 05 04 03 02 01 VCC

The first eight lines of the program illustrated in Example 9-5 identify the program title,
pattern, revision, author, company, date, and chip type with the program name. Although it is
normal to find entries in each heading, the only entry that is absolutely necessary is the CHIP
statement. In this example, the chip type is a PAL16L8 and the program is called DECODERl.
After the program is identified, a comment statement (;pins) identifies the pin numbers. Below
this comment statement appears the pins as defined for this application. Once all the pins are de-
fined, we use the EQUATIONS statement to indicate that the equations for this application
follow. In this example, the equations define the eight chip enable outputs for the eight EPROM
memory devices. Refer to Figure 9-18 for the complete schematic diagram of this PAL decoder.

FOOOOH - FlFFFH FZOOOH - FBFFFH F4000H - F5FFFH FGOOOH - F7FFFH

A12-A0
I I I I

FIGURE 9-1 8 A PAL16L8 that decodes 8 2764 (8K x 8) memory devices